1	/* Optimize by combining instructions for GNU compiler.
2	Copyright (C) 1987-2023 Free Software Foundation, Inc.
3
4	This file is part of GCC.
5
6	GCC is free software; you can redistribute it and/or modify it under
7	the terms of the GNU General Public License as published by the Free
8	Software Foundation; either version 3, or (at your option) any later
9	version.
10
11	GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12	WARRANTY; without even the implied warranty of MERCHANTABILITY or
13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14	for more details.
15
16	You should have received a copy of the GNU General Public License
17	along with GCC; see the file COPYING3. If not see
18	<http://www.gnu.org/licenses/>. */
19
20	/* This module is essentially the "combiner" phase of the U. of Arizona
21	Portable Optimizer, but redone to work on our list-structured
22	representation for RTL instead of their string representation.
23
24	The LOG_LINKS of each insn identify the most recent assignment
25	to each REG used in the insn. It is a list of previous insns,
26	each of which contains a SET for a REG that is used in this insn
27	and not used or set in between. LOG_LINKs never cross basic blocks.
28	They were set up by the preceding pass (lifetime analysis).
29
30	We try to combine each pair of insns joined by a logical link.
31	We also try to combine triplets of insns A, B and C when C has
32	a link back to B and B has a link back to A. Likewise for a
33	small number of quadruplets of insns A, B, C and D for which
34	there's high likelihood of success.
35
36	We check (with modified_between_p) to avoid combining in such a way
37	as to move a computation to a place where its value would be different.
38
39	Combination is done by mathematically substituting the previous
40	insn(s) values for the regs they set into the expressions in
41	the later insns that refer to these regs. If the result is a valid insn
42	for our target machine, according to the machine description,
43	we install it, delete the earlier insns, and update the data flow
44	information (LOG_LINKS and REG_NOTES) for what we did.
45
46	There are a few exceptions where the dataflow information isn't
47	completely updated (however this is only a local issue since it is
48	regenerated before the next pass that uses it):
49
50	- reg_live_length is not updated
51	- reg_n_refs is not adjusted in the rare case when a register is
52	no longer required in a computation
53	- there are extremely rare cases (see distribute_notes) when a
54	REG_DEAD note is lost
55	- a LOG_LINKS entry that refers to an insn with multiple SETs may be
56	removed because there is no way to know which register it was
57	linking
58
59	To simplify substitution, we combine only when the earlier insn(s)
60	consist of only a single assignment. To simplify updating afterward,
61	we never combine when a subroutine call appears in the middle. */
62
63	#include "config.h"
64	#include "system.h"
65	#include "coretypes.h"
66	#include "backend.h"
67	#include "target.h"
68	#include "rtl.h"
69	#include "tree.h"
70	#include "cfghooks.h"
71	#include "predict.h"
72	#include "df.h"
73	#include "memmodel.h"
74	#include "tm_p.h"
75	#include "optabs.h"
76	#include "regs.h"
77	#include "emit-rtl.h"
78	#include "recog.h"
79	#include "cgraph.h"
80	#include "stor-layout.h"
81	#include "cfgrtl.h"
82	#include "cfgcleanup.h"
83	/* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
84	#include "explow.h"
85	#include "insn-attr.h"
86	#include "rtlhooks-def.h"
87	#include "expr.h"
88	#include "tree-pass.h"
89	#include "valtrack.h"
90	#include "rtl-iter.h"
91	#include "print-rtl.h"
92	#include "function-abi.h"
93	#include "rtlanal.h"
94
95	/* Number of attempts to combine instructions in this function. */
96
97	static int combine_attempts;
98
99	/* Number of attempts that got as far as substitution in this function. */
100
101	static int combine_merges;
102
103	/* Number of instructions combined with added SETs in this function. */
104
105	static int combine_extras;
106
107	/* Number of instructions combined in this function. */
108
109	static int combine_successes;
110
111	/* combine_instructions may try to replace the right hand side of the
112	second instruction with the value of an associated REG_EQUAL note
113	before throwing it at try_combine. That is problematic when there
114	is a REG_DEAD note for a register used in the old right hand side
115	and can cause distribute_notes to do wrong things. This is the
116	second instruction if it has been so modified, null otherwise. */
117
118	static rtx_insn *i2mod;
119
120	/* When I2MOD is nonnull, this is a copy of the old right hand side. */
121
122	static rtx i2mod_old_rhs;
123
124	/* When I2MOD is nonnull, this is a copy of the new right hand side. */
125
126	static rtx i2mod_new_rhs;
127
128	struct reg_stat_type {
129	/* Record last point of death of (hard or pseudo) register n. */
130	rtx_insn *last_death;
131
132	/* Record last point of modification of (hard or pseudo) register n. */
133	rtx_insn *last_set;
134
135	/* The next group of fields allows the recording of the last value assigned
136	to (hard or pseudo) register n. We use this information to see if an
137	operation being processed is redundant given a prior operation performed
138	on the register. For example, an `and' with a constant is redundant if
139	all the zero bits are already known to be turned off.
140
141	We use an approach similar to that used by cse, but change it in the
142	following ways:
143
144	(1) We do not want to reinitialize at each label.
145	(2) It is useful, but not critical, to know the actual value assigned
146	to a register. Often just its form is helpful.
147
148	Therefore, we maintain the following fields:
149
150	last_set_value the last value assigned
151	last_set_label records the value of label_tick when the
152	register was assigned
153	last_set_table_tick records the value of label_tick when a
154	value using the register is assigned
155	last_set_invalid set to true when it is not valid
156	to use the value of this register in some
157	register's value
158
159	To understand the usage of these tables, it is important to understand
160	the distinction between the value in last_set_value being valid and
161	the register being validly contained in some other expression in the
162	table.
163
164	(The next two parameters are out of date).
165
166	reg_stat[i].last_set_value is valid if it is nonzero, and either
167	reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
168
169	Register I may validly appear in any expression returned for the value
170	of another register if reg_n_sets[i] is 1. It may also appear in the
171	value for register J if reg_stat[j].last_set_invalid is zero, or
172	reg_stat[i].last_set_label < reg_stat[j].last_set_label.
173
174	If an expression is found in the table containing a register which may
175	not validly appear in an expression, the register is replaced by
176	something that won't match, (clobber (const_int 0)). */
177
178	/* Record last value assigned to (hard or pseudo) register n. */
179
180	rtx last_set_value;
181
182	/* Record the value of label_tick when an expression involving register n
183	is placed in last_set_value. */
184
185	int last_set_table_tick;
186
187	/* Record the value of label_tick when the value for register n is placed in
188	last_set_value. */
189
190	int last_set_label;
191
192	/* These fields are maintained in parallel with last_set_value and are
193	used to store the mode in which the register was last set, the bits
194	that were known to be zero when it was last set, and the number of
195	sign bits copies it was known to have when it was last set. */
196
197	unsigned HOST_WIDE_INT last_set_nonzero_bits;
198	char last_set_sign_bit_copies;
199	ENUM_BITFIELD(machine_mode) last_set_mode : MACHINE_MODE_BITSIZE;
200
201	/* Set to true if references to register n in expressions should not be
202	used. last_set_invalid is set nonzero when this register is being
203	assigned to and last_set_table_tick == label_tick. */
204
205	bool last_set_invalid;
206
207	/* Some registers that are set more than once and used in more than one
208	basic block are nevertheless always set in similar ways. For example,
209	a QImode register may be loaded from memory in two places on a machine
210	where byte loads zero extend.
211
212	We record in the following fields if a register has some leading bits
213	that are always equal to the sign bit, and what we know about the
214	nonzero bits of a register, specifically which bits are known to be
215	zero.
216
217	If an entry is zero, it means that we don't know anything special. */
218
219	unsigned char sign_bit_copies;
220
221	unsigned HOST_WIDE_INT nonzero_bits;
222
223	/* Record the value of the label_tick when the last truncation
224	happened. The field truncated_to_mode is only valid if
225	truncation_label == label_tick. */
226
227	int truncation_label;
228
229	/* Record the last truncation seen for this register. If truncation
230	is not a nop to this mode we might be able to save an explicit
231	truncation if we know that value already contains a truncated
232	value. */
233
234	ENUM_BITFIELD(machine_mode) truncated_to_mode : MACHINE_MODE_BITSIZE;
235	};
236
237
238	static vec<reg_stat_type> reg_stat;
239
240	/* One plus the highest pseudo for which we track REG_N_SETS.
241	regstat_init_n_sets_and_refs allocates the array for REG_N_SETS just once,
242	but during combine_split_insns new pseudos can be created. As we don't have
243	updated DF information in that case, it is hard to initialize the array
244	after growing. The combiner only cares about REG_N_SETS (regno) == 1,
245	so instead of growing the arrays, just assume all newly created pseudos
246	during combine might be set multiple times. */
247
248	static unsigned int reg_n_sets_max;
249
250	/* Record the luid of the last insn that invalidated memory
251	(anything that writes memory, and subroutine calls, but not pushes). */
252
253	static int mem_last_set;
254
255	/* Record the luid of the last CALL_INSN
256	so we can tell whether a potential combination crosses any calls. */
257
258	static int last_call_luid;
259
260	/* When `subst' is called, this is the insn that is being modified
261	(by combining in a previous insn). The PATTERN of this insn
262	is still the old pattern partially modified and it should not be
263	looked at, but this may be used to examine the successors of the insn
264	to judge whether a simplification is valid. */
265
266	static rtx_insn *subst_insn;
267
268	/* This is the lowest LUID that `subst' is currently dealing with.
269	get_last_value will not return a value if the register was set at or
270	after this LUID. If not for this mechanism, we could get confused if
271	I2 or I1 in try_combine were an insn that used the old value of a register
272	to obtain a new value. In that case, we might erroneously get the
273	new value of the register when we wanted the old one. */
274
275	static int subst_low_luid;
276
277	/* This contains any hard registers that are used in newpat; reg_dead_at_p
278	must consider all these registers to be always live. */
279
280	static HARD_REG_SET newpat_used_regs;
281
282	/* This is an insn to which a LOG_LINKS entry has been added. If this
283	insn is the earlier than I2 or I3, combine should rescan starting at
284	that location. */
285
286	static rtx_insn *added_links_insn;
287
288	/* And similarly, for notes. */
289
290	static rtx_insn *added_notes_insn;
291
292	/* Basic block in which we are performing combines. */
293	static basic_block this_basic_block;
294	static bool optimize_this_for_speed_p;
295
296
297	/* Length of the currently allocated uid_insn_cost array. */
298
299	static int max_uid_known;
300
301	/* The following array records the insn_cost for every insn
302	in the instruction stream. */
303
304	static int *uid_insn_cost;
305
306	/* The following array records the LOG_LINKS for every insn in the
307	instruction stream as struct insn_link pointers. */
308
309	struct insn_link {
310	rtx_insn *insn;
311	unsigned int regno;
312	struct insn_link *next;
313	};
314
315	static struct insn_link **uid_log_links;
316
317	static inline int
318	insn_uid_check (const_rtx insn)
319	{
320	int uid = INSN_UID (insn);
321	gcc_checking_assert (uid <= max_uid_known);
322	return uid;
323	}
324
325	#define INSN_COST(INSN) (uid_insn_cost[insn_uid_check (INSN)])
326	#define LOG_LINKS(INSN) (uid_log_links[insn_uid_check (INSN)])
327
328	#define FOR_EACH_LOG_LINK(L, INSN) \
329	for ((L) = LOG_LINKS (INSN); (L); (L) = (L)->next)
330
331	/* Links for LOG_LINKS are allocated from this obstack. */
332
333	static struct obstack insn_link_obstack;
334
335	/* Allocate a link. */
336
337	static inline struct insn_link *
338	alloc_insn_link (rtx_insn *insn, unsigned int regno, struct insn_link *next)
339	{
340	struct insn_link *l
341	= (struct insn_link *) obstack_alloc (&insn_link_obstack,
342	sizeof (struct insn_link));
343	l->insn = insn;
344	l->regno = regno;
345	l->next = next;
346	return l;
347	}
348
349	/* Incremented for each basic block. */
350
351	static int label_tick;
352
353	/* Reset to label_tick for each extended basic block in scanning order. */
354
355	static int label_tick_ebb_start;
356
357	/* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
358	largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
359
360	static scalar_int_mode nonzero_bits_mode;
361
362	/* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
363	be safely used. It is zero while computing them and after combine has
364	completed. This former test prevents propagating values based on
365	previously set values, which can be incorrect if a variable is modified
366	in a loop. */
367
368	static int nonzero_sign_valid;
369
370
371	/* Record one modification to rtl structure
372	to be undone by storing old_contents into *where. */
373
374	enum undo_kind { UNDO_RTX, UNDO_INT, UNDO_MODE, UNDO_LINKS };
375
376	struct undo
377	{
378	struct undo *next;
379	enum undo_kind kind;
380	union { rtx r; int i; machine_mode m; struct insn_link *l; } old_contents;
381	union { rtx *r; int *i; int regno; struct insn_link **l; } where;
382	};
383
384	/* Record a bunch of changes to be undone, up to MAX_UNDO of them.
385	num_undo says how many are currently recorded.
386
387	other_insn is nonzero if we have modified some other insn in the process
388	of working on subst_insn. It must be verified too. */
389
390	struct undobuf
391	{
392	struct undo *undos;
393	struct undo *frees;
394	rtx_insn *other_insn;
395	};
396
397	static struct undobuf undobuf;
398
399	/* Number of times the pseudo being substituted for
400	was found and replaced. */
401
402	static int n_occurrences;
403
404	static rtx reg_nonzero_bits_for_combine (const_rtx, scalar_int_mode,
405	scalar_int_mode,
406	unsigned HOST_WIDE_INT *);
407	static rtx reg_num_sign_bit_copies_for_combine (const_rtx, scalar_int_mode,
408	scalar_int_mode,
409	unsigned int *);
410	static void do_SUBST (rtx *, rtx);
411	static void do_SUBST_INT (int *, int);
412	static void init_reg_last (void);
413	static void setup_incoming_promotions (rtx_insn *);
414	static void set_nonzero_bits_and_sign_copies (rtx, const_rtx, void *);
415	static bool cant_combine_insn_p (rtx_insn *);
416	static bool can_combine_p (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
417	rtx_insn *, rtx_insn *, rtx *, rtx *);
418	static bool combinable_i3pat (rtx_insn *, rtx *, rtx, rtx, rtx,
419	bool, bool, rtx *);
420	static bool contains_muldiv (rtx);
421	static rtx_insn *try_combine (rtx_insn *, rtx_insn *, rtx_insn *, rtx_insn *,
422	bool *, rtx_insn *);
423	static void undo_all (void);
424	static void undo_commit (void);
425	static rtx *find_split_point (rtx *, rtx_insn *, bool);
426	static rtx subst (rtx, rtx, rtx, bool, bool, bool);
427	static rtx combine_simplify_rtx (rtx, machine_mode, bool, bool);
428	static rtx simplify_if_then_else (rtx);
429	static rtx simplify_set (rtx);
430	static rtx simplify_logical (rtx);
431	static rtx expand_compound_operation (rtx);
432	static const_rtx expand_field_assignment (const_rtx);
433	static rtx make_extraction (machine_mode, rtx, HOST_WIDE_INT, rtx,
434	unsigned HOST_WIDE_INT, bool, bool, bool);
435	static int get_pos_from_mask (unsigned HOST_WIDE_INT,
436	unsigned HOST_WIDE_INT *);
437	static rtx canon_reg_for_combine (rtx, rtx);
438	static rtx force_int_to_mode (rtx, scalar_int_mode, scalar_int_mode,
439	scalar_int_mode, unsigned HOST_WIDE_INT, bool);
440	static rtx force_to_mode (rtx, machine_mode,
441	unsigned HOST_WIDE_INT, bool);
442	static rtx if_then_else_cond (rtx, rtx *, rtx *);
443	static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
444	static bool rtx_equal_for_field_assignment_p (rtx, rtx, bool = false);
445	static rtx make_field_assignment (rtx);
446	static rtx apply_distributive_law (rtx);
447	static rtx distribute_and_simplify_rtx (rtx, int);
448	static rtx simplify_and_const_int_1 (scalar_int_mode, rtx,
449	unsigned HOST_WIDE_INT);
450	static rtx simplify_and_const_int (rtx, scalar_int_mode, rtx,
451	unsigned HOST_WIDE_INT);
452	static bool merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
453	HOST_WIDE_INT, machine_mode, bool *);
454	static rtx simplify_shift_const_1 (enum rtx_code, machine_mode, rtx, int);
455	static rtx simplify_shift_const (rtx, enum rtx_code, machine_mode, rtx,
456	int);
457	static int recog_for_combine (rtx *, rtx_insn *, rtx *);
458	static rtx gen_lowpart_for_combine (machine_mode, rtx);
459	static enum rtx_code simplify_compare_const (enum rtx_code, machine_mode,
460	rtx *, rtx *);
461	static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
462	static void update_table_tick (rtx);
463	static void record_value_for_reg (rtx, rtx_insn *, rtx);
464	static void check_promoted_subreg (rtx_insn *, rtx);
465	static void record_dead_and_set_regs_1 (rtx, const_rtx, void *);
466	static void record_dead_and_set_regs (rtx_insn *);
467	static bool get_last_value_validate (rtx *, rtx_insn *, int, bool);
468	static rtx get_last_value (const_rtx);
469	static void reg_dead_at_p_1 (rtx, const_rtx, void *);
470	static bool reg_dead_at_p (rtx, rtx_insn *);
471	static void move_deaths (rtx, rtx, int, rtx_insn *, rtx *);
472	static bool reg_bitfield_target_p (rtx, rtx);
473	static void distribute_notes (rtx, rtx_insn *, rtx_insn *, rtx_insn *,
474	rtx, rtx, rtx);
475	static void distribute_links (struct insn_link *);
476	static void mark_used_regs_combine (rtx);
477	static void record_promoted_value (rtx_insn *, rtx);
478	static bool unmentioned_reg_p (rtx, rtx);
479	static void record_truncated_values (rtx *, void *);
480	static bool reg_truncated_to_mode (machine_mode, const_rtx);
481	static rtx gen_lowpart_or_truncate (machine_mode, rtx);
482
483
484	/* It is not safe to use ordinary gen_lowpart in combine.
485	See comments in gen_lowpart_for_combine. */
486	#undef RTL_HOOKS_GEN_LOWPART
487	#define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
488
489	/* Our implementation of gen_lowpart never emits a new pseudo. */
490	#undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
491	#define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
492
493	#undef RTL_HOOKS_REG_NONZERO_REG_BITS
494	#define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
495
496	#undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
497	#define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
498
499	#undef RTL_HOOKS_REG_TRUNCATED_TO_MODE
500	#define RTL_HOOKS_REG_TRUNCATED_TO_MODE reg_truncated_to_mode
501
502	static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
503
504
505	/* Convenience wrapper for the canonicalize_comparison target hook.
506	Target hooks cannot use enum rtx_code. */
507	static inline void
508	target_canonicalize_comparison (enum rtx_code *code, rtx *op0, rtx *op1,
509	bool op0_preserve_value)
510	{
511	int code_int = (int)*code;
512	targetm.canonicalize_comparison (&code_int, op0, op1, op0_preserve_value);
513	*code = (enum rtx_code)code_int;
514	}
515
516	/* Try to split PATTERN found in INSN. This returns NULL_RTX if
517	PATTERN cannot be split. Otherwise, it returns an insn sequence.
518	This is a wrapper around split_insns which ensures that the
519	reg_stat vector is made larger if the splitter creates a new
520	register. */
521
522	static rtx_insn *
523	combine_split_insns (rtx pattern, rtx_insn *insn)
524	{
525	rtx_insn *ret;
526	unsigned int nregs;
527
528	ret = split_insns (pattern, insn);
529	nregs = max_reg_num ();
530	if (nregs > reg_stat.length ())
531	reg_stat.safe_grow_cleared (len: nregs, exact: true);
532	return ret;
533	}
534
535	/* This is used by find_single_use to locate an rtx in LOC that
536	contains exactly one use of DEST, which is typically a REG.
537	It returns a pointer to the innermost rtx expression
538	containing DEST. Appearances of DEST that are being used to
539	totally replace it are not counted. */
540
541	static rtx *
542	find_single_use_1 (rtx dest, rtx *loc)
543	{
544	rtx x = *loc;
545	enum rtx_code code = GET_CODE (x);
546	rtx *result = NULL;
547	rtx *this_result;
548	int i;
549	const char *fmt;
550
551	switch (code)
552	{
553	case CONST:
554	case LABEL_REF:
555	case SYMBOL_REF:
556	CASE_CONST_ANY:
557	case CLOBBER:
558	return 0;
559
560	case SET:
561	/* If the destination is anything other than PC, a REG or a SUBREG
562	of a REG that occupies all of the REG, the insn uses DEST if
563	it is mentioned in the destination or the source. Otherwise, we
564	need just check the source. */
565	if (GET_CODE (SET_DEST (x)) != PC
566	&& !REG_P (SET_DEST (x))
567	&& ! (GET_CODE (SET_DEST (x)) == SUBREG
568	&& REG_P (SUBREG_REG (SET_DEST (x)))
569	&& !read_modify_subreg_p (SET_DEST (x))))
570	break;
571
572	return find_single_use_1 (dest, loc: &SET_SRC (x));
573
574	case MEM:
575	case SUBREG:
576	return find_single_use_1 (dest, loc: &XEXP (x, 0));
577
578	default:
579	break;
580	}
581
582	/* If it wasn't one of the common cases above, check each expression and
583	vector of this code. Look for a unique usage of DEST. */
584
585	fmt = GET_RTX_FORMAT (code);
586	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
587	{
588	if (fmt[i] == 'e')
589	{
590	if (dest == XEXP (x, i)
591	|| (REG_P (dest) && REG_P (XEXP (x, i))
592	&& REGNO (dest) == REGNO (XEXP (x, i))))
593	this_result = loc;
594	else
595	this_result = find_single_use_1 (dest, loc: &XEXP (x, i));
596
597	if (result == NULL)
598	result = this_result;
599	else if (this_result)
600	/* Duplicate usage. */
601	return NULL;
602	}
603	else if (fmt[i] == 'E')
604	{
605	int j;
606
607	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
608	{
609	if (XVECEXP (x, i, j) == dest
610	|| (REG_P (dest)
611	&& REG_P (XVECEXP (x, i, j))
612	&& REGNO (XVECEXP (x, i, j)) == REGNO (dest)))
613	this_result = loc;
614	else
615	this_result = find_single_use_1 (dest, loc: &XVECEXP (x, i, j));
616
617	if (result == NULL)
618	result = this_result;
619	else if (this_result)
620	return NULL;
621	}
622	}
623	}
624
625	return result;
626	}
627
628
629	/* See if DEST, produced in INSN, is used only a single time in the
630	sequel. If so, return a pointer to the innermost rtx expression in which
631	it is used.
632
633	If PLOC is nonzero, *PLOC is set to the insn containing the single use.
634
635	Otherwise, we find the single use by finding an insn that has a
636	LOG_LINKS pointing at INSN and has a REG_DEAD note for DEST. If DEST is
637	only referenced once in that insn, we know that it must be the first
638	and last insn referencing DEST. */
639
640	static rtx *
641	find_single_use (rtx dest, rtx_insn *insn, rtx_insn **ploc)
642	{
643	basic_block bb;
644	rtx_insn *next;
645	rtx *result;
646	struct insn_link *link;
647
648	if (!REG_P (dest))
649	return 0;
650
651	bb = BLOCK_FOR_INSN (insn);
652	for (next = NEXT_INSN (insn);
653	next && BLOCK_FOR_INSN (insn: next) == bb;
654	next = NEXT_INSN (insn: next))
655	if (NONDEBUG_INSN_P (next) && dead_or_set_p (next, dest))
656	{
657	FOR_EACH_LOG_LINK (link, next)
658	if (link->insn == insn && link->regno == REGNO (dest))
659	break;
660
661	if (link)
662	{
663	result = find_single_use_1 (dest, loc: &PATTERN (insn: next));
664	if (ploc)
665	*ploc = next;
666	return result;
667	}
668	}
669
670	return 0;
671	}
672
673	/* Substitute NEWVAL, an rtx expression, into INTO, a place in some
674	insn. The substitution can be undone by undo_all. If INTO is already
675	set to NEWVAL, do not record this change. Because computing NEWVAL might
676	also call SUBST, we have to compute it before we put anything into
677	the undo table. */
678
679	static void
680	do_SUBST (rtx *into, rtx newval)
681	{
682	struct undo *buf;
683	rtx oldval = *into;
684
685	if (oldval == newval)
686	return;
687
688	/* We'd like to catch as many invalid transformations here as
689	possible. Unfortunately, there are way too many mode changes
690	that are perfectly valid, so we'd waste too much effort for
691	little gain doing the checks here. Focus on catching invalid
692	transformations involving integer constants. */
693	if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
694	&& CONST_INT_P (newval))
695	{
696	/* Sanity check that we're replacing oldval with a CONST_INT
697	that is a valid sign-extension for the original mode. */
698	gcc_assert (INTVAL (newval)
699	== trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
700
701	/* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
702	CONST_INT is not valid, because after the replacement, the
703	original mode would be gone. Unfortunately, we can't tell
704	when do_SUBST is called to replace the operand thereof, so we
705	perform this test on oldval instead, checking whether an
706	invalid replacement took place before we got here. */
707	gcc_assert (!(GET_CODE (oldval) == SUBREG
708	&& CONST_INT_P (SUBREG_REG (oldval))));
709	gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
710	&& CONST_INT_P (XEXP (oldval, 0))));
711	}
712
713	if (undobuf.frees)
714	buf = undobuf.frees, undobuf.frees = buf->next;
715	else
716	buf = XNEW (struct undo);
717
718	buf->kind = UNDO_RTX;
719	buf->where.r = into;
720	buf->old_contents.r = oldval;
721	*into = newval;
722
723	buf->next = undobuf.undos, undobuf.undos = buf;
724	}
725
726	#define SUBST(INTO, NEWVAL) do_SUBST (&(INTO), (NEWVAL))
727
728	/* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
729	for the value of a HOST_WIDE_INT value (including CONST_INT) is
730	not safe. */
731
732	static void
733	do_SUBST_INT (int *into, int newval)
734	{
735	struct undo *buf;
736	int oldval = *into;
737
738	if (oldval == newval)
739	return;
740
741	if (undobuf.frees)
742	buf = undobuf.frees, undobuf.frees = buf->next;
743	else
744	buf = XNEW (struct undo);
745
746	buf->kind = UNDO_INT;
747	buf->where.i = into;
748	buf->old_contents.i = oldval;
749	*into = newval;
750
751	buf->next = undobuf.undos, undobuf.undos = buf;
752	}
753
754	#define SUBST_INT(INTO, NEWVAL) do_SUBST_INT (&(INTO), (NEWVAL))
755
756	/* Similar to SUBST, but just substitute the mode. This is used when
757	changing the mode of a pseudo-register, so that any other
758	references to the entry in the regno_reg_rtx array will change as
759	well. */
760
761	static void
762	subst_mode (int regno, machine_mode newval)
763	{
764	struct undo *buf;
765	rtx reg = regno_reg_rtx[regno];
766	machine_mode oldval = GET_MODE (reg);
767
768	if (oldval == newval)
769	return;
770
771	if (undobuf.frees)
772	buf = undobuf.frees, undobuf.frees = buf->next;
773	else
774	buf = XNEW (struct undo);
775
776	buf->kind = UNDO_MODE;
777	buf->where.regno = regno;
778	buf->old_contents.m = oldval;
779	adjust_reg_mode (reg, newval);
780
781	buf->next = undobuf.undos, undobuf.undos = buf;
782	}
783
784	/* Similar to SUBST, but NEWVAL is a LOG_LINKS expression. */
785
786	static void
787	do_SUBST_LINK (struct insn_link **into, struct insn_link *newval)
788	{
789	struct undo *buf;
790	struct insn_link * oldval = *into;
791
792	if (oldval == newval)
793	return;
794
795	if (undobuf.frees)
796	buf = undobuf.frees, undobuf.frees = buf->next;
797	else
798	buf = XNEW (struct undo);
799
800	buf->kind = UNDO_LINKS;
801	buf->where.l = into;
802	buf->old_contents.l = oldval;
803	*into = newval;
804
805	buf->next = undobuf.undos, undobuf.undos = buf;
806	}
807
808	#define SUBST_LINK(oldval, newval) do_SUBST_LINK (&oldval, newval)
809
810	/* Subroutine of try_combine. Determine whether the replacement patterns
811	NEWPAT, NEWI2PAT and NEWOTHERPAT are cheaper according to insn_cost
812	than the original sequence I0, I1, I2, I3 and undobuf.other_insn. Note
813	that I0, I1 and/or NEWI2PAT may be NULL_RTX. Similarly, NEWOTHERPAT and
814	undobuf.other_insn may also both be NULL_RTX. Return false if the cost
815	of all the instructions can be estimated and the replacements are more
816	expensive than the original sequence. */
817
818	static bool
819	combine_validate_cost (rtx_insn *i0, rtx_insn *i1, rtx_insn *i2, rtx_insn *i3,
820	rtx newpat, rtx newi2pat, rtx newotherpat)
821	{
822	int i0_cost, i1_cost, i2_cost, i3_cost;
823	int new_i2_cost, new_i3_cost;
824	int old_cost, new_cost;
825
826	/* Lookup the original insn_costs. */
827	i2_cost = INSN_COST (i2);
828	i3_cost = INSN_COST (i3);
829
830	if (i1)
831	{
832	i1_cost = INSN_COST (i1);
833	if (i0)
834	{
835	i0_cost = INSN_COST (i0);
836	old_cost = (i0_cost > 0 && i1_cost > 0 && i2_cost > 0 && i3_cost > 0
837	? i0_cost + i1_cost + i2_cost + i3_cost : 0);
838	}
839	else
840	{
841	old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0
842	? i1_cost + i2_cost + i3_cost : 0);
843	i0_cost = 0;
844	}
845	}
846	else
847	{
848	old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
849	i1_cost = i0_cost = 0;
850	}
851
852	/* If we have split a PARALLEL I2 to I1,I2, we have counted its cost twice;
853	correct that. */
854	if (old_cost && i1 && INSN_UID (insn: i1) == INSN_UID (insn: i2))
855	old_cost -= i1_cost;
856
857
858	/* Calculate the replacement insn_costs. */
859	rtx tmp = PATTERN (insn: i3);
860	PATTERN (insn: i3) = newpat;
861	int tmpi = INSN_CODE (i3);
862	INSN_CODE (i3) = -1;
863	new_i3_cost = insn_cost (i3, optimize_this_for_speed_p);
864	PATTERN (insn: i3) = tmp;
865	INSN_CODE (i3) = tmpi;
866	if (newi2pat)
867	{
868	tmp = PATTERN (insn: i2);
869	PATTERN (insn: i2) = newi2pat;
870	tmpi = INSN_CODE (i2);
871	INSN_CODE (i2) = -1;
872	new_i2_cost = insn_cost (i2, optimize_this_for_speed_p);
873	PATTERN (insn: i2) = tmp;
874	INSN_CODE (i2) = tmpi;
875	new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
876	? new_i2_cost + new_i3_cost : 0;
877	}
878	else
879	{
880	new_cost = new_i3_cost;
881	new_i2_cost = 0;
882	}
883
884	if (undobuf.other_insn)
885	{
886	int old_other_cost, new_other_cost;
887
888	old_other_cost = INSN_COST (undobuf.other_insn);
889	tmp = PATTERN (insn: undobuf.other_insn);
890	PATTERN (insn: undobuf.other_insn) = newotherpat;
891	tmpi = INSN_CODE (undobuf.other_insn);
892	INSN_CODE (undobuf.other_insn) = -1;
893	new_other_cost = insn_cost (undobuf.other_insn,
894	optimize_this_for_speed_p);
895	PATTERN (insn: undobuf.other_insn) = tmp;
896	INSN_CODE (undobuf.other_insn) = tmpi;
897	if (old_other_cost > 0 && new_other_cost > 0)
898	{
899	old_cost += old_other_cost;
900	new_cost += new_other_cost;
901	}
902	else
903	old_cost = 0;
904	}
905
906	/* Disallow this combination if both new_cost and old_cost are greater than
907	zero, and new_cost is greater than old cost. */
908	bool reject = old_cost > 0 && new_cost > old_cost;
909
910	if (dump_file)
911	{
912	fprintf (stream: dump_file, format: "%s combination of insns ",
913	reject ? "rejecting" : "allowing");
914	if (i0)
915	fprintf (stream: dump_file, format: "%d, ", INSN_UID (insn: i0));
916	if (i1 && INSN_UID (insn: i1) != INSN_UID (insn: i2))
917	fprintf (stream: dump_file, format: "%d, ", INSN_UID (insn: i1));
918	fprintf (stream: dump_file, format: "%d and %d\n", INSN_UID (insn: i2), INSN_UID (insn: i3));
919
920	fprintf (stream: dump_file, format: "original costs ");
921	if (i0)
922	fprintf (stream: dump_file, format: "%d + ", i0_cost);
923	if (i1 && INSN_UID (insn: i1) != INSN_UID (insn: i2))
924	fprintf (stream: dump_file, format: "%d + ", i1_cost);
925	fprintf (stream: dump_file, format: "%d + %d = %d\n", i2_cost, i3_cost, old_cost);
926
927	if (newi2pat)
928	fprintf (stream: dump_file, format: "replacement costs %d + %d = %d\n",
929	new_i2_cost, new_i3_cost, new_cost);
930	else
931	fprintf (stream: dump_file, format: "replacement cost %d\n", new_cost);
932	}
933
934	if (reject)
935	return false;
936
937	/* Update the uid_insn_cost array with the replacement costs. */
938	INSN_COST (i2) = new_i2_cost;
939	INSN_COST (i3) = new_i3_cost;
940	if (i1)
941	{
942	INSN_COST (i1) = 0;
943	if (i0)
944	INSN_COST (i0) = 0;
945	}
946
947	return true;
948	}
949
950
951	/* Delete any insns that copy a register to itself.
952	Return true if the CFG was changed. */
953
954	static bool
955	delete_noop_moves (void)
956	{
957	rtx_insn *insn, *next;
958	basic_block bb;
959
960	bool edges_deleted = false;
961
962	FOR_EACH_BB_FN (bb, cfun)
963	{
964	for (insn = BB_HEAD (bb); insn != NEXT_INSN (BB_END (bb)); insn = next)
965	{
966	next = NEXT_INSN (insn);
967	if (INSN_P (insn) && noop_move_p (insn))
968	{
969	if (dump_file)
970	fprintf (stream: dump_file, format: "deleting noop move %d\n", INSN_UID (insn));
971
972	edges_deleted |= delete_insn_and_edges (insn);
973	}
974	}
975	}
976
977	return edges_deleted;
978	}
979
980
981	/* Return false if we do not want to (or cannot) combine DEF. */
982	static bool
983	can_combine_def_p (df_ref def)
984	{
985	/* Do not consider if it is pre/post modification in MEM. */
986	if (DF_REF_FLAGS (def) & DF_REF_PRE_POST_MODIFY)
987	return false;
988
989	unsigned int regno = DF_REF_REGNO (def);
990
991	/* Do not combine frame pointer adjustments. */
992	if ((regno == FRAME_POINTER_REGNUM
993	&& (!reload_completed || frame_pointer_needed))
994	|| (!HARD_FRAME_POINTER_IS_FRAME_POINTER
995	&& regno == HARD_FRAME_POINTER_REGNUM
996	&& (!reload_completed || frame_pointer_needed))
997	|| (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
998	&& regno == ARG_POINTER_REGNUM && fixed_regs[regno]))
999	return false;
1000
1001	return true;
1002	}
1003
1004	/* Return false if we do not want to (or cannot) combine USE. */
1005	static bool
1006	can_combine_use_p (df_ref use)
1007	{
1008	/* Do not consider the usage of the stack pointer by function call. */
1009	if (DF_REF_FLAGS (use) & DF_REF_CALL_STACK_USAGE)
1010	return false;
1011
1012	return true;
1013	}
1014
1015	/* Fill in log links field for all insns. */
1016
1017	static void
1018	create_log_links (void)
1019	{
1020	basic_block bb;
1021	rtx_insn **next_use;
1022	rtx_insn *insn;
1023	df_ref def, use;
1024
1025	next_use = XCNEWVEC (rtx_insn *, max_reg_num ());
1026
1027	/* Pass through each block from the end, recording the uses of each
1028	register and establishing log links when def is encountered.
1029	Note that we do not clear next_use array in order to save time,
1030	so we have to test whether the use is in the same basic block as def.
1031
1032	There are a few cases below when we do not consider the definition or
1033	usage -- these are taken from original flow.c did. Don't ask me why it is
1034	done this way; I don't know and if it works, I don't want to know. */
1035
1036	FOR_EACH_BB_FN (bb, cfun)
1037	{
1038	FOR_BB_INSNS_REVERSE (bb, insn)
1039	{
1040	if (!NONDEBUG_INSN_P (insn))
1041	continue;
1042
1043	/* Log links are created only once. */
1044	gcc_assert (!LOG_LINKS (insn));
1045
1046	FOR_EACH_INSN_DEF (def, insn)
1047	{
1048	unsigned int regno = DF_REF_REGNO (def);
1049	rtx_insn *use_insn;
1050
1051	if (!next_use[regno])
1052	continue;
1053
1054	if (!can_combine_def_p (def))
1055	continue;
1056
1057	use_insn = next_use[regno];
1058	next_use[regno] = NULL;
1059
1060	if (BLOCK_FOR_INSN (insn: use_insn) != bb)
1061	continue;
1062
1063	/* flow.c claimed:
1064
1065	We don't build a LOG_LINK for hard registers contained
1066	in ASM_OPERANDs. If these registers get replaced,
1067	we might wind up changing the semantics of the insn,
1068	even if reload can make what appear to be valid
1069	assignments later. */
1070	if (regno < FIRST_PSEUDO_REGISTER
1071	&& asm_noperands (PATTERN (insn: use_insn)) >= 0)
1072	continue;
1073
1074	/* Don't add duplicate links between instructions. */
1075	struct insn_link *links;
1076	FOR_EACH_LOG_LINK (links, use_insn)
1077	if (insn == links->insn && regno == links->regno)
1078	break;
1079
1080	if (!links)
1081	LOG_LINKS (use_insn)
1082	= alloc_insn_link (insn, regno, LOG_LINKS (use_insn));
1083	}
1084
1085	FOR_EACH_INSN_USE (use, insn)
1086	if (can_combine_use_p (use))
1087	next_use[DF_REF_REGNO (use)] = insn;
1088	}
1089	}
1090
1091	free (ptr: next_use);
1092	}
1093
1094	/* Walk the LOG_LINKS of insn B to see if we find a reference to A. Return
1095	true if we found a LOG_LINK that proves that A feeds B. This only works
1096	if there are no instructions between A and B which could have a link
1097	depending on A, since in that case we would not record a link for B. */
1098
1099	static bool
1100	insn_a_feeds_b (rtx_insn *a, rtx_insn *b)
1101	{
1102	struct insn_link *links;
1103	FOR_EACH_LOG_LINK (links, b)
1104	if (links->insn == a)
1105	return true;
1106	return false;
1107	}
1108
1109	/* Main entry point for combiner. F is the first insn of the function.
1110	NREGS is the first unused pseudo-reg number.
1111
1112	Return nonzero if the CFG was changed (e.g. if the combiner has
1113	turned an indirect jump instruction into a direct jump). */
1114	static bool
1115	combine_instructions (rtx_insn *f, unsigned int nregs)
1116	{
1117	rtx_insn *insn, *next;
1118	struct insn_link *links, *nextlinks;
1119	rtx_insn *first;
1120	basic_block last_bb;
1121
1122	bool new_direct_jump_p = false;
1123
1124	for (first = f; first && !NONDEBUG_INSN_P (first); )
1125	first = NEXT_INSN (insn: first);
1126	if (!first)
1127	return false;
1128
1129	combine_attempts = 0;
1130	combine_merges = 0;
1131	combine_extras = 0;
1132	combine_successes = 0;
1133
1134	rtl_hooks = combine_rtl_hooks;
1135
1136	reg_stat.safe_grow_cleared (len: nregs, exact: true);
1137
1138	init_recog_no_volatile ();
1139
1140	/* Allocate array for insn info. */
1141	max_uid_known = get_max_uid ();
1142	uid_log_links = XCNEWVEC (struct insn_link *, max_uid_known + 1);
1143	uid_insn_cost = XCNEWVEC (int, max_uid_known + 1);
1144	gcc_obstack_init (&insn_link_obstack);
1145
1146	nonzero_bits_mode = int_mode_for_size (HOST_BITS_PER_WIDE_INT, limit: 0).require ();
1147
1148	/* Don't use reg_stat[].nonzero_bits when computing it. This can cause
1149	problems when, for example, we have j <<= 1 in a loop. */
1150
1151	nonzero_sign_valid = 0;
1152	label_tick = label_tick_ebb_start = 1;
1153
1154	/* Scan all SETs and see if we can deduce anything about what
1155	bits are known to be zero for some registers and how many copies
1156	of the sign bit are known to exist for those registers.
1157
1158	Also set any known values so that we can use it while searching
1159	for what bits are known to be set. */
1160
1161	setup_incoming_promotions (first);
1162	/* Allow the entry block and the first block to fall into the same EBB.
1163	Conceptually the incoming promotions are assigned to the entry block. */
1164	last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1165
1166	create_log_links ();
1167	FOR_EACH_BB_FN (this_basic_block, cfun)
1168	{
1169	optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1170	last_call_luid = 0;
1171	mem_last_set = -1;
1172
1173	label_tick++;
1174	if (!single_pred_p (bb: this_basic_block)
1175	|| single_pred (bb: this_basic_block) != last_bb)
1176	label_tick_ebb_start = label_tick;
1177	last_bb = this_basic_block;
1178
1179	FOR_BB_INSNS (this_basic_block, insn)
1180	if (INSN_P (insn) && BLOCK_FOR_INSN (insn))
1181	{
1182	rtx links;
1183
1184	subst_low_luid = DF_INSN_LUID (insn);
1185	subst_insn = insn;
1186
1187	note_stores (insn, set_nonzero_bits_and_sign_copies, insn);
1188	record_dead_and_set_regs (insn);
1189
1190	if (AUTO_INC_DEC)
1191	for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
1192	if (REG_NOTE_KIND (links) == REG_INC)
1193	set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
1194	insn);
1195
1196	/* Record the current insn_cost of this instruction. */
1197	INSN_COST (insn) = insn_cost (insn, optimize_this_for_speed_p);
1198	if (dump_file)
1199	{
1200	fprintf (stream: dump_file, format: "insn_cost %d for ", INSN_COST (insn));
1201	dump_insn_slim (dump_file, insn);
1202	}
1203	}
1204	}
1205
1206	nonzero_sign_valid = 1;
1207
1208	/* Now scan all the insns in forward order. */
1209	label_tick = label_tick_ebb_start = 1;
1210	init_reg_last ();
1211	setup_incoming_promotions (first);
1212	last_bb = ENTRY_BLOCK_PTR_FOR_FN (cfun);
1213	int max_combine = param_max_combine_insns;
1214
1215	FOR_EACH_BB_FN (this_basic_block, cfun)
1216	{
1217	rtx_insn *last_combined_insn = NULL;
1218
1219	/* Ignore instruction combination in basic blocks that are going to
1220	be removed as unreachable anyway. See PR82386. */
1221	if (EDGE_COUNT (this_basic_block->preds) == 0)
1222	continue;
1223
1224	optimize_this_for_speed_p = optimize_bb_for_speed_p (this_basic_block);
1225	last_call_luid = 0;
1226	mem_last_set = -1;
1227
1228	label_tick++;
1229	if (!single_pred_p (bb: this_basic_block)
1230	|| single_pred (bb: this_basic_block) != last_bb)
1231	label_tick_ebb_start = label_tick;
1232	last_bb = this_basic_block;
1233
1234	rtl_profile_for_bb (this_basic_block);
1235	for (insn = BB_HEAD (this_basic_block);
1236	insn != NEXT_INSN (BB_END (this_basic_block));
1237	insn = next ? next : NEXT_INSN (insn))
1238	{
1239	next = 0;
1240	if (!NONDEBUG_INSN_P (insn))
1241	continue;
1242
1243	while (last_combined_insn
1244	&& (!NONDEBUG_INSN_P (last_combined_insn)
1245	|| last_combined_insn->deleted ()))
1246	last_combined_insn = PREV_INSN (insn: last_combined_insn);
1247	if (last_combined_insn == NULL_RTX
1248	|| BLOCK_FOR_INSN (insn: last_combined_insn) != this_basic_block
1249	|| DF_INSN_LUID (last_combined_insn) <= DF_INSN_LUID (insn))
1250	last_combined_insn = insn;
1251
1252	/* See if we know about function return values before this
1253	insn based upon SUBREG flags. */
1254	check_promoted_subreg (insn, PATTERN (insn));
1255
1256	/* See if we can find hardregs and subreg of pseudos in
1257	narrower modes. This could help turning TRUNCATEs
1258	into SUBREGs. */
1259	note_uses (&PATTERN (insn), record_truncated_values, NULL);
1260
1261	/* Try this insn with each insn it links back to. */
1262
1263	FOR_EACH_LOG_LINK (links, insn)
1264	if ((next = try_combine (insn, links->insn, NULL,
1265	NULL, &new_direct_jump_p,
1266	last_combined_insn)) != 0)
1267	{
1268	statistics_counter_event (cfun, "two-insn combine", 1);
1269	goto retry;
1270	}
1271
1272	/* Try each sequence of three linked insns ending with this one. */
1273
1274	if (max_combine >= 3)
1275	FOR_EACH_LOG_LINK (links, insn)
1276	{
1277	rtx_insn *link = links->insn;
1278
1279	/* If the linked insn has been replaced by a note, then there
1280	is no point in pursuing this chain any further. */
1281	if (NOTE_P (link))
1282	continue;
1283
1284	FOR_EACH_LOG_LINK (nextlinks, link)
1285	if ((next = try_combine (insn, link, nextlinks->insn,
1286	NULL, &new_direct_jump_p,
1287	last_combined_insn)) != 0)
1288	{
1289	statistics_counter_event (cfun, "three-insn combine", 1);
1290	goto retry;
1291	}
1292	}
1293
1294	/* Try combining an insn with two different insns whose results it
1295	uses. */
1296	if (max_combine >= 3)
1297	FOR_EACH_LOG_LINK (links, insn)
1298	for (nextlinks = links->next; nextlinks;
1299	nextlinks = nextlinks->next)
1300	if ((next = try_combine (insn, links->insn,
1301	nextlinks->insn, NULL,
1302	&new_direct_jump_p,
1303	last_combined_insn)) != 0)
1304
1305	{
1306	statistics_counter_event (cfun, "three-insn combine", 1);
1307	goto retry;
1308	}
1309
1310	/* Try four-instruction combinations. */
1311	if (max_combine >= 4)
1312	FOR_EACH_LOG_LINK (links, insn)
1313	{
1314	struct insn_link *next1;
1315	rtx_insn *link = links->insn;
1316
1317	/* If the linked insn has been replaced by a note, then there
1318	is no point in pursuing this chain any further. */
1319	if (NOTE_P (link))
1320	continue;
1321
1322	FOR_EACH_LOG_LINK (next1, link)
1323	{
1324	rtx_insn *link1 = next1->insn;
1325	if (NOTE_P (link1))
1326	continue;
1327	/* I0 -> I1 -> I2 -> I3. */
1328	FOR_EACH_LOG_LINK (nextlinks, link1)
1329	if ((next = try_combine (insn, link, link1,
1330	nextlinks->insn,
1331	&new_direct_jump_p,
1332	last_combined_insn)) != 0)
1333	{
1334	statistics_counter_event (cfun, "four-insn combine", 1);
1335	goto retry;
1336	}
1337	/* I0, I1 -> I2, I2 -> I3. */
1338	for (nextlinks = next1->next; nextlinks;
1339	nextlinks = nextlinks->next)
1340	if ((next = try_combine (insn, link, link1,
1341	nextlinks->insn,
1342	&new_direct_jump_p,
1343	last_combined_insn)) != 0)
1344	{
1345	statistics_counter_event (cfun, "four-insn combine", 1);
1346	goto retry;
1347	}
1348	}
1349
1350	for (next1 = links->next; next1; next1 = next1->next)
1351	{
1352	rtx_insn *link1 = next1->insn;
1353	if (NOTE_P (link1))
1354	continue;
1355	/* I0 -> I2; I1, I2 -> I3. */
1356	FOR_EACH_LOG_LINK (nextlinks, link)
1357	if ((next = try_combine (insn, link, link1,
1358	nextlinks->insn,
1359	&new_direct_jump_p,
1360	last_combined_insn)) != 0)
1361	{
1362	statistics_counter_event (cfun, "four-insn combine", 1);
1363	goto retry;
1364	}
1365	/* I0 -> I1; I1, I2 -> I3. */
1366	FOR_EACH_LOG_LINK (nextlinks, link1)
1367	if ((next = try_combine (insn, link, link1,
1368	nextlinks->insn,
1369	&new_direct_jump_p,
1370	last_combined_insn)) != 0)
1371	{
1372	statistics_counter_event (cfun, "four-insn combine", 1);
1373	goto retry;
1374	}
1375	}
1376	}
1377
1378	/* Try this insn with each REG_EQUAL note it links back to. */
1379	FOR_EACH_LOG_LINK (links, insn)
1380	{
1381	rtx set, note;
1382	rtx_insn *temp = links->insn;
1383	if ((set = single_set (insn: temp)) != 0
1384	&& (note = find_reg_equal_equiv_note (temp)) != 0
1385	&& (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
1386	&& ! side_effects_p (SET_SRC (set))
1387	/* Avoid using a register that may already been marked
1388	dead by an earlier instruction. */
1389	&& ! unmentioned_reg_p (note, SET_SRC (set))
1390	&& (GET_MODE (note) == VOIDmode
1391	? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
1392	: (GET_MODE (SET_DEST (set)) == GET_MODE (note)
1393	&& (GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
1394	|| (GET_MODE (XEXP (SET_DEST (set), 0))
1395	== GET_MODE (note))))))
1396	{
1397	/* Temporarily replace the set's source with the
1398	contents of the REG_EQUAL note. The insn will
1399	be deleted or recognized by try_combine. */
1400	rtx orig_src = SET_SRC (set);
1401	rtx orig_dest = SET_DEST (set);
1402	if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT)
1403	SET_DEST (set) = XEXP (SET_DEST (set), 0);
1404	SET_SRC (set) = note;
1405	i2mod = temp;
1406	i2mod_old_rhs = copy_rtx (orig_src);
1407	i2mod_new_rhs = copy_rtx (note);
1408	next = try_combine (insn, i2mod, NULL, NULL,
1409	&new_direct_jump_p,
1410	last_combined_insn);
1411	i2mod = NULL;
1412	if (next)
1413	{
1414	statistics_counter_event (cfun, "insn-with-note combine", 1);
1415	goto retry;
1416	}
1417	INSN_CODE (temp) = -1;
1418	SET_SRC (set) = orig_src;
1419	SET_DEST (set) = orig_dest;
1420	}
1421	}
1422
1423	if (!NOTE_P (insn))
1424	record_dead_and_set_regs (insn);
1425
1426	retry:
1427	;
1428	}
1429	}
1430
1431	default_rtl_profile ();
1432	clear_bb_flags ();
1433
1434	if (purge_all_dead_edges ())
1435	new_direct_jump_p = true;
1436	if (delete_noop_moves ())
1437	new_direct_jump_p = true;
1438
1439	/* Clean up. */
1440	obstack_free (&insn_link_obstack, NULL);
1441	free (ptr: uid_log_links);
1442	free (ptr: uid_insn_cost);
1443	reg_stat.release ();
1444
1445	{
1446	struct undo *undo, *next;
1447	for (undo = undobuf.frees; undo; undo = next)
1448	{
1449	next = undo->next;
1450	free (ptr: undo);
1451	}
1452	undobuf.frees = 0;
1453	}
1454
1455	statistics_counter_event (cfun, "attempts", combine_attempts);
1456	statistics_counter_event (cfun, "merges", combine_merges);
1457	statistics_counter_event (cfun, "extras", combine_extras);
1458	statistics_counter_event (cfun, "successes", combine_successes);
1459
1460	nonzero_sign_valid = 0;
1461	rtl_hooks = general_rtl_hooks;
1462
1463	/* Make recognizer allow volatile MEMs again. */
1464	init_recog ();
1465
1466	return new_direct_jump_p;
1467	}
1468
1469	/* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
1470
1471	static void
1472	init_reg_last (void)
1473	{
1474	unsigned int i;
1475	reg_stat_type *p;
1476
1477	FOR_EACH_VEC_ELT (reg_stat, i, p)
1478	memset (s: p, c: 0, offsetof (reg_stat_type, sign_bit_copies));
1479	}
1480
1481	/* Set up any promoted values for incoming argument registers. */
1482
1483	static void
1484	setup_incoming_promotions (rtx_insn *first)
1485	{
1486	tree arg;
1487	bool strictly_local = false;
1488
1489	for (arg = DECL_ARGUMENTS (current_function_decl); arg;
1490	arg = DECL_CHAIN (arg))
1491	{
1492	rtx x, reg = DECL_INCOMING_RTL (arg);
1493	int uns1, uns3;
1494	machine_mode mode1, mode2, mode3, mode4;
1495
1496	/* Only continue if the incoming argument is in a register. */
1497	if (!REG_P (reg))
1498	continue;
1499
1500	/* Determine, if possible, whether all call sites of the current
1501	function lie within the current compilation unit. (This does
1502	take into account the exporting of a function via taking its
1503	address, and so forth.) */
1504	strictly_local
1505	= cgraph_node::local_info_node (decl: current_function_decl)->local;
1506
1507	/* The mode and signedness of the argument before any promotions happen
1508	(equal to the mode of the pseudo holding it at that stage). */
1509	mode1 = TYPE_MODE (TREE_TYPE (arg));
1510	uns1 = TYPE_UNSIGNED (TREE_TYPE (arg));
1511
1512	/* The mode and signedness of the argument after any source language and
1513	TARGET_PROMOTE_PROTOTYPES-driven promotions. */
1514	mode2 = TYPE_MODE (DECL_ARG_TYPE (arg));
1515	uns3 = TYPE_UNSIGNED (DECL_ARG_TYPE (arg));
1516
1517	/* The mode and signedness of the argument as it is actually passed,
1518	see assign_parm_setup_reg in function.cc. */
1519	mode3 = promote_function_mode (TREE_TYPE (arg), mode1, &uns3,
1520	TREE_TYPE (cfun->decl), 0);
1521
1522	/* The mode of the register in which the argument is being passed. */
1523	mode4 = GET_MODE (reg);
1524
1525	/* Eliminate sign extensions in the callee when:
1526	(a) A mode promotion has occurred; */
1527	if (mode1 == mode3)
1528	continue;
1529	/* (b) The mode of the register is the same as the mode of
1530	the argument as it is passed; */
1531	if (mode3 != mode4)
1532	continue;
1533	/* (c) There's no language level extension; */
1534	if (mode1 == mode2)
1535	;
1536	/* (c.1) All callers are from the current compilation unit. If that's
1537	the case we don't have to rely on an ABI, we only have to know
1538	what we're generating right now, and we know that we will do the
1539	mode1 to mode2 promotion with the given sign. */
1540	else if (!strictly_local)
1541	continue;
1542	/* (c.2) The combination of the two promotions is useful. This is
1543	true when the signs match, or if the first promotion is unsigned.
1544	In the later case, (sign_extend (zero_extend x)) is the same as
1545	(zero_extend (zero_extend x)), so make sure to force UNS3 true. */
1546	else if (uns1)
1547	uns3 = true;
1548	else if (uns3)
1549	continue;
1550
1551	/* Record that the value was promoted from mode1 to mode3,
1552	so that any sign extension at the head of the current
1553	function may be eliminated. */
1554	x = gen_rtx_CLOBBER (mode1, const0_rtx);
1555	x = gen_rtx_fmt_e ((uns3 ? ZERO_EXTEND : SIGN_EXTEND), mode3, x);
1556	record_value_for_reg (reg, first, x);
1557	}
1558	}
1559
1560	/* If MODE has a precision lower than PREC and SRC is a non-negative constant
1561	that would appear negative in MODE, sign-extend SRC for use in nonzero_bits
1562	because some machines (maybe most) will actually do the sign-extension and
1563	this is the conservative approach.
1564
1565	??? For 2.5, try to tighten up the MD files in this regard instead of this
1566	kludge. */
1567
1568	static rtx
1569	sign_extend_short_imm (rtx src, machine_mode mode, unsigned int prec)
1570	{
1571	scalar_int_mode int_mode;
1572	if (CONST_INT_P (src)
1573	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
1574	&& GET_MODE_PRECISION (mode: int_mode) < prec
1575	&& INTVAL (src) > 0
1576	&& val_signbit_known_set_p (int_mode, INTVAL (src)))
1577	src = GEN_INT (INTVAL (src) | ~GET_MODE_MASK (int_mode));
1578
1579	return src;
1580	}
1581
1582	/* Update RSP for pseudo-register X from INSN's REG_EQUAL note (if one exists)
1583	and SET. */
1584
1585	static void
1586	update_rsp_from_reg_equal (reg_stat_type *rsp, rtx_insn *insn, const_rtx set,
1587	rtx x)
1588	{
1589	rtx reg_equal_note = insn ? find_reg_equal_equiv_note (insn) : NULL_RTX;
1590	unsigned HOST_WIDE_INT bits = 0;
1591	rtx reg_equal = NULL, src = SET_SRC (set);
1592	unsigned int num = 0;
1593
1594	if (reg_equal_note)
1595	reg_equal = XEXP (reg_equal_note, 0);
1596
1597	if (SHORT_IMMEDIATES_SIGN_EXTEND)
1598	{
1599	src = sign_extend_short_imm (src, GET_MODE (x), BITS_PER_WORD);
1600	if (reg_equal)
1601	reg_equal = sign_extend_short_imm (src: reg_equal, GET_MODE (x), BITS_PER_WORD);
1602	}
1603
1604	/* Don't call nonzero_bits if it cannot change anything. */
1605	if (rsp->nonzero_bits != HOST_WIDE_INT_M1U)
1606	{
1607	machine_mode mode = GET_MODE (x);
1608	if (GET_MODE_CLASS (mode) == MODE_INT
1609	&& HWI_COMPUTABLE_MODE_P (mode))
1610	mode = nonzero_bits_mode;
1611	bits = nonzero_bits (src, mode);
1612	if (reg_equal && bits)
1613	bits &= nonzero_bits (reg_equal, mode);
1614	rsp->nonzero_bits |= bits;
1615	}
1616
1617	/* Don't call num_sign_bit_copies if it cannot change anything. */
1618	if (rsp->sign_bit_copies != 1)
1619	{
1620	num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1621	if (reg_equal && maybe_ne (a: num, b: GET_MODE_PRECISION (GET_MODE (x))))
1622	{
1623	unsigned int numeq = num_sign_bit_copies (reg_equal, GET_MODE (x));
1624	if (num == 0 || numeq > num)
1625	num = numeq;
1626	}
1627	if (rsp->sign_bit_copies == 0 || num < rsp->sign_bit_copies)
1628	rsp->sign_bit_copies = num;
1629	}
1630	}
1631
1632	/* Called via note_stores. If X is a pseudo that is narrower than
1633	HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
1634
1635	If we are setting only a portion of X and we can't figure out what
1636	portion, assume all bits will be used since we don't know what will
1637	be happening.
1638
1639	Similarly, set how many bits of X are known to be copies of the sign bit
1640	at all locations in the function. This is the smallest number implied
1641	by any set of X. */
1642
1643	static void
1644	set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data)
1645	{
1646	rtx_insn *insn = (rtx_insn *) data;
1647	scalar_int_mode mode;
1648
1649	if (REG_P (x)
1650	&& REGNO (x) >= FIRST_PSEUDO_REGISTER
1651	/* If this register is undefined at the start of the file, we can't
1652	say what its contents were. */
1653	&& ! REGNO_REG_SET_P
1654	(DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), REGNO (x))
1655	&& is_a <scalar_int_mode> (GET_MODE (x), result: &mode)
1656	&& HWI_COMPUTABLE_MODE_P (mode))
1657	{
1658	reg_stat_type *rsp = &reg_stat[REGNO (x)];
1659
1660	if (set == 0 || GET_CODE (set) == CLOBBER)
1661	{
1662	rsp->nonzero_bits = GET_MODE_MASK (mode);
1663	rsp->sign_bit_copies = 1;
1664	return;
1665	}
1666
1667	/* If this register is being initialized using itself, and the
1668	register is uninitialized in this basic block, and there are
1669	no LOG_LINKS which set the register, then part of the
1670	register is uninitialized. In that case we can't assume
1671	anything about the number of nonzero bits.
1672
1673	??? We could do better if we checked this in
1674	reg_{nonzero_bits,num_sign_bit_copies}_for_combine. Then we
1675	could avoid making assumptions about the insn which initially
1676	sets the register, while still using the information in other
1677	insns. We would have to be careful to check every insn
1678	involved in the combination. */
1679
1680	if (insn
1681	&& reg_referenced_p (x, PATTERN (insn))
1682	&& !REGNO_REG_SET_P (DF_LR_IN (BLOCK_FOR_INSN (insn)),
1683	REGNO (x)))
1684	{
1685	struct insn_link *link;
1686
1687	FOR_EACH_LOG_LINK (link, insn)
1688	if (dead_or_set_p (link->insn, x))
1689	break;
1690	if (!link)
1691	{
1692	rsp->nonzero_bits = GET_MODE_MASK (mode);
1693	rsp->sign_bit_copies = 1;
1694	return;
1695	}
1696	}
1697
1698	/* If this is a complex assignment, see if we can convert it into a
1699	simple assignment. */
1700	set = expand_field_assignment (set);
1701
1702	/* If this is a simple assignment, or we have a paradoxical SUBREG,
1703	set what we know about X. */
1704
1705	if (SET_DEST (set) == x
1706	|| (paradoxical_subreg_p (SET_DEST (set))
1707	&& SUBREG_REG (SET_DEST (set)) == x))
1708	update_rsp_from_reg_equal (rsp, insn, set, x);
1709	else
1710	{
1711	rsp->nonzero_bits = GET_MODE_MASK (mode);
1712	rsp->sign_bit_copies = 1;
1713	}
1714	}
1715	}
1716
1717	/* See if INSN can be combined into I3. PRED, PRED2, SUCC and SUCC2 are
1718	optionally insns that were previously combined into I3 or that will be
1719	combined into the merger of INSN and I3. The order is PRED, PRED2,
1720	INSN, SUCC, SUCC2, I3.
1721
1722	Return false if the combination is not allowed for any reason.
1723
1724	If the combination is allowed, *PDEST will be set to the single
1725	destination of INSN and *PSRC to the single source, and this function
1726	will return true. */
1727
1728	static bool
1729	can_combine_p (rtx_insn *insn, rtx_insn *i3, rtx_insn *pred ATTRIBUTE_UNUSED,
1730	rtx_insn *pred2 ATTRIBUTE_UNUSED, rtx_insn *succ, rtx_insn *succ2,
1731	rtx *pdest, rtx *psrc)
1732	{
1733	int i;
1734	const_rtx set = 0;
1735	rtx src, dest;
1736	rtx_insn *p;
1737	rtx link;
1738	bool all_adjacent = true;
1739	bool (*is_volatile_p) (const_rtx);
1740
1741	if (succ)
1742	{
1743	if (succ2)
1744	{
1745	if (next_active_insn (succ2) != i3)
1746	all_adjacent = false;
1747	if (next_active_insn (succ) != succ2)
1748	all_adjacent = false;
1749	}
1750	else if (next_active_insn (succ) != i3)
1751	all_adjacent = false;
1752	if (next_active_insn (insn) != succ)
1753	all_adjacent = false;
1754	}
1755	else if (next_active_insn (insn) != i3)
1756	all_adjacent = false;
1757
1758	/* Can combine only if previous insn is a SET of a REG or a SUBREG,
1759	or a PARALLEL consisting of such a SET and CLOBBERs.
1760
1761	If INSN has CLOBBER parallel parts, ignore them for our processing.
1762	By definition, these happen during the execution of the insn. When it
1763	is merged with another insn, all bets are off. If they are, in fact,
1764	needed and aren't also supplied in I3, they may be added by
1765	recog_for_combine. Otherwise, it won't match.
1766
1767	We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1768	note.
1769
1770	Get the source and destination of INSN. If more than one, can't
1771	combine. */
1772
1773	if (GET_CODE (PATTERN (insn)) == SET)
1774	set = PATTERN (insn);
1775	else if (GET_CODE (PATTERN (insn)) == PARALLEL
1776	&& GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1777	{
1778	for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1779	{
1780	rtx elt = XVECEXP (PATTERN (insn), 0, i);
1781
1782	switch (GET_CODE (elt))
1783	{
1784	/* This is important to combine floating point insns
1785	for the SH4 port. */
1786	case USE:
1787	/* Combining an isolated USE doesn't make sense.
1788	We depend here on combinable_i3pat to reject them. */
1789	/* The code below this loop only verifies that the inputs of
1790	the SET in INSN do not change. We call reg_set_between_p
1791	to verify that the REG in the USE does not change between
1792	I3 and INSN.
1793	If the USE in INSN was for a pseudo register, the matching
1794	insn pattern will likely match any register; combining this
1795	with any other USE would only be safe if we knew that the
1796	used registers have identical values, or if there was
1797	something to tell them apart, e.g. different modes. For
1798	now, we forgo such complicated tests and simply disallow
1799	combining of USES of pseudo registers with any other USE. */
1800	if (REG_P (XEXP (elt, 0))
1801	&& GET_CODE (PATTERN (i3)) == PARALLEL)
1802	{
1803	rtx i3pat = PATTERN (insn: i3);
1804	int i = XVECLEN (i3pat, 0) - 1;
1805	unsigned int regno = REGNO (XEXP (elt, 0));
1806
1807	do
1808	{
1809	rtx i3elt = XVECEXP (i3pat, 0, i);
1810
1811	if (GET_CODE (i3elt) == USE
1812	&& REG_P (XEXP (i3elt, 0))
1813	&& (REGNO (XEXP (i3elt, 0)) == regno
1814	? reg_set_between_p (XEXP (elt, 0),
1815	PREV_INSN (insn), i3)
1816	: regno >= FIRST_PSEUDO_REGISTER))
1817	return false;
1818	}
1819	while (--i >= 0);
1820	}
1821	break;
1822
1823	/* We can ignore CLOBBERs. */
1824	case CLOBBER:
1825	break;
1826
1827	case SET:
1828	/* Ignore SETs whose result isn't used but not those that
1829	have side-effects. */
1830	if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1831	&& insn_nothrow_p (insn)
1832	&& !side_effects_p (elt))
1833	break;
1834
1835	/* If we have already found a SET, this is a second one and
1836	so we cannot combine with this insn. */
1837	if (set)
1838	return false;
1839
1840	set = elt;
1841	break;
1842
1843	default:
1844	/* Anything else means we can't combine. */
1845	return false;
1846	}
1847	}
1848
1849	if (set == 0
1850	/* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1851	so don't do anything with it. */
1852	|| GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1853	return false;
1854	}
1855	else
1856	return false;
1857
1858	if (set == 0)
1859	return false;
1860
1861	/* The simplification in expand_field_assignment may call back to
1862	get_last_value, so set safe guard here. */
1863	subst_low_luid = DF_INSN_LUID (insn);
1864
1865	set = expand_field_assignment (set);
1866	src = SET_SRC (set), dest = SET_DEST (set);
1867
1868	/* Do not eliminate user-specified register if it is in an
1869	asm input because we may break the register asm usage defined
1870	in GCC manual if allow to do so.
1871	Be aware that this may cover more cases than we expect but this
1872	should be harmless. */
1873	if (REG_P (dest) && REG_USERVAR_P (dest) && HARD_REGISTER_P (dest)
1874	&& extract_asm_operands (PATTERN (insn: i3)))
1875	return false;
1876
1877	/* Don't eliminate a store in the stack pointer. */
1878	if (dest == stack_pointer_rtx
1879	/* Don't combine with an insn that sets a register to itself if it has
1880	a REG_EQUAL note. This may be part of a LIBCALL sequence. */
1881	|| (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1882	/* Can't merge an ASM_OPERANDS. */
1883	|| GET_CODE (src) == ASM_OPERANDS
1884	/* Can't merge a function call. */
1885	|| GET_CODE (src) == CALL
1886	/* Don't eliminate a function call argument. */
1887	|| (CALL_P (i3)
1888	&& (find_reg_fusage (i3, USE, dest)
1889	|| (REG_P (dest)
1890	&& REGNO (dest) < FIRST_PSEUDO_REGISTER
1891	&& global_regs[REGNO (dest)])))
1892	/* Don't substitute into an incremented register. */
1893	|| FIND_REG_INC_NOTE (i3, dest)
1894	|| (succ && FIND_REG_INC_NOTE (succ, dest))
1895	|| (succ2 && FIND_REG_INC_NOTE (succ2, dest))
1896	/* Don't substitute into a non-local goto, this confuses CFG. */
1897	|| (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1898	/* Make sure that DEST is not used after INSN but before SUCC, or
1899	after SUCC and before SUCC2, or after SUCC2 but before I3. */
1900	|| (!all_adjacent
1901	&& ((succ2
1902	&& (reg_used_between_p (dest, succ2, i3)
1903	|| reg_used_between_p (dest, succ, succ2)))
1904	|| (!succ2 && succ && reg_used_between_p (dest, succ, i3))
1905	|| (!succ2 && !succ && reg_used_between_p (dest, insn, i3))
1906	|| (succ
1907	/* SUCC and SUCC2 can be split halves from a PARALLEL; in
1908	that case SUCC is not in the insn stream, so use SUCC2
1909	instead for this test. */
1910	&& reg_used_between_p (dest, insn,
1911	succ2
1912	&& INSN_UID (insn: succ) == INSN_UID (insn: succ2)
1913	? succ2 : succ))))
1914	/* Make sure that the value that is to be substituted for the register
1915	does not use any registers whose values alter in between. However,
1916	If the insns are adjacent, a use can't cross a set even though we
1917	think it might (this can happen for a sequence of insns each setting
1918	the same destination; last_set of that register might point to
1919	a NOTE). If INSN has a REG_EQUIV note, the register is always
1920	equivalent to the memory so the substitution is valid even if there
1921	are intervening stores. Also, don't move a volatile asm or
1922	UNSPEC_VOLATILE across any other insns. */
1923	|| (! all_adjacent
1924	&& (((!MEM_P (src)
1925	|| ! find_reg_note (insn, REG_EQUIV, src))
1926	&& modified_between_p (src, insn, i3))
1927	|| (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1928	|| GET_CODE (src) == UNSPEC_VOLATILE))
1929	/* Don't combine across a CALL_INSN, because that would possibly
1930	change whether the life span of some REGs crosses calls or not,
1931	and it is a pain to update that information.
1932	Exception: if source is a constant, moving it later can't hurt.
1933	Accept that as a special case. */
1934	|| (DF_INSN_LUID (insn) < last_call_luid && ! CONSTANT_P (src)))
1935	return false;
1936
1937	/* DEST must be a REG. */
1938	if (REG_P (dest))
1939	{
1940	/* If register alignment is being enforced for multi-word items in all
1941	cases except for parameters, it is possible to have a register copy
1942	insn referencing a hard register that is not allowed to contain the
1943	mode being copied and which would not be valid as an operand of most
1944	insns. Eliminate this problem by not combining with such an insn.
1945
1946	Also, on some machines we don't want to extend the life of a hard
1947	register. */
1948
1949	if (REG_P (src)
1950	&& ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1951	&& !targetm.hard_regno_mode_ok (REGNO (dest), GET_MODE (dest)))
1952	/* Don't extend the life of a hard register unless it is
1953	user variable (if we have few registers) or it can't
1954	fit into the desired register (meaning something special
1955	is going on).
1956	Also avoid substituting a return register into I3, because
1957	reload can't handle a conflict with constraints of other
1958	inputs. */
1959	|| (REGNO (src) < FIRST_PSEUDO_REGISTER
1960	&& !targetm.hard_regno_mode_ok (REGNO (src),
1961	GET_MODE (src)))))
1962	return false;
1963	}
1964	else
1965	return false;
1966
1967
1968	if (GET_CODE (PATTERN (i3)) == PARALLEL)
1969	for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1970	if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1971	{
1972	rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1973
1974	/* If the clobber represents an earlyclobber operand, we must not
1975	substitute an expression containing the clobbered register.
1976	As we do not analyze the constraint strings here, we have to
1977	make the conservative assumption. However, if the register is
1978	a fixed hard reg, the clobber cannot represent any operand;
1979	we leave it up to the machine description to either accept or
1980	reject use-and-clobber patterns. */
1981	if (!REG_P (reg)
1982	|| REGNO (reg) >= FIRST_PSEUDO_REGISTER
1983	|| !fixed_regs[REGNO (reg)])
1984	if (reg_overlap_mentioned_p (reg, src))
1985	return false;
1986	}
1987
1988	/* If INSN contains anything volatile, or is an `asm' (whether volatile
1989	or not), reject, unless nothing volatile comes between it and I3 */
1990
1991	if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1992	{
1993	/* Make sure neither succ nor succ2 contains a volatile reference. */
1994	if (succ2 != 0 && volatile_refs_p (PATTERN (insn: succ2)))
1995	return false;
1996	if (succ != 0 && volatile_refs_p (PATTERN (insn: succ)))
1997	return false;
1998	/* We'll check insns between INSN and I3 below. */
1999	}
2000
2001	/* If INSN is an asm, and DEST is a hard register, reject, since it has
2002	to be an explicit register variable, and was chosen for a reason. */
2003
2004	if (GET_CODE (src) == ASM_OPERANDS
2005	&& REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
2006	return false;
2007
2008	/* If INSN contains volatile references (specifically volatile MEMs),
2009	we cannot combine across any other volatile references.
2010	Even if INSN doesn't contain volatile references, any intervening
2011	volatile insn might affect machine state. */
2012
2013	is_volatile_p = volatile_refs_p (PATTERN (insn))
2014	? volatile_refs_p
2015	: volatile_insn_p;
2016
2017	for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (insn: p))
2018	if (INSN_P (p) && p != succ && p != succ2 && is_volatile_p (PATTERN (insn: p)))
2019	return false;
2020
2021	/* If INSN contains an autoincrement or autodecrement, make sure that
2022	register is not used between there and I3, and not already used in
2023	I3 either. Neither must it be used in PRED or SUCC, if they exist.
2024	Also insist that I3 not be a jump if using LRA; if it were one
2025	and the incremented register were spilled, we would lose.
2026	Reload handles this correctly. */
2027
2028	if (AUTO_INC_DEC)
2029	for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2030	if (REG_NOTE_KIND (link) == REG_INC
2031	&& ((JUMP_P (i3) && targetm.lra_p ())
2032	|| reg_used_between_p (XEXP (link, 0), insn, i3)
2033	|| (pred != NULL_RTX
2034	&& reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: pred)))
2035	|| (pred2 != NULL_RTX
2036	&& reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: pred2)))
2037	|| (succ != NULL_RTX
2038	&& reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: succ)))
2039	|| (succ2 != NULL_RTX
2040	&& reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: succ2)))
2041	|| reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: i3))))
2042	return false;
2043
2044	/* If we get here, we have passed all the tests and the combination is
2045	to be allowed. */
2046
2047	*pdest = dest;
2048	*psrc = src;
2049
2050	return true;
2051	}
2052
2053	/* LOC is the location within I3 that contains its pattern or the component
2054	of a PARALLEL of the pattern. We validate that it is valid for combining.
2055
2056	One problem is if I3 modifies its output, as opposed to replacing it
2057	entirely, we can't allow the output to contain I2DEST, I1DEST or I0DEST as
2058	doing so would produce an insn that is not equivalent to the original insns.
2059
2060	Consider:
2061
2062	(set (reg:DI 101) (reg:DI 100))
2063	(set (subreg:SI (reg:DI 101) 0) <foo>)
2064
2065	This is NOT equivalent to:
2066
2067	(parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
2068	(set (reg:DI 101) (reg:DI 100))])
2069
2070	Not only does this modify 100 (in which case it might still be valid
2071	if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
2072
2073	We can also run into a problem if I2 sets a register that I1
2074	uses and I1 gets directly substituted into I3 (not via I2). In that
2075	case, we would be getting the wrong value of I2DEST into I3, so we
2076	must reject the combination. This case occurs when I2 and I1 both
2077	feed into I3, rather than when I1 feeds into I2, which feeds into I3.
2078	If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
2079	of a SET must prevent combination from occurring. The same situation
2080	can occur for I0, in which case I0_NOT_IN_SRC is set.
2081
2082	Before doing the above check, we first try to expand a field assignment
2083	into a set of logical operations.
2084
2085	If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
2086	we place a register that is both set and used within I3. If more than one
2087	such register is detected, we fail.
2088
2089	Return true if the combination is valid, false otherwise. */
2090
2091	static bool
2092	combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
2093	bool i1_not_in_src, bool i0_not_in_src, rtx *pi3dest_killed)
2094	{
2095	rtx x = *loc;
2096
2097	if (GET_CODE (x) == SET)
2098	{
2099	rtx set = x ;
2100	rtx dest = SET_DEST (set);
2101	rtx src = SET_SRC (set);
2102	rtx inner_dest = dest;
2103	rtx subdest;
2104
2105	while (GET_CODE (inner_dest) == STRICT_LOW_PART
2106	|| GET_CODE (inner_dest) == SUBREG
2107	|| GET_CODE (inner_dest) == ZERO_EXTRACT)
2108	inner_dest = XEXP (inner_dest, 0);
2109
2110	/* Check for the case where I3 modifies its output, as discussed
2111	above. We don't want to prevent pseudos from being combined
2112	into the address of a MEM, so only prevent the combination if
2113	i1 or i2 set the same MEM. */
2114	if ((inner_dest != dest &&
2115	(!MEM_P (inner_dest)
2116	|| rtx_equal_p (i2dest, inner_dest)
2117	|| (i1dest && rtx_equal_p (i1dest, inner_dest))
2118	|| (i0dest && rtx_equal_p (i0dest, inner_dest)))
2119	&& (reg_overlap_mentioned_p (i2dest, inner_dest)
2120	|| (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))
2121	|| (i0dest && reg_overlap_mentioned_p (i0dest, inner_dest))))
2122
2123	/* This is the same test done in can_combine_p except we can't test
2124	all_adjacent; we don't have to, since this instruction will stay
2125	in place, thus we are not considering increasing the lifetime of
2126	INNER_DEST.
2127
2128	Also, if this insn sets a function argument, combining it with
2129	something that might need a spill could clobber a previous
2130	function argument; the all_adjacent test in can_combine_p also
2131	checks this; here, we do a more specific test for this case. */
2132
2133	|| (REG_P (inner_dest)
2134	&& REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
2135	&& !targetm.hard_regno_mode_ok (REGNO (inner_dest),
2136	GET_MODE (inner_dest)))
2137	|| (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src))
2138	|| (i0_not_in_src && reg_overlap_mentioned_p (i0dest, src)))
2139	return false;
2140
2141	/* If DEST is used in I3, it is being killed in this insn, so
2142	record that for later. We have to consider paradoxical
2143	subregs here, since they kill the whole register, but we
2144	ignore partial subregs, STRICT_LOW_PART, etc.
2145	Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
2146	STACK_POINTER_REGNUM, since these are always considered to be
2147	live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
2148	subdest = dest;
2149	if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (x: subdest))
2150	subdest = SUBREG_REG (subdest);
2151	if (pi3dest_killed
2152	&& REG_P (subdest)
2153	&& reg_referenced_p (subdest, PATTERN (insn: i3))
2154	&& REGNO (subdest) != FRAME_POINTER_REGNUM
2155	&& (HARD_FRAME_POINTER_IS_FRAME_POINTER
2156	|| REGNO (subdest) != HARD_FRAME_POINTER_REGNUM)
2157	&& (FRAME_POINTER_REGNUM == ARG_POINTER_REGNUM
2158	|| (REGNO (subdest) != ARG_POINTER_REGNUM
2159	|| ! fixed_regs [REGNO (subdest)]))
2160	&& REGNO (subdest) != STACK_POINTER_REGNUM)
2161	{
2162	if (*pi3dest_killed)
2163	return false;
2164
2165	*pi3dest_killed = subdest;
2166	}
2167	}
2168
2169	else if (GET_CODE (x) == PARALLEL)
2170	{
2171	int i;
2172
2173	for (i = 0; i < XVECLEN (x, 0); i++)
2174	if (! combinable_i3pat (i3, loc: &XVECEXP (x, 0, i), i2dest, i1dest, i0dest,
2175	i1_not_in_src, i0_not_in_src, pi3dest_killed))
2176	return false;
2177	}
2178
2179	return true;
2180	}
2181
2182	/* Return true if X is an arithmetic expression that contains a multiplication
2183	and division. We don't count multiplications by powers of two here. */
2184
2185	static bool
2186	contains_muldiv (rtx x)
2187	{
2188	switch (GET_CODE (x))
2189	{
2190	case MOD: case DIV: case UMOD: case UDIV:
2191	return true;
2192
2193	case MULT:
2194	return ! (CONST_INT_P (XEXP (x, 1))
2195	&& pow2p_hwi (UINTVAL (XEXP (x, 1))));
2196	default:
2197	if (BINARY_P (x))
2198	return contains_muldiv (XEXP (x, 0))
2199	|| contains_muldiv (XEXP (x, 1));
2200
2201	if (UNARY_P (x))
2202	return contains_muldiv (XEXP (x, 0));
2203
2204	return false;
2205	}
2206	}
2207
2208	/* Determine whether INSN can be used in a combination. Return true if
2209	not. This is used in try_combine to detect early some cases where we
2210	can't perform combinations. */
2211
2212	static bool
2213	cant_combine_insn_p (rtx_insn *insn)
2214	{
2215	rtx set;
2216	rtx src, dest;
2217
2218	/* If this isn't really an insn, we can't do anything.
2219	This can occur when flow deletes an insn that it has merged into an
2220	auto-increment address. */
2221	if (!NONDEBUG_INSN_P (insn))
2222	return true;
2223
2224	/* Never combine loads and stores involving hard regs that are likely
2225	to be spilled. The register allocator can usually handle such
2226	reg-reg moves by tying. If we allow the combiner to make
2227	substitutions of likely-spilled regs, reload might die.
2228	As an exception, we allow combinations involving fixed regs; these are
2229	not available to the register allocator so there's no risk involved. */
2230
2231	set = single_set (insn);
2232	if (! set)
2233	return false;
2234	src = SET_SRC (set);
2235	dest = SET_DEST (set);
2236	if (GET_CODE (src) == SUBREG)
2237	src = SUBREG_REG (src);
2238	if (GET_CODE (dest) == SUBREG)
2239	dest = SUBREG_REG (dest);
2240	if (REG_P (src) && REG_P (dest)
2241	&& ((HARD_REGISTER_P (src)
2242	&& ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src))
2243	#ifdef LEAF_REGISTERS
2244	&& ! LEAF_REGISTERS [REGNO (src)])
2245	#else
2246	)
2247	#endif
2248	|| (HARD_REGISTER_P (dest)
2249	&& ! TEST_HARD_REG_BIT (fixed_reg_set, REGNO (dest))
2250	&& targetm.class_likely_spilled_p (REGNO_REG_CLASS (REGNO (dest))))))
2251	return true;
2252
2253	return false;
2254	}
2255
2256	struct likely_spilled_retval_info
2257	{
2258	unsigned regno, nregs;
2259	unsigned mask;
2260	};
2261
2262	/* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
2263	hard registers that are known to be written to / clobbered in full. */
2264	static void
2265	likely_spilled_retval_1 (rtx x, const_rtx set, void *data)
2266	{
2267	struct likely_spilled_retval_info *const info =
2268	(struct likely_spilled_retval_info *) data;
2269	unsigned regno, nregs;
2270	unsigned new_mask;
2271
2272	if (!REG_P (XEXP (set, 0)))
2273	return;
2274	regno = REGNO (x);
2275	if (regno >= info->regno + info->nregs)
2276	return;
2277	nregs = REG_NREGS (x);
2278	if (regno + nregs <= info->regno)
2279	return;
2280	new_mask = (2U << (nregs - 1)) - 1;
2281	if (regno < info->regno)
2282	new_mask >>= info->regno - regno;
2283	else
2284	new_mask <<= regno - info->regno;
2285	info->mask &= ~new_mask;
2286	}
2287
2288	/* Return true iff part of the return value is live during INSN, and
2289	it is likely spilled. This can happen when more than one insn is needed
2290	to copy the return value, e.g. when we consider to combine into the
2291	second copy insn for a complex value. */
2292
2293	static bool
2294	likely_spilled_retval_p (rtx_insn *insn)
2295	{
2296	rtx_insn *use = BB_END (this_basic_block);
2297	rtx reg;
2298	rtx_insn *p;
2299	unsigned regno, nregs;
2300	/* We assume here that no machine mode needs more than
2301	32 hard registers when the value overlaps with a register
2302	for which TARGET_FUNCTION_VALUE_REGNO_P is true. */
2303	unsigned mask;
2304	struct likely_spilled_retval_info info;
2305
2306	if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
2307	return false;
2308	reg = XEXP (PATTERN (use), 0);
2309	if (!REG_P (reg) || !targetm.calls.function_value_regno_p (REGNO (reg)))
2310	return false;
2311	regno = REGNO (reg);
2312	nregs = REG_NREGS (reg);
2313	if (nregs == 1)
2314	return false;
2315	mask = (2U << (nregs - 1)) - 1;
2316
2317	/* Disregard parts of the return value that are set later. */
2318	info.regno = regno;
2319	info.nregs = nregs;
2320	info.mask = mask;
2321	for (p = PREV_INSN (insn: use); info.mask && p != insn; p = PREV_INSN (insn: p))
2322	if (INSN_P (p))
2323	note_stores (p, likely_spilled_retval_1, &info);
2324	mask = info.mask;
2325
2326	/* Check if any of the (probably) live return value registers is
2327	likely spilled. */
2328	nregs --;
2329	do
2330	{
2331	if ((mask & 1 << nregs)
2332	&& targetm.class_likely_spilled_p (REGNO_REG_CLASS (regno + nregs)))
2333	return true;
2334	} while (nregs--);
2335	return false;
2336	}
2337
2338	/* Adjust INSN after we made a change to its destination.
2339
2340	Changing the destination can invalidate notes that say something about
2341	the results of the insn and a LOG_LINK pointing to the insn. */
2342
2343	static void
2344	adjust_for_new_dest (rtx_insn *insn)
2345	{
2346	/* For notes, be conservative and simply remove them. */
2347	remove_reg_equal_equiv_notes (insn, true);
2348
2349	/* The new insn will have a destination that was previously the destination
2350	of an insn just above it. Call distribute_links to make a LOG_LINK from
2351	the next use of that destination. */
2352
2353	rtx set = single_set (insn);
2354	gcc_assert (set);
2355
2356	rtx reg = SET_DEST (set);
2357
2358	while (GET_CODE (reg) == ZERO_EXTRACT
2359	|| GET_CODE (reg) == STRICT_LOW_PART
2360	|| GET_CODE (reg) == SUBREG)
2361	reg = XEXP (reg, 0);
2362	gcc_assert (REG_P (reg));
2363
2364	distribute_links (alloc_insn_link (insn, REGNO (reg), NULL));
2365
2366	df_insn_rescan (insn);
2367	}
2368
2369	/* Return TRUE if combine can reuse reg X in mode MODE.
2370	ADDED_SETS is trueif the original set is still required. */
2371	static bool
2372	can_change_dest_mode (rtx x, bool added_sets, machine_mode mode)
2373	{
2374	unsigned int regno;
2375
2376	if (!REG_P (x))
2377	return false;
2378
2379	/* Don't change between modes with different underlying register sizes,
2380	since this could lead to invalid subregs. */
2381	if (maybe_ne (REGMODE_NATURAL_SIZE (mode),
2382	REGMODE_NATURAL_SIZE (GET_MODE (x))))
2383	return false;
2384
2385	regno = REGNO (x);
2386	/* Allow hard registers if the new mode is legal, and occupies no more
2387	registers than the old mode. */
2388	if (regno < FIRST_PSEUDO_REGISTER)
2389	return (targetm.hard_regno_mode_ok (regno, mode)
2390	&& REG_NREGS (x) >= hard_regno_nregs (regno, mode));
2391
2392	/* Or a pseudo that is only used once. */
2393	return (regno < reg_n_sets_max
2394	&& REG_N_SETS (regno) == 1
2395	&& !added_sets
2396	&& !REG_USERVAR_P (x));
2397	}
2398
2399
2400	/* Check whether X, the destination of a set, refers to part of
2401	the register specified by REG. */
2402
2403	static bool
2404	reg_subword_p (rtx x, rtx reg)
2405	{
2406	/* Check that reg is an integer mode register. */
2407	if (!REG_P (reg) || GET_MODE_CLASS (GET_MODE (reg)) != MODE_INT)
2408	return false;
2409
2410	if (GET_CODE (x) == STRICT_LOW_PART
2411	|| GET_CODE (x) == ZERO_EXTRACT)
2412	x = XEXP (x, 0);
2413
2414	return GET_CODE (x) == SUBREG
2415	&& !paradoxical_subreg_p (x)
2416	&& SUBREG_REG (x) == reg
2417	&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
2418	}
2419
2420	/* Return whether PAT is a PARALLEL of exactly N register SETs followed
2421	by an arbitrary number of CLOBBERs. */
2422	static bool
2423	is_parallel_of_n_reg_sets (rtx pat, int n)
2424	{
2425	if (GET_CODE (pat) != PARALLEL)
2426	return false;
2427
2428	int len = XVECLEN (pat, 0);
2429	if (len < n)
2430	return false;
2431
2432	int i;
2433	for (i = 0; i < n; i++)
2434	if (GET_CODE (XVECEXP (pat, 0, i)) != SET
2435	|| !REG_P (SET_DEST (XVECEXP (pat, 0, i))))
2436	return false;
2437	for ( ; i < len; i++)
2438	switch (GET_CODE (XVECEXP (pat, 0, i)))
2439	{
2440	case CLOBBER:
2441	if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
2442	return false;
2443	break;
2444	default:
2445	return false;
2446	}
2447	return true;
2448	}
2449
2450	/* Return whether INSN, a PARALLEL of N register SETs (and maybe some
2451	CLOBBERs), can be split into individual SETs in that order, without
2452	changing semantics. */
2453	static bool
2454	can_split_parallel_of_n_reg_sets (rtx_insn *insn, int n)
2455	{
2456	if (!insn_nothrow_p (insn))
2457	return false;
2458
2459	rtx pat = PATTERN (insn);
2460
2461	int i, j;
2462	for (i = 0; i < n; i++)
2463	{
2464	if (side_effects_p (SET_SRC (XVECEXP (pat, 0, i))))
2465	return false;
2466
2467	rtx reg = SET_DEST (XVECEXP (pat, 0, i));
2468
2469	for (j = i + 1; j < n; j++)
2470	if (reg_referenced_p (reg, XVECEXP (pat, 0, j)))
2471	return false;
2472	}
2473
2474	return true;
2475	}
2476
2477	/* Return whether X is just a single_set, with the source
2478	a general_operand. */
2479	static bool
2480	is_just_move (rtx_insn *x)
2481	{
2482	rtx set = single_set (insn: x);
2483	if (!set)
2484	return false;
2485
2486	return general_operand (SET_SRC (set), VOIDmode);
2487	}
2488
2489	/* Callback function to count autoincs. */
2490
2491	static int
2492	count_auto_inc (rtx, rtx, rtx, rtx, rtx, void *arg)
2493	{
2494	(*((int *) arg))++;
2495
2496	return 0;
2497	}
2498
2499	/* Try to combine the insns I0, I1 and I2 into I3.
2500	Here I0, I1 and I2 appear earlier than I3.
2501	I0 and I1 can be zero; then we combine just I2 into I3, or I1 and I2 into
2502	I3.
2503
2504	If we are combining more than two insns and the resulting insn is not
2505	recognized, try splitting it into two insns. If that happens, I2 and I3
2506	are retained and I1/I0 are pseudo-deleted by turning them into a NOTE.
2507	Otherwise, I0, I1 and I2 are pseudo-deleted.
2508
2509	Return 0 if the combination does not work. Then nothing is changed.
2510	If we did the combination, return the insn at which combine should
2511	resume scanning.
2512
2513	Set NEW_DIRECT_JUMP_P to true if try_combine creates a
2514	new direct jump instruction.
2515
2516	LAST_COMBINED_INSN is either I3, or some insn after I3 that has
2517	been I3 passed to an earlier try_combine within the same basic
2518	block. */
2519
2520	static rtx_insn *
2521	try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
2522	bool *new_direct_jump_p, rtx_insn *last_combined_insn)
2523	{
2524	/* New patterns for I3 and I2, respectively. */
2525	rtx newpat, newi2pat = 0;
2526	rtvec newpat_vec_with_clobbers = 0;
2527	bool substed_i2 = false, substed_i1 = false, substed_i0 = false;
2528	/* Indicates need to preserve SET in I0, I1 or I2 in I3 if it is not
2529	dead. */
2530	bool added_sets_0, added_sets_1, added_sets_2;
2531	/* Total number of SETs to put into I3. */
2532	int total_sets;
2533	/* Nonzero if I2's or I1's body now appears in I3. */
2534	int i2_is_used = 0, i1_is_used = 0;
2535	/* INSN_CODEs for new I3, new I2, and user of condition code. */
2536	int insn_code_number, i2_code_number = 0, other_code_number = 0;
2537	/* Contains I3 if the destination of I3 is used in its source, which means
2538	that the old life of I3 is being killed. If that usage is placed into
2539	I2 and not in I3, a REG_DEAD note must be made. */
2540	rtx i3dest_killed = 0;
2541	/* SET_DEST and SET_SRC of I2, I1 and I0. */
2542	rtx i2dest = 0, i2src = 0, i1dest = 0, i1src = 0, i0dest = 0, i0src = 0;
2543	/* Copy of SET_SRC of I1 and I0, if needed. */
2544	rtx i1src_copy = 0, i0src_copy = 0, i0src_copy2 = 0;
2545	/* Set if I2DEST was reused as a scratch register. */
2546	bool i2scratch = false;
2547	/* The PATTERNs of I0, I1, and I2, or a copy of them in certain cases. */
2548	rtx i0pat = 0, i1pat = 0, i2pat = 0;
2549	/* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
2550	bool i2dest_in_i2src = false, i1dest_in_i1src = false;
2551	bool i2dest_in_i1src = false, i0dest_in_i0src = false;
2552	bool i1dest_in_i0src = false, i2dest_in_i0src = false;;
2553	bool i2dest_killed = false, i1dest_killed = false, i0dest_killed = false;
2554	bool i1_feeds_i2_n = false, i0_feeds_i2_n = false, i0_feeds_i1_n = false;
2555	/* Notes that must be added to REG_NOTES in I3 and I2. */
2556	rtx new_i3_notes, new_i2_notes;
2557	/* Notes that we substituted I3 into I2 instead of the normal case. */
2558	bool i3_subst_into_i2 = false;
2559	/* Notes that I1, I2 or I3 is a MULT operation. */
2560	bool have_mult = false;
2561	bool swap_i2i3 = false;
2562	bool split_i2i3 = false;
2563	bool changed_i3_dest = false;
2564	bool i2_was_move = false, i3_was_move = false;
2565	int n_auto_inc = 0;
2566
2567	int maxreg;
2568	rtx_insn *temp_insn;
2569	rtx temp_expr;
2570	struct insn_link *link;
2571	rtx other_pat = 0;
2572	rtx new_other_notes;
2573	int i;
2574	scalar_int_mode dest_mode, temp_mode;
2575	bool has_non_call_exception = false;
2576
2577	/* Immediately return if any of I0,I1,I2 are the same insn (I3 can
2578	never be). */
2579	if (i1 == i2 || i0 == i2 || (i0 && i0 == i1))
2580	return 0;
2581
2582	/* Only try four-insn combinations when there's high likelihood of
2583	success. Look for simple insns, such as loads of constants or
2584	binary operations involving a constant. */
2585	if (i0)
2586	{
2587	int i;
2588	int ngood = 0;
2589	int nshift = 0;
2590	rtx set0, set3;
2591
2592	if (!flag_expensive_optimizations)
2593	return 0;
2594
2595	for (i = 0; i < 4; i++)
2596	{
2597	rtx_insn *insn = i == 0 ? i0 : i == 1 ? i1 : i == 2 ? i2 : i3;
2598	rtx set = single_set (insn);
2599	rtx src;
2600	if (!set)
2601	continue;
2602	src = SET_SRC (set);
2603	if (CONSTANT_P (src))
2604	{
2605	ngood += 2;
2606	break;
2607	}
2608	else if (BINARY_P (src) && CONSTANT_P (XEXP (src, 1)))
2609	ngood++;
2610	else if (GET_CODE (src) == ASHIFT || GET_CODE (src) == ASHIFTRT
2611	|| GET_CODE (src) == LSHIFTRT)
2612	nshift++;
2613	}
2614
2615	/* If I0 loads a memory and I3 sets the same memory, then I1 and I2
2616	are likely manipulating its value. Ideally we'll be able to combine
2617	all four insns into a bitfield insertion of some kind.
2618
2619	Note the source in I0 might be inside a sign/zero extension and the
2620	memory modes in I0 and I3 might be different. So extract the address
2621	from the destination of I3 and search for it in the source of I0.
2622
2623	In the event that there's a match but the source/dest do not actually
2624	refer to the same memory, the worst that happens is we try some
2625	combinations that we wouldn't have otherwise. */
2626	if ((set0 = single_set (insn: i0))
2627	/* Ensure the source of SET0 is a MEM, possibly buried inside
2628	an extension. */
2629	&& (GET_CODE (SET_SRC (set0)) == MEM
2630	|| ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
2631	|| GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
2632	&& GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
2633	&& (set3 = single_set (insn: i3))
2634	/* Ensure the destination of SET3 is a MEM. */
2635	&& GET_CODE (SET_DEST (set3)) == MEM
2636	/* Would it be better to extract the base address for the MEM
2637	in SET3 and look for that? I don't have cases where it matters
2638	but I could envision such cases. */
2639	&& rtx_referenced_p (XEXP (SET_DEST (set3), 0), SET_SRC (set0)))
2640	ngood += 2;
2641
2642	if (ngood < 2 && nshift < 2)
2643	return 0;
2644	}
2645
2646	/* Exit early if one of the insns involved can't be used for
2647	combinations. */
2648	if (CALL_P (i2)
2649	|| (i1 && CALL_P (i1))
2650	|| (i0 && CALL_P (i0))
2651	|| cant_combine_insn_p (insn: i3)
2652	|| cant_combine_insn_p (insn: i2)
2653	|| (i1 && cant_combine_insn_p (insn: i1))
2654	|| (i0 && cant_combine_insn_p (insn: i0))
2655	|| likely_spilled_retval_p (insn: i3))
2656	return 0;
2657
2658	combine_attempts++;
2659	undobuf.other_insn = 0;
2660
2661	/* Reset the hard register usage information. */
2662	CLEAR_HARD_REG_SET (set&: newpat_used_regs);
2663
2664	if (dump_file && (dump_flags & TDF_DETAILS))
2665	{
2666	if (i0)
2667	fprintf (stream: dump_file, format: "\nTrying %d, %d, %d -> %d:\n",
2668	INSN_UID (insn: i0), INSN_UID (insn: i1), INSN_UID (insn: i2), INSN_UID (insn: i3));
2669	else if (i1)
2670	fprintf (stream: dump_file, format: "\nTrying %d, %d -> %d:\n",
2671	INSN_UID (insn: i1), INSN_UID (insn: i2), INSN_UID (insn: i3));
2672	else
2673	fprintf (stream: dump_file, format: "\nTrying %d -> %d:\n",
2674	INSN_UID (insn: i2), INSN_UID (insn: i3));
2675
2676	if (i0)
2677	dump_insn_slim (dump_file, i0);
2678	if (i1)
2679	dump_insn_slim (dump_file, i1);
2680	dump_insn_slim (dump_file, i2);
2681	dump_insn_slim (dump_file, i3);
2682	}
2683
2684	/* If multiple insns feed into one of I2 or I3, they can be in any
2685	order. To simplify the code below, reorder them in sequence. */
2686	if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i2))
2687	std::swap (a&: i0, b&: i2);
2688	if (i0 && DF_INSN_LUID (i0) > DF_INSN_LUID (i1))
2689	std::swap (a&: i0, b&: i1);
2690	if (i1 && DF_INSN_LUID (i1) > DF_INSN_LUID (i2))
2691	std::swap (a&: i1, b&: i2);
2692
2693	added_links_insn = 0;
2694	added_notes_insn = 0;
2695
2696	/* First check for one important special case that the code below will
2697	not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
2698	and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
2699	we may be able to replace that destination with the destination of I3.
2700	This occurs in the common code where we compute both a quotient and
2701	remainder into a structure, in which case we want to do the computation
2702	directly into the structure to avoid register-register copies.
2703
2704	Note that this case handles both multiple sets in I2 and also cases
2705	where I2 has a number of CLOBBERs inside the PARALLEL.
2706
2707	We make very conservative checks below and only try to handle the
2708	most common cases of this. For example, we only handle the case
2709	where I2 and I3 are adjacent to avoid making difficult register
2710	usage tests. */
2711
2712	if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
2713	&& REG_P (SET_SRC (PATTERN (i3)))
2714	&& REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
2715	&& find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
2716	&& GET_CODE (PATTERN (i2)) == PARALLEL
2717	&& ! side_effects_p (SET_DEST (PATTERN (i3)))
2718	/* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
2719	below would need to check what is inside (and reg_overlap_mentioned_p
2720	doesn't support those codes anyway). Don't allow those destinations;
2721	the resulting insn isn't likely to be recognized anyway. */
2722	&& GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
2723	&& GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
2724	&& ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
2725	SET_DEST (PATTERN (i3)))
2726	&& next_active_insn (i2) == i3)
2727	{
2728	rtx p2 = PATTERN (insn: i2);
2729
2730	/* Make sure that the destination of I3,
2731	which we are going to substitute into one output of I2,
2732	is not used within another output of I2. We must avoid making this:
2733	(parallel [(set (mem (reg 69)) ...)
2734	(set (reg 69) ...)])
2735	which is not well-defined as to order of actions.
2736	(Besides, reload can't handle output reloads for this.)
2737
2738	The problem can also happen if the dest of I3 is a memory ref,
2739	if another dest in I2 is an indirect memory ref.
2740
2741	Neither can this PARALLEL be an asm. We do not allow combining
2742	that usually (see can_combine_p), so do not here either. */
2743	bool ok = true;
2744	for (i = 0; ok && i < XVECLEN (p2, 0); i++)
2745	{
2746	if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
2747	|| GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
2748	&& reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
2749	SET_DEST (XVECEXP (p2, 0, i))))
2750	ok = false;
2751	else if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2752	&& GET_CODE (SET_SRC (XVECEXP (p2, 0, i))) == ASM_OPERANDS)
2753	ok = false;
2754	}
2755
2756	if (ok)
2757	for (i = 0; i < XVECLEN (p2, 0); i++)
2758	if (GET_CODE (XVECEXP (p2, 0, i)) == SET
2759	&& SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
2760	{
2761	combine_merges++;
2762
2763	subst_insn = i3;
2764	subst_low_luid = DF_INSN_LUID (i2);
2765
2766	added_sets_2 = added_sets_1 = added_sets_0 = false;
2767	i2src = SET_SRC (XVECEXP (p2, 0, i));
2768	i2dest = SET_DEST (XVECEXP (p2, 0, i));
2769	i2dest_killed = dead_or_set_p (i2, i2dest);
2770
2771	/* Replace the dest in I2 with our dest and make the resulting
2772	insn the new pattern for I3. Then skip to where we validate
2773	the pattern. Everything was set up above. */
2774	SUBST (SET_DEST (XVECEXP (p2, 0, i)), SET_DEST (PATTERN (i3)));
2775	newpat = p2;
2776	i3_subst_into_i2 = true;
2777	goto validate_replacement;
2778	}
2779	}
2780
2781	/* If I2 is setting a pseudo to a constant and I3 is setting some
2782	sub-part of it to another constant, merge them by making a new
2783	constant. */
2784	if (i1 == 0
2785	&& (temp_expr = single_set (insn: i2)) != 0
2786	&& is_a <scalar_int_mode> (GET_MODE (SET_DEST (temp_expr)), result: &temp_mode)
2787	&& CONST_SCALAR_INT_P (SET_SRC (temp_expr))
2788	&& GET_CODE (PATTERN (i3)) == SET
2789	&& CONST_SCALAR_INT_P (SET_SRC (PATTERN (i3)))
2790	&& reg_subword_p (SET_DEST (PATTERN (i3)), SET_DEST (temp_expr)))
2791	{
2792	rtx dest = SET_DEST (PATTERN (i3));
2793	rtx temp_dest = SET_DEST (temp_expr);
2794	int offset = -1;
2795	int width = 0;
2796
2797	if (GET_CODE (dest) == ZERO_EXTRACT)
2798	{
2799	if (CONST_INT_P (XEXP (dest, 1))
2800	&& CONST_INT_P (XEXP (dest, 2))
2801	&& is_a <scalar_int_mode> (GET_MODE (XEXP (dest, 0)),
2802	result: &dest_mode))
2803	{
2804	width = INTVAL (XEXP (dest, 1));
2805	offset = INTVAL (XEXP (dest, 2));
2806	dest = XEXP (dest, 0);
2807	if (BITS_BIG_ENDIAN)
2808	offset = GET_MODE_PRECISION (mode: dest_mode) - width - offset;
2809	}
2810	}
2811	else
2812	{
2813	if (GET_CODE (dest) == STRICT_LOW_PART)
2814	dest = XEXP (dest, 0);
2815	if (is_a <scalar_int_mode> (GET_MODE (dest), result: &dest_mode))
2816	{
2817	width = GET_MODE_PRECISION (mode: dest_mode);
2818	offset = 0;
2819	}
2820	}
2821
2822	if (offset >= 0)
2823	{
2824	/* If this is the low part, we're done. */
2825	if (subreg_lowpart_p (dest))
2826	;
2827	/* Handle the case where inner is twice the size of outer. */
2828	else if (GET_MODE_PRECISION (mode: temp_mode)
2829	== 2 * GET_MODE_PRECISION (mode: dest_mode))
2830	offset += GET_MODE_PRECISION (mode: dest_mode);
2831	/* Otherwise give up for now. */
2832	else
2833	offset = -1;
2834	}
2835
2836	if (offset >= 0)
2837	{
2838	rtx inner = SET_SRC (PATTERN (i3));
2839	rtx outer = SET_SRC (temp_expr);
2840
2841	wide_int o = wi::insert (x: rtx_mode_t (outer, temp_mode),
2842	y: rtx_mode_t (inner, dest_mode),
2843	offset, width);
2844
2845	combine_merges++;
2846	subst_insn = i3;
2847	subst_low_luid = DF_INSN_LUID (i2);
2848	added_sets_2 = added_sets_1 = added_sets_0 = false;
2849	i2dest = temp_dest;
2850	i2dest_killed = dead_or_set_p (i2, i2dest);
2851
2852	/* Replace the source in I2 with the new constant and make the
2853	resulting insn the new pattern for I3. Then skip to where we
2854	validate the pattern. Everything was set up above. */
2855	SUBST (SET_SRC (temp_expr),
2856	immed_wide_int_const (o, temp_mode));
2857
2858	newpat = PATTERN (insn: i2);
2859
2860	/* The dest of I3 has been replaced with the dest of I2. */
2861	changed_i3_dest = true;
2862	goto validate_replacement;
2863	}
2864	}
2865
2866	/* If we have no I1 and I2 looks like:
2867	(parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
2868	(set Y OP)])
2869	make up a dummy I1 that is
2870	(set Y OP)
2871	and change I2 to be
2872	(set (reg:CC X) (compare:CC Y (const_int 0)))
2873
2874	(We can ignore any trailing CLOBBERs.)
2875
2876	This undoes a previous combination and allows us to match a branch-and-
2877	decrement insn. */
2878
2879	if (i1 == 0
2880	&& is_parallel_of_n_reg_sets (pat: PATTERN (insn: i2), n: 2)
2881	&& (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
2882	== MODE_CC)
2883	&& GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
2884	&& XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
2885	&& rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
2886	SET_SRC (XVECEXP (PATTERN (i2), 0, 1)))
2887	&& !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2888	&& !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2889	{
2890	/* We make I1 with the same INSN_UID as I2. This gives it
2891	the same DF_INSN_LUID for value tracking. Our fake I1 will
2892	never appear in the insn stream so giving it the same INSN_UID
2893	as I2 will not cause a problem. */
2894
2895	i1 = gen_rtx_INSN (VOIDmode, NULL, next_insn: i2, bb: BLOCK_FOR_INSN (insn: i2),
2896	XVECEXP (PATTERN (i2), 0, 1), location: INSN_LOCATION (insn: i2),
2897	code: -1, NULL_RTX);
2898	INSN_UID (insn: i1) = INSN_UID (insn: i2);
2899
2900	SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
2901	SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
2902	SET_DEST (PATTERN (i1)));
2903	unsigned int regno = REGNO (SET_DEST (PATTERN (i1)));
2904	SUBST_LINK (LOG_LINKS (i2),
2905	alloc_insn_link (i1, regno, LOG_LINKS (i2)));
2906	}
2907
2908	/* If I2 is a PARALLEL of two SETs of REGs (and perhaps some CLOBBERs),
2909	make those two SETs separate I1 and I2 insns, and make an I0 that is
2910	the original I1. */
2911	if (i0 == 0
2912	&& is_parallel_of_n_reg_sets (pat: PATTERN (insn: i2), n: 2)
2913	&& can_split_parallel_of_n_reg_sets (insn: i2, n: 2)
2914	&& !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2915	&& !reg_used_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3)
2916	&& !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 0)), i2, i3)
2917	&& !reg_set_between_p (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)), i2, i3))
2918	{
2919	/* If there is no I1, there is no I0 either. */
2920	i0 = i1;
2921
2922	/* We make I1 with the same INSN_UID as I2. This gives it
2923	the same DF_INSN_LUID for value tracking. Our fake I1 will
2924	never appear in the insn stream so giving it the same INSN_UID
2925	as I2 will not cause a problem. */
2926
2927	i1 = gen_rtx_INSN (VOIDmode, NULL, next_insn: i2, bb: BLOCK_FOR_INSN (insn: i2),
2928	XVECEXP (PATTERN (i2), 0, 0), location: INSN_LOCATION (insn: i2),
2929	code: -1, NULL_RTX);
2930	INSN_UID (insn: i1) = INSN_UID (insn: i2);
2931
2932	SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 1));
2933	}
2934
2935	/* Verify that I2 and maybe I1 and I0 can be combined into I3. */
2936	if (!can_combine_p (insn: i2, i3, pred: i0, pred2: i1, NULL, NULL, pdest: &i2dest, psrc: &i2src))
2937	{
2938	if (dump_file && (dump_flags & TDF_DETAILS))
2939	fprintf (stream: dump_file, format: "Can't combine i2 into i3\n");
2940	undo_all ();
2941	return 0;
2942	}
2943	if (i1 && !can_combine_p (insn: i1, i3, pred: i0, NULL, succ: i2, NULL, pdest: &i1dest, psrc: &i1src))
2944	{
2945	if (dump_file && (dump_flags & TDF_DETAILS))
2946	fprintf (stream: dump_file, format: "Can't combine i1 into i3\n");
2947	undo_all ();
2948	return 0;
2949	}
2950	if (i0 && !can_combine_p (insn: i0, i3, NULL, NULL, succ: i1, succ2: i2, pdest: &i0dest, psrc: &i0src))
2951	{
2952	if (dump_file && (dump_flags & TDF_DETAILS))
2953	fprintf (stream: dump_file, format: "Can't combine i0 into i3\n");
2954	undo_all ();
2955	return 0;
2956	}
2957
2958	/* With non-call exceptions we can end up trying to combine multiple
2959	insns with possible EH side effects. Make sure we can combine
2960	that to a single insn which means there must be at most one insn
2961	in the combination with an EH side effect. */
2962	if (cfun->can_throw_non_call_exceptions)
2963	{
2964	if (find_reg_note (i3, REG_EH_REGION, NULL_RTX)
2965	|| find_reg_note (i2, REG_EH_REGION, NULL_RTX)
2966	|| (i1 && find_reg_note (i1, REG_EH_REGION, NULL_RTX))
2967	|| (i0 && find_reg_note (i0, REG_EH_REGION, NULL_RTX)))
2968	{
2969	has_non_call_exception = true;
2970	if (insn_could_throw_p (i3)
2971	+ insn_could_throw_p (i2)
2972	+ (i1 ? insn_could_throw_p (i1) : 0)
2973	+ (i0 ? insn_could_throw_p (i0) : 0) > 1)
2974	{
2975	if (dump_file && (dump_flags & TDF_DETAILS))
2976	fprintf (stream: dump_file, format: "Can't combine multiple insns with EH "
2977	"side-effects\n");
2978	undo_all ();
2979	return 0;
2980	}
2981	}
2982	}
2983
2984	/* Record whether i2 and i3 are trivial moves. */
2985	i2_was_move = is_just_move (x: i2);
2986	i3_was_move = is_just_move (x: i3);
2987
2988	/* Record whether I2DEST is used in I2SRC and similarly for the other
2989	cases. Knowing this will help in register status updating below. */
2990	i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2991	i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2992	i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2993	i0dest_in_i0src = i0 && reg_overlap_mentioned_p (i0dest, i0src);
2994	i1dest_in_i0src = i0 && reg_overlap_mentioned_p (i1dest, i0src);
2995	i2dest_in_i0src = i0 && reg_overlap_mentioned_p (i2dest, i0src);
2996	i2dest_killed = dead_or_set_p (i2, i2dest);
2997	i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2998	i0dest_killed = i0 && dead_or_set_p (i0, i0dest);
2999
3000	/* For the earlier insns, determine which of the subsequent ones they
3001	feed. */
3002	i1_feeds_i2_n = i1 && insn_a_feeds_b (a: i1, b: i2);
3003	i0_feeds_i1_n = i0 && insn_a_feeds_b (a: i0, b: i1);
3004	i0_feeds_i2_n = (i0 && (!i0_feeds_i1_n ? insn_a_feeds_b (a: i0, b: i2)
3005	: (!reg_overlap_mentioned_p (i1dest, i0dest)
3006	&& reg_overlap_mentioned_p (i0dest, i2src))));
3007
3008	/* Ensure that I3's pattern can be the destination of combines. */
3009	if (! combinable_i3pat (i3, loc: &PATTERN (insn: i3), i2dest, i1dest, i0dest,
3010	i1_not_in_src: i1 && i2dest_in_i1src && !i1_feeds_i2_n,
3011	i0_not_in_src: i0 && ((i2dest_in_i0src && !i0_feeds_i2_n)
3012	|| (i1dest_in_i0src && !i0_feeds_i1_n)),
3013	pi3dest_killed: &i3dest_killed))
3014	{
3015	undo_all ();
3016	return 0;
3017	}
3018
3019	/* See if any of the insns is a MULT operation. Unless one is, we will
3020	reject a combination that is, since it must be slower. Be conservative
3021	here. */
3022	if (GET_CODE (i2src) == MULT
3023	|| (i1 != 0 && GET_CODE (i1src) == MULT)
3024	|| (i0 != 0 && GET_CODE (i0src) == MULT)
3025	|| (GET_CODE (PATTERN (i3)) == SET
3026	&& GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
3027	have_mult = true;
3028
3029	/* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
3030	We used to do this EXCEPT in one case: I3 has a post-inc in an
3031	output operand. However, that exception can give rise to insns like
3032	mov r3,(r3)+
3033	which is a famous insn on the PDP-11 where the value of r3 used as the
3034	source was model-dependent. Avoid this sort of thing. */
3035
3036	#if 0
3037	if (!(GET_CODE (PATTERN (i3)) == SET
3038	&& REG_P (SET_SRC (PATTERN (i3)))
3039	&& MEM_P (SET_DEST (PATTERN (i3)))
3040	&& (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
3041	|| GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
3042	/* It's not the exception. */
3043	#endif
3044	if (AUTO_INC_DEC)
3045	{
3046	rtx link;
3047	for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
3048	if (REG_NOTE_KIND (link) == REG_INC
3049	&& (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: i2))
3050	|| (i1 != 0
3051	&& reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (insn: i1)))))
3052	{
3053	undo_all ();
3054	return 0;
3055	}
3056	}
3057
3058	/* See if the SETs in I1 or I2 need to be kept around in the merged
3059	instruction: whenever the value set there is still needed past I3.
3060	For the SET in I2, this is easy: we see if I2DEST dies or is set in I3.
3061
3062	For the SET in I1, we have two cases: if I1 and I2 independently feed
3063	into I3, the set in I1 needs to be kept around unless I1DEST dies
3064	or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
3065	in I1 needs to be kept around unless I1DEST dies or is set in either
3066	I2 or I3. The same considerations apply to I0. */
3067
3068	added_sets_2 = !dead_or_set_p (i3, i2dest);
3069
3070	if (i1)
3071	added_sets_1 = !(dead_or_set_p (i3, i1dest)
3072	|| (i1_feeds_i2_n && dead_or_set_p (i2, i1dest)));
3073	else
3074	added_sets_1 = false;
3075
3076	if (i0)
3077	added_sets_0 = !(dead_or_set_p (i3, i0dest)
3078	|| (i0_feeds_i1_n && dead_or_set_p (i1, i0dest))
3079	|| ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3080	&& dead_or_set_p (i2, i0dest)));
3081	else
3082	added_sets_0 = false;
3083
3084	/* We are about to copy insns for the case where they need to be kept
3085	around. Check that they can be copied in the merged instruction. */
3086
3087	if (targetm.cannot_copy_insn_p
3088	&& ((added_sets_2 && targetm.cannot_copy_insn_p (i2))
3089	|| (i1 && added_sets_1 && targetm.cannot_copy_insn_p (i1))
3090	|| (i0 && added_sets_0 && targetm.cannot_copy_insn_p (i0))))
3091	{
3092	undo_all ();
3093	return 0;
3094	}
3095
3096	/* We cannot safely duplicate volatile references in any case. */
3097
3098	if ((added_sets_2 && volatile_refs_p (PATTERN (insn: i2)))
3099	|| (added_sets_1 && volatile_refs_p (PATTERN (insn: i1)))
3100	|| (added_sets_0 && volatile_refs_p (PATTERN (insn: i0))))
3101	{
3102	undo_all ();
3103	return 0;
3104	}
3105
3106	/* Count how many auto_inc expressions there were in the original insns;
3107	we need to have the same number in the resulting patterns. */
3108
3109	if (i0)
3110	for_each_inc_dec (PATTERN (insn: i0), count_auto_inc, arg: &n_auto_inc);
3111	if (i1)
3112	for_each_inc_dec (PATTERN (insn: i1), count_auto_inc, arg: &n_auto_inc);
3113	for_each_inc_dec (PATTERN (insn: i2), count_auto_inc, arg: &n_auto_inc);
3114	for_each_inc_dec (PATTERN (insn: i3), count_auto_inc, arg: &n_auto_inc);
3115
3116	/* If the set in I2 needs to be kept around, we must make a copy of
3117	PATTERN (I2), so that when we substitute I1SRC for I1DEST in
3118	PATTERN (I2), we are only substituting for the original I1DEST, not into
3119	an already-substituted copy. This also prevents making self-referential
3120	rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
3121	I2DEST. */
3122
3123	if (added_sets_2)
3124	{
3125	if (GET_CODE (PATTERN (i2)) == PARALLEL)
3126	i2pat = gen_rtx_SET (i2dest, copy_rtx (i2src));
3127	else
3128	i2pat = copy_rtx (PATTERN (insn: i2));
3129	}
3130
3131	if (added_sets_1)
3132	{
3133	if (GET_CODE (PATTERN (i1)) == PARALLEL)
3134	i1pat = gen_rtx_SET (i1dest, copy_rtx (i1src));
3135	else
3136	i1pat = copy_rtx (PATTERN (insn: i1));
3137	}
3138
3139	if (added_sets_0)
3140	{
3141	if (GET_CODE (PATTERN (i0)) == PARALLEL)
3142	i0pat = gen_rtx_SET (i0dest, copy_rtx (i0src));
3143	else
3144	i0pat = copy_rtx (PATTERN (insn: i0));
3145	}
3146
3147	combine_merges++;
3148
3149	/* Substitute in the latest insn for the regs set by the earlier ones. */
3150
3151	maxreg = max_reg_num ();
3152
3153	subst_insn = i3;
3154
3155	/* Many machines have insns that can both perform an
3156	arithmetic operation and set the condition code. These operations will
3157	be represented as a PARALLEL with the first element of the vector
3158	being a COMPARE of an arithmetic operation with the constant zero.
3159	The second element of the vector will set some pseudo to the result
3160	of the same arithmetic operation. If we simplify the COMPARE, we won't
3161	match such a pattern and so will generate an extra insn. Here we test
3162	for this case, where both the comparison and the operation result are
3163	needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
3164	I2SRC. Later we will make the PARALLEL that contains I2. */
3165
3166	if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
3167	&& GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
3168	&& CONST_INT_P (XEXP (SET_SRC (PATTERN (i3)), 1))
3169	&& rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
3170	{
3171	rtx newpat_dest;
3172	rtx *cc_use_loc = NULL;
3173	rtx_insn *cc_use_insn = NULL;
3174	rtx op0 = i2src, op1 = XEXP (SET_SRC (PATTERN (i3)), 1);
3175	machine_mode compare_mode, orig_compare_mode;
3176	enum rtx_code compare_code = UNKNOWN, orig_compare_code = UNKNOWN;
3177	scalar_int_mode mode;
3178
3179	newpat = PATTERN (insn: i3);
3180	newpat_dest = SET_DEST (newpat);
3181	compare_mode = orig_compare_mode = GET_MODE (newpat_dest);
3182
3183	if (undobuf.other_insn == 0
3184	&& (cc_use_loc = find_single_use (SET_DEST (newpat), insn: i3,
3185	ploc: &cc_use_insn)))
3186	{
3187	compare_code = orig_compare_code = GET_CODE (*cc_use_loc);
3188	if (is_a <scalar_int_mode> (GET_MODE (i2dest), result: &mode))
3189	compare_code = simplify_compare_const (compare_code, mode,
3190	&op0, &op1);
3191	target_canonicalize_comparison (code: &compare_code, op0: &op0, op1: &op1, op0_preserve_value: 1);
3192	}
3193
3194	/* Do the rest only if op1 is const0_rtx, which may be the
3195	result of simplification. */
3196	if (op1 == const0_rtx)
3197	{
3198	/* If a single use of the CC is found, prepare to modify it
3199	when SELECT_CC_MODE returns a new CC-class mode, or when
3200	the above simplify_compare_const() returned a new comparison
3201	operator. undobuf.other_insn is assigned the CC use insn
3202	when modifying it. */
3203	if (cc_use_loc)
3204	{
3205	#ifdef SELECT_CC_MODE
3206	machine_mode new_mode
3207	= SELECT_CC_MODE (compare_code, op0, op1);
3208	if (new_mode != orig_compare_mode
3209	&& can_change_dest_mode (SET_DEST (newpat),
3210	added_sets: added_sets_2, mode: new_mode))
3211	{
3212	unsigned int regno = REGNO (newpat_dest);
3213	compare_mode = new_mode;
3214	if (regno < FIRST_PSEUDO_REGISTER)
3215	newpat_dest = gen_rtx_REG (compare_mode, regno);
3216	else
3217	{
3218	subst_mode (regno, newval: compare_mode);
3219	newpat_dest = regno_reg_rtx[regno];
3220	}
3221	}
3222	#endif
3223	/* Cases for modifying the CC-using comparison. */
3224	if (compare_code != orig_compare_code
3225	/* ??? Do we need to verify the zero rtx? */
3226	&& XEXP (*cc_use_loc, 1) == const0_rtx)
3227	{
3228	/* Replace cc_use_loc with entire new RTX. */
3229	SUBST (*cc_use_loc,
3230	gen_rtx_fmt_ee (compare_code, GET_MODE (*cc_use_loc),
3231	newpat_dest, const0_rtx));
3232	undobuf.other_insn = cc_use_insn;
3233	}
3234	else if (compare_mode != orig_compare_mode)
3235	{
3236	/* Just replace the CC reg with a new mode. */
3237	SUBST (XEXP (*cc_use_loc, 0), newpat_dest);
3238	undobuf.other_insn = cc_use_insn;
3239	}
3240	}
3241
3242	/* Now we modify the current newpat:
3243	First, SET_DEST(newpat) is updated if the CC mode has been
3244	altered. For targets without SELECT_CC_MODE, this should be
3245	optimized away. */
3246	if (compare_mode != orig_compare_mode)
3247	SUBST (SET_DEST (newpat), newpat_dest);
3248	/* This is always done to propagate i2src into newpat. */
3249	SUBST (SET_SRC (newpat),
3250	gen_rtx_COMPARE (compare_mode, op0, op1));
3251	/* Create new version of i2pat if needed; the below PARALLEL
3252	creation needs this to work correctly. */
3253	if (! rtx_equal_p (i2src, op0))
3254	i2pat = gen_rtx_SET (i2dest, op0);
3255	i2_is_used = 1;
3256	}
3257	}
3258
3259	if (i2_is_used == 0)
3260	{
3261	/* It is possible that the source of I2 or I1 may be performing
3262	an unneeded operation, such as a ZERO_EXTEND of something
3263	that is known to have the high part zero. Handle that case
3264	by letting subst look at the inner insns.
3265
3266	Another way to do this would be to have a function that tries
3267	to simplify a single insn instead of merging two or more
3268	insns. We don't do this because of the potential of infinite
3269	loops and because of the potential extra memory required.
3270	However, doing it the way we are is a bit of a kludge and
3271	doesn't catch all cases.
3272
3273	But only do this if -fexpensive-optimizations since it slows
3274	things down and doesn't usually win.
3275
3276	This is not done in the COMPARE case above because the
3277	unmodified I2PAT is used in the PARALLEL and so a pattern
3278	with a modified I2SRC would not match. */
3279
3280	if (flag_expensive_optimizations)
3281	{
3282	/* Pass pc_rtx so no substitutions are done, just
3283	simplifications. */
3284	if (i1)
3285	{
3286	subst_low_luid = DF_INSN_LUID (i1);
3287	i1src = subst (i1src, pc_rtx, pc_rtx, false, false, false);
3288	}
3289
3290	subst_low_luid = DF_INSN_LUID (i2);
3291	i2src = subst (i2src, pc_rtx, pc_rtx, false, false, false);
3292	}
3293
3294	n_occurrences = 0; /* `subst' counts here */
3295	subst_low_luid = DF_INSN_LUID (i2);
3296
3297	/* If I1 feeds into I2 and I1DEST is in I1SRC, we need to make a unique
3298	copy of I2SRC each time we substitute it, in order to avoid creating
3299	self-referential RTL when we will be substituting I1SRC for I1DEST
3300	later. Likewise if I0 feeds into I2, either directly or indirectly
3301	through I1, and I0DEST is in I0SRC. */
3302	newpat = subst (PATTERN (insn: i3), i2dest, i2src, false, false,
3303	(i1_feeds_i2_n && i1dest_in_i1src)
3304	|| ((i0_feeds_i2_n || (i0_feeds_i1_n && i1_feeds_i2_n))
3305	&& i0dest_in_i0src));
3306	substed_i2 = true;
3307
3308	/* Record whether I2's body now appears within I3's body. */
3309	i2_is_used = n_occurrences;
3310	}
3311
3312	/* If we already got a failure, don't try to do more. Otherwise, try to
3313	substitute I1 if we have it. */
3314
3315	if (i1 && GET_CODE (newpat) != CLOBBER)
3316	{
3317	/* Before we can do this substitution, we must redo the test done
3318	above (see detailed comments there) that ensures I1DEST isn't
3319	mentioned in any SETs in NEWPAT that are field assignments. */
3320	if (!combinable_i3pat (NULL, loc: &newpat, i2dest: i1dest, NULL_RTX, NULL_RTX,
3321	i1_not_in_src: false, i0_not_in_src: false, pi3dest_killed: 0))
3322	{
3323	undo_all ();
3324	return 0;
3325	}
3326
3327	n_occurrences = 0;
3328	subst_low_luid = DF_INSN_LUID (i1);
3329
3330	/* If the following substitution will modify I1SRC, make a copy of it
3331	for the case where it is substituted for I1DEST in I2PAT later. */
3332	if (added_sets_2 && i1_feeds_i2_n)
3333	i1src_copy = copy_rtx (i1src);
3334
3335	/* If I0 feeds into I1 and I0DEST is in I0SRC, we need to make a unique
3336	copy of I1SRC each time we substitute it, in order to avoid creating
3337	self-referential RTL when we will be substituting I0SRC for I0DEST
3338	later. */
3339	newpat = subst (newpat, i1dest, i1src, false, false,
3340	i0_feeds_i1_n && i0dest_in_i0src);
3341	substed_i1 = true;
3342
3343	/* Record whether I1's body now appears within I3's body. */
3344	i1_is_used = n_occurrences;
3345	}
3346
3347	/* Likewise for I0 if we have it. */
3348
3349	if (i0 && GET_CODE (newpat) != CLOBBER)
3350	{
3351	if (!combinable_i3pat (NULL, loc: &newpat, i2dest: i0dest, NULL_RTX, NULL_RTX,
3352	i1_not_in_src: false, i0_not_in_src: false, pi3dest_killed: 0))
3353	{
3354	undo_all ();
3355	return 0;
3356	}
3357
3358	/* If the following substitution will modify I0SRC, make a copy of it
3359	for the case where it is substituted for I0DEST in I1PAT later. */
3360	if (added_sets_1 && i0_feeds_i1_n)
3361	i0src_copy = copy_rtx (i0src);
3362	/* And a copy for I0DEST in I2PAT substitution. */
3363	if (added_sets_2 && ((i0_feeds_i1_n && i1_feeds_i2_n)
3364	|| (i0_feeds_i2_n)))
3365	i0src_copy2 = copy_rtx (i0src);
3366
3367	n_occurrences = 0;
3368	subst_low_luid = DF_INSN_LUID (i0);
3369	newpat = subst (newpat, i0dest, i0src, false, false, false);
3370	substed_i0 = true;
3371	}
3372
3373	if (n_auto_inc)
3374	{
3375	int new_n_auto_inc = 0;
3376	for_each_inc_dec (newpat, count_auto_inc, arg: &new_n_auto_inc);
3377
3378	if (n_auto_inc != new_n_auto_inc)
3379	{
3380	if (dump_file && (dump_flags & TDF_DETAILS))
3381	fprintf (stream: dump_file, format: "Number of auto_inc expressions changed\n");
3382	undo_all ();
3383	return 0;
3384	}
3385	}
3386
3387	/* Fail if an autoincrement side-effect has been duplicated. Be careful
3388	to count all the ways that I2SRC and I1SRC can be used. */
3389	if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
3390	&& i2_is_used + added_sets_2 > 1)
3391	|| (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
3392	&& (i1_is_used + added_sets_1 + (added_sets_2 && i1_feeds_i2_n) > 1))
3393	|| (i0 != 0 && FIND_REG_INC_NOTE (i0, NULL_RTX) != 0
3394	&& (n_occurrences + added_sets_0
3395	+ (added_sets_1 && i0_feeds_i1_n)
3396	+ (added_sets_2 && i0_feeds_i2_n) > 1))
3397	/* Fail if we tried to make a new register. */
3398	|| max_reg_num () != maxreg
3399	/* Fail if we couldn't do something and have a CLOBBER. */
3400	|| GET_CODE (newpat) == CLOBBER
3401	/* Fail if this new pattern is a MULT and we didn't have one before
3402	at the outer level. */
3403	|| (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
3404	&& ! have_mult))
3405	{
3406	undo_all ();
3407	return 0;
3408	}
3409
3410	/* If the actions of the earlier insns must be kept
3411	in addition to substituting them into the latest one,
3412	we must make a new PARALLEL for the latest insn
3413	to hold additional the SETs. */
3414
3415	if (added_sets_0 || added_sets_1 || added_sets_2)
3416	{
3417	int extra_sets = added_sets_0 + added_sets_1 + added_sets_2;
3418	combine_extras++;
3419
3420	if (GET_CODE (newpat) == PARALLEL)
3421	{
3422	rtvec old = XVEC (newpat, 0);
3423	total_sets = XVECLEN (newpat, 0) + extra_sets;
3424	newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3425	memcpy (XVEC (newpat, 0)->elem, src: &old->elem[0],
3426	n: sizeof (old->elem[0]) * old->num_elem);
3427	}
3428	else
3429	{
3430	rtx old = newpat;
3431	total_sets = 1 + extra_sets;
3432	newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
3433	XVECEXP (newpat, 0, 0) = old;
3434	}
3435
3436	if (added_sets_0)
3437	XVECEXP (newpat, 0, --total_sets) = i0pat;
3438
3439	if (added_sets_1)
3440	{
3441	rtx t = i1pat;
3442	if (i0_feeds_i1_n)
3443	t = subst (t, i0dest, i0src_copy ? i0src_copy : i0src,
3444	false, false, false);
3445
3446	XVECEXP (newpat, 0, --total_sets) = t;
3447	}
3448	if (added_sets_2)
3449	{
3450	rtx t = i2pat;
3451	if (i1_feeds_i2_n)
3452	t = subst (t, i1dest, i1src_copy ? i1src_copy : i1src, false, false,
3453	i0_feeds_i1_n && i0dest_in_i0src);
3454	if ((i0_feeds_i1_n && i1_feeds_i2_n) || i0_feeds_i2_n)
3455	t = subst (t, i0dest, i0src_copy2 ? i0src_copy2 : i0src,
3456	false, false, false);
3457
3458	XVECEXP (newpat, 0, --total_sets) = t;
3459	}
3460	}
3461
3462	validate_replacement:
3463
3464	/* Note which hard regs this insn has as inputs. */
3465	mark_used_regs_combine (newpat);
3466
3467	/* If recog_for_combine fails, it strips existing clobbers. If we'll
3468	consider splitting this pattern, we might need these clobbers. */
3469	if (i1 && GET_CODE (newpat) == PARALLEL
3470	&& GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
3471	{
3472	int len = XVECLEN (newpat, 0);
3473
3474	newpat_vec_with_clobbers = rtvec_alloc (len);
3475	for (i = 0; i < len; i++)
3476	RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
3477	}
3478
3479	/* We have recognized nothing yet. */
3480	insn_code_number = -1;
3481
3482	/* See if this is a PARALLEL of two SETs where one SET's destination is
3483	a register that is unused and this isn't marked as an instruction that
3484	might trap in an EH region. In that case, we just need the other SET.
3485	We prefer this over the PARALLEL.
3486
3487	This can occur when simplifying a divmod insn. We *must* test for this
3488	case here because the code below that splits two independent SETs doesn't
3489	handle this case correctly when it updates the register status.
3490
3491	It's pointless doing this if we originally had two sets, one from
3492	i3, and one from i2. Combining then splitting the parallel results
3493	in the original i2 again plus an invalid insn (which we delete).
3494	The net effect is only to move instructions around, which makes
3495	debug info less accurate.
3496
3497	If the remaining SET came from I2 its destination should not be used
3498	between I2 and I3. See PR82024. */
3499
3500	if (!(added_sets_2 && i1 == 0)
3501	&& is_parallel_of_n_reg_sets (pat: newpat, n: 2)
3502	&& asm_noperands (newpat) < 0)
3503	{
3504	rtx set0 = XVECEXP (newpat, 0, 0);
3505	rtx set1 = XVECEXP (newpat, 0, 1);
3506	rtx oldpat = newpat;
3507
3508	if (((REG_P (SET_DEST (set1))
3509	&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
3510	|| (GET_CODE (SET_DEST (set1)) == SUBREG
3511	&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
3512	&& insn_nothrow_p (i3)
3513	&& !side_effects_p (SET_SRC (set1)))
3514	{
3515	newpat = set0;
3516	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3517	}
3518
3519	else if (((REG_P (SET_DEST (set0))
3520	&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
3521	|| (GET_CODE (SET_DEST (set0)) == SUBREG
3522	&& find_reg_note (i3, REG_UNUSED,
3523	SUBREG_REG (SET_DEST (set0)))))
3524	&& insn_nothrow_p (i3)
3525	&& !side_effects_p (SET_SRC (set0)))
3526	{
3527	rtx dest = SET_DEST (set1);
3528	if (GET_CODE (dest) == SUBREG)
3529	dest = SUBREG_REG (dest);
3530	if (!reg_used_between_p (dest, i2, i3))
3531	{
3532	newpat = set1;
3533	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3534
3535	if (insn_code_number >= 0)
3536	changed_i3_dest = true;
3537	}
3538	}
3539
3540	if (insn_code_number < 0)
3541	newpat = oldpat;
3542	}
3543
3544	/* Is the result of combination a valid instruction? */
3545	if (insn_code_number < 0)
3546	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3547
3548	/* If we were combining three insns and the result is a simple SET
3549	with no ASM_OPERANDS that wasn't recognized, try to split it into two
3550	insns. There are two ways to do this. It can be split using a
3551	machine-specific method (like when you have an addition of a large
3552	constant) or by combine in the function find_split_point. */
3553
3554	if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
3555	&& asm_noperands (newpat) < 0)
3556	{
3557	rtx parallel, *split;
3558	rtx_insn *m_split_insn;
3559
3560	/* See if the MD file can split NEWPAT. If it can't, see if letting it
3561	use I2DEST as a scratch register will help. In the latter case,
3562	convert I2DEST to the mode of the source of NEWPAT if we can. */
3563
3564	m_split_insn = combine_split_insns (pattern: newpat, insn: i3);
3565
3566	/* We can only use I2DEST as a scratch reg if it doesn't overlap any
3567	inputs of NEWPAT. */
3568
3569	/* ??? If I2DEST is not safe, and I1DEST exists, then it would be
3570	possible to try that as a scratch reg. This would require adding
3571	more code to make it work though. */
3572
3573	if (m_split_insn == 0 && ! reg_overlap_mentioned_p (i2dest, newpat))
3574	{
3575	machine_mode new_mode = GET_MODE (SET_DEST (newpat));
3576
3577	/* ??? Reusing i2dest without resetting the reg_stat entry for it
3578	(temporarily, until we are committed to this instruction
3579	combination) does not work: for example, any call to nonzero_bits
3580	on the register (from a splitter in the MD file, for example)
3581	will get the old information, which is invalid.
3582
3583	Since nowadays we can create registers during combine just fine,
3584	we should just create a new one here, not reuse i2dest. */
3585
3586	/* First try to split using the original register as a
3587	scratch register. */
3588	parallel = gen_rtx_PARALLEL (VOIDmode,
3589	gen_rtvec (2, newpat,
3590	gen_rtx_CLOBBER (VOIDmode,
3591	i2dest)));
3592	m_split_insn = combine_split_insns (pattern: parallel, insn: i3);
3593
3594	/* If that didn't work, try changing the mode of I2DEST if
3595	we can. */
3596	if (m_split_insn == 0
3597	&& new_mode != GET_MODE (i2dest)
3598	&& new_mode != VOIDmode
3599	&& can_change_dest_mode (x: i2dest, added_sets: added_sets_2, mode: new_mode))
3600	{
3601	machine_mode old_mode = GET_MODE (i2dest);
3602	rtx ni2dest;
3603
3604	if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3605	ni2dest = gen_rtx_REG (new_mode, REGNO (i2dest));
3606	else
3607	{
3608	subst_mode (REGNO (i2dest), newval: new_mode);
3609	ni2dest = regno_reg_rtx[REGNO (i2dest)];
3610	}
3611
3612	parallel = (gen_rtx_PARALLEL
3613	(VOIDmode,
3614	gen_rtvec (2, newpat,
3615	gen_rtx_CLOBBER (VOIDmode,
3616	ni2dest))));
3617	m_split_insn = combine_split_insns (pattern: parallel, insn: i3);
3618
3619	if (m_split_insn == 0
3620	&& REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
3621	{
3622	struct undo *buf;
3623
3624	adjust_reg_mode (regno_reg_rtx[REGNO (i2dest)], old_mode);
3625	buf = undobuf.undos;
3626	undobuf.undos = buf->next;
3627	buf->next = undobuf.frees;
3628	undobuf.frees = buf;
3629	}
3630	}
3631
3632	i2scratch = m_split_insn != 0;
3633	}
3634
3635	/* If recog_for_combine has discarded clobbers, try to use them
3636	again for the split. */
3637	if (m_split_insn == 0 && newpat_vec_with_clobbers)
3638	{
3639	parallel = gen_rtx_PARALLEL (VOIDmode, newpat_vec_with_clobbers);
3640	m_split_insn = combine_split_insns (pattern: parallel, insn: i3);
3641	}
3642
3643	if (m_split_insn && NEXT_INSN (insn: m_split_insn) == NULL_RTX)
3644	{
3645	rtx m_split_pat = PATTERN (insn: m_split_insn);
3646	insn_code_number = recog_for_combine (&m_split_pat, i3, &new_i3_notes);
3647	if (insn_code_number >= 0)
3648	newpat = m_split_pat;
3649	}
3650	else if (m_split_insn && NEXT_INSN (insn: NEXT_INSN (insn: m_split_insn)) == NULL_RTX
3651	&& (next_nonnote_nondebug_insn (i2) == i3
3652	|| !modified_between_p (PATTERN (insn: m_split_insn), i2, i3)))
3653	{
3654	rtx i2set, i3set;
3655	rtx newi3pat = PATTERN (insn: NEXT_INSN (insn: m_split_insn));
3656	newi2pat = PATTERN (insn: m_split_insn);
3657
3658	i3set = single_set (insn: NEXT_INSN (insn: m_split_insn));
3659	i2set = single_set (insn: m_split_insn);
3660
3661	i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3662
3663	/* If I2 or I3 has multiple SETs, we won't know how to track
3664	register status, so don't use these insns. If I2's destination
3665	is used between I2 and I3, we also can't use these insns. */
3666
3667	if (i2_code_number >= 0 && i2set && i3set
3668	&& (next_nonnote_nondebug_insn (i2) == i3
3669	|| ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
3670	insn_code_number = recog_for_combine (&newi3pat, i3,
3671	&new_i3_notes);
3672	if (insn_code_number >= 0)
3673	newpat = newi3pat;
3674
3675	/* It is possible that both insns now set the destination of I3.
3676	If so, we must show an extra use of it. */
3677
3678	if (insn_code_number >= 0)
3679	{
3680	rtx new_i3_dest = SET_DEST (i3set);
3681	rtx new_i2_dest = SET_DEST (i2set);
3682
3683	while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
3684	|| GET_CODE (new_i3_dest) == STRICT_LOW_PART
3685	|| GET_CODE (new_i3_dest) == SUBREG)
3686	new_i3_dest = XEXP (new_i3_dest, 0);
3687
3688	while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
3689	|| GET_CODE (new_i2_dest) == STRICT_LOW_PART
3690	|| GET_CODE (new_i2_dest) == SUBREG)
3691	new_i2_dest = XEXP (new_i2_dest, 0);
3692
3693	if (REG_P (new_i3_dest)
3694	&& REG_P (new_i2_dest)
3695	&& REGNO (new_i3_dest) == REGNO (new_i2_dest)
3696	&& REGNO (new_i2_dest) < reg_n_sets_max)
3697	INC_REG_N_SETS (REGNO (new_i2_dest), 1);
3698	}
3699	}
3700
3701	/* If we can split it and use I2DEST, go ahead and see if that
3702	helps things be recognized. Verify that none of the registers
3703	are set between I2 and I3. */
3704	if (insn_code_number < 0
3705	&& (split = find_split_point (&newpat, i3, false)) != 0
3706	/* We need I2DEST in the proper mode. If it is a hard register
3707	or the only use of a pseudo, we can change its mode.
3708	Make sure we don't change a hard register to have a mode that
3709	isn't valid for it, or change the number of registers. */
3710	&& (GET_MODE (*split) == GET_MODE (i2dest)
3711	|| GET_MODE (*split) == VOIDmode
3712	|| can_change_dest_mode (x: i2dest, added_sets: added_sets_2,
3713	GET_MODE (*split)))
3714	&& (next_nonnote_nondebug_insn (i2) == i3
3715	|| !modified_between_p (*split, i2, i3))
3716	/* We can't overwrite I2DEST if its value is still used by
3717	NEWPAT. */
3718	&& ! reg_referenced_p (i2dest, newpat)
3719	/* We should not split a possibly trapping part when we
3720	care about non-call EH and have REG_EH_REGION notes
3721	to distribute. */
3722	&& ! (cfun->can_throw_non_call_exceptions
3723	&& has_non_call_exception
3724	&& may_trap_p (*split)))
3725	{
3726	rtx newdest = i2dest;
3727	enum rtx_code split_code = GET_CODE (*split);
3728	machine_mode split_mode = GET_MODE (*split);
3729	bool subst_done = false;
3730	newi2pat = NULL_RTX;
3731
3732	i2scratch = true;
3733
3734	/* *SPLIT may be part of I2SRC, so make sure we have the
3735	original expression around for later debug processing.
3736	We should not need I2SRC any more in other cases. */
3737	if (MAY_HAVE_DEBUG_BIND_INSNS)
3738	i2src = copy_rtx (i2src);
3739	else
3740	i2src = NULL;
3741
3742	/* Get NEWDEST as a register in the proper mode. We have already
3743	validated that we can do this. */
3744	if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
3745	{
3746	if (REGNO (i2dest) < FIRST_PSEUDO_REGISTER)
3747	newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
3748	else
3749	{
3750	subst_mode (REGNO (i2dest), newval: split_mode);
3751	newdest = regno_reg_rtx[REGNO (i2dest)];
3752	}
3753	}
3754
3755	/* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
3756	an ASHIFT. This can occur if it was inside a PLUS and hence
3757	appeared to be a memory address. This is a kludge. */
3758	if (split_code == MULT
3759	&& CONST_INT_P (XEXP (*split, 1))
3760	&& INTVAL (XEXP (*split, 1)) > 0
3761	&& (i = exact_log2 (UINTVAL (XEXP (*split, 1)))) >= 0)
3762	{
3763	rtx i_rtx = gen_int_shift_amount (split_mode, i);
3764	SUBST (*split, gen_rtx_ASHIFT (split_mode,
3765	XEXP (*split, 0), i_rtx));
3766	/* Update split_code because we may not have a multiply
3767	anymore. */
3768	split_code = GET_CODE (*split);
3769	}
3770
3771	/* Similarly for (plus (mult FOO (const_int pow2))). */
3772	if (split_code == PLUS
3773	&& GET_CODE (XEXP (*split, 0)) == MULT
3774	&& CONST_INT_P (XEXP (XEXP (*split, 0), 1))
3775	&& INTVAL (XEXP (XEXP (*split, 0), 1)) > 0
3776	&& (i = exact_log2 (UINTVAL (XEXP (XEXP (*split, 0), 1)))) >= 0)
3777	{
3778	rtx nsplit = XEXP (*split, 0);
3779	rtx i_rtx = gen_int_shift_amount (GET_MODE (nsplit), i);
3780	SUBST (XEXP (*split, 0), gen_rtx_ASHIFT (GET_MODE (nsplit),
3781	XEXP (nsplit, 0),
3782	i_rtx));
3783	/* Update split_code because we may not have a multiply
3784	anymore. */
3785	split_code = GET_CODE (*split);
3786	}
3787
3788	#ifdef INSN_SCHEDULING
3789	/* If *SPLIT is a paradoxical SUBREG, when we split it, it should
3790	be written as a ZERO_EXTEND. */
3791	if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
3792	{
3793	/* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
3794	what it really is. */
3795	if (load_extend_op (GET_MODE (SUBREG_REG (*split)))
3796	== SIGN_EXTEND)
3797	SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
3798	SUBREG_REG (*split)));
3799	else
3800	SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
3801	SUBREG_REG (*split)));
3802	}
3803	#endif
3804
3805	/* Attempt to split binary operators using arithmetic identities. */
3806	if (BINARY_P (SET_SRC (newpat))
3807	&& split_mode == GET_MODE (SET_SRC (newpat))
3808	&& ! side_effects_p (SET_SRC (newpat)))
3809	{
3810	rtx setsrc = SET_SRC (newpat);
3811	machine_mode mode = GET_MODE (setsrc);
3812	enum rtx_code code = GET_CODE (setsrc);
3813	rtx src_op0 = XEXP (setsrc, 0);
3814	rtx src_op1 = XEXP (setsrc, 1);
3815
3816	/* Split "X = Y op Y" as "Z = Y; X = Z op Z". */
3817	if (rtx_equal_p (src_op0, src_op1))
3818	{
3819	newi2pat = gen_rtx_SET (newdest, src_op0);
3820	SUBST (XEXP (setsrc, 0), newdest);
3821	SUBST (XEXP (setsrc, 1), newdest);
3822	subst_done = true;
3823	}
3824	/* Split "((P op Q) op R) op S" where op is PLUS or MULT. */
3825	else if ((code == PLUS || code == MULT)
3826	&& GET_CODE (src_op0) == code
3827	&& GET_CODE (XEXP (src_op0, 0)) == code
3828	&& (INTEGRAL_MODE_P (mode)
3829	|| (FLOAT_MODE_P (mode)
3830	&& flag_unsafe_math_optimizations)))
3831	{
3832	rtx p = XEXP (XEXP (src_op0, 0), 0);
3833	rtx q = XEXP (XEXP (src_op0, 0), 1);
3834	rtx r = XEXP (src_op0, 1);
3835	rtx s = src_op1;
3836
3837	/* Split both "((X op Y) op X) op Y" and
3838	"((X op Y) op Y) op X" as "T op T" where T is
3839	"X op Y". */
3840	if ((rtx_equal_p (p,r) && rtx_equal_p (q,s))
3841	|| (rtx_equal_p (p,s) && rtx_equal_p (q,r)))
3842	{
3843	newi2pat = gen_rtx_SET (newdest, XEXP (src_op0, 0));
3844	SUBST (XEXP (setsrc, 0), newdest);
3845	SUBST (XEXP (setsrc, 1), newdest);
3846	subst_done = true;
3847	}
3848	/* Split "((X op X) op Y) op Y)" as "T op T" where
3849	T is "X op Y". */
3850	else if (rtx_equal_p (p,q) && rtx_equal_p (r,s))
3851	{
3852	rtx tmp = simplify_gen_binary (code, mode, op0: p, op1: r);
3853	newi2pat = gen_rtx_SET (newdest, tmp);
3854	SUBST (XEXP (setsrc, 0), newdest);
3855	SUBST (XEXP (setsrc, 1), newdest);
3856	subst_done = true;
3857	}
3858	}
3859	}
3860
3861	if (!subst_done)
3862	{
3863	newi2pat = gen_rtx_SET (newdest, *split);
3864	SUBST (*split, newdest);
3865	}
3866
3867	i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3868
3869	/* recog_for_combine might have added CLOBBERs to newi2pat.
3870	Make sure NEWPAT does not depend on the clobbered regs. */
3871	if (GET_CODE (newi2pat) == PARALLEL)
3872	for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
3873	if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
3874	{
3875	rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
3876	if (reg_overlap_mentioned_p (reg, newpat))
3877	{
3878	undo_all ();
3879	return 0;
3880	}
3881	}
3882
3883	/* If the split point was a MULT and we didn't have one before,
3884	don't use one now. */
3885	if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
3886	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3887	}
3888	}
3889
3890	/* Check for a case where we loaded from memory in a narrow mode and
3891	then sign extended it, but we need both registers. In that case,
3892	we have a PARALLEL with both loads from the same memory location.
3893	We can split this into a load from memory followed by a register-register
3894	copy. This saves at least one insn, more if register allocation can
3895	eliminate the copy.
3896
3897	We cannot do this if the destination of the first assignment is a
3898	condition code register. We eliminate this case by making sure
3899	the SET_DEST and SET_SRC have the same mode.
3900
3901	We cannot do this if the destination of the second assignment is
3902	a register that we have already assumed is zero-extended. Similarly
3903	for a SUBREG of such a register. */
3904
3905	else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
3906	&& GET_CODE (newpat) == PARALLEL
3907	&& XVECLEN (newpat, 0) == 2
3908	&& GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3909	&& GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
3910	&& (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
3911	== GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
3912	&& GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3913	&& rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
3914	XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
3915	&& !modified_between_p (SET_SRC (XVECEXP (newpat, 0, 1)), i2, i3)
3916	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3917	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3918	&& ! (temp_expr = SET_DEST (XVECEXP (newpat, 0, 1)),
3919	(REG_P (temp_expr)
3920	&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3921	&& known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3922	BITS_PER_WORD)
3923	&& known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3924	HOST_BITS_PER_INT)
3925	&& (reg_stat[REGNO (temp_expr)].nonzero_bits
3926	!= GET_MODE_MASK (word_mode))))
3927	&& ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
3928	&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
3929	(REG_P (temp_expr)
3930	&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
3931	&& known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3932	BITS_PER_WORD)
3933	&& known_lt (GET_MODE_PRECISION (GET_MODE (temp_expr)),
3934	HOST_BITS_PER_INT)
3935	&& (reg_stat[REGNO (temp_expr)].nonzero_bits
3936	!= GET_MODE_MASK (word_mode)))))
3937	&& ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3938	SET_SRC (XVECEXP (newpat, 0, 1)))
3939	&& ! find_reg_note (i3, REG_UNUSED,
3940	SET_DEST (XVECEXP (newpat, 0, 0))))
3941	{
3942	rtx ni2dest;
3943
3944	newi2pat = XVECEXP (newpat, 0, 0);
3945	ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
3946	newpat = XVECEXP (newpat, 0, 1);
3947	SUBST (SET_SRC (newpat),
3948	gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
3949	i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
3950
3951	if (i2_code_number >= 0)
3952	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
3953
3954	if (insn_code_number >= 0)
3955	swap_i2i3 = 1;
3956	}
3957
3958	/* Similarly, check for a case where we have a PARALLEL of two independent
3959	SETs but we started with three insns. In this case, we can do the sets
3960	as two separate insns. This case occurs when some SET allows two
3961	other insns to combine, but the destination of that SET is still live.
3962
3963	Also do this if we started with two insns and (at least) one of the
3964	resulting sets is a noop; this noop will be deleted later.
3965
3966	Also do this if we started with two insns neither of which was a simple
3967	move. */
3968
3969	else if (insn_code_number < 0 && asm_noperands (newpat) < 0
3970	&& GET_CODE (newpat) == PARALLEL
3971	&& XVECLEN (newpat, 0) == 2
3972	&& GET_CODE (XVECEXP (newpat, 0, 0)) == SET
3973	&& GET_CODE (XVECEXP (newpat, 0, 1)) == SET
3974	&& (i1
3975	|| set_noop_p (XVECEXP (newpat, 0, 0))
3976	|| set_noop_p (XVECEXP (newpat, 0, 1))
3977	|| (!i2_was_move && !i3_was_move))
3978	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
3979	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
3980	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
3981	&& GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
3982	&& ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
3983	XVECEXP (newpat, 0, 0))
3984	&& ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
3985	XVECEXP (newpat, 0, 1))
3986	&& ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
3987	&& contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
3988	{
3989	rtx set0 = XVECEXP (newpat, 0, 0);
3990	rtx set1 = XVECEXP (newpat, 0, 1);
3991
3992	/* Normally, it doesn't matter which of the two is done first, but
3993	one which uses any regs/memory set in between i2 and i3 can't
3994	be first. The PARALLEL might also have been pre-existing in i3,
3995	so we need to make sure that we won't wrongly hoist a SET to i2
3996	that would conflict with a death note present in there, or would
3997	have its dest modified between i2 and i3. */
3998	if (!modified_between_p (SET_SRC (set1), i2, i3)
3999	&& !(REG_P (SET_DEST (set1))
4000	&& find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
4001	&& !(GET_CODE (SET_DEST (set1)) == SUBREG
4002	&& find_reg_note (i2, REG_DEAD,
4003	SUBREG_REG (SET_DEST (set1))))
4004	&& !modified_between_p (SET_DEST (set1), i2, i3)
4005	/* If I3 is a jump, ensure that set0 is a jump so that
4006	we do not create invalid RTL. */
4007	&& (!JUMP_P (i3) || SET_DEST (set0) == pc_rtx)
4008	)
4009	{
4010	newi2pat = set1;
4011	newpat = set0;
4012	}
4013	else if (!modified_between_p (SET_SRC (set0), i2, i3)
4014	&& !(REG_P (SET_DEST (set0))
4015	&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
4016	&& !(GET_CODE (SET_DEST (set0)) == SUBREG
4017	&& find_reg_note (i2, REG_DEAD,
4018	SUBREG_REG (SET_DEST (set0))))
4019	&& !modified_between_p (SET_DEST (set0), i2, i3)
4020	/* If I3 is a jump, ensure that set1 is a jump so that
4021	we do not create invalid RTL. */
4022	&& (!JUMP_P (i3) || SET_DEST (set1) == pc_rtx)
4023	)
4024	{
4025	newi2pat = set0;
4026	newpat = set1;
4027	}
4028	else
4029	{
4030	undo_all ();
4031	return 0;
4032	}
4033
4034	i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
4035
4036	if (i2_code_number >= 0)
4037	{
4038	/* recog_for_combine might have added CLOBBERs to newi2pat.
4039	Make sure NEWPAT does not depend on the clobbered regs. */
4040	if (GET_CODE (newi2pat) == PARALLEL)
4041	{
4042	for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
4043	if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
4044	{
4045	rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
4046	if (reg_overlap_mentioned_p (reg, newpat))
4047	{
4048	undo_all ();
4049	return 0;
4050	}
4051	}
4052	}
4053
4054	insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
4055
4056	/* Likewise, recog_for_combine might have added clobbers to NEWPAT.
4057	Checking that the SET0's SET_DEST and SET1's SET_DEST aren't
4058	mentioned/clobbered, ensures NEWI2PAT's SET_DEST is live. */
4059	if (insn_code_number >= 0 && GET_CODE (newpat) == PARALLEL)
4060	{
4061	for (i = XVECLEN (newpat, 0) - 1; i >= 0; i--)
4062	if (GET_CODE (XVECEXP (newpat, 0, i)) == CLOBBER)
4063	{
4064	rtx reg = XEXP (XVECEXP (newpat, 0, i), 0);
4065	if (reg_overlap_mentioned_p (reg, SET_DEST (set0))
4066	|| reg_overlap_mentioned_p (reg, SET_DEST (set1)))
4067	{
4068	undo_all ();
4069	return 0;
4070	}
4071	}
4072	}
4073
4074	if (insn_code_number >= 0)
4075	split_i2i3 = true;
4076	}
4077	}
4078
4079	/* If it still isn't recognized, fail and change things back the way they
4080	were. */
4081	if ((insn_code_number < 0
4082	/* Is the result a reasonable ASM_OPERANDS? */
4083	&& (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
4084	{
4085	undo_all ();
4086	return 0;
4087	}
4088
4089	/* If we had to change another insn, make sure it is valid also. */
4090	if (undobuf.other_insn)
4091	{
4092	CLEAR_HARD_REG_SET (set&: newpat_used_regs);
4093
4094	other_pat = PATTERN (insn: undobuf.other_insn);
4095	other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
4096	&new_other_notes);
4097
4098	if (other_code_number < 0 && ! check_asm_operands (other_pat))
4099	{
4100	undo_all ();
4101	return 0;
4102	}
4103	}
4104
4105	/* Only allow this combination if insn_cost reports that the
4106	replacement instructions are cheaper than the originals. */
4107	if (!combine_validate_cost (i0, i1, i2, i3, newpat, newi2pat, newotherpat: other_pat))
4108	{
4109	undo_all ();
4110	return 0;
4111	}
4112
4113	if (MAY_HAVE_DEBUG_BIND_INSNS)
4114	{
4115	struct undo *undo;
4116
4117	for (undo = undobuf.undos; undo; undo = undo->next)
4118	if (undo->kind == UNDO_MODE)
4119	{
4120	rtx reg = regno_reg_rtx[undo->where.regno];
4121	machine_mode new_mode = GET_MODE (reg);
4122	machine_mode old_mode = undo->old_contents.m;
4123
4124	/* Temporarily revert mode back. */
4125	adjust_reg_mode (reg, old_mode);
4126
4127	if (reg == i2dest && i2scratch)
4128	{
4129	/* If we used i2dest as a scratch register with a
4130	different mode, substitute it for the original
4131	i2src while its original mode is temporarily
4132	restored, and then clear i2scratch so that we don't
4133	do it again later. */
4134	propagate_for_debug (i2, last_combined_insn, reg, i2src,
4135	this_basic_block);
4136	i2scratch = false;
4137	/* Put back the new mode. */
4138	adjust_reg_mode (reg, new_mode);
4139	}
4140	else
4141	{
4142	rtx tempreg = gen_raw_REG (old_mode, REGNO (reg));
4143	rtx_insn *first, *last;
4144
4145	if (reg == i2dest)
4146	{
4147	first = i2;
4148	last = last_combined_insn;
4149	}
4150	else
4151	{
4152	first = i3;
4153	last = undobuf.other_insn;
4154	gcc_assert (last);
4155	if (DF_INSN_LUID (last)
4156	< DF_INSN_LUID (last_combined_insn))
4157	last = last_combined_insn;
4158	}
4159
4160	/* We're dealing with a reg that changed mode but not
4161	meaning, so we want to turn it into a subreg for
4162	the new mode. However, because of REG sharing and
4163	because its mode had already changed, we have to do
4164	it in two steps. First, replace any debug uses of
4165	reg, with its original mode temporarily restored,
4166	with this copy we have created; then, replace the
4167	copy with the SUBREG of the original shared reg,
4168	once again changed to the new mode. */
4169	propagate_for_debug (first, last, reg, tempreg,
4170	this_basic_block);
4171	adjust_reg_mode (reg, new_mode);
4172	propagate_for_debug (first, last, tempreg,
4173	lowpart_subreg (outermode: old_mode, op: reg, innermode: new_mode),
4174	this_basic_block);
4175	}
4176	}
4177	}
4178
4179	/* If we will be able to accept this, we have made a
4180	change to the destination of I3. This requires us to
4181	do a few adjustments. */
4182
4183	if (changed_i3_dest)
4184	{
4185	PATTERN (insn: i3) = newpat;
4186	adjust_for_new_dest (insn: i3);
4187	}
4188
4189	/* We now know that we can do this combination. Merge the insns and
4190	update the status of registers and LOG_LINKS. */
4191
4192	if (undobuf.other_insn)
4193	{
4194	rtx note, next;
4195
4196	PATTERN (insn: undobuf.other_insn) = other_pat;
4197
4198	/* If any of the notes in OTHER_INSN were REG_DEAD or REG_UNUSED,
4199	ensure that they are still valid. Then add any non-duplicate
4200	notes added by recog_for_combine. */
4201	for (note = REG_NOTES (undobuf.other_insn); note; note = next)
4202	{
4203	next = XEXP (note, 1);
4204
4205	if ((REG_NOTE_KIND (note) == REG_DEAD
4206	&& !reg_referenced_p (XEXP (note, 0),
4207	PATTERN (insn: undobuf.other_insn)))
4208	||(REG_NOTE_KIND (note) == REG_UNUSED
4209	&& !reg_set_p (XEXP (note, 0),
4210	PATTERN (insn: undobuf.other_insn)))
4211	/* Simply drop equal note since it may be no longer valid
4212	for other_insn. It may be possible to record that CC
4213	register is changed and only discard those notes, but
4214	in practice it's unnecessary complication and doesn't
4215	give any meaningful improvement.
4216
4217	See PR78559. */
4218	|| REG_NOTE_KIND (note) == REG_EQUAL
4219	|| REG_NOTE_KIND (note) == REG_EQUIV)
4220	remove_note (undobuf.other_insn, note);
4221	}
4222
4223	distribute_notes (new_other_notes, undobuf.other_insn,
4224	undobuf.other_insn, NULL, NULL_RTX, NULL_RTX,
4225	NULL_RTX);
4226	}
4227
4228	if (swap_i2i3)
4229	{
4230	/* I3 now uses what used to be its destination and which is now
4231	I2's destination. This requires us to do a few adjustments. */
4232	PATTERN (insn: i3) = newpat;
4233	adjust_for_new_dest (insn: i3);
4234	}
4235
4236	if (swap_i2i3 || split_i2i3)
4237	{
4238	/* We might need a LOG_LINK from I3 to I2. But then we used to
4239	have one, so we still will.
4240
4241	However, some later insn might be using I2's dest and have
4242	a LOG_LINK pointing at I3. We should change it to point at
4243	I2 instead. */
4244
4245	/* newi2pat is usually a SET here; however, recog_for_combine might
4246	have added some clobbers. */
4247	rtx x = newi2pat;
4248	if (GET_CODE (x) == PARALLEL)
4249	x = XVECEXP (newi2pat, 0, 0);
4250
4251	if (REG_P (SET_DEST (x))
4252	|| (GET_CODE (SET_DEST (x)) == SUBREG
4253	&& REG_P (SUBREG_REG (SET_DEST (x)))))
4254	{
4255	unsigned int regno = reg_or_subregno (SET_DEST (x));
4256
4257	bool done = false;
4258	for (rtx_insn *insn = NEXT_INSN (insn: i3);
4259	!done
4260	&& insn
4261	&& INSN_P (insn)
4262	&& BLOCK_FOR_INSN (insn) == this_basic_block;
4263	insn = NEXT_INSN (insn))
4264	{
4265	if (DEBUG_INSN_P (insn))
4266	continue;
4267	struct insn_link *link;
4268	FOR_EACH_LOG_LINK (link, insn)
4269	if (link->insn == i3 && link->regno == regno)
4270	{
4271	link->insn = i2;
4272	done = true;
4273	break;
4274	}
4275	}
4276	}
4277	}
4278
4279	{
4280	rtx i3notes, i2notes, i1notes = 0, i0notes = 0;
4281	struct insn_link *i3links, *i2links, *i1links = 0, *i0links = 0;
4282	rtx midnotes = 0;
4283	int from_luid;
4284	/* Compute which registers we expect to eliminate. newi2pat may be setting
4285	either i3dest or i2dest, so we must check it. */
4286	rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
4287	|| i2dest_in_i2src || i2dest_in_i1src || i2dest_in_i0src
4288	|| !i2dest_killed
4289	? 0 : i2dest);
4290	/* For i1, we need to compute both local elimination and global
4291	elimination information with respect to newi2pat because i1dest
4292	may be the same as i3dest, in which case newi2pat may be setting
4293	i1dest. Global information is used when distributing REG_DEAD
4294	note for i2 and i3, in which case it does matter if newi2pat sets
4295	i1dest or not.
4296
4297	Local information is used when distributing REG_DEAD note for i1,
4298	in which case it doesn't matter if newi2pat sets i1dest or not.
4299	See PR62151, if we have four insns combination:
4300	i0: r0 <- i0src
4301	i1: r1 <- i1src (using r0)
4302	REG_DEAD (r0)
4303	i2: r0 <- i2src (using r1)
4304	i3: r3 <- i3src (using r0)
4305	ix: using r0
4306	From i1's point of view, r0 is eliminated, no matter if it is set
4307	by newi2pat or not. In other words, REG_DEAD info for r0 in i1
4308	should be discarded.
4309
4310	Note local information only affects cases in forms like "I1->I2->I3",
4311	"I0->I1->I2->I3" or "I0&I1->I2, I2->I3". For other cases like
4312	"I0->I1, I1&I2->I3" or "I1&I2->I3", newi2pat won't set i1dest or
4313	i0dest anyway. */
4314	rtx local_elim_i1 = (i1 == 0 || i1dest_in_i1src || i1dest_in_i0src
4315	|| !i1dest_killed
4316	? 0 : i1dest);
4317	rtx elim_i1 = (local_elim_i1 == 0
4318	|| (newi2pat && reg_set_p (i1dest, newi2pat))
4319	? 0 : i1dest);
4320	/* Same case as i1. */
4321	rtx local_elim_i0 = (i0 == 0 || i0dest_in_i0src || !i0dest_killed
4322	? 0 : i0dest);
4323	rtx elim_i0 = (local_elim_i0 == 0
4324	|| (newi2pat && reg_set_p (i0dest, newi2pat))
4325	? 0 : i0dest);
4326
4327	/* Get the old REG_NOTES and LOG_LINKS from all our insns and
4328	clear them. */
4329	i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
4330	i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
4331	if (i1)
4332	i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
4333	if (i0)
4334	i0notes = REG_NOTES (i0), i0links = LOG_LINKS (i0);
4335
4336	/* Ensure that we do not have something that should not be shared but
4337	occurs multiple times in the new insns. Check this by first
4338	resetting all the `used' flags and then copying anything is shared. */
4339
4340	reset_used_flags (i3notes);
4341	reset_used_flags (i2notes);
4342	reset_used_flags (i1notes);
4343	reset_used_flags (i0notes);
4344	reset_used_flags (newpat);
4345	reset_used_flags (newi2pat);
4346	if (undobuf.other_insn)
4347	reset_used_flags (PATTERN (insn: undobuf.other_insn));
4348
4349	i3notes = copy_rtx_if_shared (i3notes);
4350	i2notes = copy_rtx_if_shared (i2notes);
4351	i1notes = copy_rtx_if_shared (i1notes);
4352	i0notes = copy_rtx_if_shared (i0notes);
4353	newpat = copy_rtx_if_shared (newpat);
4354	newi2pat = copy_rtx_if_shared (newi2pat);
4355	if (undobuf.other_insn)
4356	reset_used_flags (PATTERN (insn: undobuf.other_insn));
4357
4358	INSN_CODE (i3) = insn_code_number;
4359	PATTERN (insn: i3) = newpat;
4360
4361	if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
4362	{
4363	for (rtx link = CALL_INSN_FUNCTION_USAGE (i3); link;
4364	link = XEXP (link, 1))
4365	{
4366	if (substed_i2)
4367	{
4368	/* I2SRC must still be meaningful at this point. Some
4369	splitting operations can invalidate I2SRC, but those
4370	operations do not apply to calls. */
4371	gcc_assert (i2src);
4372	XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4373	i2dest, i2src);
4374	}
4375	if (substed_i1)
4376	XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4377	i1dest, i1src);
4378	if (substed_i0)
4379	XEXP (link, 0) = simplify_replace_rtx (XEXP (link, 0),
4380	i0dest, i0src);
4381	}
4382	}
4383
4384	if (undobuf.other_insn)
4385	INSN_CODE (undobuf.other_insn) = other_code_number;
4386
4387	/* We had one special case above where I2 had more than one set and
4388	we replaced a destination of one of those sets with the destination
4389	of I3. In that case, we have to update LOG_LINKS of insns later
4390	in this basic block. Note that this (expensive) case is rare.
4391
4392	Also, in this case, we must pretend that all REG_NOTEs for I2
4393	actually came from I3, so that REG_UNUSED notes from I2 will be
4394	properly handled. */
4395
4396	if (i3_subst_into_i2)
4397	{
4398	for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
4399	if ((GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == SET
4400	|| GET_CODE (XVECEXP (PATTERN (i2), 0, i)) == CLOBBER)
4401	&& REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
4402	&& SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
4403	&& ! find_reg_note (i2, REG_UNUSED,
4404	SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
4405	for (temp_insn = NEXT_INSN (insn: i2);
4406	temp_insn
4407	&& (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
4408	|| BB_HEAD (this_basic_block) != temp_insn);
4409	temp_insn = NEXT_INSN (insn: temp_insn))
4410	if (temp_insn != i3 && NONDEBUG_INSN_P (temp_insn))
4411	FOR_EACH_LOG_LINK (link, temp_insn)
4412	if (link->insn == i2)
4413	link->insn = i3;
4414
4415	if (i3notes)
4416	{
4417	rtx link = i3notes;
4418	while (XEXP (link, 1))
4419	link = XEXP (link, 1);
4420	XEXP (link, 1) = i2notes;
4421	}
4422	else
4423	i3notes = i2notes;
4424	i2notes = 0;
4425	}
4426
4427	LOG_LINKS (i3) = NULL;
4428	REG_NOTES (i3) = 0;
4429	LOG_LINKS (i2) = NULL;
4430	REG_NOTES (i2) = 0;
4431
4432	if (newi2pat)
4433	{
4434	if (MAY_HAVE_DEBUG_BIND_INSNS && i2scratch)
4435	propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4436	this_basic_block);
4437	INSN_CODE (i2) = i2_code_number;
4438	PATTERN (insn: i2) = newi2pat;
4439	}
4440	else
4441	{
4442	if (MAY_HAVE_DEBUG_BIND_INSNS && i2src)
4443	propagate_for_debug (i2, last_combined_insn, i2dest, i2src,
4444	this_basic_block);
4445	SET_INSN_DELETED (i2);
4446	}
4447
4448	if (i1)
4449	{
4450	LOG_LINKS (i1) = NULL;
4451	REG_NOTES (i1) = 0;
4452	if (MAY_HAVE_DEBUG_BIND_INSNS)
4453	propagate_for_debug (i1, last_combined_insn, i1dest, i1src,
4454	this_basic_block);
4455	SET_INSN_DELETED (i1);
4456	}
4457
4458	if (i0)
4459	{
4460	LOG_LINKS (i0) = NULL;
4461	REG_NOTES (i0) = 0;
4462	if (MAY_HAVE_DEBUG_BIND_INSNS)
4463	propagate_for_debug (i0, last_combined_insn, i0dest, i0src,
4464	this_basic_block);
4465	SET_INSN_DELETED (i0);
4466	}
4467
4468	/* Get death notes for everything that is now used in either I3 or
4469	I2 and used to die in a previous insn. If we built two new
4470	patterns, move from I1 to I2 then I2 to I3 so that we get the
4471	proper movement on registers that I2 modifies. */
4472
4473	if (i0)
4474	from_luid = DF_INSN_LUID (i0);
4475	else if (i1)
4476	from_luid = DF_INSN_LUID (i1);
4477	else
4478	from_luid = DF_INSN_LUID (i2);
4479	if (newi2pat)
4480	move_deaths (newi2pat, NULL_RTX, from_luid, i2, &midnotes);
4481	move_deaths (newpat, newi2pat, from_luid, i3, &midnotes);
4482
4483	/* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
4484	if (i3notes)
4485	distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL,
4486	elim_i2, elim_i1, elim_i0);
4487	if (i2notes)
4488	distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL,
4489	elim_i2, elim_i1, elim_i0);
4490	if (i1notes)
4491	distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL,
4492	elim_i2, local_elim_i1, local_elim_i0);
4493	if (i0notes)
4494	distribute_notes (i0notes, i0, i3, newi2pat ? i2 : NULL,
4495	elim_i2, elim_i1, local_elim_i0);
4496	if (midnotes)
4497	distribute_notes (midnotes, NULL, i3, newi2pat ? i2 : NULL,
4498	elim_i2, elim_i1, elim_i0);
4499
4500	/* Distribute any notes added to I2 or I3 by recog_for_combine. We
4501	know these are REG_UNUSED and want them to go to the desired insn,
4502	so we always pass it as i3. */
4503
4504	if (newi2pat && new_i2_notes)
4505	distribute_notes (new_i2_notes, i2, i2, NULL, NULL_RTX, NULL_RTX,
4506	NULL_RTX);
4507
4508	if (new_i3_notes)
4509	distribute_notes (new_i3_notes, i3, i3, NULL, NULL_RTX, NULL_RTX,
4510	NULL_RTX);
4511
4512	/* If I3DEST was used in I3SRC, it really died in I3. We may need to
4513	put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
4514	I3DEST, the death must be somewhere before I2, not I3. If we passed I3
4515	in that case, it might delete I2. Similarly for I2 and I1.
4516	Show an additional death due to the REG_DEAD note we make here. If
4517	we discard it in distribute_notes, we will decrement it again. */
4518
4519	if (i3dest_killed)
4520	{
4521	rtx new_note = alloc_reg_note (REG_DEAD, i3dest_killed, NULL_RTX);
4522	if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
4523	distribute_notes (new_note, NULL, i2, NULL, elim_i2,
4524	elim_i1, elim_i0);
4525	else
4526	distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4527	elim_i2, elim_i1, elim_i0);
4528	}
4529
4530	if (i2dest_in_i2src)
4531	{
4532	rtx new_note = alloc_reg_note (REG_DEAD, i2dest, NULL_RTX);
4533	if (newi2pat && reg_set_p (i2dest, newi2pat))
4534	distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4535	NULL_RTX, NULL_RTX);
4536	else
4537	distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4538	NULL_RTX, NULL_RTX, NULL_RTX);
4539	}
4540
4541	if (i1dest_in_i1src)
4542	{
4543	rtx new_note = alloc_reg_note (REG_DEAD, i1dest, NULL_RTX);
4544	if (newi2pat && reg_set_p (i1dest, newi2pat))
4545	distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4546	NULL_RTX, NULL_RTX);
4547	else
4548	distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4549	NULL_RTX, NULL_RTX, NULL_RTX);
4550	}
4551
4552	if (i0dest_in_i0src)
4553	{
4554	rtx new_note = alloc_reg_note (REG_DEAD, i0dest, NULL_RTX);
4555	if (newi2pat && reg_set_p (i0dest, newi2pat))
4556	distribute_notes (new_note, NULL, i2, NULL, NULL_RTX,
4557	NULL_RTX, NULL_RTX);
4558	else
4559	distribute_notes (new_note, NULL, i3, newi2pat ? i2 : NULL,
4560	NULL_RTX, NULL_RTX, NULL_RTX);
4561	}
4562
4563	distribute_links (i3links);
4564	distribute_links (i2links);
4565	distribute_links (i1links);
4566	distribute_links (i0links);
4567
4568	if (REG_P (i2dest))
4569	{
4570	struct insn_link *link;
4571	rtx_insn *i2_insn = 0;
4572	rtx i2_val = 0, set;
4573
4574	/* The insn that used to set this register doesn't exist, and
4575	this life of the register may not exist either. See if one of
4576	I3's links points to an insn that sets I2DEST. If it does,
4577	that is now the last known value for I2DEST. If we don't update
4578	this and I2 set the register to a value that depended on its old
4579	contents, we will get confused. If this insn is used, thing
4580	will be set correctly in combine_instructions. */
4581	FOR_EACH_LOG_LINK (link, i3)
4582	if ((set = single_set (insn: link->insn)) != 0
4583	&& rtx_equal_p (i2dest, SET_DEST (set)))
4584	i2_insn = link->insn, i2_val = SET_SRC (set);
4585
4586	record_value_for_reg (i2dest, i2_insn, i2_val);
4587
4588	/* If the reg formerly set in I2 died only once and that was in I3,
4589	zero its use count so it won't make `reload' do any work. */
4590	if (! added_sets_2
4591	&& (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
4592	&& ! i2dest_in_i2src
4593	&& REGNO (i2dest) < reg_n_sets_max)
4594	INC_REG_N_SETS (REGNO (i2dest), -1);
4595	}
4596
4597	if (i1 && REG_P (i1dest))
4598	{
4599	struct insn_link *link;
4600	rtx_insn *i1_insn = 0;
4601	rtx i1_val = 0, set;
4602
4603	FOR_EACH_LOG_LINK (link, i3)
4604	if ((set = single_set (insn: link->insn)) != 0
4605	&& rtx_equal_p (i1dest, SET_DEST (set)))
4606	i1_insn = link->insn, i1_val = SET_SRC (set);
4607
4608	record_value_for_reg (i1dest, i1_insn, i1_val);
4609
4610	if (! added_sets_1
4611	&& ! i1dest_in_i1src
4612	&& REGNO (i1dest) < reg_n_sets_max)
4613	INC_REG_N_SETS (REGNO (i1dest), -1);
4614	}
4615
4616	if (i0 && REG_P (i0dest))
4617	{
4618	struct insn_link *link;
4619	rtx_insn *i0_insn = 0;
4620	rtx i0_val = 0, set;
4621
4622	FOR_EACH_LOG_LINK (link, i3)
4623	if ((set = single_set (insn: link->insn)) != 0
4624	&& rtx_equal_p (i0dest, SET_DEST (set)))
4625	i0_insn = link->insn, i0_val = SET_SRC (set);
4626
4627	record_value_for_reg (i0dest, i0_insn, i0_val);
4628
4629	if (! added_sets_0
4630	&& ! i0dest_in_i0src
4631	&& REGNO (i0dest) < reg_n_sets_max)
4632	INC_REG_N_SETS (REGNO (i0dest), -1);
4633	}
4634
4635	/* Update reg_stat[].nonzero_bits et al for any changes that may have
4636	been made to this insn. The order is important, because newi2pat
4637	can affect nonzero_bits of newpat. */
4638	if (newi2pat)
4639	note_pattern_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
4640	note_pattern_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
4641	}
4642
4643	if (undobuf.other_insn != NULL_RTX)
4644	{
4645	if (dump_file)
4646	{
4647	fprintf (stream: dump_file, format: "modifying other_insn ");
4648	dump_insn_slim (dump_file, undobuf.other_insn);
4649	}
4650	df_insn_rescan (undobuf.other_insn);
4651	}
4652
4653	if (i0 && !(NOTE_P (i0) && (NOTE_KIND (i0) == NOTE_INSN_DELETED)))
4654	{
4655	if (dump_file)
4656	{
4657	fprintf (stream: dump_file, format: "modifying insn i0 ");
4658	dump_insn_slim (dump_file, i0);
4659	}
4660	df_insn_rescan (i0);
4661	}
4662
4663	if (i1 && !(NOTE_P (i1) && (NOTE_KIND (i1) == NOTE_INSN_DELETED)))
4664	{
4665	if (dump_file)
4666	{
4667	fprintf (stream: dump_file, format: "modifying insn i1 ");
4668	dump_insn_slim (dump_file, i1);
4669	}
4670	df_insn_rescan (i1);
4671	}
4672
4673	if (i2 && !(NOTE_P (i2) && (NOTE_KIND (i2) == NOTE_INSN_DELETED)))
4674	{
4675	if (dump_file)
4676	{
4677	fprintf (stream: dump_file, format: "modifying insn i2 ");
4678	dump_insn_slim (dump_file, i2);
4679	}
4680	df_insn_rescan (i2);
4681	}
4682
4683	if (i3 && !(NOTE_P (i3) && (NOTE_KIND (i3) == NOTE_INSN_DELETED)))
4684	{
4685	if (dump_file)
4686	{
4687	fprintf (stream: dump_file, format: "modifying insn i3 ");
4688	dump_insn_slim (dump_file, i3);
4689	}
4690	df_insn_rescan (i3);
4691	}
4692
4693	/* Set new_direct_jump_p if a new return or simple jump instruction
4694	has been created. Adjust the CFG accordingly. */
4695	if (returnjump_p (i3) || any_uncondjump_p (i3))
4696	{
4697	*new_direct_jump_p = 1;
4698	mark_jump_label (PATTERN (insn: i3), i3, 0);
4699	update_cfg_for_uncondjump (i3);
4700	}
4701
4702	if (undobuf.other_insn != NULL_RTX
4703	&& (returnjump_p (undobuf.other_insn)
4704	|| any_uncondjump_p (undobuf.other_insn)))
4705	{
4706	*new_direct_jump_p = 1;
4707	update_cfg_for_uncondjump (undobuf.other_insn);
4708	}
4709
4710	if (GET_CODE (PATTERN (i3)) == TRAP_IF
4711	&& XEXP (PATTERN (i3), 0) == const1_rtx)
4712	{
4713	basic_block bb = BLOCK_FOR_INSN (insn: i3);
4714	gcc_assert (bb);
4715	remove_edge (split_block (bb, i3));
4716	emit_barrier_after_bb (bb);
4717	*new_direct_jump_p = 1;
4718	}
4719
4720	if (undobuf.other_insn
4721	&& GET_CODE (PATTERN (undobuf.other_insn)) == TRAP_IF
4722	&& XEXP (PATTERN (undobuf.other_insn), 0) == const1_rtx)
4723	{
4724	basic_block bb = BLOCK_FOR_INSN (insn: undobuf.other_insn);
4725	gcc_assert (bb);
4726	remove_edge (split_block (bb, undobuf.other_insn));
4727	emit_barrier_after_bb (bb);
4728	*new_direct_jump_p = 1;
4729	}
4730
4731	/* A noop might also need cleaning up of CFG, if it comes from the
4732	simplification of a jump. */
4733	if (JUMP_P (i3)
4734	&& GET_CODE (newpat) == SET
4735	&& SET_SRC (newpat) == pc_rtx
4736	&& SET_DEST (newpat) == pc_rtx)
4737	{
4738	*new_direct_jump_p = 1;
4739	update_cfg_for_uncondjump (i3);
4740	}
4741
4742	if (undobuf.other_insn != NULL_RTX
4743	&& JUMP_P (undobuf.other_insn)
4744	&& GET_CODE (PATTERN (undobuf.other_insn)) == SET
4745	&& SET_SRC (PATTERN (undobuf.other_insn)) == pc_rtx
4746	&& SET_DEST (PATTERN (undobuf.other_insn)) == pc_rtx)
4747	{
4748	*new_direct_jump_p = 1;
4749	update_cfg_for_uncondjump (undobuf.other_insn);
4750	}
4751
4752	combine_successes++;
4753	undo_commit ();
4754
4755	rtx_insn *ret = newi2pat ? i2 : i3;
4756	if (added_links_insn && DF_INSN_LUID (added_links_insn) < DF_INSN_LUID (ret))
4757	ret = added_links_insn;
4758	if (added_notes_insn && DF_INSN_LUID (added_notes_insn) < DF_INSN_LUID (ret))
4759	ret = added_notes_insn;
4760
4761	return ret;
4762	}
4763
4764	/* Get a marker for undoing to the current state. */
4765
4766	static void *
4767	get_undo_marker (void)
4768	{
4769	return undobuf.undos;
4770	}
4771
4772	/* Undo the modifications up to the marker. */
4773
4774	static void
4775	undo_to_marker (void *marker)
4776	{
4777	struct undo *undo, *next;
4778
4779	for (undo = undobuf.undos; undo != marker; undo = next)
4780	{
4781	gcc_assert (undo);
4782
4783	next = undo->next;
4784	switch (undo->kind)
4785	{
4786	case UNDO_RTX:
4787	*undo->where.r = undo->old_contents.r;
4788	break;
4789	case UNDO_INT:
4790	*undo->where.i = undo->old_contents.i;
4791	break;
4792	case UNDO_MODE:
4793	adjust_reg_mode (regno_reg_rtx[undo->where.regno],
4794	undo->old_contents.m);
4795	break;
4796	case UNDO_LINKS:
4797	*undo->where.l = undo->old_contents.l;
4798	break;
4799	default:
4800	gcc_unreachable ();
4801	}
4802
4803	undo->next = undobuf.frees;
4804	undobuf.frees = undo;
4805	}
4806
4807	undobuf.undos = (struct undo *) marker;
4808	}
4809
4810	/* Undo all the modifications recorded in undobuf. */
4811
4812	static void
4813	undo_all (void)
4814	{
4815	undo_to_marker (marker: 0);
4816	}
4817
4818	/* We've committed to accepting the changes we made. Move all
4819	of the undos to the free list. */
4820
4821	static void
4822	undo_commit (void)
4823	{
4824	struct undo *undo, *next;
4825
4826	for (undo = undobuf.undos; undo; undo = next)
4827	{
4828	next = undo->next;
4829	undo->next = undobuf.frees;
4830	undobuf.frees = undo;
4831	}
4832	undobuf.undos = 0;
4833	}
4834
4835	/* Find the innermost point within the rtx at LOC, possibly LOC itself,
4836	where we have an arithmetic expression and return that point. LOC will
4837	be inside INSN.
4838
4839	try_combine will call this function to see if an insn can be split into
4840	two insns. */
4841
4842	static rtx *
4843	find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
4844	{
4845	rtx x = *loc;
4846	enum rtx_code code = GET_CODE (x);
4847	rtx *split;
4848	unsigned HOST_WIDE_INT len = 0;
4849	HOST_WIDE_INT pos = 0;
4850	bool unsignedp = false;
4851	rtx inner = NULL_RTX;
4852	scalar_int_mode mode, inner_mode;
4853
4854	/* First special-case some codes. */
4855	switch (code)
4856	{
4857	case SUBREG:
4858	#ifdef INSN_SCHEDULING
4859	/* If we are making a paradoxical SUBREG invalid, it becomes a split
4860	point. */
4861	if (MEM_P (SUBREG_REG (x)))
4862	return loc;
4863	#endif
4864	return find_split_point (loc: &SUBREG_REG (x), insn, set_src: false);
4865
4866	case MEM:
4867	/* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
4868	using LO_SUM and HIGH. */
4869	if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
4870	|| GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
4871	{
4872	machine_mode address_mode = get_address_mode (mem: x);
4873
4874	SUBST (XEXP (x, 0),
4875	gen_rtx_LO_SUM (address_mode,
4876	gen_rtx_HIGH (address_mode, XEXP (x, 0)),
4877	XEXP (x, 0)));
4878	return &XEXP (XEXP (x, 0), 0);
4879	}
4880
4881	/* If we have a PLUS whose second operand is a constant and the
4882	address is not valid, perhaps we can split it up using
4883	the machine-specific way to split large constants. We use
4884	the first pseudo-reg (one of the virtual regs) as a placeholder;
4885	it will not remain in the result. */
4886	if (GET_CODE (XEXP (x, 0)) == PLUS
4887	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
4888	&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4889	MEM_ADDR_SPACE (x)))
4890	{
4891	rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
4892	rtx_insn *seq = combine_split_insns (gen_rtx_SET (reg, XEXP (x, 0)),
4893	insn: subst_insn);
4894
4895	/* This should have produced two insns, each of which sets our
4896	placeholder. If the source of the second is a valid address,
4897	we can put both sources together and make a split point
4898	in the middle. */
4899
4900	if (seq
4901	&& NEXT_INSN (insn: seq) != NULL_RTX
4902	&& NEXT_INSN (insn: NEXT_INSN (insn: seq)) == NULL_RTX
4903	&& NONJUMP_INSN_P (seq)
4904	&& GET_CODE (PATTERN (seq)) == SET
4905	&& SET_DEST (PATTERN (seq)) == reg
4906	&& ! reg_mentioned_p (reg,
4907	SET_SRC (PATTERN (seq)))
4908	&& NONJUMP_INSN_P (NEXT_INSN (seq))
4909	&& GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
4910	&& SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
4911	&& memory_address_addr_space_p
4912	(GET_MODE (x), SET_SRC (PATTERN (NEXT_INSN (seq))),
4913	MEM_ADDR_SPACE (x)))
4914	{
4915	rtx src1 = SET_SRC (PATTERN (seq));
4916	rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
4917
4918	/* Replace the placeholder in SRC2 with SRC1. If we can
4919	find where in SRC2 it was placed, that can become our
4920	split point and we can replace this address with SRC2.
4921	Just try two obvious places. */
4922
4923	src2 = replace_rtx (src2, reg, src1);
4924	split = 0;
4925	if (XEXP (src2, 0) == src1)
4926	split = &XEXP (src2, 0);
4927	else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
4928	&& XEXP (XEXP (src2, 0), 0) == src1)
4929	split = &XEXP (XEXP (src2, 0), 0);
4930
4931	if (split)
4932	{
4933	SUBST (XEXP (x, 0), src2);
4934	return split;
4935	}
4936	}
4937
4938	/* If that didn't work and we have a nested plus, like:
4939	((REG1 * CONST1) + REG2) + CONST2 and (REG1 + REG2) + CONST2
4940	is valid address, try to split (REG1 * CONST1). */
4941	if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4942	&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4943	&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4944	&& ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
4945	&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4946	0), 0)))))
4947	{
4948	rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 0);
4949	XEXP (XEXP (XEXP (x, 0), 0), 0) = reg;
4950	if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4951	MEM_ADDR_SPACE (x)))
4952	{
4953	XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4954	return &XEXP (XEXP (XEXP (x, 0), 0), 0);
4955	}
4956	XEXP (XEXP (XEXP (x, 0), 0), 0) = tem;
4957	}
4958	else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
4959	&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
4960	&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
4961	&& ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
4962	&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
4963	0), 1)))))
4964	{
4965	rtx tem = XEXP (XEXP (XEXP (x, 0), 0), 1);
4966	XEXP (XEXP (XEXP (x, 0), 0), 1) = reg;
4967	if (memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4968	MEM_ADDR_SPACE (x)))
4969	{
4970	XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
4971	return &XEXP (XEXP (XEXP (x, 0), 0), 1);
4972	}
4973	XEXP (XEXP (XEXP (x, 0), 0), 1) = tem;
4974	}
4975
4976	/* If that didn't work, perhaps the first operand is complex and
4977	needs to be computed separately, so make a split point there.
4978	This will occur on machines that just support REG + CONST
4979	and have a constant moved through some previous computation. */
4980	if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
4981	&& ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4982	&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4983	return &XEXP (XEXP (x, 0), 0);
4984	}
4985
4986	/* If we have a PLUS whose first operand is complex, try computing it
4987	separately by making a split there. */
4988	if (GET_CODE (XEXP (x, 0)) == PLUS
4989	&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
4990	MEM_ADDR_SPACE (x))
4991	&& ! OBJECT_P (XEXP (XEXP (x, 0), 0))
4992	&& ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
4993	&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
4994	return &XEXP (XEXP (x, 0), 0);
4995	break;
4996
4997	case SET:
4998	/* See if we can split SET_SRC as it stands. */
4999	split = find_split_point (loc: &SET_SRC (x), insn, set_src: true);
5000	if (split && split != &SET_SRC (x))
5001	return split;
5002
5003	/* See if we can split SET_DEST as it stands. */
5004	split = find_split_point (loc: &SET_DEST (x), insn, set_src: false);
5005	if (split && split != &SET_DEST (x))
5006	return split;
5007
5008	/* See if this is a bitfield assignment with everything constant. If
5009	so, this is an IOR of an AND, so split it into that. */
5010	if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5011	&& is_a <scalar_int_mode> (GET_MODE (XEXP (SET_DEST (x), 0)),
5012	result: &inner_mode)
5013	&& HWI_COMPUTABLE_MODE_P (mode: inner_mode)
5014	&& CONST_INT_P (XEXP (SET_DEST (x), 1))
5015	&& CONST_INT_P (XEXP (SET_DEST (x), 2))
5016	&& CONST_INT_P (SET_SRC (x))
5017	&& ((INTVAL (XEXP (SET_DEST (x), 1))
5018	+ INTVAL (XEXP (SET_DEST (x), 2)))
5019	<= GET_MODE_PRECISION (mode: inner_mode))
5020	&& ! side_effects_p (XEXP (SET_DEST (x), 0)))
5021	{
5022	HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
5023	unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
5024	rtx dest = XEXP (SET_DEST (x), 0);
5025	unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << len) - 1;
5026	unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x)) & mask;
5027	rtx or_mask;
5028
5029	if (BITS_BIG_ENDIAN)
5030	pos = GET_MODE_PRECISION (mode: inner_mode) - len - pos;
5031
5032	or_mask = gen_int_mode (src << pos, inner_mode);
5033	if (src == mask)
5034	SUBST (SET_SRC (x),
5035	simplify_gen_binary (IOR, inner_mode, dest, or_mask));
5036	else
5037	{
5038	rtx negmask = gen_int_mode (~(mask << pos), inner_mode);
5039	SUBST (SET_SRC (x),
5040	simplify_gen_binary (IOR, inner_mode,
5041	simplify_gen_binary (AND, inner_mode,
5042	dest, negmask),
5043	or_mask));
5044	}
5045
5046	SUBST (SET_DEST (x), dest);
5047
5048	split = find_split_point (loc: &SET_SRC (x), insn, set_src: true);
5049	if (split && split != &SET_SRC (x))
5050	return split;
5051	}
5052
5053	/* Otherwise, see if this is an operation that we can split into two.
5054	If so, try to split that. */
5055	code = GET_CODE (SET_SRC (x));
5056
5057	switch (code)
5058	{
5059	case AND:
5060	/* If we are AND'ing with a large constant that is only a single
5061	bit and the result is only being used in a context where we
5062	need to know if it is zero or nonzero, replace it with a bit
5063	extraction. This will avoid the large constant, which might
5064	have taken more than one insn to make. If the constant were
5065	not a valid argument to the AND but took only one insn to make,
5066	this is no worse, but if it took more than one insn, it will
5067	be better. */
5068
5069	if (CONST_INT_P (XEXP (SET_SRC (x), 1))
5070	&& REG_P (XEXP (SET_SRC (x), 0))
5071	&& (pos = exact_log2 (UINTVAL (XEXP (SET_SRC (x), 1)))) >= 7
5072	&& REG_P (SET_DEST (x))
5073	&& (split = find_single_use (SET_DEST (x), insn, NULL)) != 0
5074	&& (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
5075	&& XEXP (*split, 0) == SET_DEST (x)
5076	&& XEXP (*split, 1) == const0_rtx)
5077	{
5078	rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
5079	XEXP (SET_SRC (x), 0),
5080	pos, NULL_RTX, 1,
5081	true, false, false);
5082	if (extraction != 0)
5083	{
5084	SUBST (SET_SRC (x), extraction);
5085	return find_split_point (loc, insn, set_src: false);
5086	}
5087	}
5088	break;
5089
5090	case NE:
5091	/* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
5092	is known to be on, this can be converted into a NEG of a shift. */
5093	if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
5094	&& GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
5095	&& ((pos = exact_log2 (x: nonzero_bits (XEXP (SET_SRC (x), 0),
5096	GET_MODE (XEXP (SET_SRC (x),
5097	0))))) >= 1))
5098	{
5099	machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
5100	rtx pos_rtx = gen_int_shift_amount (mode, pos);
5101	SUBST (SET_SRC (x),
5102	gen_rtx_NEG (mode,
5103	gen_rtx_LSHIFTRT (mode,
5104	XEXP (SET_SRC (x), 0),
5105	pos_rtx)));
5106
5107	split = find_split_point (loc: &SET_SRC (x), insn, set_src: true);
5108	if (split && split != &SET_SRC (x))
5109	return split;
5110	}
5111	break;
5112
5113	case SIGN_EXTEND:
5114	inner = XEXP (SET_SRC (x), 0);
5115
5116	/* We can't optimize if either mode is a partial integer
5117	mode as we don't know how many bits are significant
5118	in those modes. */
5119	if (!is_int_mode (GET_MODE (inner), int_mode: &inner_mode)
5120	|| GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
5121	break;
5122
5123	pos = 0;
5124	len = GET_MODE_PRECISION (mode: inner_mode);
5125	unsignedp = false;
5126	break;
5127
5128	case SIGN_EXTRACT:
5129	case ZERO_EXTRACT:
5130	if (is_a <scalar_int_mode> (GET_MODE (XEXP (SET_SRC (x), 0)),
5131	result: &inner_mode)
5132	&& CONST_INT_P (XEXP (SET_SRC (x), 1))
5133	&& CONST_INT_P (XEXP (SET_SRC (x), 2)))
5134	{
5135	inner = XEXP (SET_SRC (x), 0);
5136	len = INTVAL (XEXP (SET_SRC (x), 1));
5137	pos = INTVAL (XEXP (SET_SRC (x), 2));
5138
5139	if (BITS_BIG_ENDIAN)
5140	pos = GET_MODE_PRECISION (mode: inner_mode) - len - pos;
5141	unsignedp = (code == ZERO_EXTRACT);
5142	}
5143	break;
5144
5145	default:
5146	break;
5147	}
5148
5149	if (len
5150	&& known_subrange_p (pos1: pos, size1: len,
5151	pos2: 0, size2: GET_MODE_PRECISION (GET_MODE (inner)))
5152	&& is_a <scalar_int_mode> (GET_MODE (SET_SRC (x)), result: &mode))
5153	{
5154	/* For unsigned, we have a choice of a shift followed by an
5155	AND or two shifts. Use two shifts for field sizes where the
5156	constant might be too large. We assume here that we can
5157	always at least get 8-bit constants in an AND insn, which is
5158	true for every current RISC. */
5159
5160	if (unsignedp && len <= 8)
5161	{
5162	unsigned HOST_WIDE_INT mask
5163	= (HOST_WIDE_INT_1U << len) - 1;
5164	rtx pos_rtx = gen_int_shift_amount (mode, pos);
5165	SUBST (SET_SRC (x),
5166	gen_rtx_AND (mode,
5167	gen_rtx_LSHIFTRT
5168	(mode, gen_lowpart (mode, inner), pos_rtx),
5169	gen_int_mode (mask, mode)));
5170
5171	split = find_split_point (loc: &SET_SRC (x), insn, set_src: true);
5172	if (split && split != &SET_SRC (x))
5173	return split;
5174	}
5175	else
5176	{
5177	int left_bits = GET_MODE_PRECISION (mode) - len - pos;
5178	int right_bits = GET_MODE_PRECISION (mode) - len;
5179	SUBST (SET_SRC (x),
5180	gen_rtx_fmt_ee
5181	(unsignedp ? LSHIFTRT : ASHIFTRT, mode,
5182	gen_rtx_ASHIFT (mode,
5183	gen_lowpart (mode, inner),
5184	gen_int_shift_amount (mode, left_bits)),
5185	gen_int_shift_amount (mode, right_bits)));
5186
5187	split = find_split_point (loc: &SET_SRC (x), insn, set_src: true);
5188	if (split && split != &SET_SRC (x))
5189	return split;
5190	}
5191	}
5192
5193	/* See if this is a simple operation with a constant as the second
5194	operand. It might be that this constant is out of range and hence
5195	could be used as a split point. */
5196	if (BINARY_P (SET_SRC (x))
5197	&& CONSTANT_P (XEXP (SET_SRC (x), 1))
5198	&& (OBJECT_P (XEXP (SET_SRC (x), 0))
5199	|| (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
5200	&& OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
5201	return &XEXP (SET_SRC (x), 1);
5202
5203	/* Finally, see if this is a simple operation with its first operand
5204	not in a register. The operation might require this operand in a
5205	register, so return it as a split point. We can always do this
5206	because if the first operand were another operation, we would have
5207	already found it as a split point. */
5208	if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
5209	&& ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
5210	return &XEXP (SET_SRC (x), 0);
5211
5212	return 0;
5213
5214	case AND:
5215	case IOR:
5216	/* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
5217	it is better to write this as (not (ior A B)) so we can split it.
5218	Similarly for IOR. */
5219	if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
5220	{
5221	SUBST (*loc,
5222	gen_rtx_NOT (GET_MODE (x),
5223	gen_rtx_fmt_ee (code == IOR ? AND : IOR,
5224	GET_MODE (x),
5225	XEXP (XEXP (x, 0), 0),
5226	XEXP (XEXP (x, 1), 0))));
5227	return find_split_point (loc, insn, set_src);
5228	}
5229
5230	/* Many RISC machines have a large set of logical insns. If the
5231	second operand is a NOT, put it first so we will try to split the
5232	other operand first. */
5233	if (GET_CODE (XEXP (x, 1)) == NOT)
5234	{
5235	rtx tem = XEXP (x, 0);
5236	SUBST (XEXP (x, 0), XEXP (x, 1));
5237	SUBST (XEXP (x, 1), tem);
5238	}
5239	break;
5240
5241	case PLUS:
5242	case MINUS:
5243	/* Canonicalization can produce (minus A (mult B C)), where C is a
5244	constant. It may be better to try splitting (plus (mult B -C) A)
5245	instead if this isn't a multiply by a power of two. */
5246	if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
5247	&& GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
5248	&& !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
5249	{
5250	machine_mode mode = GET_MODE (x);
5251	unsigned HOST_WIDE_INT this_int = INTVAL (XEXP (XEXP (x, 1), 1));
5252	HOST_WIDE_INT other_int = trunc_int_for_mode (-this_int, mode);
5253	SUBST (*loc, gen_rtx_PLUS (mode,
5254	gen_rtx_MULT (mode,
5255	XEXP (XEXP (x, 1), 0),
5256	gen_int_mode (other_int,
5257	mode)),
5258	XEXP (x, 0)));
5259	return find_split_point (loc, insn, set_src);
5260	}
5261
5262	/* Split at a multiply-accumulate instruction. However if this is
5263	the SET_SRC, we likely do not have such an instruction and it's
5264	worthless to try this split. */
5265	if (!set_src
5266	&& (GET_CODE (XEXP (x, 0)) == MULT
5267	|| (GET_CODE (XEXP (x, 0)) == ASHIFT
5268	&& GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
5269	return loc;
5270
5271	default:
5272	break;
5273	}
5274
5275	/* Otherwise, select our actions depending on our rtx class. */
5276	switch (GET_RTX_CLASS (code))
5277	{
5278	case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
5279	case RTX_TERNARY:
5280	split = find_split_point (loc: &XEXP (x, 2), insn, set_src: false);
5281	if (split)
5282	return split;
5283	/* fall through */
5284	case RTX_BIN_ARITH:
5285	case RTX_COMM_ARITH:
5286	case RTX_COMPARE:
5287	case RTX_COMM_COMPARE:
5288	split = find_split_point (loc: &XEXP (x, 1), insn, set_src: false);
5289	if (split)
5290	return split;
5291	/* fall through */
5292	case RTX_UNARY:
5293	/* Some machines have (and (shift ...) ...) insns. If X is not
5294	an AND, but XEXP (X, 0) is, use it as our split point. */
5295	if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
5296	return &XEXP (x, 0);
5297
5298	split = find_split_point (loc: &XEXP (x, 0), insn, set_src: false);
5299	if (split)
5300	return split;
5301	return loc;
5302
5303	default:
5304	/* Otherwise, we don't have a split point. */
5305	return 0;
5306	}
5307	}
5308
5309	/* Throughout X, replace FROM with TO, and return the result.
5310	The result is TO if X is FROM;
5311	otherwise the result is X, but its contents may have been modified.
5312	If they were modified, a record was made in undobuf so that
5313	undo_all will (among other things) return X to its original state.
5314
5315	If the number of changes necessary is too much to record to undo,
5316	the excess changes are not made, so the result is invalid.
5317	The changes already made can still be undone.
5318	undobuf.num_undo is incremented for such changes, so by testing that
5319	the caller can tell whether the result is valid.
5320
5321	`n_occurrences' is incremented each time FROM is replaced.
5322
5323	IN_DEST is true if we are processing the SET_DEST of a SET.
5324
5325	IN_COND is true if we are at the top level of a condition.
5326
5327	UNIQUE_COPY is true if each substitution must be unique. We do this
5328	by copying if `n_occurrences' is nonzero. */
5329
5330	static rtx
5331	subst (rtx x, rtx from, rtx to, bool in_dest, bool in_cond, bool unique_copy)
5332	{
5333	enum rtx_code code = GET_CODE (x);
5334	machine_mode op0_mode = VOIDmode;
5335	const char *fmt;
5336	int len, i;
5337	rtx new_rtx;
5338
5339	/* Two expressions are equal if they are identical copies of a shared
5340	RTX or if they are both registers with the same register number
5341	and mode. */
5342
5343	#define COMBINE_RTX_EQUAL_P(X,Y) \
5344	((X) == (Y) \
5345	|| (REG_P (X) && REG_P (Y) \
5346	&& REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
5347
5348	/* Do not substitute into clobbers of regs -- this will never result in
5349	valid RTL. */
5350	if (GET_CODE (x) == CLOBBER && REG_P (XEXP (x, 0)))
5351	return x;
5352
5353	if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
5354	{
5355	n_occurrences++;
5356	return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
5357	}
5358
5359	/* If X and FROM are the same register but different modes, they
5360	will not have been seen as equal above. However, the log links code
5361	will make a LOG_LINKS entry for that case. If we do nothing, we
5362	will try to rerecognize our original insn and, when it succeeds,
5363	we will delete the feeding insn, which is incorrect.
5364
5365	So force this insn not to match in this (rare) case. */
5366	if (! in_dest && code == REG && REG_P (from)
5367	&& reg_overlap_mentioned_p (x, from))
5368	return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
5369
5370	/* If this is an object, we are done unless it is a MEM or LO_SUM, both
5371	of which may contain things that can be combined. */
5372	if (code != MEM && code != LO_SUM && OBJECT_P (x))
5373	return x;
5374
5375	/* It is possible to have a subexpression appear twice in the insn.
5376	Suppose that FROM is a register that appears within TO.
5377	Then, after that subexpression has been scanned once by `subst',
5378	the second time it is scanned, TO may be found. If we were
5379	to scan TO here, we would find FROM within it and create a
5380	self-referent rtl structure which is completely wrong. */
5381	if (COMBINE_RTX_EQUAL_P (x, to))
5382	return to;
5383
5384	/* Parallel asm_operands need special attention because all of the
5385	inputs are shared across the arms. Furthermore, unsharing the
5386	rtl results in recognition failures. Failure to handle this case
5387	specially can result in circular rtl.
5388
5389	Solve this by doing a normal pass across the first entry of the
5390	parallel, and only processing the SET_DESTs of the subsequent
5391	entries. Ug. */
5392
5393	if (code == PARALLEL
5394	&& GET_CODE (XVECEXP (x, 0, 0)) == SET
5395	&& GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
5396	{
5397	new_rtx = subst (XVECEXP (x, 0, 0), from, to, in_dest: false, in_cond: false, unique_copy);
5398
5399	/* If this substitution failed, this whole thing fails. */
5400	if (GET_CODE (new_rtx) == CLOBBER
5401	&& XEXP (new_rtx, 0) == const0_rtx)
5402	return new_rtx;
5403
5404	SUBST (XVECEXP (x, 0, 0), new_rtx);
5405
5406	for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
5407	{
5408	rtx dest = SET_DEST (XVECEXP (x, 0, i));
5409
5410	if (!REG_P (dest) && GET_CODE (dest) != PC)
5411	{
5412	new_rtx = subst (x: dest, from, to, in_dest: false, in_cond: false, unique_copy);
5413
5414	/* If this substitution failed, this whole thing fails. */
5415	if (GET_CODE (new_rtx) == CLOBBER
5416	&& XEXP (new_rtx, 0) == const0_rtx)
5417	return new_rtx;
5418
5419	SUBST (SET_DEST (XVECEXP (x, 0, i)), new_rtx);
5420	}
5421	}
5422	}
5423	else
5424	{
5425	len = GET_RTX_LENGTH (code);
5426	fmt = GET_RTX_FORMAT (code);
5427
5428	/* We don't need to process a SET_DEST that is a register or PC, so
5429	set up to skip this common case. All other cases where we want
5430	to suppress replacing something inside a SET_SRC are handled via
5431	the IN_DEST operand. */
5432	if (code == SET
5433	&& (REG_P (SET_DEST (x))
5434	|| GET_CODE (SET_DEST (x)) == PC))
5435	fmt = "ie";
5436
5437	/* Trying to simplify the operands of a widening MULT is not likely
5438	to create RTL matching a machine insn. */
5439	if (code == MULT
5440	&& (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
5441	|| GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
5442	&& (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
5443	|| GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
5444	&& REG_P (XEXP (XEXP (x, 0), 0))
5445	&& REG_P (XEXP (XEXP (x, 1), 0))
5446	&& from == to)
5447	return x;
5448
5449
5450	/* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
5451	constant. */
5452	if (fmt[0] == 'e')
5453	op0_mode = GET_MODE (XEXP (x, 0));
5454
5455	for (i = 0; i < len; i++)
5456	{
5457	if (fmt[i] == 'E')
5458	{
5459	int j;
5460	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
5461	{
5462	if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
5463	{
5464	new_rtx = (unique_copy && n_occurrences
5465	? copy_rtx (to) : to);
5466	n_occurrences++;
5467	}
5468	else
5469	{
5470	new_rtx = subst (XVECEXP (x, i, j), from, to,
5471	in_dest: false, in_cond: false, unique_copy);
5472
5473	/* If this substitution failed, this whole thing
5474	fails. */
5475	if (GET_CODE (new_rtx) == CLOBBER
5476	&& XEXP (new_rtx, 0) == const0_rtx)
5477	return new_rtx;
5478	}
5479
5480	SUBST (XVECEXP (x, i, j), new_rtx);
5481	}
5482	}
5483	else if (fmt[i] == 'e')
5484	{
5485	/* If this is a register being set, ignore it. */
5486	new_rtx = XEXP (x, i);
5487	if (in_dest
5488	&& i == 0
5489	&& (((code == SUBREG || code == ZERO_EXTRACT)
5490	&& REG_P (new_rtx))
5491	|| code == STRICT_LOW_PART))
5492	;
5493
5494	else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
5495	{
5496	/* In general, don't install a subreg involving two
5497	modes not tieable. It can worsen register
5498	allocation, and can even make invalid reload
5499	insns, since the reg inside may need to be copied
5500	from in the outside mode, and that may be invalid
5501	if it is an fp reg copied in integer mode.
5502
5503	We allow an exception to this: It is valid if
5504	it is inside another SUBREG and the mode of that
5505	SUBREG and the mode of the inside of TO is
5506	tieable. */
5507
5508	if (GET_CODE (to) == SUBREG
5509	&& !targetm.modes_tieable_p (GET_MODE (to),
5510	GET_MODE (SUBREG_REG (to)))
5511	&& ! (code == SUBREG
5512	&& (targetm.modes_tieable_p
5513	(GET_MODE (x), GET_MODE (SUBREG_REG (to))))))
5514	return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5515
5516	if (code == SUBREG
5517	&& REG_P (to)
5518	&& REGNO (to) < FIRST_PSEUDO_REGISTER
5519	&& simplify_subreg_regno (REGNO (to), GET_MODE (to),
5520	SUBREG_BYTE (x),
5521	GET_MODE (x)) < 0)
5522	return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5523
5524	new_rtx = (unique_copy && n_occurrences ? copy_rtx (to) : to);
5525	n_occurrences++;
5526	}
5527	else
5528	/* If we are in a SET_DEST, suppress most cases unless we
5529	have gone inside a MEM, in which case we want to
5530	simplify the address. We assume here that things that
5531	are actually part of the destination have their inner
5532	parts in the first expression. This is true for SUBREG,
5533	STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
5534	things aside from REG and MEM that should appear in a
5535	SET_DEST. */
5536	new_rtx = subst (XEXP (x, i), from, to,
5537	in_dest: (((in_dest
5538	&& (code == SUBREG || code == STRICT_LOW_PART
5539	|| code == ZERO_EXTRACT))
5540	|| code == SET)
5541	&& i == 0),
5542	in_cond: code == IF_THEN_ELSE && i == 0,
5543	unique_copy);
5544
5545	/* If we found that we will have to reject this combination,
5546	indicate that by returning the CLOBBER ourselves, rather than
5547	an expression containing it. This will speed things up as
5548	well as prevent accidents where two CLOBBERs are considered
5549	to be equal, thus producing an incorrect simplification. */
5550
5551	if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
5552	return new_rtx;
5553
5554	if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
5555	{
5556	machine_mode mode = GET_MODE (x);
5557
5558	x = simplify_subreg (GET_MODE (x), op: new_rtx,
5559	GET_MODE (SUBREG_REG (x)),
5560	SUBREG_BYTE (x));
5561	if (! x)
5562	x = gen_rtx_CLOBBER (mode, const0_rtx);
5563	}
5564	else if (CONST_SCALAR_INT_P (new_rtx)
5565	&& (GET_CODE (x) == ZERO_EXTEND
5566	|| GET_CODE (x) == SIGN_EXTEND
5567	|| GET_CODE (x) == FLOAT
5568	|| GET_CODE (x) == UNSIGNED_FLOAT))
5569	{
5570	x = simplify_unary_operation (GET_CODE (x), GET_MODE (x),
5571	op: new_rtx,
5572	GET_MODE (XEXP (x, 0)));
5573	if (!x)
5574	return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5575	}
5576	/* CONST_INTs shouldn't be substituted into PRE_DEC, PRE_MODIFY
5577	etc. arguments, otherwise we can ICE before trying to recog
5578	it. See PR104446. */
5579	else if (CONST_SCALAR_INT_P (new_rtx)
5580	&& GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
5581	return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
5582	else
5583	SUBST (XEXP (x, i), new_rtx);
5584	}
5585	}
5586	}
5587
5588	/* Check if we are loading something from the constant pool via float
5589	extension; in this case we would undo compress_float_constant
5590	optimization and degenerate constant load to an immediate value. */
5591	if (GET_CODE (x) == FLOAT_EXTEND
5592	&& MEM_P (XEXP (x, 0))
5593	&& MEM_READONLY_P (XEXP (x, 0)))
5594	{
5595	rtx tmp = avoid_constant_pool_reference (x);
5596	if (x != tmp)
5597	return x;
5598	}
5599
5600	/* Try to simplify X. If the simplification changed the code, it is likely
5601	that further simplification will help, so loop, but limit the number
5602	of repetitions that will be performed. */
5603
5604	for (i = 0; i < 4; i++)
5605	{
5606	/* If X is sufficiently simple, don't bother trying to do anything
5607	with it. */
5608	if (code != CONST_INT && code != REG && code != CLOBBER)
5609	x = combine_simplify_rtx (x, op0_mode, in_dest, in_cond);
5610
5611	if (GET_CODE (x) == code)
5612	break;
5613
5614	code = GET_CODE (x);
5615
5616	/* We no longer know the original mode of operand 0 since we
5617	have changed the form of X) */
5618	op0_mode = VOIDmode;
5619	}
5620
5621	return x;
5622	}
5623
5624	/* If X is a commutative operation whose operands are not in the canonical
5625	order, use substitutions to swap them. */
5626
5627	static void
5628	maybe_swap_commutative_operands (rtx x)
5629	{
5630	if (COMMUTATIVE_ARITH_P (x)
5631	&& swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
5632	{
5633	rtx temp = XEXP (x, 0);
5634	SUBST (XEXP (x, 0), XEXP (x, 1));
5635	SUBST (XEXP (x, 1), temp);
5636	}
5637
5638	unsigned n_elts = 0;
5639	if (GET_CODE (x) == VEC_MERGE
5640	&& CONST_INT_P (XEXP (x, 2))
5641	&& GET_MODE_NUNITS (GET_MODE (x)).is_constant (const_value: &n_elts)
5642	&& (swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))
5643	/* Two operands have same precedence, then
5644	first bit of mask select first operand. */
5645	|| (!swap_commutative_operands_p (XEXP (x, 1), XEXP (x, 0))
5646	&& !(UINTVAL (XEXP (x, 2)) & 1))))
5647	{
5648	rtx temp = XEXP (x, 0);
5649	unsigned HOST_WIDE_INT sel = UINTVAL (XEXP (x, 2));
5650	unsigned HOST_WIDE_INT mask = HOST_WIDE_INT_1U;
5651	if (n_elts == HOST_BITS_PER_WIDE_INT)
5652	mask = -1;
5653	else
5654	mask = (HOST_WIDE_INT_1U << n_elts) - 1;
5655	SUBST (XEXP (x, 0), XEXP (x, 1));
5656	SUBST (XEXP (x, 1), temp);
5657	SUBST (XEXP (x, 2), GEN_INT (~sel & mask));
5658	}
5659	}
5660
5661	/* Simplify X, a piece of RTL. We just operate on the expression at the
5662	outer level; call `subst' to simplify recursively. Return the new
5663	expression.
5664
5665	OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is true
5666	if we are inside a SET_DEST. IN_COND is true if we are at the top level
5667	of a condition. */
5668
5669	static rtx
5670	combine_simplify_rtx (rtx x, machine_mode op0_mode, bool in_dest, bool in_cond)
5671	{
5672	enum rtx_code code = GET_CODE (x);
5673	machine_mode mode = GET_MODE (x);
5674	scalar_int_mode int_mode;
5675	rtx temp;
5676	int i;
5677
5678	/* If this is a commutative operation, put a constant last and a complex
5679	expression first. We don't need to do this for comparisons here. */
5680	maybe_swap_commutative_operands (x);
5681
5682	/* Try to fold this expression in case we have constants that weren't
5683	present before. */
5684	temp = 0;
5685	switch (GET_RTX_CLASS (code))
5686	{
5687	case RTX_UNARY:
5688	if (op0_mode == VOIDmode)
5689	op0_mode = GET_MODE (XEXP (x, 0));
5690	temp = simplify_unary_operation (code, mode, XEXP (x, 0), op_mode: op0_mode);
5691	break;
5692	case RTX_COMPARE:
5693	case RTX_COMM_COMPARE:
5694	{
5695	machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
5696	if (cmp_mode == VOIDmode)
5697	{
5698	cmp_mode = GET_MODE (XEXP (x, 1));
5699	if (cmp_mode == VOIDmode)
5700	cmp_mode = op0_mode;
5701	}
5702	temp = simplify_relational_operation (code, mode, op_mode: cmp_mode,
5703	XEXP (x, 0), XEXP (x, 1));
5704	}
5705	break;
5706	case RTX_COMM_ARITH:
5707	case RTX_BIN_ARITH:
5708	temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
5709	break;
5710	case RTX_BITFIELD_OPS:
5711	case RTX_TERNARY:
5712	temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
5713	XEXP (x, 1), XEXP (x, 2));
5714	break;
5715	default:
5716	break;
5717	}
5718
5719	if (temp)
5720	{
5721	x = temp;
5722	code = GET_CODE (temp);
5723	op0_mode = VOIDmode;
5724	mode = GET_MODE (temp);
5725	}
5726
5727	/* If this is a simple operation applied to an IF_THEN_ELSE, try
5728	applying it to the arms of the IF_THEN_ELSE. This often simplifies
5729	things. Check for cases where both arms are testing the same
5730	condition.
5731
5732	Don't do anything if all operands are very simple. */
5733
5734	if ((BINARY_P (x)
5735	&& ((!OBJECT_P (XEXP (x, 0))
5736	&& ! (GET_CODE (XEXP (x, 0)) == SUBREG
5737	&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
5738	|| (!OBJECT_P (XEXP (x, 1))
5739	&& ! (GET_CODE (XEXP (x, 1)) == SUBREG
5740	&& OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
5741	|| (UNARY_P (x)
5742	&& (!OBJECT_P (XEXP (x, 0))
5743	&& ! (GET_CODE (XEXP (x, 0)) == SUBREG
5744	&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
5745	{
5746	rtx cond, true_rtx, false_rtx;
5747
5748	cond = if_then_else_cond (x, &true_rtx, &false_rtx);
5749	if (cond != 0
5750	/* If everything is a comparison, what we have is highly unlikely
5751	to be simpler, so don't use it. */
5752	&& ! (COMPARISON_P (x)
5753	&& (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx)))
5754	/* Similarly, if we end up with one of the expressions the same
5755	as the original, it is certainly not simpler. */
5756	&& ! rtx_equal_p (x, true_rtx)
5757	&& ! rtx_equal_p (x, false_rtx))
5758	{
5759	rtx cop1 = const0_rtx;
5760	enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
5761
5762	if (cond_code == NE && COMPARISON_P (cond))
5763	return x;
5764
5765	/* Simplify the alternative arms; this may collapse the true and
5766	false arms to store-flag values. Be careful to use copy_rtx
5767	here since true_rtx or false_rtx might share RTL with x as a
5768	result of the if_then_else_cond call above. */
5769	true_rtx = subst (x: copy_rtx (true_rtx), from: pc_rtx, to: pc_rtx,
5770	in_dest: false, in_cond: false, unique_copy: false);
5771	false_rtx = subst (x: copy_rtx (false_rtx), from: pc_rtx, to: pc_rtx,
5772	in_dest: false, in_cond: false, unique_copy: false);
5773
5774	/* If true_rtx and false_rtx are not general_operands, an if_then_else
5775	is unlikely to be simpler. */
5776	if (general_operand (true_rtx, VOIDmode)
5777	&& general_operand (false_rtx, VOIDmode))
5778	{
5779	enum rtx_code reversed;
5780
5781	/* Restarting if we generate a store-flag expression will cause
5782	us to loop. Just drop through in this case. */
5783
5784	/* If the result values are STORE_FLAG_VALUE and zero, we can
5785	just make the comparison operation. */
5786	if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
5787	x = simplify_gen_relational (code: cond_code, mode, VOIDmode,
5788	op0: cond, op1: cop1);
5789	else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
5790	&& ((reversed = reversed_comparison_code_parts
5791	(cond_code, cond, cop1, NULL))
5792	!= UNKNOWN))
5793	x = simplify_gen_relational (code: reversed, mode, VOIDmode,
5794	op0: cond, op1: cop1);
5795
5796	/* Likewise, we can make the negate of a comparison operation
5797	if the result values are - STORE_FLAG_VALUE and zero. */
5798	else if (CONST_INT_P (true_rtx)
5799	&& INTVAL (true_rtx) == - STORE_FLAG_VALUE
5800	&& false_rtx == const0_rtx)
5801	x = simplify_gen_unary (code: NEG, mode,
5802	op: simplify_gen_relational (code: cond_code,
5803	mode, VOIDmode,
5804	op0: cond, op1: cop1),
5805	op_mode: mode);
5806	else if (CONST_INT_P (false_rtx)
5807	&& INTVAL (false_rtx) == - STORE_FLAG_VALUE
5808	&& true_rtx == const0_rtx
5809	&& ((reversed = reversed_comparison_code_parts
5810	(cond_code, cond, cop1, NULL))
5811	!= UNKNOWN))
5812	x = simplify_gen_unary (code: NEG, mode,
5813	op: simplify_gen_relational (code: reversed,
5814	mode, VOIDmode,
5815	op0: cond, op1: cop1),
5816	op_mode: mode);
5817
5818	code = GET_CODE (x);
5819	op0_mode = VOIDmode;
5820	}
5821	}
5822	}
5823
5824	/* First see if we can apply the inverse distributive law. */
5825	if (code == PLUS || code == MINUS
5826	|| code == AND || code == IOR || code == XOR)
5827	{
5828	x = apply_distributive_law (x);
5829	code = GET_CODE (x);
5830	op0_mode = VOIDmode;
5831	}
5832
5833	/* If CODE is an associative operation not otherwise handled, see if we
5834	can associate some operands. This can win if they are constants or
5835	if they are logically related (i.e. (a & b) & a). */
5836	if ((code == PLUS || code == MINUS || code == MULT || code == DIV
5837	|| code == AND || code == IOR || code == XOR
5838	|| code == SMAX || code == SMIN || code == UMAX || code == UMIN)
5839	&& ((INTEGRAL_MODE_P (mode) && code != DIV)
5840	|| (flag_associative_math && FLOAT_MODE_P (mode))))
5841	{
5842	if (GET_CODE (XEXP (x, 0)) == code)
5843	{
5844	rtx other = XEXP (XEXP (x, 0), 0);
5845	rtx inner_op0 = XEXP (XEXP (x, 0), 1);
5846	rtx inner_op1 = XEXP (x, 1);
5847	rtx inner;
5848
5849	/* Make sure we pass the constant operand if any as the second
5850	one if this is a commutative operation. */
5851	if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
5852	std::swap (a&: inner_op0, b&: inner_op1);
5853	inner = simplify_binary_operation (code: code == MINUS ? PLUS
5854	: code == DIV ? MULT
5855	: code,
5856	mode, op0: inner_op0, op1: inner_op1);
5857
5858	/* For commutative operations, try the other pair if that one
5859	didn't simplify. */
5860	if (inner == 0 && COMMUTATIVE_ARITH_P (x))
5861	{
5862	other = XEXP (XEXP (x, 0), 1);
5863	inner = simplify_binary_operation (code, mode,
5864	XEXP (XEXP (x, 0), 0),
5865	XEXP (x, 1));
5866	}
5867
5868	if (inner)
5869	return simplify_gen_binary (code, mode, op0: other, op1: inner);
5870	}
5871	}
5872
5873	/* A little bit of algebraic simplification here. */
5874	switch (code)
5875	{
5876	case MEM:
5877	/* Ensure that our address has any ASHIFTs converted to MULT in case
5878	address-recognizing predicates are called later. */
5879	temp = make_compound_operation (XEXP (x, 0), MEM);
5880	SUBST (XEXP (x, 0), temp);
5881	break;
5882
5883	case SUBREG:
5884	if (op0_mode == VOIDmode)
5885	op0_mode = GET_MODE (SUBREG_REG (x));
5886
5887	/* See if this can be moved to simplify_subreg. */
5888	if (CONSTANT_P (SUBREG_REG (x))
5889	&& known_eq (subreg_lowpart_offset (mode, op0_mode), SUBREG_BYTE (x))
5890	/* Don't call gen_lowpart if the inner mode
5891	is VOIDmode and we cannot simplify it, as SUBREG without
5892	inner mode is invalid. */
5893	&& (GET_MODE (SUBREG_REG (x)) != VOIDmode
5894	|| gen_lowpart_common (mode, SUBREG_REG (x))))
5895	return gen_lowpart (mode, SUBREG_REG (x));
5896
5897	if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
5898	break;
5899	{
5900	rtx temp;
5901	temp = simplify_subreg (outermode: mode, SUBREG_REG (x), innermode: op0_mode,
5902	SUBREG_BYTE (x));
5903	if (temp)
5904	return temp;
5905
5906	/* If op is known to have all lower bits zero, the result is zero. */
5907	scalar_int_mode int_mode, int_op0_mode;
5908	if (!in_dest
5909	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
5910	&& is_a <scalar_int_mode> (m: op0_mode, result: &int_op0_mode)
5911	&& (GET_MODE_PRECISION (mode: int_mode)
5912	< GET_MODE_PRECISION (mode: int_op0_mode))
5913	&& known_eq (subreg_lowpart_offset (int_mode, int_op0_mode),
5914	SUBREG_BYTE (x))
5915	&& HWI_COMPUTABLE_MODE_P (mode: int_op0_mode)
5916	&& ((nonzero_bits (SUBREG_REG (x), int_op0_mode)
5917	& GET_MODE_MASK (int_mode)) == 0)
5918	&& !side_effects_p (SUBREG_REG (x)))
5919	return CONST0_RTX (int_mode);
5920	}
5921
5922	/* Don't change the mode of the MEM if that would change the meaning
5923	of the address. */
5924	if (MEM_P (SUBREG_REG (x))
5925	&& (MEM_VOLATILE_P (SUBREG_REG (x))
5926	|| mode_dependent_address_p (XEXP (SUBREG_REG (x), 0),
5927	MEM_ADDR_SPACE (SUBREG_REG (x)))))
5928	return gen_rtx_CLOBBER (mode, const0_rtx);
5929
5930	/* Note that we cannot do any narrowing for non-constants since
5931	we might have been counting on using the fact that some bits were
5932	zero. We now do this in the SET. */
5933
5934	break;
5935
5936	case NEG:
5937	temp = expand_compound_operation (XEXP (x, 0));
5938
5939	/* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
5940	replaced by (lshiftrt X C). This will convert
5941	(neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
5942
5943	if (GET_CODE (temp) == ASHIFTRT
5944	&& CONST_INT_P (XEXP (temp, 1))
5945	&& INTVAL (XEXP (temp, 1)) == GET_MODE_UNIT_PRECISION (mode) - 1)
5946	return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (temp, 0),
5947	INTVAL (XEXP (temp, 1)));
5948
5949	/* If X has only a single bit that might be nonzero, say, bit I, convert
5950	(neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
5951	MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
5952	(sign_extract X 1 Y). But only do this if TEMP isn't a register
5953	or a SUBREG of one since we'd be making the expression more
5954	complex if it was just a register. */
5955
5956	if (!REG_P (temp)
5957	&& ! (GET_CODE (temp) == SUBREG
5958	&& REG_P (SUBREG_REG (temp)))
5959	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
5960	&& (i = exact_log2 (x: nonzero_bits (temp, int_mode))) >= 0)
5961	{
5962	rtx temp1 = simplify_shift_const
5963	(NULL_RTX, ASHIFTRT, int_mode,
5964	simplify_shift_const (NULL_RTX, ASHIFT, int_mode, temp,
5965	GET_MODE_PRECISION (mode: int_mode) - 1 - i),
5966	GET_MODE_PRECISION (mode: int_mode) - 1 - i);
5967
5968	/* If all we did was surround TEMP with the two shifts, we
5969	haven't improved anything, so don't use it. Otherwise,
5970	we are better off with TEMP1. */
5971	if (GET_CODE (temp1) != ASHIFTRT
5972	|| GET_CODE (XEXP (temp1, 0)) != ASHIFT
5973	|| XEXP (XEXP (temp1, 0), 0) != temp)
5974	return temp1;
5975	}
5976	break;
5977
5978	case TRUNCATE:
5979	/* We can't handle truncation to a partial integer mode here
5980	because we don't know the real bitsize of the partial
5981	integer mode. */
5982	if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
5983	break;
5984
5985	if (HWI_COMPUTABLE_MODE_P (mode))
5986	SUBST (XEXP (x, 0),
5987	force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
5988	GET_MODE_MASK (mode), false));
5989
5990	/* We can truncate a constant value and return it. */
5991	{
5992	poly_int64 c;
5993	if (poly_int_rtx_p (XEXP (x, 0), res: &c))
5994	return gen_int_mode (c, mode);
5995	}
5996
5997	/* Similarly to what we do in simplify-rtx.cc, a truncate of a register
5998	whose value is a comparison can be replaced with a subreg if
5999	STORE_FLAG_VALUE permits. */
6000	if (HWI_COMPUTABLE_MODE_P (mode)
6001	&& (STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
6002	&& (temp = get_last_value (XEXP (x, 0)))
6003	&& COMPARISON_P (temp)
6004	&& TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (XEXP (x, 0))))
6005	return gen_lowpart (mode, XEXP (x, 0));
6006	break;
6007
6008	case CONST:
6009	/* (const (const X)) can become (const X). Do it this way rather than
6010	returning the inner CONST since CONST can be shared with a
6011	REG_EQUAL note. */
6012	if (GET_CODE (XEXP (x, 0)) == CONST)
6013	SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
6014	break;
6015
6016	case LO_SUM:
6017	/* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
6018	can add in an offset. find_split_point will split this address up
6019	again if it doesn't match. */
6020	if (HAVE_lo_sum && GET_CODE (XEXP (x, 0)) == HIGH
6021	&& rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
6022	return XEXP (x, 1);
6023	break;
6024
6025	case PLUS:
6026	/* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
6027	when c is (const_int (pow2 + 1) / 2) is a sign extension of a
6028	bit-field and can be replaced by either a sign_extend or a
6029	sign_extract. The `and' may be a zero_extend and the two
6030	<c>, -<c> constants may be reversed. */
6031	if (GET_CODE (XEXP (x, 0)) == XOR
6032	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
6033	&& CONST_INT_P (XEXP (x, 1))
6034	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
6035	&& INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
6036	&& ((i = exact_log2 (UINTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
6037	|| (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0)
6038	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
6039	&& ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
6040	&& CONST_INT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
6041	&& (UINTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
6042	== (HOST_WIDE_INT_1U << (i + 1)) - 1))
6043	|| (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
6044	&& known_eq ((GET_MODE_PRECISION
6045	(GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))),
6046	(unsigned int) i + 1))))
6047	return simplify_shift_const
6048	(NULL_RTX, ASHIFTRT, int_mode,
6049	simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6050	XEXP (XEXP (XEXP (x, 0), 0), 0),
6051	GET_MODE_PRECISION (mode: int_mode) - (i + 1)),
6052	GET_MODE_PRECISION (mode: int_mode) - (i + 1));
6053
6054	/* If only the low-order bit of X is possibly nonzero, (plus x -1)
6055	can become (ashiftrt (ashift (xor x 1) C) C) where C is
6056	the bitsize of the mode - 1. This allows simplification of
6057	"a = (b & 8) == 0;" */
6058	if (XEXP (x, 1) == constm1_rtx
6059	&& !REG_P (XEXP (x, 0))
6060	&& ! (GET_CODE (XEXP (x, 0)) == SUBREG
6061	&& REG_P (SUBREG_REG (XEXP (x, 0))))
6062	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
6063	&& nonzero_bits (XEXP (x, 0), int_mode) == 1)
6064	return simplify_shift_const
6065	(NULL_RTX, ASHIFTRT, int_mode,
6066	simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6067	gen_rtx_XOR (int_mode, XEXP (x, 0),
6068	const1_rtx),
6069	GET_MODE_PRECISION (mode: int_mode) - 1),
6070	GET_MODE_PRECISION (mode: int_mode) - 1);
6071
6072	/* If we are adding two things that have no bits in common, convert
6073	the addition into an IOR. This will often be further simplified,
6074	for example in cases like ((a & 1) + (a & 2)), which can
6075	become a & 3. */
6076
6077	if (HWI_COMPUTABLE_MODE_P (mode)
6078	&& (nonzero_bits (XEXP (x, 0), mode)
6079	& nonzero_bits (XEXP (x, 1), mode)) == 0)
6080	{
6081	/* Try to simplify the expression further. */
6082	rtx tor = simplify_gen_binary (code: IOR, mode, XEXP (x, 0), XEXP (x, 1));
6083	temp = combine_simplify_rtx (x: tor, VOIDmode, in_dest, in_cond: false);
6084
6085	/* If we could, great. If not, do not go ahead with the IOR
6086	replacement, since PLUS appears in many special purpose
6087	address arithmetic instructions. */
6088	if (GET_CODE (temp) != CLOBBER
6089	&& (GET_CODE (temp) != IOR
6090	|| ((XEXP (temp, 0) != XEXP (x, 0)
6091	|| XEXP (temp, 1) != XEXP (x, 1))
6092	&& (XEXP (temp, 0) != XEXP (x, 1)
6093	|| XEXP (temp, 1) != XEXP (x, 0)))))
6094	return temp;
6095	}
6096
6097	/* Canonicalize x + x into x << 1. */
6098	if (GET_MODE_CLASS (mode) == MODE_INT
6099	&& rtx_equal_p (XEXP (x, 0), XEXP (x, 1))
6100	&& !side_effects_p (XEXP (x, 0)))
6101	return simplify_gen_binary (code: ASHIFT, mode, XEXP (x, 0), const1_rtx);
6102
6103	break;
6104
6105	case MINUS:
6106	/* (minus <foo> (and <foo> (const_int -pow2))) becomes
6107	(and <foo> (const_int pow2-1)) */
6108	if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
6109	&& GET_CODE (XEXP (x, 1)) == AND
6110	&& CONST_INT_P (XEXP (XEXP (x, 1), 1))
6111	&& pow2p_hwi (x: -UINTVAL (XEXP (XEXP (x, 1), 1)))
6112	&& rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
6113	return simplify_and_const_int (NULL_RTX, int_mode, XEXP (x, 0),
6114	-INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
6115	break;
6116
6117	case MULT:
6118	/* If we have (mult (plus A B) C), apply the distributive law and then
6119	the inverse distributive law to see if things simplify. This
6120	occurs mostly in addresses, often when unrolling loops. */
6121
6122	if (GET_CODE (XEXP (x, 0)) == PLUS)
6123	{
6124	rtx result = distribute_and_simplify_rtx (x, 0);
6125	if (result)
6126	return result;
6127	}
6128
6129	/* Try simplify a*(b/c) as (a*b)/c. */
6130	if (FLOAT_MODE_P (mode) && flag_associative_math
6131	&& GET_CODE (XEXP (x, 0)) == DIV)
6132	{
6133	rtx tem = simplify_binary_operation (code: MULT, mode,
6134	XEXP (XEXP (x, 0), 0),
6135	XEXP (x, 1));
6136	if (tem)
6137	return simplify_gen_binary (code: DIV, mode, op0: tem, XEXP (XEXP (x, 0), 1));
6138	}
6139	break;
6140
6141	case UDIV:
6142	/* If this is a divide by a power of two, treat it as a shift if
6143	its first operand is a shift. */
6144	if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
6145	&& CONST_INT_P (XEXP (x, 1))
6146	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
6147	&& (GET_CODE (XEXP (x, 0)) == ASHIFT
6148	|| GET_CODE (XEXP (x, 0)) == LSHIFTRT
6149	|| GET_CODE (XEXP (x, 0)) == ASHIFTRT
6150	|| GET_CODE (XEXP (x, 0)) == ROTATE
6151	|| GET_CODE (XEXP (x, 0)) == ROTATERT))
6152	return simplify_shift_const (NULL_RTX, LSHIFTRT, int_mode,
6153	XEXP (x, 0), i);
6154	break;
6155
6156	case EQ: case NE:
6157	case GT: case GTU: case GE: case GEU:
6158	case LT: case LTU: case LE: case LEU:
6159	case UNEQ: case LTGT:
6160	case UNGT: case UNGE:
6161	case UNLT: case UNLE:
6162	case UNORDERED: case ORDERED:
6163	/* If the first operand is a condition code, we can't do anything
6164	with it. */
6165	if (GET_CODE (XEXP (x, 0)) == COMPARE
6166	|| GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC)
6167	{
6168	rtx op0 = XEXP (x, 0);
6169	rtx op1 = XEXP (x, 1);
6170	enum rtx_code new_code;
6171
6172	if (GET_CODE (op0) == COMPARE)
6173	op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
6174
6175	/* Simplify our comparison, if possible. */
6176	new_code = simplify_comparison (code, &op0, &op1);
6177
6178	/* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
6179	if only the low-order bit is possibly nonzero in X (such as when
6180	X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
6181	(xor X 1) or (minus 1 X); we use the former. Finally, if X is
6182	known to be either 0 or -1, NE becomes a NEG and EQ becomes
6183	(plus X 1).
6184
6185	Remove any ZERO_EXTRACT we made when thinking this was a
6186	comparison. It may now be simpler to use, e.g., an AND. If a
6187	ZERO_EXTRACT is indeed appropriate, it will be placed back by
6188	the call to make_compound_operation in the SET case.
6189
6190	Don't apply these optimizations if the caller would
6191	prefer a comparison rather than a value.
6192	E.g., for the condition in an IF_THEN_ELSE most targets need
6193	an explicit comparison. */
6194
6195	if (in_cond)
6196	;
6197
6198	else if (STORE_FLAG_VALUE == 1
6199	&& new_code == NE
6200	&& is_int_mode (mode, int_mode: &int_mode)
6201	&& op1 == const0_rtx
6202	&& int_mode == GET_MODE (op0)
6203	&& nonzero_bits (op0, int_mode) == 1)
6204	return gen_lowpart (int_mode,
6205	expand_compound_operation (op0));
6206
6207	else if (STORE_FLAG_VALUE == 1
6208	&& new_code == NE
6209	&& is_int_mode (mode, int_mode: &int_mode)
6210	&& op1 == const0_rtx
6211	&& int_mode == GET_MODE (op0)
6212	&& (num_sign_bit_copies (op0, int_mode)
6213	== GET_MODE_PRECISION (mode: int_mode)))
6214	{
6215	op0 = expand_compound_operation (op0);
6216	return simplify_gen_unary (code: NEG, mode: int_mode,
6217	gen_lowpart (int_mode, op0),
6218	op_mode: int_mode);
6219	}
6220
6221	else if (STORE_FLAG_VALUE == 1
6222	&& new_code == EQ
6223	&& is_int_mode (mode, int_mode: &int_mode)
6224	&& op1 == const0_rtx
6225	&& int_mode == GET_MODE (op0)
6226	&& nonzero_bits (op0, int_mode) == 1)
6227	{
6228	op0 = expand_compound_operation (op0);
6229	return simplify_gen_binary (code: XOR, mode: int_mode,
6230	gen_lowpart (int_mode, op0),
6231	const1_rtx);
6232	}
6233
6234	else if (STORE_FLAG_VALUE == 1
6235	&& new_code == EQ
6236	&& is_int_mode (mode, int_mode: &int_mode)
6237	&& op1 == const0_rtx
6238	&& int_mode == GET_MODE (op0)
6239	&& (num_sign_bit_copies (op0, int_mode)
6240	== GET_MODE_PRECISION (mode: int_mode)))
6241	{
6242	op0 = expand_compound_operation (op0);
6243	return plus_constant (int_mode, gen_lowpart (int_mode, op0), 1);
6244	}
6245
6246	/* If STORE_FLAG_VALUE is -1, we have cases similar to
6247	those above. */
6248	if (in_cond)
6249	;
6250
6251	else if (STORE_FLAG_VALUE == -1
6252	&& new_code == NE
6253	&& is_int_mode (mode, int_mode: &int_mode)
6254	&& op1 == const0_rtx
6255	&& int_mode == GET_MODE (op0)
6256	&& (num_sign_bit_copies (op0, int_mode)
6257	== GET_MODE_PRECISION (mode: int_mode)))
6258	return gen_lowpart (int_mode, expand_compound_operation (op0));
6259
6260	else if (STORE_FLAG_VALUE == -1
6261	&& new_code == NE
6262	&& is_int_mode (mode, int_mode: &int_mode)
6263	&& op1 == const0_rtx
6264	&& int_mode == GET_MODE (op0)
6265	&& nonzero_bits (op0, int_mode) == 1)
6266	{
6267	op0 = expand_compound_operation (op0);
6268	return simplify_gen_unary (code: NEG, mode: int_mode,
6269	gen_lowpart (int_mode, op0),
6270	op_mode: int_mode);
6271	}
6272
6273	else if (STORE_FLAG_VALUE == -1
6274	&& new_code == EQ
6275	&& is_int_mode (mode, int_mode: &int_mode)
6276	&& op1 == const0_rtx
6277	&& int_mode == GET_MODE (op0)
6278	&& (num_sign_bit_copies (op0, int_mode)
6279	== GET_MODE_PRECISION (mode: int_mode)))
6280	{
6281	op0 = expand_compound_operation (op0);
6282	return simplify_gen_unary (code: NOT, mode: int_mode,
6283	gen_lowpart (int_mode, op0),
6284	op_mode: int_mode);
6285	}
6286
6287	/* If X is 0/1, (eq X 0) is X-1. */
6288	else if (STORE_FLAG_VALUE == -1
6289	&& new_code == EQ
6290	&& is_int_mode (mode, int_mode: &int_mode)
6291	&& op1 == const0_rtx
6292	&& int_mode == GET_MODE (op0)
6293	&& nonzero_bits (op0, int_mode) == 1)
6294	{
6295	op0 = expand_compound_operation (op0);
6296	return plus_constant (int_mode, gen_lowpart (int_mode, op0), -1);
6297	}
6298
6299	/* If STORE_FLAG_VALUE says to just test the sign bit and X has just
6300	one bit that might be nonzero, we can convert (ne x 0) to
6301	(ashift x c) where C puts the bit in the sign bit. Remove any
6302	AND with STORE_FLAG_VALUE when we are done, since we are only
6303	going to test the sign bit. */
6304	if (new_code == NE
6305	&& is_int_mode (mode, int_mode: &int_mode)
6306	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
6307	&& val_signbit_p (int_mode, STORE_FLAG_VALUE)
6308	&& op1 == const0_rtx
6309	&& int_mode == GET_MODE (op0)
6310	&& (i = exact_log2 (x: nonzero_bits (op0, int_mode))) >= 0)
6311	{
6312	x = simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6313	expand_compound_operation (op0),
6314	GET_MODE_PRECISION (mode: int_mode) - 1 - i);
6315	if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
6316	return XEXP (x, 0);
6317	else
6318	return x;
6319	}
6320
6321	/* If the code changed, return a whole new comparison.
6322	We also need to avoid using SUBST in cases where
6323	simplify_comparison has widened a comparison with a CONST_INT,
6324	since in that case the wider CONST_INT may fail the sanity
6325	checks in do_SUBST. */
6326	if (new_code != code
6327	|| (CONST_INT_P (op1)
6328	&& GET_MODE (op0) != GET_MODE (XEXP (x, 0))
6329	&& GET_MODE (op0) != GET_MODE (XEXP (x, 1))))
6330	return gen_rtx_fmt_ee (new_code, mode, op0, op1);
6331
6332	/* Otherwise, keep this operation, but maybe change its operands.
6333	This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
6334	SUBST (XEXP (x, 0), op0);
6335	SUBST (XEXP (x, 1), op1);
6336	}
6337	break;
6338
6339	case IF_THEN_ELSE:
6340	return simplify_if_then_else (x);
6341
6342	case ZERO_EXTRACT:
6343	case SIGN_EXTRACT:
6344	case ZERO_EXTEND:
6345	case SIGN_EXTEND:
6346	/* If we are processing SET_DEST, we are done. */
6347	if (in_dest)
6348	return x;
6349
6350	return expand_compound_operation (x);
6351
6352	case SET:
6353	return simplify_set (x);
6354
6355	case AND:
6356	case IOR:
6357	return simplify_logical (x);
6358
6359	case ASHIFT:
6360	case LSHIFTRT:
6361	case ASHIFTRT:
6362	case ROTATE:
6363	case ROTATERT:
6364	/* If this is a shift by a constant amount, simplify it. */
6365	if (CONST_INT_P (XEXP (x, 1)))
6366	return simplify_shift_const (x, code, mode, XEXP (x, 0),
6367	INTVAL (XEXP (x, 1)));
6368
6369	else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
6370	SUBST (XEXP (x, 1),
6371	force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
6372	(HOST_WIDE_INT_1U
6373	<< exact_log2 (GET_MODE_UNIT_BITSIZE
6374	(GET_MODE (x)))) - 1, false));
6375	break;
6376	case VEC_SELECT:
6377	{
6378	rtx trueop0 = XEXP (x, 0);
6379	mode = GET_MODE (trueop0);
6380	rtx trueop1 = XEXP (x, 1);
6381	/* If we select a low-part subreg, return that. */
6382	if (vec_series_lowpart_p (GET_MODE (x), op_mode: mode, sel: trueop1))
6383	{
6384	rtx new_rtx = lowpart_subreg (GET_MODE (x), op: trueop0, innermode: mode);
6385	if (new_rtx != NULL_RTX)
6386	return new_rtx;
6387	}
6388	}
6389
6390	default:
6391	break;
6392	}
6393
6394	return x;
6395	}
6396
6397	/* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
6398
6399	static rtx
6400	simplify_if_then_else (rtx x)
6401	{
6402	machine_mode mode = GET_MODE (x);
6403	rtx cond = XEXP (x, 0);
6404	rtx true_rtx = XEXP (x, 1);
6405	rtx false_rtx = XEXP (x, 2);
6406	enum rtx_code true_code = GET_CODE (cond);
6407	bool comparison_p = COMPARISON_P (cond);
6408	rtx temp;
6409	int i;
6410	enum rtx_code false_code;
6411	rtx reversed;
6412	scalar_int_mode int_mode, inner_mode;
6413
6414	/* Simplify storing of the truth value. */
6415	if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
6416	return simplify_gen_relational (code: true_code, mode, VOIDmode,
6417	XEXP (cond, 0), XEXP (cond, 1));
6418
6419	/* Also when the truth value has to be reversed. */
6420	if (comparison_p
6421	&& true_rtx == const0_rtx && false_rtx == const_true_rtx
6422	&& (reversed = reversed_comparison (cond, mode)))
6423	return reversed;
6424
6425	/* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
6426	in it is being compared against certain values. Get the true and false
6427	comparisons and see if that says anything about the value of each arm. */
6428
6429	if (comparison_p
6430	&& ((false_code = reversed_comparison_code (cond, NULL))
6431	!= UNKNOWN)
6432	&& REG_P (XEXP (cond, 0)))
6433	{
6434	HOST_WIDE_INT nzb;
6435	rtx from = XEXP (cond, 0);
6436	rtx true_val = XEXP (cond, 1);
6437	rtx false_val = true_val;
6438	bool swapped = false;
6439
6440	/* If FALSE_CODE is EQ, swap the codes and arms. */
6441
6442	if (false_code == EQ)
6443	{
6444	swapped = true, true_code = EQ, false_code = NE;
6445	std::swap (a&: true_rtx, b&: false_rtx);
6446	}
6447
6448	scalar_int_mode from_mode;
6449	if (is_a <scalar_int_mode> (GET_MODE (from), result: &from_mode))
6450	{
6451	/* If we are comparing against zero and the expression being
6452	tested has only a single bit that might be nonzero, that is
6453	its value when it is not equal to zero. Similarly if it is
6454	known to be -1 or 0. */
6455	if (true_code == EQ
6456	&& true_val == const0_rtx
6457	&& pow2p_hwi (x: nzb = nonzero_bits (from, from_mode)))
6458	{
6459	false_code = EQ;
6460	false_val = gen_int_mode (nzb, from_mode);
6461	}
6462	else if (true_code == EQ
6463	&& true_val == const0_rtx
6464	&& (num_sign_bit_copies (from, from_mode)
6465	== GET_MODE_PRECISION (mode: from_mode)))
6466	{
6467	false_code = EQ;
6468	false_val = constm1_rtx;
6469	}
6470	}
6471
6472	/* Now simplify an arm if we know the value of the register in the
6473	branch and it is used in the arm. Be careful due to the potential
6474	of locally-shared RTL. */
6475
6476	if (reg_mentioned_p (from, true_rtx))
6477	true_rtx = subst (x: known_cond (copy_rtx (true_rtx), true_code,
6478	from, true_val),
6479	from: pc_rtx, to: pc_rtx, in_dest: false, in_cond: false, unique_copy: false);
6480	if (reg_mentioned_p (from, false_rtx))
6481	false_rtx = subst (x: known_cond (copy_rtx (false_rtx), false_code,
6482	from, false_val),
6483	from: pc_rtx, to: pc_rtx, in_dest: false, in_cond: false, unique_copy: false);
6484
6485	SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
6486	SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
6487
6488	true_rtx = XEXP (x, 1);
6489	false_rtx = XEXP (x, 2);
6490	true_code = GET_CODE (cond);
6491	}
6492
6493	/* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
6494	reversed, do so to avoid needing two sets of patterns for
6495	subtract-and-branch insns. Similarly if we have a constant in the true
6496	arm, the false arm is the same as the first operand of the comparison, or
6497	the false arm is more complicated than the true arm. */
6498
6499	if (comparison_p
6500	&& reversed_comparison_code (cond, NULL) != UNKNOWN
6501	&& (true_rtx == pc_rtx
6502	|| (CONSTANT_P (true_rtx)
6503	&& !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
6504	|| true_rtx == const0_rtx
6505	|| (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
6506	|| (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
6507	&& !OBJECT_P (false_rtx))
6508	|| reg_mentioned_p (true_rtx, false_rtx)
6509	|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
6510	{
6511	SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
6512	SUBST (XEXP (x, 1), false_rtx);
6513	SUBST (XEXP (x, 2), true_rtx);
6514
6515	std::swap (a&: true_rtx, b&: false_rtx);
6516	cond = XEXP (x, 0);
6517
6518	/* It is possible that the conditional has been simplified out. */
6519	true_code = GET_CODE (cond);
6520	comparison_p = COMPARISON_P (cond);
6521	}
6522
6523	/* If the two arms are identical, we don't need the comparison. */
6524
6525	if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
6526	return true_rtx;
6527
6528	/* Convert a == b ? b : a to "a". */
6529	if (true_code == EQ && ! side_effects_p (cond)
6530	&& !HONOR_NANS (mode)
6531	&& rtx_equal_p (XEXP (cond, 0), false_rtx)
6532	&& rtx_equal_p (XEXP (cond, 1), true_rtx))
6533	return false_rtx;
6534	else if (true_code == NE && ! side_effects_p (cond)
6535	&& !HONOR_NANS (mode)
6536	&& rtx_equal_p (XEXP (cond, 0), true_rtx)
6537	&& rtx_equal_p (XEXP (cond, 1), false_rtx))
6538	return true_rtx;
6539
6540	/* Look for cases where we have (abs x) or (neg (abs X)). */
6541
6542	if (GET_MODE_CLASS (mode) == MODE_INT
6543	&& comparison_p
6544	&& XEXP (cond, 1) == const0_rtx
6545	&& GET_CODE (false_rtx) == NEG
6546	&& rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
6547	&& rtx_equal_p (true_rtx, XEXP (cond, 0))
6548	&& ! side_effects_p (true_rtx))
6549	switch (true_code)
6550	{
6551	case GT:
6552	case GE:
6553	return simplify_gen_unary (code: ABS, mode, op: true_rtx, op_mode: mode);
6554	case LT:
6555	case LE:
6556	return
6557	simplify_gen_unary (code: NEG, mode,
6558	op: simplify_gen_unary (code: ABS, mode, op: true_rtx, op_mode: mode),
6559	op_mode: mode);
6560	default:
6561	break;
6562	}
6563
6564	/* Look for MIN or MAX. */
6565
6566	if ((! FLOAT_MODE_P (mode)
6567	|| (flag_unsafe_math_optimizations
6568	&& !HONOR_NANS (mode)
6569	&& !HONOR_SIGNED_ZEROS (mode)))
6570	&& comparison_p
6571	&& rtx_equal_p (XEXP (cond, 0), true_rtx)
6572	&& rtx_equal_p (XEXP (cond, 1), false_rtx)
6573	&& ! side_effects_p (cond))
6574	switch (true_code)
6575	{
6576	case GE:
6577	case GT:
6578	return simplify_gen_binary (code: SMAX, mode, op0: true_rtx, op1: false_rtx);
6579	case LE:
6580	case LT:
6581	return simplify_gen_binary (code: SMIN, mode, op0: true_rtx, op1: false_rtx);
6582	case GEU:
6583	case GTU:
6584	return simplify_gen_binary (code: UMAX, mode, op0: true_rtx, op1: false_rtx);
6585	case LEU:
6586	case LTU:
6587	return simplify_gen_binary (code: UMIN, mode, op0: true_rtx, op1: false_rtx);
6588	default:
6589	break;
6590	}
6591
6592	/* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
6593	second operand is zero, this can be done as (OP Z (mult COND C2)) where
6594	C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
6595	SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
6596	We can do this kind of thing in some cases when STORE_FLAG_VALUE is
6597	neither 1 or -1, but it isn't worth checking for. */
6598
6599	if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
6600	&& comparison_p
6601	&& is_int_mode (mode, int_mode: &int_mode)
6602	&& ! side_effects_p (x))
6603	{
6604	rtx t = make_compound_operation (true_rtx, SET);
6605	rtx f = make_compound_operation (false_rtx, SET);
6606	rtx cond_op0 = XEXP (cond, 0);
6607	rtx cond_op1 = XEXP (cond, 1);
6608	enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
6609	scalar_int_mode m = int_mode;
6610	rtx z = 0, c1 = NULL_RTX;
6611
6612	if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
6613	|| GET_CODE (t) == IOR || GET_CODE (t) == XOR
6614	|| GET_CODE (t) == ASHIFT
6615	|| GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
6616	&& rtx_equal_p (XEXP (t, 0), f))
6617	c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
6618
6619	/* If an identity-zero op is commutative, check whether there
6620	would be a match if we swapped the operands. */
6621	else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
6622	|| GET_CODE (t) == XOR)
6623	&& rtx_equal_p (XEXP (t, 1), f))
6624	c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
6625	else if (GET_CODE (t) == SIGN_EXTEND
6626	&& is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), result: &inner_mode)
6627	&& (GET_CODE (XEXP (t, 0)) == PLUS
6628	|| GET_CODE (XEXP (t, 0)) == MINUS
6629	|| GET_CODE (XEXP (t, 0)) == IOR
6630	|| GET_CODE (XEXP (t, 0)) == XOR
6631	|| GET_CODE (XEXP (t, 0)) == ASHIFT
6632	|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
6633	|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6634	&& GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6635	&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6636	&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6637	&& (num_sign_bit_copies (f, GET_MODE (f))
6638	> (unsigned int)
6639	(GET_MODE_PRECISION (mode: int_mode)
6640	- GET_MODE_PRECISION (mode: inner_mode))))
6641	{
6642	c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6643	extend_op = SIGN_EXTEND;
6644	m = inner_mode;
6645	}
6646	else if (GET_CODE (t) == SIGN_EXTEND
6647	&& is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), result: &inner_mode)
6648	&& (GET_CODE (XEXP (t, 0)) == PLUS
6649	|| GET_CODE (XEXP (t, 0)) == IOR
6650	|| GET_CODE (XEXP (t, 0)) == XOR)
6651	&& GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6652	&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6653	&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6654	&& (num_sign_bit_copies (f, GET_MODE (f))
6655	> (unsigned int)
6656	(GET_MODE_PRECISION (mode: int_mode)
6657	- GET_MODE_PRECISION (mode: inner_mode))))
6658	{
6659	c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6660	extend_op = SIGN_EXTEND;
6661	m = inner_mode;
6662	}
6663	else if (GET_CODE (t) == ZERO_EXTEND
6664	&& is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), result: &inner_mode)
6665	&& (GET_CODE (XEXP (t, 0)) == PLUS
6666	|| GET_CODE (XEXP (t, 0)) == MINUS
6667	|| GET_CODE (XEXP (t, 0)) == IOR
6668	|| GET_CODE (XEXP (t, 0)) == XOR
6669	|| GET_CODE (XEXP (t, 0)) == ASHIFT
6670	|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
6671	|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
6672	&& GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
6673	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
6674	&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
6675	&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
6676	&& ((nonzero_bits (f, GET_MODE (f))
6677	& ~GET_MODE_MASK (inner_mode))
6678	== 0))
6679	{
6680	c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
6681	extend_op = ZERO_EXTEND;
6682	m = inner_mode;
6683	}
6684	else if (GET_CODE (t) == ZERO_EXTEND
6685	&& is_a <scalar_int_mode> (GET_MODE (XEXP (t, 0)), result: &inner_mode)
6686	&& (GET_CODE (XEXP (t, 0)) == PLUS
6687	|| GET_CODE (XEXP (t, 0)) == IOR
6688	|| GET_CODE (XEXP (t, 0)) == XOR)
6689	&& GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
6690	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
6691	&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
6692	&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
6693	&& ((nonzero_bits (f, GET_MODE (f))
6694	& ~GET_MODE_MASK (inner_mode))
6695	== 0))
6696	{
6697	c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
6698	extend_op = ZERO_EXTEND;
6699	m = inner_mode;
6700	}
6701
6702	if (z)
6703	{
6704	machine_mode cm = m;
6705	if ((op == ASHIFT || op == LSHIFTRT || op == ASHIFTRT)
6706	&& GET_MODE (c1) != VOIDmode)
6707	cm = GET_MODE (c1);
6708	temp = subst (x: simplify_gen_relational (code: true_code, mode: cm, VOIDmode,
6709	op0: cond_op0, op1: cond_op1),
6710	from: pc_rtx, to: pc_rtx, in_dest: false, in_cond: false, unique_copy: false);
6711	temp = simplify_gen_binary (code: MULT, mode: cm, op0: temp,
6712	op1: simplify_gen_binary (code: MULT, mode: cm, op0: c1,
6713	op1: const_true_rtx));
6714	temp = subst (x: temp, from: pc_rtx, to: pc_rtx, in_dest: false, in_cond: false, unique_copy: false);
6715	temp = simplify_gen_binary (code: op, mode: m, gen_lowpart (m, z), op1: temp);
6716
6717	if (extend_op != UNKNOWN)
6718	temp = simplify_gen_unary (code: extend_op, mode: int_mode, op: temp, op_mode: m);
6719
6720	return temp;
6721	}
6722	}
6723
6724	/* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
6725	1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
6726	negation of a single bit, we can convert this operation to a shift. We
6727	can actually do this more generally, but it doesn't seem worth it. */
6728
6729	if (true_code == NE
6730	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
6731	&& XEXP (cond, 1) == const0_rtx
6732	&& false_rtx == const0_rtx
6733	&& CONST_INT_P (true_rtx)
6734	&& ((nonzero_bits (XEXP (cond, 0), int_mode) == 1
6735	&& (i = exact_log2 (UINTVAL (true_rtx))) >= 0)
6736	|| ((num_sign_bit_copies (XEXP (cond, 0), int_mode)
6737	== GET_MODE_PRECISION (mode: int_mode))
6738	&& (i = exact_log2 (x: -UINTVAL (true_rtx))) >= 0)))
6739	return
6740	simplify_shift_const (NULL_RTX, ASHIFT, int_mode,
6741	gen_lowpart (int_mode, XEXP (cond, 0)), i);
6742
6743	/* (IF_THEN_ELSE (NE A 0) C1 0) is A or a zero-extend of A if the only
6744	non-zero bit in A is C1. */
6745	if (true_code == NE && XEXP (cond, 1) == const0_rtx
6746	&& false_rtx == const0_rtx && CONST_INT_P (true_rtx)
6747	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
6748	&& is_a <scalar_int_mode> (GET_MODE (XEXP (cond, 0)), result: &inner_mode)
6749	&& (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))
6750	== nonzero_bits (XEXP (cond, 0), inner_mode)
6751	&& (i = exact_log2 (UINTVAL (true_rtx) & GET_MODE_MASK (int_mode))) >= 0)
6752	{
6753	rtx val = XEXP (cond, 0);
6754	if (inner_mode == int_mode)
6755	return val;
6756	else if (GET_MODE_PRECISION (mode: inner_mode) < GET_MODE_PRECISION (mode: int_mode))
6757	return simplify_gen_unary (code: ZERO_EXTEND, mode: int_mode, op: val, op_mode: inner_mode);
6758	}
6759
6760	return x;
6761	}
6762
6763	/* Simplify X, a SET expression. Return the new expression. */
6764
6765	static rtx
6766	simplify_set (rtx x)
6767	{
6768	rtx src = SET_SRC (x);
6769	rtx dest = SET_DEST (x);
6770	machine_mode mode
6771	= GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
6772	rtx_insn *other_insn;
6773	rtx *cc_use;
6774	scalar_int_mode int_mode;
6775
6776	/* (set (pc) (return)) gets written as (return). */
6777	if (GET_CODE (dest) == PC && ANY_RETURN_P (src))
6778	return src;
6779
6780	/* Now that we know for sure which bits of SRC we are using, see if we can
6781	simplify the expression for the object knowing that we only need the
6782	low-order bits. */
6783
6784	if (GET_MODE_CLASS (mode) == MODE_INT && HWI_COMPUTABLE_MODE_P (mode))
6785	{
6786	src = force_to_mode (src, mode, HOST_WIDE_INT_M1U, false);
6787	SUBST (SET_SRC (x), src);
6788	}
6789
6790	/* If the source is a COMPARE, look for the use of the comparison result
6791	and try to simplify it unless we already have used undobuf.other_insn. */
6792	if ((GET_MODE_CLASS (mode) == MODE_CC || GET_CODE (src) == COMPARE)
6793	&& (cc_use = find_single_use (dest, insn: subst_insn, ploc: &other_insn)) != 0
6794	&& (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
6795	&& COMPARISON_P (*cc_use)
6796	&& rtx_equal_p (XEXP (*cc_use, 0), dest))
6797	{
6798	enum rtx_code old_code = GET_CODE (*cc_use);
6799	enum rtx_code new_code;
6800	rtx op0, op1, tmp;
6801	bool other_changed = false;
6802	rtx inner_compare = NULL_RTX;
6803	machine_mode compare_mode = GET_MODE (dest);
6804
6805	if (GET_CODE (src) == COMPARE)
6806	{
6807	op0 = XEXP (src, 0), op1 = XEXP (src, 1);
6808	if (GET_CODE (op0) == COMPARE && op1 == const0_rtx)
6809	{
6810	inner_compare = op0;
6811	op0 = XEXP (inner_compare, 0), op1 = XEXP (inner_compare, 1);
6812	}
6813	}
6814	else
6815	op0 = src, op1 = CONST0_RTX (GET_MODE (src));
6816
6817	tmp = simplify_relational_operation (code: old_code, mode: compare_mode, VOIDmode,
6818	op0, op1);
6819	if (!tmp)
6820	new_code = old_code;
6821	else if (!CONSTANT_P (tmp))
6822	{
6823	new_code = GET_CODE (tmp);
6824	op0 = XEXP (tmp, 0);
6825	op1 = XEXP (tmp, 1);
6826	}
6827	else
6828	{
6829	rtx pat = PATTERN (insn: other_insn);
6830	undobuf.other_insn = other_insn;
6831	SUBST (*cc_use, tmp);
6832
6833	/* Attempt to simplify CC user. */
6834	if (GET_CODE (pat) == SET)
6835	{
6836	rtx new_rtx = simplify_rtx (SET_SRC (pat));
6837	if (new_rtx != NULL_RTX)
6838	SUBST (SET_SRC (pat), new_rtx);
6839	}
6840
6841	/* Convert X into a no-op move. */
6842	SUBST (SET_DEST (x), pc_rtx);
6843	SUBST (SET_SRC (x), pc_rtx);
6844	return x;
6845	}
6846
6847	/* Simplify our comparison, if possible. */
6848	new_code = simplify_comparison (new_code, &op0, &op1);
6849
6850	#ifdef SELECT_CC_MODE
6851	/* If this machine has CC modes other than CCmode, check to see if we
6852	need to use a different CC mode here. */
6853	if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6854	compare_mode = GET_MODE (op0);
6855	else if (inner_compare
6856	&& GET_MODE_CLASS (GET_MODE (inner_compare)) == MODE_CC
6857	&& new_code == old_code
6858	&& op0 == XEXP (inner_compare, 0)
6859	&& op1 == XEXP (inner_compare, 1))
6860	compare_mode = GET_MODE (inner_compare);
6861	else
6862	compare_mode = SELECT_CC_MODE (new_code, op0, op1);
6863
6864	/* If the mode changed, we have to change SET_DEST, the mode in the
6865	compare, and the mode in the place SET_DEST is used. If SET_DEST is
6866	a hard register, just build new versions with the proper mode. If it
6867	is a pseudo, we lose unless it is only time we set the pseudo, in
6868	which case we can safely change its mode. */
6869	if (compare_mode != GET_MODE (dest))
6870	{
6871	if (can_change_dest_mode (x: dest, added_sets: 0, mode: compare_mode))
6872	{
6873	unsigned int regno = REGNO (dest);
6874	rtx new_dest;
6875
6876	if (regno < FIRST_PSEUDO_REGISTER)
6877	new_dest = gen_rtx_REG (compare_mode, regno);
6878	else
6879	{
6880	subst_mode (regno, newval: compare_mode);
6881	new_dest = regno_reg_rtx[regno];
6882	}
6883
6884	SUBST (SET_DEST (x), new_dest);
6885	SUBST (XEXP (*cc_use, 0), new_dest);
6886	other_changed = true;
6887
6888	dest = new_dest;
6889	}
6890	}
6891	#endif /* SELECT_CC_MODE */
6892
6893	/* If the code changed, we have to build a new comparison in
6894	undobuf.other_insn. */
6895	if (new_code != old_code)
6896	{
6897	bool other_changed_previously = other_changed;
6898	unsigned HOST_WIDE_INT mask;
6899	rtx old_cc_use = *cc_use;
6900
6901	SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
6902	dest, const0_rtx));
6903	other_changed = true;
6904
6905	/* If the only change we made was to change an EQ into an NE or
6906	vice versa, OP0 has only one bit that might be nonzero, and OP1
6907	is zero, check if changing the user of the condition code will
6908	produce a valid insn. If it won't, we can keep the original code
6909	in that insn by surrounding our operation with an XOR. */
6910
6911	if (((old_code == NE && new_code == EQ)
6912	|| (old_code == EQ && new_code == NE))
6913	&& ! other_changed_previously && op1 == const0_rtx
6914	&& HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
6915	&& pow2p_hwi (x: mask = nonzero_bits (op0, GET_MODE (op0))))
6916	{
6917	rtx pat = PATTERN (insn: other_insn), note = 0;
6918
6919	if ((recog_for_combine (&pat, other_insn, &note) < 0
6920	&& ! check_asm_operands (pat)))
6921	{
6922	*cc_use = old_cc_use;
6923	other_changed = false;
6924
6925	op0 = simplify_gen_binary (code: XOR, GET_MODE (op0), op0,
6926	op1: gen_int_mode (mask,
6927	GET_MODE (op0)));
6928	}
6929	}
6930	}
6931
6932	if (other_changed)
6933	undobuf.other_insn = other_insn;
6934
6935	/* Don't generate a compare of a CC with 0, just use that CC. */
6936	if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
6937	{
6938	SUBST (SET_SRC (x), op0);
6939	src = SET_SRC (x);
6940	}
6941	/* Otherwise, if we didn't previously have the same COMPARE we
6942	want, create it from scratch. */
6943	else if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode
6944	|| XEXP (src, 0) != op0 || XEXP (src, 1) != op1)
6945	{
6946	SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
6947	src = SET_SRC (x);
6948	}
6949	}
6950	else
6951	{
6952	/* Get SET_SRC in a form where we have placed back any
6953	compound expressions. Then do the checks below. */
6954	src = make_compound_operation (src, SET);
6955	SUBST (SET_SRC (x), src);
6956	}
6957
6958	/* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
6959	and X being a REG or (subreg (reg)), we may be able to convert this to
6960	(set (subreg:m2 x) (op)).
6961
6962	We can always do this if M1 is narrower than M2 because that means that
6963	we only care about the low bits of the result.
6964
6965	However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
6966	perform a narrower operation than requested since the high-order bits will
6967	be undefined. On machine where it is defined, this transformation is safe
6968	as long as M1 and M2 have the same number of words. */
6969
6970	if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
6971	&& !OBJECT_P (SUBREG_REG (src))
6972	&& (known_equal_after_align_up
6973	(a: GET_MODE_SIZE (GET_MODE (src)),
6974	b: GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))),
6975	UNITS_PER_WORD))
6976	&& (WORD_REGISTER_OPERATIONS || !paradoxical_subreg_p (x: src))
6977	&& ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
6978	&& !REG_CAN_CHANGE_MODE_P (REGNO (dest),
6979	GET_MODE (SUBREG_REG (src)),
6980	GET_MODE (src)))
6981	&& (REG_P (dest)
6982	|| (GET_CODE (dest) == SUBREG
6983	&& REG_P (SUBREG_REG (dest)))))
6984	{
6985	SUBST (SET_DEST (x),
6986	gen_lowpart (GET_MODE (SUBREG_REG (src)),
6987	dest));
6988	SUBST (SET_SRC (x), SUBREG_REG (src));
6989
6990	src = SET_SRC (x), dest = SET_DEST (x);
6991	}
6992
6993	/* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
6994	would require a paradoxical subreg. Replace the subreg with a
6995	zero_extend to avoid the reload that would otherwise be required.
6996	Don't do this unless we have a scalar integer mode, otherwise the
6997	transformation is incorrect. */
6998
6999	enum rtx_code extend_op;
7000	if (paradoxical_subreg_p (x: src)
7001	&& MEM_P (SUBREG_REG (src))
7002	&& SCALAR_INT_MODE_P (GET_MODE (src))
7003	&& (extend_op = load_extend_op (GET_MODE (SUBREG_REG (src)))) != UNKNOWN)
7004	{
7005	SUBST (SET_SRC (x),
7006	gen_rtx_fmt_e (extend_op, GET_MODE (src), SUBREG_REG (src)));
7007
7008	src = SET_SRC (x);
7009	}
7010
7011	/* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
7012	are comparing an item known to be 0 or -1 against 0, use a logical
7013	operation instead. Check for one of the arms being an IOR of the other
7014	arm with some value. We compute three terms to be IOR'ed together. In
7015	practice, at most two will be nonzero. Then we do the IOR's. */
7016
7017	if (GET_CODE (dest) != PC
7018	&& GET_CODE (src) == IF_THEN_ELSE
7019	&& is_int_mode (GET_MODE (src), int_mode: &int_mode)
7020	&& (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
7021	&& XEXP (XEXP (src, 0), 1) == const0_rtx
7022	&& int_mode == GET_MODE (XEXP (XEXP (src, 0), 0))
7023	&& (!HAVE_conditional_move
7024	|| ! can_conditionally_move_p (mode: int_mode))
7025	&& (num_sign_bit_copies (XEXP (XEXP (src, 0), 0), int_mode)
7026	== GET_MODE_PRECISION (mode: int_mode))
7027	&& ! side_effects_p (src))
7028	{
7029	rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
7030	? XEXP (src, 1) : XEXP (src, 2));
7031	rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
7032	? XEXP (src, 2) : XEXP (src, 1));
7033	rtx term1 = const0_rtx, term2, term3;
7034
7035	if (GET_CODE (true_rtx) == IOR
7036	&& rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
7037	term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
7038	else if (GET_CODE (true_rtx) == IOR
7039	&& rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
7040	term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
7041	else if (GET_CODE (false_rtx) == IOR
7042	&& rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
7043	term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
7044	else if (GET_CODE (false_rtx) == IOR
7045	&& rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
7046	term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
7047
7048	term2 = simplify_gen_binary (code: AND, mode: int_mode,
7049	XEXP (XEXP (src, 0), 0), op1: true_rtx);
7050	term3 = simplify_gen_binary (code: AND, mode: int_mode,
7051	op0: simplify_gen_unary (code: NOT, mode: int_mode,
7052	XEXP (XEXP (src, 0), 0),
7053	op_mode: int_mode),
7054	op1: false_rtx);
7055
7056	SUBST (SET_SRC (x),
7057	simplify_gen_binary (IOR, int_mode,
7058	simplify_gen_binary (IOR, int_mode,
7059	term1, term2),
7060	term3));
7061
7062	src = SET_SRC (x);
7063	}
7064
7065	/* If either SRC or DEST is a CLOBBER of (const_int 0), make this
7066	whole thing fail. */
7067	if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
7068	return src;
7069	else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
7070	return dest;
7071	else
7072	/* Convert this into a field assignment operation, if possible. */
7073	return make_field_assignment (x);
7074	}
7075
7076	/* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
7077	result. */
7078
7079	static rtx
7080	simplify_logical (rtx x)
7081	{
7082	rtx op0 = XEXP (x, 0);
7083	rtx op1 = XEXP (x, 1);
7084	scalar_int_mode mode;
7085
7086	switch (GET_CODE (x))
7087	{
7088	case AND:
7089	/* We can call simplify_and_const_int only if we don't lose
7090	any (sign) bits when converting INTVAL (op1) to
7091	"unsigned HOST_WIDE_INT". */
7092	if (is_a <scalar_int_mode> (GET_MODE (x), result: &mode)
7093	&& CONST_INT_P (op1)
7094	&& (HWI_COMPUTABLE_MODE_P (mode)
7095	|| INTVAL (op1) > 0))
7096	{
7097	x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
7098	if (GET_CODE (x) != AND)
7099	return x;
7100
7101	op0 = XEXP (x, 0);
7102	op1 = XEXP (x, 1);
7103	}
7104
7105	/* If we have any of (and (ior A B) C) or (and (xor A B) C),
7106	apply the distributive law and then the inverse distributive
7107	law to see if things simplify. */
7108	if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
7109	{
7110	rtx result = distribute_and_simplify_rtx (x, 0);
7111	if (result)
7112	return result;
7113	}
7114	if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
7115	{
7116	rtx result = distribute_and_simplify_rtx (x, 1);
7117	if (result)
7118	return result;
7119	}
7120	break;
7121
7122	case IOR:
7123	/* If we have (ior (and A B) C), apply the distributive law and then
7124	the inverse distributive law to see if things simplify. */
7125
7126	if (GET_CODE (op0) == AND)
7127	{
7128	rtx result = distribute_and_simplify_rtx (x, 0);
7129	if (result)
7130	return result;
7131	}
7132
7133	if (GET_CODE (op1) == AND)
7134	{
7135	rtx result = distribute_and_simplify_rtx (x, 1);
7136	if (result)
7137	return result;
7138	}
7139	break;
7140
7141	default:
7142	gcc_unreachable ();
7143	}
7144
7145	return x;
7146	}
7147
7148	/* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
7149	operations" because they can be replaced with two more basic operations.
7150	ZERO_EXTEND is also considered "compound" because it can be replaced with
7151	an AND operation, which is simpler, though only one operation.
7152
7153	The function expand_compound_operation is called with an rtx expression
7154	and will convert it to the appropriate shifts and AND operations,
7155	simplifying at each stage.
7156
7157	The function make_compound_operation is called to convert an expression
7158	consisting of shifts and ANDs into the equivalent compound expression.
7159	It is the inverse of this function, loosely speaking. */
7160
7161	static rtx
7162	expand_compound_operation (rtx x)
7163	{
7164	unsigned HOST_WIDE_INT pos = 0, len;
7165	bool unsignedp = false;
7166	unsigned int modewidth;
7167	rtx tem;
7168	scalar_int_mode inner_mode;
7169
7170	switch (GET_CODE (x))
7171	{
7172	case ZERO_EXTEND:
7173	unsignedp = true;
7174	/* FALLTHRU */
7175	case SIGN_EXTEND:
7176	/* We can't necessarily use a const_int for a multiword mode;
7177	it depends on implicitly extending the value.
7178	Since we don't know the right way to extend it,
7179	we can't tell whether the implicit way is right.
7180
7181	Even for a mode that is no wider than a const_int,
7182	we can't win, because we need to sign extend one of its bits through
7183	the rest of it, and we don't know which bit. */
7184	if (CONST_INT_P (XEXP (x, 0)))
7185	return x;
7186
7187	/* Reject modes that aren't scalar integers because turning vector
7188	or complex modes into shifts causes problems. */
7189	if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), result: &inner_mode))
7190	return x;
7191
7192	/* Return if (subreg:MODE FROM 0) is not a safe replacement for
7193	(zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
7194	because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
7195	reloaded. If not for that, MEM's would very rarely be safe.
7196
7197	Reject modes bigger than a word, because we might not be able
7198	to reference a two-register group starting with an arbitrary register
7199	(and currently gen_lowpart might crash for a SUBREG). */
7200
7201	if (GET_MODE_SIZE (mode: inner_mode) > UNITS_PER_WORD)
7202	return x;
7203
7204	len = GET_MODE_PRECISION (mode: inner_mode);
7205	/* If the inner object has VOIDmode (the only way this can happen
7206	is if it is an ASM_OPERANDS), we can't do anything since we don't
7207	know how much masking to do. */
7208	if (len == 0)
7209	return x;
7210
7211	break;
7212
7213	case ZERO_EXTRACT:
7214	unsignedp = true;
7215
7216	/* fall through */
7217
7218	case SIGN_EXTRACT:
7219	/* If the operand is a CLOBBER, just return it. */
7220	if (GET_CODE (XEXP (x, 0)) == CLOBBER)
7221	return XEXP (x, 0);
7222
7223	if (!CONST_INT_P (XEXP (x, 1))
7224	|| !CONST_INT_P (XEXP (x, 2)))
7225	return x;
7226
7227	/* Reject modes that aren't scalar integers because turning vector
7228	or complex modes into shifts causes problems. */
7229	if (!is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), result: &inner_mode))
7230	return x;
7231
7232	len = INTVAL (XEXP (x, 1));
7233	pos = INTVAL (XEXP (x, 2));
7234
7235	/* This should stay within the object being extracted, fail otherwise. */
7236	if (len + pos > GET_MODE_PRECISION (mode: inner_mode))
7237	return x;
7238
7239	if (BITS_BIG_ENDIAN)
7240	pos = GET_MODE_PRECISION (mode: inner_mode) - len - pos;
7241
7242	break;
7243
7244	default:
7245	return x;
7246	}
7247
7248	/* We've rejected non-scalar operations by now. */
7249	scalar_int_mode mode = as_a <scalar_int_mode> (GET_MODE (x));
7250
7251	/* Convert sign extension to zero extension, if we know that the high
7252	bit is not set, as this is easier to optimize. It will be converted
7253	back to cheaper alternative in make_extraction. */
7254	if (GET_CODE (x) == SIGN_EXTEND
7255	&& HWI_COMPUTABLE_MODE_P (mode)
7256	&& ((nonzero_bits (XEXP (x, 0), inner_mode)
7257	& ~(((unsigned HOST_WIDE_INT) GET_MODE_MASK (inner_mode)) >> 1))
7258	== 0))
7259	{
7260	rtx temp = gen_rtx_ZERO_EXTEND (mode, XEXP (x, 0));
7261	rtx temp2 = expand_compound_operation (x: temp);
7262
7263	/* Make sure this is a profitable operation. */
7264	if (set_src_cost (x, mode, speed_p: optimize_this_for_speed_p)
7265	> set_src_cost (x: temp2, mode, speed_p: optimize_this_for_speed_p))
7266	return temp2;
7267	else if (set_src_cost (x, mode, speed_p: optimize_this_for_speed_p)
7268	> set_src_cost (x: temp, mode, speed_p: optimize_this_for_speed_p))
7269	return temp;
7270	else
7271	return x;
7272	}
7273
7274	/* We can optimize some special cases of ZERO_EXTEND. */
7275	if (GET_CODE (x) == ZERO_EXTEND)
7276	{
7277	/* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
7278	know that the last value didn't have any inappropriate bits
7279	set. */
7280	if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7281	&& GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7282	&& HWI_COMPUTABLE_MODE_P (mode)
7283	&& (nonzero_bits (XEXP (XEXP (x, 0), 0), mode)
7284	& ~GET_MODE_MASK (inner_mode)) == 0)
7285	return XEXP (XEXP (x, 0), 0);
7286
7287	/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7288	if (GET_CODE (XEXP (x, 0)) == SUBREG
7289	&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7290	&& subreg_lowpart_p (XEXP (x, 0))
7291	&& HWI_COMPUTABLE_MODE_P (mode)
7292	&& (nonzero_bits (SUBREG_REG (XEXP (x, 0)), mode)
7293	& ~GET_MODE_MASK (inner_mode)) == 0)
7294	return SUBREG_REG (XEXP (x, 0));
7295
7296	/* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
7297	is a comparison and STORE_FLAG_VALUE permits. This is like
7298	the first case, but it works even when MODE is larger
7299	than HOST_WIDE_INT. */
7300	if (GET_CODE (XEXP (x, 0)) == TRUNCATE
7301	&& GET_MODE (XEXP (XEXP (x, 0), 0)) == mode
7302	&& COMPARISON_P (XEXP (XEXP (x, 0), 0))
7303	&& GET_MODE_PRECISION (mode: inner_mode) <= HOST_BITS_PER_WIDE_INT
7304	&& (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7305	return XEXP (XEXP (x, 0), 0);
7306
7307	/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
7308	if (GET_CODE (XEXP (x, 0)) == SUBREG
7309	&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
7310	&& subreg_lowpart_p (XEXP (x, 0))
7311	&& COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
7312	&& GET_MODE_PRECISION (mode: inner_mode) <= HOST_BITS_PER_WIDE_INT
7313	&& (STORE_FLAG_VALUE & ~GET_MODE_MASK (inner_mode)) == 0)
7314	return SUBREG_REG (XEXP (x, 0));
7315
7316	}
7317
7318	/* If we reach here, we want to return a pair of shifts. The inner
7319	shift is a left shift of BITSIZE - POS - LEN bits. The outer
7320	shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
7321	logical depending on the value of UNSIGNEDP.
7322
7323	If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
7324	converted into an AND of a shift.
7325
7326	We must check for the case where the left shift would have a negative
7327	count. This can happen in a case like (x >> 31) & 255 on machines
7328	that can't shift by a constant. On those machines, we would first
7329	combine the shift with the AND to produce a variable-position
7330	extraction. Then the constant of 31 would be substituted in
7331	to produce such a position. */
7332
7333	modewidth = GET_MODE_PRECISION (mode);
7334	if (modewidth >= pos + len)
7335	{
7336	tem = gen_lowpart (mode, XEXP (x, 0));
7337	if (!tem || GET_CODE (tem) == CLOBBER)
7338	return x;
7339	tem = simplify_shift_const (NULL_RTX, ASHIFT, mode,
7340	tem, modewidth - pos - len);
7341	tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
7342	mode, tem, modewidth - len);
7343	}
7344	else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
7345	{
7346	tem = simplify_shift_const (NULL_RTX, LSHIFTRT, inner_mode,
7347	XEXP (x, 0), pos);
7348	tem = gen_lowpart (mode, tem);
7349	if (!tem || GET_CODE (tem) == CLOBBER)
7350	return x;
7351	tem = simplify_and_const_int (NULL_RTX, mode, tem,
7352	(HOST_WIDE_INT_1U << len) - 1);
7353	}
7354	else
7355	/* Any other cases we can't handle. */
7356	return x;
7357
7358	/* If we couldn't do this for some reason, return the original
7359	expression. */
7360	if (GET_CODE (tem) == CLOBBER)
7361	return x;
7362
7363	return tem;
7364	}
7365
7366	/* X is a SET which contains an assignment of one object into
7367	a part of another (such as a bit-field assignment, STRICT_LOW_PART,
7368	or certain SUBREGS). If possible, convert it into a series of
7369	logical operations.
7370
7371	We half-heartedly support variable positions, but do not at all
7372	support variable lengths. */
7373
7374	static const_rtx
7375	expand_field_assignment (const_rtx x)
7376	{
7377	rtx inner;
7378	rtx pos; /* Always counts from low bit. */
7379	int len, inner_len;
7380	rtx mask, cleared, masked;
7381	scalar_int_mode compute_mode;
7382
7383	/* Loop until we find something we can't simplify. */
7384	while (1)
7385	{
7386	if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
7387	&& GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
7388	{
7389	rtx x0 = XEXP (SET_DEST (x), 0);
7390	if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (const_value: &len))
7391	break;
7392	inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
7393	pos = gen_int_mode (subreg_lsb (XEXP (SET_DEST (x), 0)),
7394	MAX_MODE_INT);
7395	}
7396	else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
7397	&& CONST_INT_P (XEXP (SET_DEST (x), 1)))
7398	{
7399	inner = XEXP (SET_DEST (x), 0);
7400	if (!GET_MODE_PRECISION (GET_MODE (inner)).is_constant (const_value: &inner_len))
7401	break;
7402
7403	len = INTVAL (XEXP (SET_DEST (x), 1));
7404	pos = XEXP (SET_DEST (x), 2);
7405
7406	/* A constant position should stay within the width of INNER. */
7407	if (CONST_INT_P (pos) && INTVAL (pos) + len > inner_len)
7408	break;
7409
7410	if (BITS_BIG_ENDIAN)
7411	{
7412	if (CONST_INT_P (pos))
7413	pos = GEN_INT (inner_len - len - INTVAL (pos));
7414	else if (GET_CODE (pos) == MINUS
7415	&& CONST_INT_P (XEXP (pos, 1))
7416	&& INTVAL (XEXP (pos, 1)) == inner_len - len)
7417	/* If position is ADJUST - X, new position is X. */
7418	pos = XEXP (pos, 0);
7419	else
7420	pos = simplify_gen_binary (code: MINUS, GET_MODE (pos),
7421	op0: gen_int_mode (inner_len - len,
7422	GET_MODE (pos)),
7423	op1: pos);
7424	}
7425	}
7426
7427	/* If the destination is a subreg that overwrites the whole of the inner
7428	register, we can move the subreg to the source. */
7429	else if (GET_CODE (SET_DEST (x)) == SUBREG
7430	/* We need SUBREGs to compute nonzero_bits properly. */
7431	&& nonzero_sign_valid
7432	&& !read_modify_subreg_p (SET_DEST (x)))
7433	{
7434	x = gen_rtx_SET (SUBREG_REG (SET_DEST (x)),
7435	gen_lowpart
7436	(GET_MODE (SUBREG_REG (SET_DEST (x))),
7437	SET_SRC (x)));
7438	continue;
7439	}
7440	else
7441	break;
7442
7443	while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
7444	inner = SUBREG_REG (inner);
7445
7446	/* Don't attempt bitwise arithmetic on non scalar integer modes. */
7447	if (!is_a <scalar_int_mode> (GET_MODE (inner), result: &compute_mode))
7448	{
7449	/* Don't do anything for vector or complex integral types. */
7450	if (! FLOAT_MODE_P (GET_MODE (inner)))
7451	break;
7452
7453	/* Try to find an integral mode to pun with. */
7454	if (!int_mode_for_size (size: GET_MODE_BITSIZE (GET_MODE (inner)), limit: 0)
7455	.exists (mode: &compute_mode))
7456	break;
7457
7458	inner = gen_lowpart (compute_mode, inner);
7459	}
7460
7461	/* Compute a mask of LEN bits, if we can do this on the host machine. */
7462	if (len >= HOST_BITS_PER_WIDE_INT)
7463	break;
7464
7465	/* Don't try to compute in too wide unsupported modes. */
7466	if (!targetm.scalar_mode_supported_p (compute_mode))
7467	break;
7468
7469	/* Now compute the equivalent expression. Make a copy of INNER
7470	for the SET_DEST in case it is a MEM into which we will substitute;
7471	we don't want shared RTL in that case. */
7472	mask = gen_int_mode ((HOST_WIDE_INT_1U << len) - 1,
7473	compute_mode);
7474	cleared = simplify_gen_binary (code: AND, mode: compute_mode,
7475	op0: simplify_gen_unary (code: NOT, mode: compute_mode,
7476	op: simplify_gen_binary (code: ASHIFT,
7477	mode: compute_mode,
7478	op0: mask, op1: pos),
7479	op_mode: compute_mode),
7480	op1: inner);
7481	masked = simplify_gen_binary (code: ASHIFT, mode: compute_mode,
7482	op0: simplify_gen_binary (
7483	code: AND, mode: compute_mode,
7484	gen_lowpart (compute_mode, SET_SRC (x)),
7485	op1: mask),
7486	op1: pos);
7487
7488	x = gen_rtx_SET (copy_rtx (inner),
7489	simplify_gen_binary (IOR, compute_mode,
7490	cleared, masked));
7491	}
7492
7493	return x;
7494	}
7495
7496	/* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
7497	it is an RTX that represents the (variable) starting position; otherwise,
7498	POS is the (constant) starting bit position. Both are counted from the LSB.
7499
7500	UNSIGNEDP is true for an unsigned reference and zero for a signed one.
7501
7502	IN_DEST is true if this is a reference in the destination of a SET.
7503	This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
7504	a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
7505	be used.
7506
7507	IN_COMPARE is true if we are in a COMPARE. This means that a
7508	ZERO_EXTRACT should be built even for bits starting at bit 0.
7509
7510	MODE is the desired mode of the result (if IN_DEST == 0).
7511
7512	The result is an RTX for the extraction or NULL_RTX if the target
7513	can't handle it. */
7514
7515	static rtx
7516	make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
7517	rtx pos_rtx, unsigned HOST_WIDE_INT len, bool unsignedp,
7518	bool in_dest, bool in_compare)
7519	{
7520	/* This mode describes the size of the storage area
7521	to fetch the overall value from. Within that, we
7522	ignore the POS lowest bits, etc. */
7523	machine_mode is_mode = GET_MODE (inner);
7524	machine_mode inner_mode;
7525	scalar_int_mode wanted_inner_mode;
7526	scalar_int_mode wanted_inner_reg_mode = word_mode;
7527	scalar_int_mode pos_mode = word_mode;
7528	machine_mode extraction_mode = word_mode;
7529	rtx new_rtx = 0;
7530	rtx orig_pos_rtx = pos_rtx;
7531	HOST_WIDE_INT orig_pos;
7532
7533	if (pos_rtx && CONST_INT_P (pos_rtx))
7534	pos = INTVAL (pos_rtx), pos_rtx = 0;
7535
7536	if (GET_CODE (inner) == SUBREG
7537	&& subreg_lowpart_p (inner)
7538	&& (paradoxical_subreg_p (x: inner)
7539	/* If trying or potentionally trying to extract
7540	bits outside of is_mode, don't look through
7541	non-paradoxical SUBREGs. See PR82192. */
7542	|| (pos_rtx == NULL_RTX
7543	&& known_le (pos + len, GET_MODE_PRECISION (is_mode)))))
7544	{
7545	/* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
7546	consider just the QI as the memory to extract from.
7547	The subreg adds or removes high bits; its mode is
7548	irrelevant to the meaning of this extraction,
7549	since POS and LEN count from the lsb. */
7550	if (MEM_P (SUBREG_REG (inner)))
7551	is_mode = GET_MODE (SUBREG_REG (inner));
7552	inner = SUBREG_REG (inner);
7553	}
7554	else if (GET_CODE (inner) == ASHIFT
7555	&& CONST_INT_P (XEXP (inner, 1))
7556	&& pos_rtx == 0 && pos == 0
7557	&& len > UINTVAL (XEXP (inner, 1)))
7558	{
7559	/* We're extracting the least significant bits of an rtx
7560	(ashift X (const_int C)), where LEN > C. Extract the
7561	least significant (LEN - C) bits of X, giving an rtx
7562	whose mode is MODE, then shift it left C times. */
7563	new_rtx = make_extraction (mode, XEXP (inner, 0),
7564	pos: 0, pos_rtx: 0, len: len - INTVAL (XEXP (inner, 1)),
7565	unsignedp, in_dest, in_compare);
7566	if (new_rtx != 0)
7567	return gen_rtx_ASHIFT (mode, new_rtx, XEXP (inner, 1));
7568	}
7569	else if (GET_CODE (inner) == MULT
7570	&& CONST_INT_P (XEXP (inner, 1))
7571	&& pos_rtx == 0 && pos == 0)
7572	{
7573	/* We're extracting the least significant bits of an rtx
7574	(mult X (const_int 2^C)), where LEN > C. Extract the
7575	least significant (LEN - C) bits of X, giving an rtx
7576	whose mode is MODE, then multiply it by 2^C. */
7577	const HOST_WIDE_INT shift_amt = exact_log2 (INTVAL (XEXP (inner, 1)));
7578	if (IN_RANGE (shift_amt, 1, len - 1))
7579	{
7580	new_rtx = make_extraction (mode, XEXP (inner, 0),
7581	pos: 0, pos_rtx: 0, len: len - shift_amt,
7582	unsignedp, in_dest, in_compare);
7583	if (new_rtx)
7584	return gen_rtx_MULT (mode, new_rtx, XEXP (inner, 1));
7585	}
7586	}
7587	else if (GET_CODE (inner) == TRUNCATE
7588	/* If trying or potentionally trying to extract
7589	bits outside of is_mode, don't look through
7590	TRUNCATE. See PR82192. */
7591	&& pos_rtx == NULL_RTX
7592	&& known_le (pos + len, GET_MODE_PRECISION (is_mode)))
7593	inner = XEXP (inner, 0);
7594
7595	inner_mode = GET_MODE (inner);
7596
7597	/* See if this can be done without an extraction. We never can if the
7598	width of the field is not the same as that of some integer mode. For
7599	registers, we can only avoid the extraction if the position is at the
7600	low-order bit and this is either not in the destination or we have the
7601	appropriate STRICT_LOW_PART operation available.
7602
7603	For MEM, we can avoid an extract if the field starts on an appropriate
7604	boundary and we can change the mode of the memory reference. */
7605
7606	scalar_int_mode tmode;
7607	if (int_mode_for_size (size: len, limit: 1).exists (mode: &tmode)
7608	&& ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
7609	&& !MEM_P (inner)
7610	&& (pos == 0 || REG_P (inner))
7611	&& (inner_mode == tmode
7612	|| !REG_P (inner)
7613	|| TRULY_NOOP_TRUNCATION_MODES_P (tmode, inner_mode)
7614	|| reg_truncated_to_mode (tmode, inner))
7615	&& (! in_dest
7616	|| (REG_P (inner)
7617	&& have_insn_for (STRICT_LOW_PART, tmode))))
7618	|| (MEM_P (inner) && pos_rtx == 0
7619	&& (pos
7620	% (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
7621	: BITS_PER_UNIT)) == 0
7622	/* We can't do this if we are widening INNER_MODE (it
7623	may not be aligned, for one thing). */
7624	&& !paradoxical_subreg_p (outermode: tmode, innermode: inner_mode)
7625	&& known_le (pos + len, GET_MODE_PRECISION (is_mode))
7626	&& (inner_mode == tmode
7627	|| (! mode_dependent_address_p (XEXP (inner, 0),
7628	MEM_ADDR_SPACE (inner))
7629	&& ! MEM_VOLATILE_P (inner))))))
7630	{
7631	/* If INNER is a MEM, make a new MEM that encompasses just the desired
7632	field. If the original and current mode are the same, we need not
7633	adjust the offset. Otherwise, we do if bytes big endian.
7634
7635	If INNER is not a MEM, get a piece consisting of just the field
7636	of interest (in this case POS % BITS_PER_WORD must be 0). */
7637
7638	if (MEM_P (inner))
7639	{
7640	poly_int64 offset;
7641
7642	/* POS counts from lsb, but make OFFSET count in memory order. */
7643	if (BYTES_BIG_ENDIAN)
7644	offset = bits_to_bytes_round_down (GET_MODE_PRECISION (is_mode)
7645	- len - pos);
7646	else
7647	offset = pos / BITS_PER_UNIT;
7648
7649	new_rtx = adjust_address_nv (inner, tmode, offset);
7650	}
7651	else if (REG_P (inner))
7652	{
7653	if (tmode != inner_mode)
7654	{
7655	/* We can't call gen_lowpart in a DEST since we
7656	always want a SUBREG (see below) and it would sometimes
7657	return a new hard register. */
7658	if (pos || in_dest)
7659	{
7660	poly_uint64 offset
7661	= subreg_offset_from_lsb (outer_mode: tmode, inner_mode, lsb_shift: pos);
7662
7663	/* Avoid creating invalid subregs, for example when
7664	simplifying (x>>32)&255. */
7665	if (!validate_subreg (tmode, inner_mode, inner, offset))
7666	return NULL_RTX;
7667
7668	new_rtx = gen_rtx_SUBREG (tmode, inner, offset);
7669	}
7670	else
7671	new_rtx = gen_lowpart (tmode, inner);
7672	}
7673	else
7674	new_rtx = inner;
7675	}
7676	else
7677	new_rtx = force_to_mode (inner, tmode,
7678	len >= HOST_BITS_PER_WIDE_INT
7679	? HOST_WIDE_INT_M1U
7680	: (HOST_WIDE_INT_1U << len) - 1, false);
7681
7682	/* If this extraction is going into the destination of a SET,
7683	make a STRICT_LOW_PART unless we made a MEM. */
7684
7685	if (in_dest)
7686	return (MEM_P (new_rtx) ? new_rtx
7687	: (GET_CODE (new_rtx) != SUBREG
7688	? gen_rtx_CLOBBER (tmode, const0_rtx)
7689	: gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
7690
7691	if (mode == tmode)
7692	return new_rtx;
7693
7694	if (CONST_SCALAR_INT_P (new_rtx))
7695	return simplify_unary_operation (code: unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7696	mode, op: new_rtx, op_mode: tmode);
7697
7698	/* If we know that no extraneous bits are set, and that the high
7699	bit is not set, convert the extraction to the cheaper of
7700	sign and zero extension, that are equivalent in these cases. */
7701	if (flag_expensive_optimizations
7702	&& (HWI_COMPUTABLE_MODE_P (mode: tmode)
7703	&& ((nonzero_bits (new_rtx, tmode)
7704	& ~(((unsigned HOST_WIDE_INT)GET_MODE_MASK (tmode)) >> 1))
7705	== 0)))
7706	{
7707	rtx temp = gen_rtx_ZERO_EXTEND (mode, new_rtx);
7708	rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new_rtx);
7709
7710	/* Prefer ZERO_EXTENSION, since it gives more information to
7711	backends. */
7712	if (set_src_cost (x: temp, mode, speed_p: optimize_this_for_speed_p)
7713	<= set_src_cost (x: temp1, mode, speed_p: optimize_this_for_speed_p))
7714	return temp;
7715	return temp1;
7716	}
7717
7718	/* Otherwise, sign- or zero-extend unless we already are in the
7719	proper mode. */
7720
7721	return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
7722	mode, new_rtx));
7723	}
7724
7725	/* Unless this is a COMPARE or we have a funny memory reference,
7726	don't do anything with zero-extending field extracts starting at
7727	the low-order bit since they are simple AND operations. */
7728	if (pos_rtx == 0 && pos == 0 && ! in_dest
7729	&& ! in_compare && unsignedp)
7730	return 0;
7731
7732	/* Unless INNER is not MEM, reject this if we would be spanning bytes or
7733	if the position is not a constant and the length is not 1. In all
7734	other cases, we would only be going outside our object in cases when
7735	an original shift would have been undefined. */
7736	if (MEM_P (inner)
7737	&& ((pos_rtx == 0 && maybe_gt (pos + len, GET_MODE_PRECISION (is_mode)))
7738	|| (pos_rtx != 0 && len != 1)))
7739	return 0;
7740
7741	enum extraction_pattern pattern = (in_dest ? EP_insv
7742	: unsignedp ? EP_extzv : EP_extv);
7743
7744	/* If INNER is not from memory, we want it to have the mode of a register
7745	extraction pattern's structure operand, or word_mode if there is no
7746	such pattern. The same applies to extraction_mode and pos_mode
7747	and their respective operands.
7748
7749	For memory, assume that the desired extraction_mode and pos_mode
7750	are the same as for a register operation, since at present we don't
7751	have named patterns for aligned memory structures. */
7752	class extraction_insn insn;
7753	unsigned int inner_size;
7754	if (GET_MODE_BITSIZE (mode: inner_mode).is_constant (const_value: &inner_size)
7755	&& get_best_reg_extraction_insn (&insn, pattern, inner_size, mode))
7756	{
7757	wanted_inner_reg_mode = insn.struct_mode.require ();
7758	pos_mode = insn.pos_mode;
7759	extraction_mode = insn.field_mode;
7760	}
7761
7762	/* Never narrow an object, since that might not be safe. */
7763
7764	if (mode != VOIDmode
7765	&& partial_subreg_p (outermode: extraction_mode, innermode: mode))
7766	extraction_mode = mode;
7767
7768	/* Punt if len is too large for extraction_mode. */
7769	if (maybe_gt (len, GET_MODE_PRECISION (extraction_mode)))
7770	return NULL_RTX;
7771
7772	if (!MEM_P (inner))
7773	wanted_inner_mode = wanted_inner_reg_mode;
7774	else
7775	{
7776	/* Be careful not to go beyond the extracted object and maintain the
7777	natural alignment of the memory. */
7778	wanted_inner_mode = smallest_int_mode_for_size (size: len);
7779	while (pos % GET_MODE_BITSIZE (mode: wanted_inner_mode) + len
7780	> GET_MODE_BITSIZE (mode: wanted_inner_mode))
7781	wanted_inner_mode = GET_MODE_WIDER_MODE (m: wanted_inner_mode).require ();
7782	}
7783
7784	orig_pos = pos;
7785
7786	if (BITS_BIG_ENDIAN)
7787	{
7788	/* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
7789	BITS_BIG_ENDIAN style. If position is constant, compute new
7790	position. Otherwise, build subtraction.
7791	Note that POS is relative to the mode of the original argument.
7792	If it's a MEM we need to recompute POS relative to that.
7793	However, if we're extracting from (or inserting into) a register,
7794	we want to recompute POS relative to wanted_inner_mode. */
7795	int width;
7796	if (!MEM_P (inner))
7797	width = GET_MODE_BITSIZE (mode: wanted_inner_mode);
7798	else if (!GET_MODE_BITSIZE (mode: is_mode).is_constant (const_value: &width))
7799	return NULL_RTX;
7800
7801	if (pos_rtx == 0)
7802	pos = width - len - pos;
7803	else
7804	pos_rtx
7805	= gen_rtx_MINUS (GET_MODE (pos_rtx),
7806	gen_int_mode (width - len, GET_MODE (pos_rtx)),
7807	pos_rtx);
7808	/* POS may be less than 0 now, but we check for that below.
7809	Note that it can only be less than 0 if !MEM_P (inner). */
7810	}
7811
7812	/* If INNER has a wider mode, and this is a constant extraction, try to
7813	make it smaller and adjust the byte to point to the byte containing
7814	the value. */
7815	if (wanted_inner_mode != VOIDmode
7816	&& inner_mode != wanted_inner_mode
7817	&& ! pos_rtx
7818	&& partial_subreg_p (outermode: wanted_inner_mode, innermode: is_mode)
7819	&& MEM_P (inner)
7820	&& ! mode_dependent_address_p (XEXP (inner, 0), MEM_ADDR_SPACE (inner))
7821	&& ! MEM_VOLATILE_P (inner))
7822	{
7823	poly_int64 offset = 0;
7824
7825	/* The computations below will be correct if the machine is big
7826	endian in both bits and bytes or little endian in bits and bytes.
7827	If it is mixed, we must adjust. */
7828
7829	/* If bytes are big endian and we had a paradoxical SUBREG, we must
7830	adjust OFFSET to compensate. */
7831	if (BYTES_BIG_ENDIAN
7832	&& paradoxical_subreg_p (outermode: is_mode, innermode: inner_mode))
7833	offset -= GET_MODE_SIZE (mode: is_mode) - GET_MODE_SIZE (mode: inner_mode);
7834
7835	/* We can now move to the desired byte. */
7836	offset += (pos / GET_MODE_BITSIZE (mode: wanted_inner_mode))
7837	* GET_MODE_SIZE (mode: wanted_inner_mode);
7838	pos %= GET_MODE_BITSIZE (mode: wanted_inner_mode);
7839
7840	if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
7841	&& is_mode != wanted_inner_mode)
7842	offset = (GET_MODE_SIZE (mode: is_mode)
7843	- GET_MODE_SIZE (mode: wanted_inner_mode) - offset);
7844
7845	inner = adjust_address_nv (inner, wanted_inner_mode, offset);
7846	}
7847
7848	/* If INNER is not memory, get it into the proper mode. If we are changing
7849	its mode, POS must be a constant and smaller than the size of the new
7850	mode. */
7851	else if (!MEM_P (inner))
7852	{
7853	/* On the LHS, don't create paradoxical subregs implicitely truncating
7854	the register unless TARGET_TRULY_NOOP_TRUNCATION. */
7855	if (in_dest
7856	&& !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (inner),
7857	wanted_inner_mode))
7858	return NULL_RTX;
7859
7860	if (GET_MODE (inner) != wanted_inner_mode
7861	&& (pos_rtx != 0
7862	|| orig_pos + len > GET_MODE_BITSIZE (mode: wanted_inner_mode)))
7863	return NULL_RTX;
7864
7865	if (orig_pos < 0)
7866	return NULL_RTX;
7867
7868	inner = force_to_mode (inner, wanted_inner_mode,
7869	pos_rtx
7870	|| len + orig_pos >= HOST_BITS_PER_WIDE_INT
7871	? HOST_WIDE_INT_M1U
7872	: (((HOST_WIDE_INT_1U << len) - 1)
7873	<< orig_pos), false);
7874	}
7875
7876	/* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
7877	have to zero extend. Otherwise, we can just use a SUBREG.
7878
7879	We dealt with constant rtxes earlier, so pos_rtx cannot
7880	have VOIDmode at this point. */
7881	if (pos_rtx != 0
7882	&& (GET_MODE_SIZE (mode: pos_mode)
7883	> GET_MODE_SIZE (mode: as_a <scalar_int_mode> (GET_MODE (pos_rtx)))))
7884	{
7885	rtx temp = simplify_gen_unary (code: ZERO_EXTEND, mode: pos_mode, op: pos_rtx,
7886	GET_MODE (pos_rtx));
7887
7888	/* If we know that no extraneous bits are set, and that the high
7889	bit is not set, convert extraction to cheaper one - either
7890	SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
7891	cases. */
7892	if (flag_expensive_optimizations
7893	&& (HWI_COMPUTABLE_MODE_P (GET_MODE (pos_rtx))
7894	&& ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
7895	& ~(((unsigned HOST_WIDE_INT)
7896	GET_MODE_MASK (GET_MODE (pos_rtx)))
7897	>> 1))
7898	== 0)))
7899	{
7900	rtx temp1 = simplify_gen_unary (code: SIGN_EXTEND, mode: pos_mode, op: pos_rtx,
7901	GET_MODE (pos_rtx));
7902
7903	/* Prefer ZERO_EXTENSION, since it gives more information to
7904	backends. */
7905	if (set_src_cost (x: temp1, mode: pos_mode, speed_p: optimize_this_for_speed_p)
7906	< set_src_cost (x: temp, mode: pos_mode, speed_p: optimize_this_for_speed_p))
7907	temp = temp1;
7908	}
7909	pos_rtx = temp;
7910	}
7911
7912	/* Make POS_RTX unless we already have it and it is correct. If we don't
7913	have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
7914	be a CONST_INT. */
7915	if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
7916	pos_rtx = orig_pos_rtx;
7917
7918	else if (pos_rtx == 0)
7919	pos_rtx = GEN_INT (pos);
7920
7921	/* Make the required operation. See if we can use existing rtx. */
7922	new_rtx = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
7923	extraction_mode, inner, GEN_INT (len), pos_rtx);
7924	if (! in_dest)
7925	new_rtx = gen_lowpart (mode, new_rtx);
7926
7927	return new_rtx;
7928	}
7929
7930	/* See if X (of mode MODE) contains an ASHIFT of COUNT or more bits that
7931	can be commuted with any other operations in X. Return X without
7932	that shift if so. */
7933
7934	static rtx
7935	extract_left_shift (scalar_int_mode mode, rtx x, int count)
7936	{
7937	enum rtx_code code = GET_CODE (x);
7938	rtx tem;
7939
7940	switch (code)
7941	{
7942	case ASHIFT:
7943	/* This is the shift itself. If it is wide enough, we will return
7944	either the value being shifted if the shift count is equal to
7945	COUNT or a shift for the difference. */
7946	if (CONST_INT_P (XEXP (x, 1))
7947	&& INTVAL (XEXP (x, 1)) >= count)
7948	return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
7949	INTVAL (XEXP (x, 1)) - count);
7950	break;
7951
7952	case NEG: case NOT:
7953	if ((tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
7954	return simplify_gen_unary (code, mode, op: tem, op_mode: mode);
7955
7956	break;
7957
7958	case PLUS: case IOR: case XOR: case AND:
7959	/* If we can safely shift this constant and we find the inner shift,
7960	make a new operation. */
7961	if (CONST_INT_P (XEXP (x, 1))
7962	&& (UINTVAL (XEXP (x, 1))
7963	& (((HOST_WIDE_INT_1U << count)) - 1)) == 0
7964	&& (tem = extract_left_shift (mode, XEXP (x, 0), count)) != 0)
7965	{
7966	HOST_WIDE_INT val = INTVAL (XEXP (x, 1)) >> count;
7967	return simplify_gen_binary (code, mode, op0: tem,
7968	op1: gen_int_mode (val, mode));
7969	}
7970	break;
7971
7972	default:
7973	break;
7974	}
7975
7976	return 0;
7977	}
7978
7979	/* Subroutine of make_compound_operation. *X_PTR is the rtx at the current
7980	level of the expression and MODE is its mode. IN_CODE is as for
7981	make_compound_operation. *NEXT_CODE_PTR is the value of IN_CODE
7982	that should be used when recursing on operands of *X_PTR.
7983
7984	There are two possible actions:
7985
7986	- Return null. This tells the caller to recurse on *X_PTR with IN_CODE
7987	equal to *NEXT_CODE_PTR, after which *X_PTR holds the final value.
7988
7989	- Return a new rtx, which the caller returns directly. */
7990
7991	static rtx
7992	make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
7993	enum rtx_code in_code,
7994	enum rtx_code *next_code_ptr)
7995	{
7996	rtx x = *x_ptr;
7997	enum rtx_code next_code = *next_code_ptr;
7998	enum rtx_code code = GET_CODE (x);
7999	int mode_width = GET_MODE_PRECISION (mode);
8000	rtx rhs, lhs;
8001	rtx new_rtx = 0;
8002	int i;
8003	rtx tem;
8004	scalar_int_mode inner_mode;
8005	bool equality_comparison = false;
8006
8007	if (in_code == EQ)
8008	{
8009	equality_comparison = true;
8010	in_code = COMPARE;
8011	}
8012
8013	/* Process depending on the code of this operation. If NEW is set
8014	nonzero, it will be returned. */
8015
8016	switch (code)
8017	{
8018	case ASHIFT:
8019	/* Convert shifts by constants into multiplications if inside
8020	an address. */
8021	if (in_code == MEM && CONST_INT_P (XEXP (x, 1))
8022	&& INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8023	&& INTVAL (XEXP (x, 1)) >= 0)
8024	{
8025	HOST_WIDE_INT count = INTVAL (XEXP (x, 1));
8026	HOST_WIDE_INT multval = HOST_WIDE_INT_1 << count;
8027
8028	new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8029	if (GET_CODE (new_rtx) == NEG)
8030	{
8031	new_rtx = XEXP (new_rtx, 0);
8032	multval = -multval;
8033	}
8034	multval = trunc_int_for_mode (multval, mode);
8035	new_rtx = gen_rtx_MULT (mode, new_rtx, gen_int_mode (multval, mode));
8036	}
8037	break;
8038
8039	case PLUS:
8040	lhs = XEXP (x, 0);
8041	rhs = XEXP (x, 1);
8042	lhs = make_compound_operation (lhs, next_code);
8043	rhs = make_compound_operation (rhs, next_code);
8044	if (GET_CODE (lhs) == MULT && GET_CODE (XEXP (lhs, 0)) == NEG)
8045	{
8046	tem = simplify_gen_binary (code: MULT, mode, XEXP (XEXP (lhs, 0), 0),
8047	XEXP (lhs, 1));
8048	new_rtx = simplify_gen_binary (code: MINUS, mode, op0: rhs, op1: tem);
8049	}
8050	else if (GET_CODE (lhs) == MULT
8051	&& (CONST_INT_P (XEXP (lhs, 1)) && INTVAL (XEXP (lhs, 1)) < 0))
8052	{
8053	tem = simplify_gen_binary (code: MULT, mode, XEXP (lhs, 0),
8054	op1: simplify_gen_unary (code: NEG, mode,
8055	XEXP (lhs, 1),
8056	op_mode: mode));
8057	new_rtx = simplify_gen_binary (code: MINUS, mode, op0: rhs, op1: tem);
8058	}
8059	else
8060	{
8061	SUBST (XEXP (x, 0), lhs);
8062	SUBST (XEXP (x, 1), rhs);
8063	}
8064	maybe_swap_commutative_operands (x);
8065	return x;
8066
8067	case MINUS:
8068	lhs = XEXP (x, 0);
8069	rhs = XEXP (x, 1);
8070	lhs = make_compound_operation (lhs, next_code);
8071	rhs = make_compound_operation (rhs, next_code);
8072	if (GET_CODE (rhs) == MULT && GET_CODE (XEXP (rhs, 0)) == NEG)
8073	{
8074	tem = simplify_gen_binary (code: MULT, mode, XEXP (XEXP (rhs, 0), 0),
8075	XEXP (rhs, 1));
8076	return simplify_gen_binary (code: PLUS, mode, op0: tem, op1: lhs);
8077	}
8078	else if (GET_CODE (rhs) == MULT
8079	&& (CONST_INT_P (XEXP (rhs, 1)) && INTVAL (XEXP (rhs, 1)) < 0))
8080	{
8081	tem = simplify_gen_binary (code: MULT, mode, XEXP (rhs, 0),
8082	op1: simplify_gen_unary (code: NEG, mode,
8083	XEXP (rhs, 1),
8084	op_mode: mode));
8085	return simplify_gen_binary (code: PLUS, mode, op0: tem, op1: lhs);
8086	}
8087	else
8088	{
8089	SUBST (XEXP (x, 0), lhs);
8090	SUBST (XEXP (x, 1), rhs);
8091	return x;
8092	}
8093
8094	case AND:
8095	/* If the second operand is not a constant, we can't do anything
8096	with it. */
8097	if (!CONST_INT_P (XEXP (x, 1)))
8098	break;
8099
8100	/* If the constant is a power of two minus one and the first operand
8101	is a logical right shift, make an extraction. */
8102	if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8103	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8104	{
8105	new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8106	new_rtx = make_extraction (mode, inner: new_rtx, pos: 0, XEXP (XEXP (x, 0), 1),
8107	len: i, unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8108	}
8109
8110	/* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
8111	else if (GET_CODE (XEXP (x, 0)) == SUBREG
8112	&& subreg_lowpart_p (XEXP (x, 0))
8113	&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
8114	result: &inner_mode)
8115	&& GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
8116	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8117	{
8118	rtx inner_x0 = SUBREG_REG (XEXP (x, 0));
8119	new_rtx = make_compound_operation (XEXP (inner_x0, 0), next_code);
8120	new_rtx = make_extraction (mode: inner_mode, inner: new_rtx, pos: 0,
8121	XEXP (inner_x0, 1),
8122	len: i, unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8123
8124	/* If we narrowed the mode when dropping the subreg, then we lose. */
8125	if (GET_MODE_SIZE (mode: inner_mode) < GET_MODE_SIZE (mode))
8126	new_rtx = NULL;
8127
8128	/* If that didn't give anything, see if the AND simplifies on
8129	its own. */
8130	if (!new_rtx && i >= 0)
8131	{
8132	new_rtx = make_compound_operation (XEXP (x, 0), next_code);
8133	new_rtx = make_extraction (mode, inner: new_rtx, pos: 0, NULL_RTX, len: i,
8134	unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8135	}
8136	}
8137	/* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
8138	else if ((GET_CODE (XEXP (x, 0)) == XOR
8139	|| GET_CODE (XEXP (x, 0)) == IOR)
8140	&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
8141	&& GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
8142	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8143	{
8144	/* Apply the distributive law, and then try to make extractions. */
8145	new_rtx = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
8146	gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
8147	XEXP (x, 1)),
8148	gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
8149	XEXP (x, 1)));
8150	new_rtx = make_compound_operation (new_rtx, in_code);
8151	}
8152
8153	/* If we are have (and (rotate X C) M) and C is larger than the number
8154	of bits in M, this is an extraction. */
8155
8156	else if (GET_CODE (XEXP (x, 0)) == ROTATE
8157	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
8158	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0
8159	&& i <= INTVAL (XEXP (XEXP (x, 0), 1)))
8160	{
8161	new_rtx = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
8162	new_rtx = make_extraction (mode, inner: new_rtx,
8163	pos: (GET_MODE_PRECISION (mode)
8164	- INTVAL (XEXP (XEXP (x, 0), 1))),
8165	NULL_RTX, len: i, unsignedp: true, in_dest: false,
8166	in_compare: in_code == COMPARE);
8167	}
8168
8169	/* On machines without logical shifts, if the operand of the AND is
8170	a logical shift and our mask turns off all the propagated sign
8171	bits, we can replace the logical shift with an arithmetic shift. */
8172	else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8173	&& !have_insn_for (LSHIFTRT, mode)
8174	&& have_insn_for (ASHIFTRT, mode)
8175	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
8176	&& INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8177	&& INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8178	&& mode_width <= HOST_BITS_PER_WIDE_INT)
8179	{
8180	unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
8181
8182	mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
8183	if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
8184	SUBST (XEXP (x, 0),
8185	gen_rtx_ASHIFTRT (mode,
8186	make_compound_operation (XEXP (XEXP (x,
8187	0),
8188	0),
8189	next_code),
8190	XEXP (XEXP (x, 0), 1)));
8191	}
8192
8193	/* If the constant is one less than a power of two, this might be
8194	representable by an extraction even if no shift is present.
8195	If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
8196	we are in a COMPARE. */
8197	else if ((i = exact_log2 (UINTVAL (XEXP (x, 1)) + 1)) >= 0)
8198	new_rtx = make_extraction (mode,
8199	inner: make_compound_operation (XEXP (x, 0),
8200	next_code),
8201	pos: 0, NULL_RTX, len: i,
8202	unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8203
8204	/* If we are in a comparison and this is an AND with a power of two,
8205	convert this into the appropriate bit extract. */
8206	else if (in_code == COMPARE
8207	&& (i = exact_log2 (UINTVAL (XEXP (x, 1)))) >= 0
8208	&& (equality_comparison || i < GET_MODE_PRECISION (mode) - 1))
8209	new_rtx = make_extraction (mode,
8210	inner: make_compound_operation (XEXP (x, 0),
8211	next_code),
8212	pos: i, NULL_RTX, len: 1, unsignedp: true, in_dest: false, in_compare: true);
8213
8214	/* If the one operand is a paradoxical subreg of a register or memory and
8215	the constant (limited to the smaller mode) has only zero bits where
8216	the sub expression has known zero bits, this can be expressed as
8217	a zero_extend. */
8218	else if (GET_CODE (XEXP (x, 0)) == SUBREG)
8219	{
8220	rtx sub;
8221
8222	sub = XEXP (XEXP (x, 0), 0);
8223	machine_mode sub_mode = GET_MODE (sub);
8224	int sub_width;
8225	if ((REG_P (sub) || MEM_P (sub))
8226	&& GET_MODE_PRECISION (mode: sub_mode).is_constant (const_value: &sub_width)
8227	&& sub_width < mode_width)
8228	{
8229	unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (sub_mode);
8230	unsigned HOST_WIDE_INT mask;
8231
8232	/* original AND constant with all the known zero bits set */
8233	mask = UINTVAL (XEXP (x, 1)) | (~nonzero_bits (sub, sub_mode));
8234	if ((mask & mode_mask) == mode_mask)
8235	{
8236	new_rtx = make_compound_operation (sub, next_code);
8237	new_rtx = make_extraction (mode, inner: new_rtx, pos: 0, pos_rtx: 0, len: sub_width,
8238	unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8239	}
8240	}
8241	}
8242
8243	break;
8244
8245	case LSHIFTRT:
8246	/* If the sign bit is known to be zero, replace this with an
8247	arithmetic shift. */
8248	if (have_insn_for (ASHIFTRT, mode)
8249	&& ! have_insn_for (LSHIFTRT, mode)
8250	&& mode_width <= HOST_BITS_PER_WIDE_INT
8251	&& (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
8252	{
8253	new_rtx = gen_rtx_ASHIFTRT (mode,
8254	make_compound_operation (XEXP (x, 0),
8255	next_code),
8256	XEXP (x, 1));
8257	break;
8258	}
8259
8260	/* fall through */
8261
8262	case ASHIFTRT:
8263	lhs = XEXP (x, 0);
8264	rhs = XEXP (x, 1);
8265
8266	/* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
8267	this is a SIGN_EXTRACT. */
8268	if (CONST_INT_P (rhs)
8269	&& GET_CODE (lhs) == ASHIFT
8270	&& CONST_INT_P (XEXP (lhs, 1))
8271	&& INTVAL (rhs) >= INTVAL (XEXP (lhs, 1))
8272	&& INTVAL (XEXP (lhs, 1)) >= 0
8273	&& INTVAL (rhs) < mode_width)
8274	{
8275	new_rtx = make_compound_operation (XEXP (lhs, 0), next_code);
8276	new_rtx = make_extraction (mode, inner: new_rtx,
8277	INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
8278	NULL_RTX, len: mode_width - INTVAL (rhs),
8279	unsignedp: code == LSHIFTRT, in_dest: false,
8280	in_compare: in_code == COMPARE);
8281	break;
8282	}
8283
8284	/* See if we have operations between an ASHIFTRT and an ASHIFT.
8285	If so, try to merge the shifts into a SIGN_EXTEND. We could
8286	also do this for some cases of SIGN_EXTRACT, but it doesn't
8287	seem worth the effort; the case checked for occurs on Alpha. */
8288
8289	if (!OBJECT_P (lhs)
8290	&& ! (GET_CODE (lhs) == SUBREG
8291	&& (OBJECT_P (SUBREG_REG (lhs))))
8292	&& CONST_INT_P (rhs)
8293	&& INTVAL (rhs) >= 0
8294	&& INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
8295	&& INTVAL (rhs) < mode_width
8296	&& (new_rtx = extract_left_shift (mode, x: lhs, INTVAL (rhs))) != 0)
8297	new_rtx = make_extraction (mode, inner: make_compound_operation (new_rtx,
8298	next_code),
8299	pos: 0, NULL_RTX, len: mode_width - INTVAL (rhs),
8300	unsignedp: code == LSHIFTRT, in_dest: false, in_compare: in_code == COMPARE);
8301
8302	break;
8303
8304	case SUBREG:
8305	/* Call ourselves recursively on the inner expression. If we are
8306	narrowing the object and it has a different RTL code from
8307	what it originally did, do this SUBREG as a force_to_mode. */
8308	{
8309	rtx inner = SUBREG_REG (x), simplified;
8310	enum rtx_code subreg_code = in_code;
8311
8312	/* If the SUBREG is masking of a logical right shift,
8313	make an extraction. */
8314	if (GET_CODE (inner) == LSHIFTRT
8315	&& is_a <scalar_int_mode> (GET_MODE (inner), result: &inner_mode)
8316	&& GET_MODE_SIZE (mode) < GET_MODE_SIZE (mode: inner_mode)
8317	&& CONST_INT_P (XEXP (inner, 1))
8318	&& UINTVAL (XEXP (inner, 1)) < GET_MODE_PRECISION (mode: inner_mode)
8319	&& subreg_lowpart_p (x))
8320	{
8321	new_rtx = make_compound_operation (XEXP (inner, 0), next_code);
8322	int width = GET_MODE_PRECISION (mode: inner_mode)
8323	- INTVAL (XEXP (inner, 1));
8324	if (width > mode_width)
8325	width = mode_width;
8326	new_rtx = make_extraction (mode, inner: new_rtx, pos: 0, XEXP (inner, 1),
8327	len: width, unsignedp: true, in_dest: false, in_compare: in_code == COMPARE);
8328	break;
8329	}
8330
8331	/* If in_code is COMPARE, it isn't always safe to pass it through
8332	to the recursive make_compound_operation call. */
8333	if (subreg_code == COMPARE
8334	&& (!subreg_lowpart_p (x)
8335	|| GET_CODE (inner) == SUBREG
8336	/* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
8337	is (const_int 0), rather than
8338	(subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
8339	Similarly (subreg:QI (and:SI (reg:SI) (const_int 0x80)) 0)
8340	for non-equality comparisons against 0 is not equivalent
8341	to (subreg:QI (lshiftrt:SI (reg:SI) (const_int 7)) 0). */
8342	|| (GET_CODE (inner) == AND
8343	&& CONST_INT_P (XEXP (inner, 1))
8344	&& partial_subreg_p (x)
8345	&& exact_log2 (UINTVAL (XEXP (inner, 1)))
8346	>= GET_MODE_BITSIZE (mode) - 1)))
8347	subreg_code = SET;
8348
8349	tem = make_compound_operation (inner, subreg_code);
8350
8351	simplified
8352	= simplify_subreg (outermode: mode, op: tem, GET_MODE (inner), SUBREG_BYTE (x));
8353	if (simplified)
8354	tem = simplified;
8355
8356	if (GET_CODE (tem) != GET_CODE (inner)
8357	&& partial_subreg_p (x)
8358	&& subreg_lowpart_p (x))
8359	{
8360	rtx newer
8361	= force_to_mode (tem, mode, HOST_WIDE_INT_M1U, false);
8362
8363	/* If we have something other than a SUBREG, we might have
8364	done an expansion, so rerun ourselves. */
8365	if (GET_CODE (newer) != SUBREG)
8366	newer = make_compound_operation (newer, in_code);
8367
8368	/* force_to_mode can expand compounds. If it just re-expanded
8369	the compound, use gen_lowpart to convert to the desired
8370	mode. */
8371	if (rtx_equal_p (newer, x)
8372	/* Likewise if it re-expanded the compound only partially.
8373	This happens for SUBREG of ZERO_EXTRACT if they extract
8374	the same number of bits. */
8375	|| (GET_CODE (newer) == SUBREG
8376	&& (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
8377	|| GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
8378	&& GET_CODE (inner) == AND
8379	&& rtx_equal_p (SUBREG_REG (newer), XEXP (inner, 0))))
8380	return gen_lowpart (GET_MODE (x), tem);
8381
8382	return newer;
8383	}
8384
8385	if (simplified)
8386	return tem;
8387	}
8388	break;
8389
8390	default:
8391	break;
8392	}
8393
8394	if (new_rtx)
8395	*x_ptr = gen_lowpart (mode, new_rtx);
8396	*next_code_ptr = next_code;
8397	return NULL_RTX;
8398	}
8399
8400	/* Look at the expression rooted at X. Look for expressions
8401	equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
8402	Form these expressions.
8403
8404	Return the new rtx, usually just X.
8405
8406	Also, for machines like the VAX that don't have logical shift insns,
8407	try to convert logical to arithmetic shift operations in cases where
8408	they are equivalent. This undoes the canonicalizations to logical
8409	shifts done elsewhere.
8410
8411	We try, as much as possible, to re-use rtl expressions to save memory.
8412
8413	IN_CODE says what kind of expression we are processing. Normally, it is
8414	SET. In a memory address it is MEM. When processing the arguments of
8415	a comparison or a COMPARE against zero, it is COMPARE, or EQ if more
8416	precisely it is an equality comparison against zero. */
8417
8418	rtx
8419	make_compound_operation (rtx x, enum rtx_code in_code)
8420	{
8421	enum rtx_code code = GET_CODE (x);
8422	const char *fmt;
8423	int i, j;
8424	enum rtx_code next_code;
8425	rtx new_rtx, tem;
8426
8427	/* Select the code to be used in recursive calls. Once we are inside an
8428	address, we stay there. If we have a comparison, set to COMPARE,
8429	but once inside, go back to our default of SET. */
8430
8431	next_code = (code == MEM ? MEM
8432	: ((code == COMPARE || COMPARISON_P (x))
8433	&& XEXP (x, 1) == const0_rtx) ? COMPARE
8434	: in_code == COMPARE || in_code == EQ ? SET : in_code);
8435
8436	scalar_int_mode mode;
8437	if (is_a <scalar_int_mode> (GET_MODE (x), result: &mode))
8438	{
8439	rtx new_rtx = make_compound_operation_int (mode, x_ptr: &x, in_code,
8440	next_code_ptr: &next_code);
8441	if (new_rtx)
8442	return new_rtx;
8443	code = GET_CODE (x);
8444	}
8445
8446	/* Now recursively process each operand of this operation. We need to
8447	handle ZERO_EXTEND specially so that we don't lose track of the
8448	inner mode. */
8449	if (code == ZERO_EXTEND)
8450	{
8451	new_rtx = make_compound_operation (XEXP (x, 0), in_code: next_code);
8452	tem = simplify_unary_operation (code: ZERO_EXTEND, GET_MODE (x),
8453	op: new_rtx, GET_MODE (XEXP (x, 0)));
8454	if (tem)
8455	return tem;
8456	SUBST (XEXP (x, 0), new_rtx);
8457	return x;
8458	}
8459
8460	fmt = GET_RTX_FORMAT (code);
8461	for (i = 0; i < GET_RTX_LENGTH (code); i++)
8462	if (fmt[i] == 'e')
8463	{
8464	new_rtx = make_compound_operation (XEXP (x, i), in_code: next_code);
8465	SUBST (XEXP (x, i), new_rtx);
8466	}
8467	else if (fmt[i] == 'E')
8468	for (j = 0; j < XVECLEN (x, i); j++)
8469	{
8470	new_rtx = make_compound_operation (XVECEXP (x, i, j), in_code: next_code);
8471	SUBST (XVECEXP (x, i, j), new_rtx);
8472	}
8473
8474	maybe_swap_commutative_operands (x);
8475	return x;
8476	}
8477
8478	/* Given M see if it is a value that would select a field of bits
8479	within an item, but not the entire word. Return -1 if not.
8480	Otherwise, return the starting position of the field, where 0 is the
8481	low-order bit.
8482
8483	*PLEN is set to the length of the field. */
8484
8485	static int
8486	get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
8487	{
8488	/* Get the bit number of the first 1 bit from the right, -1 if none. */
8489	int pos = m ? ctz_hwi (x: m) : -1;
8490	int len = 0;
8491
8492	if (pos >= 0)
8493	/* Now shift off the low-order zero bits and see if we have a
8494	power of two minus 1. */
8495	len = exact_log2 (x: (m >> pos) + 1);
8496
8497	if (len <= 0)
8498	pos = -1;
8499
8500	*plen = len;
8501	return pos;
8502	}
8503
8504	/* If X refers to a register that equals REG in value, replace these
8505	references with REG. */
8506	static rtx
8507	canon_reg_for_combine (rtx x, rtx reg)
8508	{
8509	rtx op0, op1, op2;
8510	const char *fmt;
8511	int i;
8512	bool copied;
8513
8514	enum rtx_code code = GET_CODE (x);
8515	switch (GET_RTX_CLASS (code))
8516	{
8517	case RTX_UNARY:
8518	op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8519	if (op0 != XEXP (x, 0))
8520	return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op: op0,
8521	GET_MODE (reg));
8522	break;
8523
8524	case RTX_BIN_ARITH:
8525	case RTX_COMM_ARITH:
8526	op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8527	op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8528	if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8529	return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
8530	break;
8531
8532	case RTX_COMPARE:
8533	case RTX_COMM_COMPARE:
8534	op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8535	op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8536	if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8537	return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
8538	GET_MODE (op0), op0, op1);
8539	break;
8540
8541	case RTX_TERNARY:
8542	case RTX_BITFIELD_OPS:
8543	op0 = canon_reg_for_combine (XEXP (x, 0), reg);
8544	op1 = canon_reg_for_combine (XEXP (x, 1), reg);
8545	op2 = canon_reg_for_combine (XEXP (x, 2), reg);
8546	if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
8547	return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
8548	GET_MODE (op0), op0, op1, op2);
8549	/* FALLTHRU */
8550
8551	case RTX_OBJ:
8552	if (REG_P (x))
8553	{
8554	if (rtx_equal_p (get_last_value (reg), x)
8555	|| rtx_equal_p (reg, get_last_value (x)))
8556	return reg;
8557	else
8558	break;
8559	}
8560
8561	/* fall through */
8562
8563	default:
8564	fmt = GET_RTX_FORMAT (code);
8565	copied = false;
8566	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8567	if (fmt[i] == 'e')
8568	{
8569	rtx op = canon_reg_for_combine (XEXP (x, i), reg);
8570	if (op != XEXP (x, i))
8571	{
8572	if (!copied)
8573	{
8574	copied = true;
8575	x = copy_rtx (x);
8576	}
8577	XEXP (x, i) = op;
8578	}
8579	}
8580	else if (fmt[i] == 'E')
8581	{
8582	int j;
8583	for (j = 0; j < XVECLEN (x, i); j++)
8584	{
8585	rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
8586	if (op != XVECEXP (x, i, j))
8587	{
8588	if (!copied)
8589	{
8590	copied = true;
8591	x = copy_rtx (x);
8592	}
8593	XVECEXP (x, i, j) = op;
8594	}
8595	}
8596	}
8597
8598	break;
8599	}
8600
8601	return x;
8602	}
8603
8604	/* Return X converted to MODE. If the value is already truncated to
8605	MODE we can just return a subreg even though in the general case we
8606	would need an explicit truncation. */
8607
8608	static rtx
8609	gen_lowpart_or_truncate (machine_mode mode, rtx x)
8610	{
8611	if (!CONST_INT_P (x)
8612	&& partial_subreg_p (outermode: mode, GET_MODE (x))
8613	&& !TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (x))
8614	&& !(REG_P (x) && reg_truncated_to_mode (mode, x)))
8615	{
8616	/* Bit-cast X into an integer mode. */
8617	if (!SCALAR_INT_MODE_P (GET_MODE (x)))
8618	x = gen_lowpart (int_mode_for_mode (GET_MODE (x)).require (), x);
8619	x = simplify_gen_unary (code: TRUNCATE, mode: int_mode_for_mode (mode).require (),
8620	op: x, GET_MODE (x));
8621	}
8622
8623	return gen_lowpart (mode, x);
8624	}
8625
8626	/* See if X can be simplified knowing that we will only refer to it in
8627	MODE and will only refer to those bits that are nonzero in MASK.
8628	If other bits are being computed or if masking operations are done
8629	that select a superset of the bits in MASK, they can sometimes be
8630	ignored.
8631
8632	Return a possibly simplified expression, but always convert X to
8633	MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
8634
8635	If JUST_SELECT is true, don't optimize by noticing that bits in MASK
8636	are all off in X. This is used when X will be complemented, by either
8637	NOT, NEG, or XOR. */
8638
8639	static rtx
8640	force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
8641	bool just_select)
8642	{
8643	enum rtx_code code = GET_CODE (x);
8644	bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8645	machine_mode op_mode;
8646	unsigned HOST_WIDE_INT nonzero;
8647
8648	/* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
8649	code below will do the wrong thing since the mode of such an
8650	expression is VOIDmode.
8651
8652	Also do nothing if X is a CLOBBER; this can happen if X was
8653	the return value from a call to gen_lowpart. */
8654	if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
8655	return x;
8656
8657	/* We want to perform the operation in its present mode unless we know
8658	that the operation is valid in MODE, in which case we do the operation
8659	in MODE. */
8660	op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
8661	&& have_insn_for (code, mode))
8662	? mode : GET_MODE (x));
8663
8664	/* It is not valid to do a right-shift in a narrower mode
8665	than the one it came in with. */
8666	if ((code == LSHIFTRT || code == ASHIFTRT)
8667	&& partial_subreg_p (outermode: mode, GET_MODE (x)))
8668	op_mode = GET_MODE (x);
8669
8670	/* Truncate MASK to fit OP_MODE. */
8671	if (op_mode)
8672	mask &= GET_MODE_MASK (op_mode);
8673
8674	/* Determine what bits of X are guaranteed to be (non)zero. */
8675	nonzero = nonzero_bits (x, mode);
8676
8677	/* If none of the bits in X are needed, return a zero. */
8678	if (!just_select && (nonzero & mask) == 0 && !side_effects_p (x))
8679	x = const0_rtx;
8680
8681	/* If X is a CONST_INT, return a new one. Do this here since the
8682	test below will fail. */
8683	if (CONST_INT_P (x))
8684	{
8685	if (SCALAR_INT_MODE_P (mode))
8686	return gen_int_mode (INTVAL (x) & mask, mode);
8687	else
8688	{
8689	x = GEN_INT (INTVAL (x) & mask);
8690	return gen_lowpart_common (mode, x);
8691	}
8692	}
8693
8694	/* If X is narrower than MODE and we want all the bits in X's mode, just
8695	get X in the proper mode. */
8696	if (paradoxical_subreg_p (outermode: mode, GET_MODE (x))
8697	&& (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
8698	return gen_lowpart (mode, x);
8699
8700	/* We can ignore the effect of a SUBREG if it narrows the mode or
8701	if the constant masks to zero all the bits the mode doesn't have. */
8702	if (GET_CODE (x) == SUBREG
8703	&& subreg_lowpart_p (x)
8704	&& (partial_subreg_p (x)
8705	|| (mask
8706	& GET_MODE_MASK (GET_MODE (x))
8707	& ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))) == 0))
8708	return force_to_mode (SUBREG_REG (x), mode, mask, just_select: next_select);
8709
8710	scalar_int_mode int_mode, xmode;
8711	if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
8712	&& is_a <scalar_int_mode> (GET_MODE (x), result: &xmode))
8713	/* OP_MODE is either MODE or XMODE, so it must be a scalar
8714	integer too. */
8715	return force_int_to_mode (x, int_mode, xmode,
8716	as_a <scalar_int_mode> (m: op_mode),
8717	mask, just_select);
8718
8719	return gen_lowpart_or_truncate (mode, x);
8720	}
8721
8722	/* Subroutine of force_to_mode that handles cases in which both X and
8723	the result are scalar integers. MODE is the mode of the result,
8724	XMODE is the mode of X, and OP_MODE says which of MODE or XMODE
8725	is preferred for simplified versions of X. The other arguments
8726	are as for force_to_mode. */
8727
8728	static rtx
8729	force_int_to_mode (rtx x, scalar_int_mode mode, scalar_int_mode xmode,
8730	scalar_int_mode op_mode, unsigned HOST_WIDE_INT mask,
8731	bool just_select)
8732	{
8733	enum rtx_code code = GET_CODE (x);
8734	bool next_select = just_select || code == XOR || code == NOT || code == NEG;
8735	unsigned HOST_WIDE_INT fuller_mask;
8736	rtx op0, op1, temp;
8737	poly_int64 const_op0;
8738
8739	/* When we have an arithmetic operation, or a shift whose count we
8740	do not know, we need to assume that all bits up to the highest-order
8741	bit in MASK will be needed. This is how we form such a mask. */
8742	if (mask & (HOST_WIDE_INT_1U << (HOST_BITS_PER_WIDE_INT - 1)))
8743	fuller_mask = HOST_WIDE_INT_M1U;
8744	else
8745	fuller_mask = ((HOST_WIDE_INT_1U << (floor_log2 (x: mask) + 1)) - 1);
8746
8747	switch (code)
8748	{
8749	case CLOBBER:
8750	/* If X is a (clobber (const_int)), return it since we know we are
8751	generating something that won't match. */
8752	return x;
8753
8754	case SIGN_EXTEND:
8755	case ZERO_EXTEND:
8756	case ZERO_EXTRACT:
8757	case SIGN_EXTRACT:
8758	x = expand_compound_operation (x);
8759	if (GET_CODE (x) != code)
8760	return force_to_mode (x, mode, mask, just_select: next_select);
8761	break;
8762
8763	case TRUNCATE:
8764	/* Similarly for a truncate. */
8765	return force_to_mode (XEXP (x, 0), mode, mask, just_select: next_select);
8766
8767	case AND:
8768	/* If this is an AND with a constant, convert it into an AND
8769	whose constant is the AND of that constant with MASK. If it
8770	remains an AND of MASK, delete it since it is redundant. */
8771
8772	if (CONST_INT_P (XEXP (x, 1)))
8773	{
8774	x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
8775	mask & INTVAL (XEXP (x, 1)));
8776	xmode = op_mode;
8777
8778	/* If X is still an AND, see if it is an AND with a mask that
8779	is just some low-order bits. If so, and it is MASK, we don't
8780	need it. */
8781
8782	if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8783	&& (INTVAL (XEXP (x, 1)) & GET_MODE_MASK (xmode)) == mask)
8784	x = XEXP (x, 0);
8785
8786	/* If it remains an AND, try making another AND with the bits
8787	in the mode mask that aren't in MASK turned on. If the
8788	constant in the AND is wide enough, this might make a
8789	cheaper constant. */
8790
8791	if (GET_CODE (x) == AND && CONST_INT_P (XEXP (x, 1))
8792	&& GET_MODE_MASK (xmode) != mask
8793	&& HWI_COMPUTABLE_MODE_P (mode: xmode))
8794	{
8795	unsigned HOST_WIDE_INT cval
8796	= UINTVAL (XEXP (x, 1)) | (GET_MODE_MASK (xmode) & ~mask);
8797	rtx y;
8798
8799	y = simplify_gen_binary (code: AND, mode: xmode, XEXP (x, 0),
8800	op1: gen_int_mode (cval, xmode));
8801	if (set_src_cost (x: y, mode: xmode, speed_p: optimize_this_for_speed_p)
8802	< set_src_cost (x, mode: xmode, speed_p: optimize_this_for_speed_p))
8803	x = y;
8804	}
8805
8806	break;
8807	}
8808
8809	goto binop;
8810
8811	case PLUS:
8812	/* In (and (plus FOO C1) M), if M is a mask that just turns off
8813	low-order bits (as in an alignment operation) and FOO is already
8814	aligned to that boundary, mask C1 to that boundary as well.
8815	This may eliminate that PLUS and, later, the AND. */
8816
8817	{
8818	unsigned int width = GET_MODE_PRECISION (mode);
8819	unsigned HOST_WIDE_INT smask = mask;
8820
8821	/* If MODE is narrower than HOST_WIDE_INT and mask is a negative
8822	number, sign extend it. */
8823
8824	if (width < HOST_BITS_PER_WIDE_INT
8825	&& (smask & (HOST_WIDE_INT_1U << (width - 1))) != 0)
8826	smask |= HOST_WIDE_INT_M1U << width;
8827
8828	if (CONST_INT_P (XEXP (x, 1))
8829	&& pow2p_hwi (x: - smask)
8830	&& (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
8831	&& (INTVAL (XEXP (x, 1)) & ~smask) != 0)
8832	return force_to_mode (x: plus_constant (xmode, XEXP (x, 0),
8833	(INTVAL (XEXP (x, 1)) & smask)),
8834	mode, mask: smask, just_select: next_select);
8835	}
8836
8837	/* fall through */
8838
8839	case MULT:
8840	/* Substituting into the operands of a widening MULT is not likely to
8841	create RTL matching a machine insn. */
8842	if (code == MULT
8843	&& (GET_CODE (XEXP (x, 0)) == ZERO_EXTEND
8844	|| GET_CODE (XEXP (x, 0)) == SIGN_EXTEND)
8845	&& (GET_CODE (XEXP (x, 1)) == ZERO_EXTEND
8846	|| GET_CODE (XEXP (x, 1)) == SIGN_EXTEND)
8847	&& REG_P (XEXP (XEXP (x, 0), 0))
8848	&& REG_P (XEXP (XEXP (x, 1), 0)))
8849	return gen_lowpart_or_truncate (mode, x);
8850
8851	/* For PLUS, MINUS and MULT, we need any bits less significant than the
8852	most significant bit in MASK since carries from those bits will
8853	affect the bits we are interested in. */
8854	mask = fuller_mask;
8855	goto binop;
8856
8857	case MINUS:
8858	/* If X is (minus C Y) where C's least set bit is larger than any bit
8859	in the mask, then we may replace with (neg Y). */
8860	if (poly_int_rtx_p (XEXP (x, 0), res: &const_op0)
8861	&& known_alignment (a: poly_uint64 (const_op0)) > mask)
8862	{
8863	x = simplify_gen_unary (code: NEG, mode: xmode, XEXP (x, 1), op_mode: xmode);
8864	return force_to_mode (x, mode, mask, just_select: next_select);
8865	}
8866
8867	/* Similarly, if C contains every bit in the fuller_mask, then we may
8868	replace with (not Y). */
8869	if (CONST_INT_P (XEXP (x, 0))
8870	&& ((UINTVAL (XEXP (x, 0)) | fuller_mask) == UINTVAL (XEXP (x, 0))))
8871	{
8872	x = simplify_gen_unary (code: NOT, mode: xmode, XEXP (x, 1), op_mode: xmode);
8873	return force_to_mode (x, mode, mask, just_select: next_select);
8874	}
8875
8876	mask = fuller_mask;
8877	goto binop;
8878
8879	case IOR:
8880	case XOR:
8881	/* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
8882	LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
8883	operation which may be a bitfield extraction. Ensure that the
8884	constant we form is not wider than the mode of X. */
8885
8886	if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
8887	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
8888	&& INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
8889	&& INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
8890	&& CONST_INT_P (XEXP (x, 1))
8891	&& ((INTVAL (XEXP (XEXP (x, 0), 1))
8892	+ floor_log2 (INTVAL (XEXP (x, 1))))
8893	< GET_MODE_PRECISION (mode: xmode))
8894	&& (UINTVAL (XEXP (x, 1))
8895	& ~nonzero_bits (XEXP (x, 0), xmode)) == 0)
8896	{
8897	temp = gen_int_mode ((INTVAL (XEXP (x, 1)) & mask)
8898	<< INTVAL (XEXP (XEXP (x, 0), 1)),
8899	xmode);
8900	temp = simplify_gen_binary (GET_CODE (x), mode: xmode,
8901	XEXP (XEXP (x, 0), 0), op1: temp);
8902	x = simplify_gen_binary (code: LSHIFTRT, mode: xmode, op0: temp,
8903	XEXP (XEXP (x, 0), 1));
8904	return force_to_mode (x, mode, mask, just_select: next_select);
8905	}
8906
8907	binop:
8908	/* For most binary operations, just propagate into the operation and
8909	change the mode if we have an operation of that mode. */
8910
8911	op0 = force_to_mode (XEXP (x, 0), mode, mask, just_select: next_select);
8912	op1 = force_to_mode (XEXP (x, 1), mode, mask, just_select: next_select);
8913
8914	/* If we ended up truncating both operands, truncate the result of the
8915	operation instead. */
8916	if (GET_CODE (op0) == TRUNCATE
8917	&& GET_CODE (op1) == TRUNCATE)
8918	{
8919	op0 = XEXP (op0, 0);
8920	op1 = XEXP (op1, 0);
8921	}
8922
8923	op0 = gen_lowpart_or_truncate (mode: op_mode, x: op0);
8924	op1 = gen_lowpart_or_truncate (mode: op_mode, x: op1);
8925
8926	if (op_mode != xmode || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
8927	{
8928	x = simplify_gen_binary (code, mode: op_mode, op0, op1);
8929	xmode = op_mode;
8930	}
8931	break;
8932
8933	case ASHIFT:
8934	/* For left shifts, do the same, but just for the first operand.
8935	However, we cannot do anything with shifts where we cannot
8936	guarantee that the counts are smaller than the size of the mode
8937	because such a count will have a different meaning in a
8938	wider mode. */
8939
8940	if (! (CONST_INT_P (XEXP (x, 1))
8941	&& INTVAL (XEXP (x, 1)) >= 0
8942	&& INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode))
8943	&& ! (GET_MODE (XEXP (x, 1)) != VOIDmode
8944	&& (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
8945	< (unsigned HOST_WIDE_INT) GET_MODE_PRECISION (mode))))
8946	break;
8947
8948	/* If the shift count is a constant and we can do arithmetic in
8949	the mode of the shift, refine which bits we need. Otherwise, use the
8950	conservative form of the mask. */
8951	if (CONST_INT_P (XEXP (x, 1))
8952	&& INTVAL (XEXP (x, 1)) >= 0
8953	&& INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (mode: op_mode)
8954	&& HWI_COMPUTABLE_MODE_P (mode: op_mode))
8955	mask >>= INTVAL (XEXP (x, 1));
8956	else
8957	mask = fuller_mask;
8958
8959	op0 = gen_lowpart_or_truncate (mode: op_mode,
8960	x: force_to_mode (XEXP (x, 0), mode,
8961	mask, just_select: next_select));
8962
8963	if (op_mode != xmode || op0 != XEXP (x, 0))
8964	{
8965	x = simplify_gen_binary (code, mode: op_mode, op0, XEXP (x, 1));
8966	xmode = op_mode;
8967	}
8968	break;
8969
8970	case LSHIFTRT:
8971	/* Here we can only do something if the shift count is a constant,
8972	this shift constant is valid for the host, and we can do arithmetic
8973	in OP_MODE. */
8974
8975	if (CONST_INT_P (XEXP (x, 1))
8976	&& INTVAL (XEXP (x, 1)) >= 0
8977	&& INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
8978	&& HWI_COMPUTABLE_MODE_P (mode: op_mode))
8979	{
8980	rtx inner = XEXP (x, 0);
8981	unsigned HOST_WIDE_INT inner_mask;
8982
8983	/* Select the mask of the bits we need for the shift operand. */
8984	inner_mask = mask << INTVAL (XEXP (x, 1));
8985
8986	/* We can only change the mode of the shift if we can do arithmetic
8987	in the mode of the shift and INNER_MASK is no wider than the
8988	width of X's mode. */
8989	if ((inner_mask & ~GET_MODE_MASK (xmode)) != 0)
8990	op_mode = xmode;
8991
8992	inner = force_to_mode (x: inner, mode: op_mode, mask: inner_mask, just_select: next_select);
8993
8994	if (xmode != op_mode || inner != XEXP (x, 0))
8995	{
8996	x = simplify_gen_binary (code: LSHIFTRT, mode: op_mode, op0: inner, XEXP (x, 1));
8997	xmode = op_mode;
8998	}
8999	}
9000
9001	/* If we have (and (lshiftrt FOO C1) C2) where the combination of the
9002	shift and AND produces only copies of the sign bit (C2 is one less
9003	than a power of two), we can do this with just a shift. */
9004
9005	if (GET_CODE (x) == LSHIFTRT
9006	&& CONST_INT_P (XEXP (x, 1))
9007	/* The shift puts one of the sign bit copies in the least significant
9008	bit. */
9009	&& ((INTVAL (XEXP (x, 1))
9010	+ num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
9011	>= GET_MODE_PRECISION (mode: xmode))
9012	&& pow2p_hwi (x: mask + 1)
9013	/* Number of bits left after the shift must be more than the mask
9014	needs. */
9015	&& ((INTVAL (XEXP (x, 1)) + exact_log2 (x: mask + 1))
9016	<= GET_MODE_PRECISION (mode: xmode))
9017	/* Must be more sign bit copies than the mask needs. */
9018	&& ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
9019	>= exact_log2 (x: mask + 1)))
9020	{
9021	int nbits = GET_MODE_PRECISION (mode: xmode) - exact_log2 (x: mask + 1);
9022	x = simplify_gen_binary (code: LSHIFTRT, mode: xmode, XEXP (x, 0),
9023	op1: gen_int_shift_amount (xmode, nbits));
9024	}
9025	goto shiftrt;
9026
9027	case ASHIFTRT:
9028	/* If we are just looking for the sign bit, we don't need this shift at
9029	all, even if it has a variable count. */
9030	if (val_signbit_p (xmode, mask))
9031	return force_to_mode (XEXP (x, 0), mode, mask, just_select: next_select);
9032
9033	/* If this is a shift by a constant, get a mask that contains those bits
9034	that are not copies of the sign bit. We then have two cases: If
9035	MASK only includes those bits, this can be a logical shift, which may
9036	allow simplifications. If MASK is a single-bit field not within
9037	those bits, we are requesting a copy of the sign bit and hence can
9038	shift the sign bit to the appropriate location. */
9039
9040	if (CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0
9041	&& INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
9042	{
9043	unsigned HOST_WIDE_INT nonzero;
9044	int i;
9045
9046	/* If the considered data is wider than HOST_WIDE_INT, we can't
9047	represent a mask for all its bits in a single scalar.
9048	But we only care about the lower bits, so calculate these. */
9049
9050	if (GET_MODE_PRECISION (mode: xmode) > HOST_BITS_PER_WIDE_INT)
9051	{
9052	nonzero = HOST_WIDE_INT_M1U;
9053
9054	/* GET_MODE_PRECISION (GET_MODE (x)) - INTVAL (XEXP (x, 1))
9055	is the number of bits a full-width mask would have set.
9056	We need only shift if these are fewer than nonzero can
9057	hold. If not, we must keep all bits set in nonzero. */
9058
9059	if (GET_MODE_PRECISION (mode: xmode) - INTVAL (XEXP (x, 1))
9060	< HOST_BITS_PER_WIDE_INT)
9061	nonzero >>= INTVAL (XEXP (x, 1))
9062	+ HOST_BITS_PER_WIDE_INT
9063	- GET_MODE_PRECISION (mode: xmode);
9064	}
9065	else
9066	{
9067	nonzero = GET_MODE_MASK (xmode);
9068	nonzero >>= INTVAL (XEXP (x, 1));
9069	}
9070
9071	if ((mask & ~nonzero) == 0)
9072	{
9073	x = simplify_shift_const (NULL_RTX, LSHIFTRT, xmode,
9074	XEXP (x, 0), INTVAL (XEXP (x, 1)));
9075	if (GET_CODE (x) != ASHIFTRT)
9076	return force_to_mode (x, mode, mask, just_select: next_select);
9077	}
9078
9079	else if ((i = exact_log2 (x: mask)) >= 0)
9080	{
9081	x = simplify_shift_const
9082	(NULL_RTX, LSHIFTRT, xmode, XEXP (x, 0),
9083	GET_MODE_PRECISION (mode: xmode) - 1 - i);
9084
9085	if (GET_CODE (x) != ASHIFTRT)
9086	return force_to_mode (x, mode, mask, just_select: next_select);
9087	}
9088	}
9089
9090	/* If MASK is 1, convert this to an LSHIFTRT. This can be done
9091	even if the shift count isn't a constant. */
9092	if (mask == 1)
9093	x = simplify_gen_binary (code: LSHIFTRT, mode: xmode, XEXP (x, 0), XEXP (x, 1));
9094
9095	shiftrt:
9096
9097	/* If this is a zero- or sign-extension operation that just affects bits
9098	we don't care about, remove it. Be sure the call above returned
9099	something that is still a shift. */
9100
9101	if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
9102	&& CONST_INT_P (XEXP (x, 1))
9103	&& INTVAL (XEXP (x, 1)) >= 0
9104	&& (INTVAL (XEXP (x, 1))
9105	<= GET_MODE_PRECISION (mode: xmode) - (floor_log2 (x: mask) + 1))
9106	&& GET_CODE (XEXP (x, 0)) == ASHIFT
9107	&& XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
9108	return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask, just_select: next_select);
9109
9110	break;
9111
9112	case ROTATE:
9113	case ROTATERT:
9114	/* If the shift count is constant and we can do computations
9115	in the mode of X, compute where the bits we care about are.
9116	Otherwise, we can't do anything. Don't change the mode of
9117	the shift or propagate MODE into the shift, though. */
9118	if (CONST_INT_P (XEXP (x, 1))
9119	&& INTVAL (XEXP (x, 1)) >= 0)
9120	{
9121	temp = simplify_binary_operation (code: code == ROTATE ? ROTATERT : ROTATE,
9122	mode: xmode, op0: gen_int_mode (mask, xmode),
9123	XEXP (x, 1));
9124	if (temp && CONST_INT_P (temp))
9125	x = simplify_gen_binary (code, mode: xmode,
9126	op0: force_to_mode (XEXP (x, 0), mode: xmode,
9127	INTVAL (temp), just_select: next_select),
9128	XEXP (x, 1));
9129	}
9130	break;
9131
9132	case NEG:
9133	/* If we just want the low-order bit, the NEG isn't needed since it
9134	won't change the low-order bit. */
9135	if (mask == 1)
9136	return force_to_mode (XEXP (x, 0), mode, mask, just_select);
9137
9138	/* We need any bits less significant than the most significant bit in
9139	MASK since carries from those bits will affect the bits we are
9140	interested in. */
9141	mask = fuller_mask;
9142	goto unop;
9143
9144	case NOT:
9145	/* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
9146	same as the XOR case above. Ensure that the constant we form is not
9147	wider than the mode of X. */
9148
9149	if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
9150	&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
9151	&& INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
9152	&& (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (x: mask)
9153	< GET_MODE_PRECISION (mode: xmode))
9154	&& INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
9155	{
9156	temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)), xmode);
9157	temp = simplify_gen_binary (code: XOR, mode: xmode, XEXP (XEXP (x, 0), 0), op1: temp);
9158	x = simplify_gen_binary (code: LSHIFTRT, mode: xmode,
9159	op0: temp, XEXP (XEXP (x, 0), 1));
9160
9161	return force_to_mode (x, mode, mask, just_select: next_select);
9162	}
9163
9164	/* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
9165	use the full mask inside the NOT. */
9166	mask = fuller_mask;
9167
9168	unop:
9169	op0 = gen_lowpart_or_truncate (mode: op_mode,
9170	x: force_to_mode (XEXP (x, 0), mode, mask,
9171	just_select: next_select));
9172	if (op_mode != xmode || op0 != XEXP (x, 0))
9173	{
9174	x = simplify_gen_unary (code, mode: op_mode, op: op0, op_mode);
9175	xmode = op_mode;
9176	}
9177	break;
9178
9179	case NE:
9180	/* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
9181	in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
9182	which is equal to STORE_FLAG_VALUE. */
9183	if ((mask & ~STORE_FLAG_VALUE) == 0
9184	&& XEXP (x, 1) == const0_rtx
9185	&& GET_MODE (XEXP (x, 0)) == mode
9186	&& pow2p_hwi (x: nonzero_bits (XEXP (x, 0), mode))
9187	&& (nonzero_bits (XEXP (x, 0), mode)
9188	== (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
9189	return force_to_mode (XEXP (x, 0), mode, mask, just_select: next_select);
9190
9191	break;
9192
9193	case IF_THEN_ELSE:
9194	/* We have no way of knowing if the IF_THEN_ELSE can itself be
9195	written in a narrower mode. We play it safe and do not do so. */
9196
9197	op0 = gen_lowpart_or_truncate (mode: xmode,
9198	x: force_to_mode (XEXP (x, 1), mode,
9199	mask, just_select: next_select));
9200	op1 = gen_lowpart_or_truncate (mode: xmode,
9201	x: force_to_mode (XEXP (x, 2), mode,
9202	mask, just_select: next_select));
9203	if (op0 != XEXP (x, 1) || op1 != XEXP (x, 2))
9204	x = simplify_gen_ternary (code: IF_THEN_ELSE, mode: xmode,
9205	GET_MODE (XEXP (x, 0)), XEXP (x, 0),
9206	op1: op0, op2: op1);
9207	break;
9208
9209	default:
9210	break;
9211	}
9212
9213	/* Ensure we return a value of the proper mode. */
9214	return gen_lowpart_or_truncate (mode, x);
9215	}
9216
9217	/* Return nonzero if X is an expression that has one of two values depending on
9218	whether some other value is zero or nonzero. In that case, we return the
9219	value that is being tested, *PTRUE is set to the value if the rtx being
9220	returned has a nonzero value, and *PFALSE is set to the other alternative.
9221
9222	If we return zero, we set *PTRUE and *PFALSE to X. */
9223
9224	static rtx
9225	if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
9226	{
9227	machine_mode mode = GET_MODE (x);
9228	enum rtx_code code = GET_CODE (x);
9229	rtx cond0, cond1, true0, true1, false0, false1;
9230	unsigned HOST_WIDE_INT nz;
9231	scalar_int_mode int_mode;
9232
9233	/* If we are comparing a value against zero, we are done. */
9234	if ((code == NE || code == EQ)
9235	&& XEXP (x, 1) == const0_rtx)
9236	{
9237	*ptrue = (code == NE) ? const_true_rtx : const0_rtx;
9238	*pfalse = (code == NE) ? const0_rtx : const_true_rtx;
9239	return XEXP (x, 0);
9240	}
9241
9242	/* If this is a unary operation whose operand has one of two values, apply
9243	our opcode to compute those values. */
9244	else if (UNARY_P (x)
9245	&& (cond0 = if_then_else_cond (XEXP (x, 0), ptrue: &true0, pfalse: &false0)) != 0)
9246	{
9247	*ptrue = simplify_gen_unary (code, mode, op: true0, GET_MODE (XEXP (x, 0)));
9248	*pfalse = simplify_gen_unary (code, mode, op: false0,
9249	GET_MODE (XEXP (x, 0)));
9250	return cond0;
9251	}
9252
9253	/* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
9254	make can't possibly match and would suppress other optimizations. */
9255	else if (code == COMPARE)
9256	;
9257
9258	/* If this is a binary operation, see if either side has only one of two
9259	values. If either one does or if both do and they are conditional on
9260	the same value, compute the new true and false values. */
9261	else if (BINARY_P (x))
9262	{
9263	rtx op0 = XEXP (x, 0);
9264	rtx op1 = XEXP (x, 1);
9265	cond0 = if_then_else_cond (x: op0, ptrue: &true0, pfalse: &false0);
9266	cond1 = if_then_else_cond (x: op1, ptrue: &true1, pfalse: &false1);
9267
9268	if ((cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1))
9269	&& (REG_P (op0) || REG_P (op1)))
9270	{
9271	/* Try to enable a simplification by undoing work done by
9272	if_then_else_cond if it converted a REG into something more
9273	complex. */
9274	if (REG_P (op0))
9275	{
9276	cond0 = 0;
9277	true0 = false0 = op0;
9278	}
9279	else
9280	{
9281	cond1 = 0;
9282	true1 = false1 = op1;
9283	}
9284	}
9285
9286	if ((cond0 != 0 || cond1 != 0)
9287	&& ! (cond0 != 0 && cond1 != 0 && !rtx_equal_p (cond0, cond1)))
9288	{
9289	/* If if_then_else_cond returned zero, then true/false are the
9290	same rtl. We must copy one of them to prevent invalid rtl
9291	sharing. */
9292	if (cond0 == 0)
9293	true0 = copy_rtx (true0);
9294	else if (cond1 == 0)
9295	true1 = copy_rtx (true1);
9296
9297	if (COMPARISON_P (x))
9298	{
9299	*ptrue = simplify_gen_relational (code, mode, VOIDmode,
9300	op0: true0, op1: true1);
9301	*pfalse = simplify_gen_relational (code, mode, VOIDmode,
9302	op0: false0, op1: false1);
9303	}
9304	else
9305	{
9306	*ptrue = simplify_gen_binary (code, mode, op0: true0, op1: true1);
9307	*pfalse = simplify_gen_binary (code, mode, op0: false0, op1: false1);
9308	}
9309
9310	return cond0 ? cond0 : cond1;
9311	}
9312
9313	/* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
9314	operands is zero when the other is nonzero, and vice-versa,
9315	and STORE_FLAG_VALUE is 1 or -1. */
9316
9317	if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9318	&& (code == PLUS || code == IOR || code == XOR || code == MINUS
9319	|| code == UMAX)
9320	&& GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9321	{
9322	rtx op0 = XEXP (XEXP (x, 0), 1);
9323	rtx op1 = XEXP (XEXP (x, 1), 1);
9324
9325	cond0 = XEXP (XEXP (x, 0), 0);
9326	cond1 = XEXP (XEXP (x, 1), 0);
9327
9328	if (COMPARISON_P (cond0)
9329	&& COMPARISON_P (cond1)
9330	&& SCALAR_INT_MODE_P (mode)
9331	&& ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9332	&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9333	&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9334	|| ((swap_condition (GET_CODE (cond0))
9335	== reversed_comparison_code (cond1, NULL))
9336	&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9337	&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9338	&& ! side_effects_p (x))
9339	{
9340	*ptrue = simplify_gen_binary (code: MULT, mode, op0, op1: const_true_rtx);
9341	*pfalse = simplify_gen_binary (code: MULT, mode,
9342	op0: (code == MINUS
9343	? simplify_gen_unary (code: NEG, mode,
9344	op: op1, op_mode: mode)
9345	: op1),
9346	op1: const_true_rtx);
9347	return cond0;
9348	}
9349	}
9350
9351	/* Similarly for MULT, AND and UMIN, except that for these the result
9352	is always zero. */
9353	if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
9354	&& (code == MULT || code == AND || code == UMIN)
9355	&& GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
9356	{
9357	cond0 = XEXP (XEXP (x, 0), 0);
9358	cond1 = XEXP (XEXP (x, 1), 0);
9359
9360	if (COMPARISON_P (cond0)
9361	&& COMPARISON_P (cond1)
9362	&& ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
9363	&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
9364	&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
9365	|| ((swap_condition (GET_CODE (cond0))
9366	== reversed_comparison_code (cond1, NULL))
9367	&& rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
9368	&& rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
9369	&& ! side_effects_p (x))
9370	{
9371	*ptrue = *pfalse = const0_rtx;
9372	return cond0;
9373	}
9374	}
9375	}
9376
9377	else if (code == IF_THEN_ELSE)
9378	{
9379	/* If we have IF_THEN_ELSE already, extract the condition and
9380	canonicalize it if it is NE or EQ. */
9381	cond0 = XEXP (x, 0);
9382	*ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
9383	if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
9384	return XEXP (cond0, 0);
9385	else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
9386	{
9387	*ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
9388	return XEXP (cond0, 0);
9389	}
9390	else
9391	return cond0;
9392	}
9393
9394	/* If X is a SUBREG, we can narrow both the true and false values
9395	if the inner expression, if there is a condition. */
9396	else if (code == SUBREG
9397	&& (cond0 = if_then_else_cond (SUBREG_REG (x), ptrue: &true0,
9398	pfalse: &false0)) != 0)
9399	{
9400	true0 = simplify_gen_subreg (outermode: mode, op: true0,
9401	GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9402	false0 = simplify_gen_subreg (outermode: mode, op: false0,
9403	GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
9404	if (true0 && false0)
9405	{
9406	*ptrue = true0;
9407	*pfalse = false0;
9408	return cond0;
9409	}
9410	}
9411
9412	/* If X is a constant, this isn't special and will cause confusions
9413	if we treat it as such. Likewise if it is equivalent to a constant. */
9414	else if (CONSTANT_P (x)
9415	|| ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
9416	;
9417
9418	/* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
9419	will be least confusing to the rest of the compiler. */
9420	else if (mode == BImode)
9421	{
9422	*ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
9423	return x;
9424	}
9425
9426	/* If X is known to be either 0 or -1, those are the true and
9427	false values when testing X. */
9428	else if (x == constm1_rtx || x == const0_rtx
9429	|| (is_a <scalar_int_mode> (m: mode, result: &int_mode)
9430	&& (num_sign_bit_copies (x, int_mode)
9431	== GET_MODE_PRECISION (mode: int_mode))))
9432	{
9433	*ptrue = constm1_rtx, *pfalse = const0_rtx;
9434	return x;
9435	}
9436
9437	/* Likewise for 0 or a single bit. */
9438	else if (HWI_COMPUTABLE_MODE_P (mode)
9439	&& pow2p_hwi (x: nz = nonzero_bits (x, mode)))
9440	{
9441	*ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
9442	return x;
9443	}
9444
9445	/* Otherwise fail; show no condition with true and false values the same. */
9446	*ptrue = *pfalse = x;
9447	return 0;
9448	}
9449
9450	/* Return the value of expression X given the fact that condition COND
9451	is known to be true when applied to REG as its first operand and VAL
9452	as its second. X is known to not be shared and so can be modified in
9453	place.
9454
9455	We only handle the simplest cases, and specifically those cases that
9456	arise with IF_THEN_ELSE expressions. */
9457
9458	static rtx
9459	known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
9460	{
9461	enum rtx_code code = GET_CODE (x);
9462	const char *fmt;
9463	int i, j;
9464
9465	if (side_effects_p (x))
9466	return x;
9467
9468	/* If either operand of the condition is a floating point value,
9469	then we have to avoid collapsing an EQ comparison. */
9470	if (cond == EQ
9471	&& rtx_equal_p (x, reg)
9472	&& ! FLOAT_MODE_P (GET_MODE (x))
9473	&& ! FLOAT_MODE_P (GET_MODE (val)))
9474	return val;
9475
9476	if (cond == UNEQ && rtx_equal_p (x, reg))
9477	return val;
9478
9479	/* If X is (abs REG) and we know something about REG's relationship
9480	with zero, we may be able to simplify this. */
9481
9482	if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
9483	switch (cond)
9484	{
9485	case GE: case GT: case EQ:
9486	return XEXP (x, 0);
9487	case LT: case LE:
9488	return simplify_gen_unary (code: NEG, GET_MODE (XEXP (x, 0)),
9489	XEXP (x, 0),
9490	GET_MODE (XEXP (x, 0)));
9491	default:
9492	break;
9493	}
9494
9495	/* The only other cases we handle are MIN, MAX, and comparisons if the
9496	operands are the same as REG and VAL. */
9497
9498	else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
9499	{
9500	if (rtx_equal_p (XEXP (x, 0), val))
9501	{
9502	std::swap (a&: val, b&: reg);
9503	cond = swap_condition (cond);
9504	}
9505
9506	if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
9507	{
9508	if (COMPARISON_P (x))
9509	{
9510	if (comparison_dominates_p (cond, code))
9511	return VECTOR_MODE_P (GET_MODE (x)) ? x : const_true_rtx;
9512
9513	code = reversed_comparison_code (x, NULL);
9514	if (code != UNKNOWN
9515	&& comparison_dominates_p (cond, code))
9516	return CONST0_RTX (GET_MODE (x));
9517	else
9518	return x;
9519	}
9520	else if (code == SMAX || code == SMIN
9521	|| code == UMIN || code == UMAX)
9522	{
9523	int unsignedp = (code == UMIN || code == UMAX);
9524
9525	/* Do not reverse the condition when it is NE or EQ.
9526	This is because we cannot conclude anything about
9527	the value of 'SMAX (x, y)' when x is not equal to y,
9528	but we can when x equals y. */
9529	if ((code == SMAX || code == UMAX)
9530	&& ! (cond == EQ || cond == NE))
9531	cond = reverse_condition (cond);
9532
9533	switch (cond)
9534	{
9535	case GE: case GT:
9536	return unsignedp ? x : XEXP (x, 1);
9537	case LE: case LT:
9538	return unsignedp ? x : XEXP (x, 0);
9539	case GEU: case GTU:
9540	return unsignedp ? XEXP (x, 1) : x;
9541	case LEU: case LTU:
9542	return unsignedp ? XEXP (x, 0) : x;
9543	default:
9544	break;
9545	}
9546	}
9547	}
9548	}
9549	else if (code == SUBREG)
9550	{
9551	machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
9552	rtx new_rtx, r = known_cond (SUBREG_REG (x), cond, reg, val);
9553
9554	if (SUBREG_REG (x) != r)
9555	{
9556	/* We must simplify subreg here, before we lose track of the
9557	original inner_mode. */
9558	new_rtx = simplify_subreg (GET_MODE (x), op: r,
9559	innermode: inner_mode, SUBREG_BYTE (x));
9560	if (new_rtx)
9561	return new_rtx;
9562	else
9563	SUBST (SUBREG_REG (x), r);
9564	}
9565
9566	return x;
9567	}
9568	/* We don't have to handle SIGN_EXTEND here, because even in the
9569	case of replacing something with a modeless CONST_INT, a
9570	CONST_INT is already (supposed to be) a valid sign extension for
9571	its narrower mode, which implies it's already properly
9572	sign-extended for the wider mode. Now, for ZERO_EXTEND, the
9573	story is different. */
9574	else if (code == ZERO_EXTEND)
9575	{
9576	machine_mode inner_mode = GET_MODE (XEXP (x, 0));
9577	rtx new_rtx, r = known_cond (XEXP (x, 0), cond, reg, val);
9578
9579	if (XEXP (x, 0) != r)
9580	{
9581	/* We must simplify the zero_extend here, before we lose
9582	track of the original inner_mode. */
9583	new_rtx = simplify_unary_operation (code: ZERO_EXTEND, GET_MODE (x),
9584	op: r, op_mode: inner_mode);
9585	if (new_rtx)
9586	return new_rtx;
9587	else
9588	SUBST (XEXP (x, 0), r);
9589	}
9590
9591	return x;
9592	}
9593
9594	fmt = GET_RTX_FORMAT (code);
9595	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9596	{
9597	if (fmt[i] == 'e')
9598	SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
9599	else if (fmt[i] == 'E')
9600	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9601	SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
9602	cond, reg, val));
9603	}
9604
9605	return x;
9606	}
9607
9608	/* See if X and Y are equal for the purposes of seeing if we can rewrite an
9609	assignment as a field assignment. */
9610
9611	static bool
9612	rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
9613	{
9614	if (widen_x && GET_MODE (x) != GET_MODE (y))
9615	{
9616	if (paradoxical_subreg_p (GET_MODE (x), GET_MODE (y)))
9617	return false;
9618	if (BYTES_BIG_ENDIAN != WORDS_BIG_ENDIAN)
9619	return false;
9620	x = adjust_address_nv (x, GET_MODE (y),
9621	byte_lowpart_offset (GET_MODE (y),
9622	GET_MODE (x)));
9623	}
9624
9625	if (x == y || rtx_equal_p (x, y))
9626	return true;
9627
9628	if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
9629	return false;
9630
9631	/* Check for a paradoxical SUBREG of a MEM compared with the MEM.
9632	Note that all SUBREGs of MEM are paradoxical; otherwise they
9633	would have been rewritten. */
9634	if (MEM_P (x) && GET_CODE (y) == SUBREG
9635	&& MEM_P (SUBREG_REG (y))
9636	&& rtx_equal_p (SUBREG_REG (y),
9637	gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
9638	return true;
9639
9640	if (MEM_P (y) && GET_CODE (x) == SUBREG
9641	&& MEM_P (SUBREG_REG (x))
9642	&& rtx_equal_p (SUBREG_REG (x),
9643	gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
9644	return true;
9645
9646	/* We used to see if get_last_value of X and Y were the same but that's
9647	not correct. In one direction, we'll cause the assignment to have
9648	the wrong destination and in the case, we'll import a register into this
9649	insn that might have already have been dead. So fail if none of the
9650	above cases are true. */
9651	return false;
9652	}
9653
9654	/* See if X, a SET operation, can be rewritten as a bit-field assignment.
9655	Return that assignment if so.
9656
9657	We only handle the most common cases. */
9658
9659	static rtx
9660	make_field_assignment (rtx x)
9661	{
9662	rtx dest = SET_DEST (x);
9663	rtx src = SET_SRC (x);
9664	rtx assign;
9665	rtx rhs, lhs;
9666	HOST_WIDE_INT c1;
9667	HOST_WIDE_INT pos;
9668	unsigned HOST_WIDE_INT len;
9669	rtx other;
9670
9671	/* All the rules in this function are specific to scalar integers. */
9672	scalar_int_mode mode;
9673	if (!is_a <scalar_int_mode> (GET_MODE (dest), result: &mode))
9674	return x;
9675
9676	/* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
9677	a clear of a one-bit field. We will have changed it to
9678	(and (rotate (const_int -2) POS) DEST), so check for that. Also check
9679	for a SUBREG. */
9680
9681	if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
9682	&& CONST_INT_P (XEXP (XEXP (src, 0), 0))
9683	&& INTVAL (XEXP (XEXP (src, 0), 0)) == -2
9684	&& rtx_equal_for_field_assignment_p (x: dest, XEXP (src, 1)))
9685	{
9686	assign = make_extraction (VOIDmode, inner: dest, pos: 0, XEXP (XEXP (src, 0), 1),
9687	len: 1, unsignedp: true, in_dest: true, in_compare: false);
9688	if (assign != 0)
9689	return gen_rtx_SET (assign, const0_rtx);
9690	return x;
9691	}
9692
9693	if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
9694	&& subreg_lowpart_p (XEXP (src, 0))
9695	&& partial_subreg_p (XEXP (src, 0))
9696	&& GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
9697	&& CONST_INT_P (XEXP (SUBREG_REG (XEXP (src, 0)), 0))
9698	&& INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
9699	&& rtx_equal_for_field_assignment_p (x: dest, XEXP (src, 1)))
9700	{
9701	assign = make_extraction (VOIDmode, inner: dest, pos: 0,
9702	XEXP (SUBREG_REG (XEXP (src, 0)), 1),
9703	len: 1, unsignedp: true, in_dest: true, in_compare: false);
9704	if (assign != 0)
9705	return gen_rtx_SET (assign, const0_rtx);
9706	return x;
9707	}
9708
9709	/* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
9710	one-bit field. */
9711	if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
9712	&& XEXP (XEXP (src, 0), 0) == const1_rtx
9713	&& rtx_equal_for_field_assignment_p (x: dest, XEXP (src, 1)))
9714	{
9715	assign = make_extraction (VOIDmode, inner: dest, pos: 0, XEXP (XEXP (src, 0), 1),
9716	len: 1, unsignedp: true, in_dest: true, in_compare: false);
9717	if (assign != 0)
9718	return gen_rtx_SET (assign, const1_rtx);
9719	return x;
9720	}
9721
9722	/* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
9723	SRC is an AND with all bits of that field set, then we can discard
9724	the AND. */
9725	if (GET_CODE (dest) == ZERO_EXTRACT
9726	&& CONST_INT_P (XEXP (dest, 1))
9727	&& GET_CODE (src) == AND
9728	&& CONST_INT_P (XEXP (src, 1)))
9729	{
9730	HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
9731	unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
9732	unsigned HOST_WIDE_INT ze_mask;
9733
9734	if (width >= HOST_BITS_PER_WIDE_INT)
9735	ze_mask = -1;
9736	else
9737	ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
9738
9739	/* Complete overlap. We can remove the source AND. */
9740	if ((and_mask & ze_mask) == ze_mask)
9741	return gen_rtx_SET (dest, XEXP (src, 0));
9742
9743	/* Partial overlap. We can reduce the source AND. */
9744	if ((and_mask & ze_mask) != and_mask)
9745	{
9746	src = gen_rtx_AND (mode, XEXP (src, 0),
9747	gen_int_mode (and_mask & ze_mask, mode));
9748	return gen_rtx_SET (dest, src);
9749	}
9750	}
9751
9752	/* The other case we handle is assignments into a constant-position
9753	field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
9754	a mask that has all one bits except for a group of zero bits and
9755	OTHER is known to have zeros where C1 has ones, this is such an
9756	assignment. Compute the position and length from C1. Shift OTHER
9757	to the appropriate position, force it to the required mode, and
9758	make the extraction. Check for the AND in both operands. */
9759
9760	/* One or more SUBREGs might obscure the constant-position field
9761	assignment. The first one we are likely to encounter is an outer
9762	narrowing SUBREG, which we can just strip for the purposes of
9763	identifying the constant-field assignment. */
9764	scalar_int_mode src_mode = mode;
9765	if (GET_CODE (src) == SUBREG
9766	&& subreg_lowpart_p (src)
9767	&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), result: &src_mode))
9768	src = SUBREG_REG (src);
9769
9770	if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
9771	return x;
9772
9773	rhs = expand_compound_operation (XEXP (src, 0));
9774	lhs = expand_compound_operation (XEXP (src, 1));
9775
9776	if (GET_CODE (rhs) == AND
9777	&& CONST_INT_P (XEXP (rhs, 1))
9778	&& rtx_equal_for_field_assignment_p (XEXP (rhs, 0), y: dest))
9779	c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9780	/* The second SUBREG that might get in the way is a paradoxical
9781	SUBREG around the first operand of the AND. We want to
9782	pretend the operand is as wide as the destination here. We
9783	do this by adjusting the MEM to wider mode for the sole
9784	purpose of the call to rtx_equal_for_field_assignment_p. Also
9785	note this trick only works for MEMs. */
9786	else if (GET_CODE (rhs) == AND
9787	&& paradoxical_subreg_p (XEXP (rhs, 0))
9788	&& MEM_P (SUBREG_REG (XEXP (rhs, 0)))
9789	&& CONST_INT_P (XEXP (rhs, 1))
9790	&& rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (rhs, 0)),
9791	y: dest, widen_x: true))
9792	c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
9793	else if (GET_CODE (lhs) == AND
9794	&& CONST_INT_P (XEXP (lhs, 1))
9795	&& rtx_equal_for_field_assignment_p (XEXP (lhs, 0), y: dest))
9796	c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9797	/* The second SUBREG that might get in the way is a paradoxical
9798	SUBREG around the first operand of the AND. We want to
9799	pretend the operand is as wide as the destination here. We
9800	do this by adjusting the MEM to wider mode for the sole
9801	purpose of the call to rtx_equal_for_field_assignment_p. Also
9802	note this trick only works for MEMs. */
9803	else if (GET_CODE (lhs) == AND
9804	&& paradoxical_subreg_p (XEXP (lhs, 0))
9805	&& MEM_P (SUBREG_REG (XEXP (lhs, 0)))
9806	&& CONST_INT_P (XEXP (lhs, 1))
9807	&& rtx_equal_for_field_assignment_p (SUBREG_REG (XEXP (lhs, 0)),
9808	y: dest, widen_x: true))
9809	c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
9810	else
9811	return x;
9812
9813	pos = get_pos_from_mask (m: (~c1) & GET_MODE_MASK (mode), plen: &len);
9814	if (pos < 0
9815	|| pos + len > GET_MODE_PRECISION (mode)
9816	|| GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT
9817	|| (c1 & nonzero_bits (other, mode)) != 0)
9818	return x;
9819
9820	assign = make_extraction (VOIDmode, inner: dest, pos, NULL_RTX, len,
9821	unsignedp: true, in_dest: true, in_compare: false);
9822	if (assign == 0)
9823	return x;
9824
9825	/* The mode to use for the source is the mode of the assignment, or of
9826	what is inside a possible STRICT_LOW_PART. */
9827	machine_mode new_mode = (GET_CODE (assign) == STRICT_LOW_PART
9828	? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
9829
9830	/* Shift OTHER right POS places and make it the source, restricting it
9831	to the proper length and mode. */
9832
9833	src = canon_reg_for_combine (x: simplify_shift_const (NULL_RTX, LSHIFTRT,
9834	src_mode, other, pos),
9835	reg: dest);
9836	src = force_to_mode (x: src, mode: new_mode,
9837	mask: len >= HOST_BITS_PER_WIDE_INT
9838	? HOST_WIDE_INT_M1U
9839	: (HOST_WIDE_INT_1U << len) - 1, just_select: false);
9840
9841	/* If SRC is masked by an AND that does not make a difference in
9842	the value being stored, strip it. */
9843	if (GET_CODE (assign) == ZERO_EXTRACT
9844	&& CONST_INT_P (XEXP (assign, 1))
9845	&& INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
9846	&& GET_CODE (src) == AND
9847	&& CONST_INT_P (XEXP (src, 1))
9848	&& UINTVAL (XEXP (src, 1))
9849	== (HOST_WIDE_INT_1U << INTVAL (XEXP (assign, 1))) - 1)
9850	src = XEXP (src, 0);
9851
9852	return gen_rtx_SET (assign, src);
9853	}
9854
9855	/* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
9856	if so. */
9857
9858	static rtx
9859	apply_distributive_law (rtx x)
9860	{
9861	enum rtx_code code = GET_CODE (x);
9862	enum rtx_code inner_code;
9863	rtx lhs, rhs, other;
9864	rtx tem;
9865
9866	/* Distributivity is not true for floating point as it can change the
9867	value. So we don't do it unless -funsafe-math-optimizations. */
9868	if (FLOAT_MODE_P (GET_MODE (x))
9869	&& ! flag_unsafe_math_optimizations)
9870	return x;
9871
9872	/* The outer operation can only be one of the following: */
9873	if (code != IOR && code != AND && code != XOR
9874	&& code != PLUS && code != MINUS)
9875	return x;
9876
9877	lhs = XEXP (x, 0);
9878	rhs = XEXP (x, 1);
9879
9880	/* If either operand is a primitive we can't do anything, so get out
9881	fast. */
9882	if (OBJECT_P (lhs) || OBJECT_P (rhs))
9883	return x;
9884
9885	lhs = expand_compound_operation (x: lhs);
9886	rhs = expand_compound_operation (x: rhs);
9887	inner_code = GET_CODE (lhs);
9888	if (inner_code != GET_CODE (rhs))
9889	return x;
9890
9891	/* See if the inner and outer operations distribute. */
9892	switch (inner_code)
9893	{
9894	case LSHIFTRT:
9895	case ASHIFTRT:
9896	case AND:
9897	case IOR:
9898	/* These all distribute except over PLUS. */
9899	if (code == PLUS || code == MINUS)
9900	return x;
9901	break;
9902
9903	case MULT:
9904	if (code != PLUS && code != MINUS)
9905	return x;
9906	break;
9907
9908	case ASHIFT:
9909	/* This is also a multiply, so it distributes over everything. */
9910	break;
9911
9912	/* This used to handle SUBREG, but this turned out to be counter-
9913	productive, since (subreg (op ...)) usually is not handled by
9914	insn patterns, and this "optimization" therefore transformed
9915	recognizable patterns into unrecognizable ones. Therefore the
9916	SUBREG case was removed from here.
9917
9918	It is possible that distributing SUBREG over arithmetic operations
9919	leads to an intermediate result than can then be optimized further,
9920	e.g. by moving the outer SUBREG to the other side of a SET as done
9921	in simplify_set. This seems to have been the original intent of
9922	handling SUBREGs here.
9923
9924	However, with current GCC this does not appear to actually happen,
9925	at least on major platforms. If some case is found where removing
9926	the SUBREG case here prevents follow-on optimizations, distributing
9927	SUBREGs ought to be re-added at that place, e.g. in simplify_set. */
9928
9929	default:
9930	return x;
9931	}
9932
9933	/* Set LHS and RHS to the inner operands (A and B in the example
9934	above) and set OTHER to the common operand (C in the example).
9935	There is only one way to do this unless the inner operation is
9936	commutative. */
9937	if (COMMUTATIVE_ARITH_P (lhs)
9938	&& rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
9939	other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
9940	else if (COMMUTATIVE_ARITH_P (lhs)
9941	&& rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
9942	other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
9943	else if (COMMUTATIVE_ARITH_P (lhs)
9944	&& rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
9945	other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
9946	else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
9947	other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
9948	else
9949	return x;
9950
9951	/* Form the new inner operation, seeing if it simplifies first. */
9952	tem = simplify_gen_binary (code, GET_MODE (x), op0: lhs, op1: rhs);
9953
9954	/* There is one exception to the general way of distributing:
9955	(a | c) ^ (b | c) -> (a ^ b) & ~c */
9956	if (code == XOR && inner_code == IOR)
9957	{
9958	inner_code = AND;
9959	other = simplify_gen_unary (code: NOT, GET_MODE (x), op: other, GET_MODE (x));
9960	}
9961
9962	/* We may be able to continuing distributing the result, so call
9963	ourselves recursively on the inner operation before forming the
9964	outer operation, which we return. */
9965	return simplify_gen_binary (code: inner_code, GET_MODE (x),
9966	op0: apply_distributive_law (x: tem), op1: other);
9967	}
9968
9969	/* See if X is of the form (* (+ A B) C), and if so convert to
9970	(+ (* A C) (* B C)) and try to simplify.
9971
9972	Most of the time, this results in no change. However, if some of
9973	the operands are the same or inverses of each other, simplifications
9974	will result.
9975
9976	For example, (and (ior A B) (not B)) can occur as the result of
9977	expanding a bit field assignment. When we apply the distributive
9978	law to this, we get (ior (and (A (not B))) (and (B (not B)))),
9979	which then simplifies to (and (A (not B))).
9980
9981	Note that no checks happen on the validity of applying the inverse
9982	distributive law. This is pointless since we can do it in the
9983	few places where this routine is called.
9984
9985	N is the index of the term that is decomposed (the arithmetic operation,
9986	i.e. (+ A B) in the first example above). !N is the index of the term that
9987	is distributed, i.e. of C in the first example above. */
9988	static rtx
9989	distribute_and_simplify_rtx (rtx x, int n)
9990	{
9991	machine_mode mode;
9992	enum rtx_code outer_code, inner_code;
9993	rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
9994
9995	/* Distributivity is not true for floating point as it can change the
9996	value. So we don't do it unless -funsafe-math-optimizations. */
9997	if (FLOAT_MODE_P (GET_MODE (x))
9998	&& ! flag_unsafe_math_optimizations)
9999	return NULL_RTX;
10000
10001	decomposed = XEXP (x, n);
10002	if (!ARITHMETIC_P (decomposed))
10003	return NULL_RTX;
10004
10005	mode = GET_MODE (x);
10006	outer_code = GET_CODE (x);
10007	distributed = XEXP (x, !n);
10008
10009	inner_code = GET_CODE (decomposed);
10010	inner_op0 = XEXP (decomposed, 0);
10011	inner_op1 = XEXP (decomposed, 1);
10012
10013	/* Special case (and (xor B C) (not A)), which is equivalent to
10014	(xor (ior A B) (ior A C)) */
10015	if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
10016	{
10017	distributed = XEXP (distributed, 0);
10018	outer_code = IOR;
10019	}
10020
10021	if (n == 0)
10022	{
10023	/* Distribute the second term. */
10024	new_op0 = simplify_gen_binary (code: outer_code, mode, op0: inner_op0, op1: distributed);
10025	new_op1 = simplify_gen_binary (code: outer_code, mode, op0: inner_op1, op1: distributed);
10026	}
10027	else
10028	{
10029	/* Distribute the first term. */
10030	new_op0 = simplify_gen_binary (code: outer_code, mode, op0: distributed, op1: inner_op0);
10031	new_op1 = simplify_gen_binary (code: outer_code, mode, op0: distributed, op1: inner_op1);
10032	}
10033
10034	tmp = apply_distributive_law (x: simplify_gen_binary (code: inner_code, mode,
10035	op0: new_op0, op1: new_op1));
10036	if (GET_CODE (tmp) != outer_code
10037	&& (set_src_cost (x: tmp, mode, speed_p: optimize_this_for_speed_p)
10038	< set_src_cost (x, mode, speed_p: optimize_this_for_speed_p)))
10039	return tmp;
10040
10041	return NULL_RTX;
10042	}
10043
10044	/* Simplify a logical `and' of VAROP with the constant CONSTOP, to be done
10045	in MODE. Return an equivalent form, if different from (and VAROP
10046	(const_int CONSTOP)). Otherwise, return NULL_RTX. */
10047
10048	static rtx
10049	simplify_and_const_int_1 (scalar_int_mode mode, rtx varop,
10050	unsigned HOST_WIDE_INT constop)
10051	{
10052	unsigned HOST_WIDE_INT nonzero;
10053	unsigned HOST_WIDE_INT orig_constop;
10054	rtx orig_varop;
10055	int i;
10056
10057	orig_varop = varop;
10058	orig_constop = constop;
10059	if (GET_CODE (varop) == CLOBBER)
10060	return NULL_RTX;
10061
10062	/* Simplify VAROP knowing that we will be only looking at some of the
10063	bits in it.
10064
10065	Note by passing in CONSTOP, we guarantee that the bits not set in
10066	CONSTOP are not significant and will never be examined. We must
10067	ensure that is the case by explicitly masking out those bits
10068	before returning. */
10069	varop = force_to_mode (x: varop, mode, mask: constop, just_select: false);
10070
10071	/* If VAROP is a CLOBBER, we will fail so return it. */
10072	if (GET_CODE (varop) == CLOBBER)
10073	return varop;
10074
10075	/* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
10076	to VAROP and return the new constant. */
10077	if (CONST_INT_P (varop))
10078	return gen_int_mode (INTVAL (varop) & constop, mode);
10079
10080	/* See what bits may be nonzero in VAROP. Unlike the general case of
10081	a call to nonzero_bits, here we don't care about bits outside
10082	MODE unless WORD_REGISTER_OPERATIONS is true. */
10083
10084	scalar_int_mode tmode = mode;
10085	if (WORD_REGISTER_OPERATIONS && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
10086	tmode = word_mode;
10087	nonzero = nonzero_bits (varop, tmode) & GET_MODE_MASK (tmode);
10088
10089	/* Turn off all bits in the constant that are known to already be zero.
10090	Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
10091	which is tested below. */
10092
10093	constop &= nonzero;
10094
10095	/* If we don't have any bits left, return zero. */
10096	if (constop == 0 && !side_effects_p (varop))
10097	return const0_rtx;
10098
10099	/* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
10100	a power of two, we can replace this with an ASHIFT. */
10101	if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), tmode) == 1
10102	&& (i = exact_log2 (x: constop)) >= 0)
10103	return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
10104
10105	/* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
10106	or XOR, then try to apply the distributive law. This may eliminate
10107	operations if either branch can be simplified because of the AND.
10108	It may also make some cases more complex, but those cases probably
10109	won't match a pattern either with or without this. */
10110
10111	if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
10112	{
10113	scalar_int_mode varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10114	return
10115	gen_lowpart
10116	(mode,
10117	apply_distributive_law
10118	(x: simplify_gen_binary (GET_CODE (varop), mode: varop_mode,
10119	op0: simplify_and_const_int (NULL_RTX, varop_mode,
10120	XEXP (varop, 0),
10121	constop),
10122	op1: simplify_and_const_int (NULL_RTX, varop_mode,
10123	XEXP (varop, 1),
10124	constop))));
10125	}
10126
10127	/* If VAROP is PLUS, and the constant is a mask of low bits, distribute
10128	the AND and see if one of the operands simplifies to zero. If so, we
10129	may eliminate it. */
10130
10131	if (GET_CODE (varop) == PLUS
10132	&& pow2p_hwi (x: constop + 1))
10133	{
10134	rtx o0, o1;
10135
10136	o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
10137	o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
10138	if (o0 == const0_rtx)
10139	return o1;
10140	if (o1 == const0_rtx)
10141	return o0;
10142	}
10143
10144	/* Make a SUBREG if necessary. If we can't make it, fail. */
10145	varop = gen_lowpart (mode, varop);
10146	if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
10147	return NULL_RTX;
10148
10149	/* If we are only masking insignificant bits, return VAROP. */
10150	if (constop == nonzero)
10151	return varop;
10152
10153	if (varop == orig_varop && constop == orig_constop)
10154	return NULL_RTX;
10155
10156	/* Otherwise, return an AND. */
10157	return simplify_gen_binary (code: AND, mode, op0: varop, op1: gen_int_mode (constop, mode));
10158	}
10159
10160
10161	/* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
10162	in MODE.
10163
10164	Return an equivalent form, if different from X. Otherwise, return X. If
10165	X is zero, we are to always construct the equivalent form. */
10166
10167	static rtx
10168	simplify_and_const_int (rtx x, scalar_int_mode mode, rtx varop,
10169	unsigned HOST_WIDE_INT constop)
10170	{
10171	rtx tem = simplify_and_const_int_1 (mode, varop, constop);
10172	if (tem)
10173	return tem;
10174
10175	if (!x)
10176	x = simplify_gen_binary (code: AND, GET_MODE (varop), op0: varop,
10177	op1: gen_int_mode (constop, mode));
10178	if (GET_MODE (x) != mode)
10179	x = gen_lowpart (mode, x);
10180	return x;
10181	}
10182
10183	/* Given a REG X of mode XMODE, compute which bits in X can be nonzero.
10184	We don't care about bits outside of those defined in MODE.
10185	We DO care about all the bits in MODE, even if XMODE is smaller than MODE.
10186
10187	For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
10188	a shift, AND, or zero_extract, we can do better. */
10189
10190	static rtx
10191	reg_nonzero_bits_for_combine (const_rtx x, scalar_int_mode xmode,
10192	scalar_int_mode mode,
10193	unsigned HOST_WIDE_INT *nonzero)
10194	{
10195	rtx tem;
10196	reg_stat_type *rsp;
10197
10198	/* If X is a register whose nonzero bits value is current, use it.
10199	Otherwise, if X is a register whose value we can find, use that
10200	value. Otherwise, use the previously-computed global nonzero bits
10201	for this register. */
10202
10203	rsp = &reg_stat[REGNO (x)];
10204	if (rsp->last_set_value != 0
10205	&& (rsp->last_set_mode == mode
10206	|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
10207	&& GET_MODE_CLASS (rsp->last_set_mode) == MODE_INT
10208	&& GET_MODE_CLASS (mode) == MODE_INT))
10209	&& ((rsp->last_set_label >= label_tick_ebb_start
10210	&& rsp->last_set_label < label_tick)
10211	|| (rsp->last_set_label == label_tick
10212	&& DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10213	|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
10214	&& REGNO (x) < reg_n_sets_max
10215	&& REG_N_SETS (REGNO (x)) == 1
10216	&& !REGNO_REG_SET_P
10217	(DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10218	REGNO (x)))))
10219	{
10220	/* Note that, even if the precision of last_set_mode is lower than that
10221	of mode, record_value_for_reg invoked nonzero_bits on the register
10222	with nonzero_bits_mode (because last_set_mode is necessarily integral
10223	and HWI_COMPUTABLE_MODE_P in this case) so bits in nonzero_bits_mode
10224	are all valid, hence in mode too since nonzero_bits_mode is defined
10225	to the largest HWI_COMPUTABLE_MODE_P mode. */
10226	*nonzero &= rsp->last_set_nonzero_bits;
10227	return NULL;
10228	}
10229
10230	tem = get_last_value (x);
10231	if (tem)
10232	{
10233	if (SHORT_IMMEDIATES_SIGN_EXTEND)
10234	tem = sign_extend_short_imm (src: tem, mode: xmode, prec: GET_MODE_PRECISION (mode));
10235
10236	return tem;
10237	}
10238
10239	if (nonzero_sign_valid && rsp->nonzero_bits)
10240	{
10241	unsigned HOST_WIDE_INT mask = rsp->nonzero_bits;
10242
10243	if (GET_MODE_PRECISION (mode: xmode) < GET_MODE_PRECISION (mode))
10244	/* We don't know anything about the upper bits. */
10245	mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (xmode);
10246
10247	*nonzero &= mask;
10248	}
10249
10250	return NULL;
10251	}
10252
10253	/* Given a reg X of mode XMODE, return the number of bits at the high-order
10254	end of X that are known to be equal to the sign bit. X will be used
10255	in mode MODE; the returned value will always be between 1 and the
10256	number of bits in MODE. */
10257
10258	static rtx
10259	reg_num_sign_bit_copies_for_combine (const_rtx x, scalar_int_mode xmode,
10260	scalar_int_mode mode,
10261	unsigned int *result)
10262	{
10263	rtx tem;
10264	reg_stat_type *rsp;
10265
10266	rsp = &reg_stat[REGNO (x)];
10267	if (rsp->last_set_value != 0
10268	&& rsp->last_set_mode == mode
10269	&& ((rsp->last_set_label >= label_tick_ebb_start
10270	&& rsp->last_set_label < label_tick)
10271	|| (rsp->last_set_label == label_tick
10272	&& DF_INSN_LUID (rsp->last_set) < subst_low_luid)
10273	|| (REGNO (x) >= FIRST_PSEUDO_REGISTER
10274	&& REGNO (x) < reg_n_sets_max
10275	&& REG_N_SETS (REGNO (x)) == 1
10276	&& !REGNO_REG_SET_P
10277	(DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
10278	REGNO (x)))))
10279	{
10280	*result = rsp->last_set_sign_bit_copies;
10281	return NULL;
10282	}
10283
10284	tem = get_last_value (x);
10285	if (tem != 0)
10286	return tem;
10287
10288	if (nonzero_sign_valid && rsp->sign_bit_copies != 0
10289	&& GET_MODE_PRECISION (mode: xmode) == GET_MODE_PRECISION (mode))
10290	*result = rsp->sign_bit_copies;
10291
10292	return NULL;
10293	}
10294
10295	/* Return the number of "extended" bits there are in X, when interpreted
10296	as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
10297	unsigned quantities, this is the number of high-order zero bits.
10298	For signed quantities, this is the number of copies of the sign bit
10299	minus 1. In both case, this function returns the number of "spare"
10300	bits. For example, if two quantities for which this function returns
10301	at least 1 are added, the addition is known not to overflow.
10302
10303	This function will always return 0 unless called during combine, which
10304	implies that it must be called from a define_split. */
10305
10306	unsigned int
10307	extended_count (const_rtx x, machine_mode mode, bool unsignedp)
10308	{
10309	if (nonzero_sign_valid == 0)
10310	return 0;
10311
10312	scalar_int_mode int_mode;
10313	return (unsignedp
10314	? (is_a <scalar_int_mode> (m: mode, result: &int_mode)
10315	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
10316	? (unsigned int) (GET_MODE_PRECISION (mode: int_mode) - 1
10317	- floor_log2 (x: nonzero_bits (x, int_mode)))
10318	: 0)
10319	: num_sign_bit_copies (x, mode) - 1);
10320	}
10321
10322	/* This function is called from `simplify_shift_const' to merge two
10323	outer operations. Specifically, we have already found that we need
10324	to perform operation *POP0 with constant *PCONST0 at the outermost
10325	position. We would now like to also perform OP1 with constant CONST1
10326	(with *POP0 being done last).
10327
10328	Return true if we can do the operation and update *POP0 and *PCONST0 with
10329	the resulting operation. *PCOMP_P is set to true if we would need to
10330	complement the innermost operand, otherwise it is unchanged.
10331
10332	MODE is the mode in which the operation will be done. No bits outside
10333	the width of this mode matter. It is assumed that the width of this mode
10334	is smaller than or equal to HOST_BITS_PER_WIDE_INT.
10335
10336	If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
10337	IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
10338	result is simply *PCONST0.
10339
10340	If the resulting operation cannot be expressed as one operation, we
10341	return false and do not change *POP0, *PCONST0, and *PCOMP_P. */
10342
10343	static bool
10344	merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0,
10345	enum rtx_code op1, HOST_WIDE_INT const1,
10346	machine_mode mode, bool *pcomp_p)
10347	{
10348	enum rtx_code op0 = *pop0;
10349	HOST_WIDE_INT const0 = *pconst0;
10350
10351	const0 &= GET_MODE_MASK (mode);
10352	const1 &= GET_MODE_MASK (mode);
10353
10354	/* If OP0 is an AND, clear unimportant bits in CONST1. */
10355	if (op0 == AND)
10356	const1 &= const0;
10357
10358	/* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
10359	if OP0 is SET. */
10360
10361	if (op1 == UNKNOWN || op0 == SET)
10362	return true;
10363
10364	else if (op0 == UNKNOWN)
10365	op0 = op1, const0 = const1;
10366
10367	else if (op0 == op1)
10368	{
10369	switch (op0)
10370	{
10371	case AND:
10372	const0 &= const1;
10373	break;
10374	case IOR:
10375	const0 |= const1;
10376	break;
10377	case XOR:
10378	const0 ^= const1;
10379	break;
10380	case PLUS:
10381	const0 += const1;
10382	break;
10383	case NEG:
10384	op0 = UNKNOWN;
10385	break;
10386	default:
10387	break;
10388	}
10389	}
10390
10391	/* Otherwise, if either is a PLUS or NEG, we can't do anything. */
10392	else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
10393	return false;
10394
10395	/* If the two constants aren't the same, we can't do anything. The
10396	remaining six cases can all be done. */
10397	else if (const0 != const1)
10398	return false;
10399
10400	else
10401	switch (op0)
10402	{
10403	case IOR:
10404	if (op1 == AND)
10405	/* (a & b) | b == b */
10406	op0 = SET;
10407	else /* op1 == XOR */
10408	/* (a ^ b) | b == a | b */
10409	{;}
10410	break;
10411
10412	case XOR:
10413	if (op1 == AND)
10414	/* (a & b) ^ b == (~a) & b */
10415	op0 = AND, *pcomp_p = true;
10416	else /* op1 == IOR */
10417	/* (a | b) ^ b == a & ~b */
10418	op0 = AND, const0 = ~const0;
10419	break;
10420
10421	case AND:
10422	if (op1 == IOR)
10423	/* (a | b) & b == b */
10424	op0 = SET;
10425	else /* op1 == XOR */
10426	/* (a ^ b) & b) == (~a) & b */
10427	*pcomp_p = true;
10428	break;
10429	default:
10430	break;
10431	}
10432
10433	/* Check for NO-OP cases. */
10434	const0 &= GET_MODE_MASK (mode);
10435	if (const0 == 0
10436	&& (op0 == IOR || op0 == XOR || op0 == PLUS))
10437	op0 = UNKNOWN;
10438	else if (const0 == 0 && op0 == AND)
10439	op0 = SET;
10440	else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
10441	&& op0 == AND)
10442	op0 = UNKNOWN;
10443
10444	*pop0 = op0;
10445
10446	/* ??? Slightly redundant with the above mask, but not entirely.
10447	Moving this above means we'd have to sign-extend the mode mask
10448	for the final test. */
10449	if (op0 != UNKNOWN && op0 != NEG)
10450	*pconst0 = trunc_int_for_mode (const0, mode);
10451
10452	return true;
10453	}
10454
10455	/* A helper to simplify_shift_const_1 to determine the mode we can perform
10456	the shift in. The original shift operation CODE is performed on OP in
10457	ORIG_MODE. Return the wider mode MODE if we can perform the operation
10458	in that mode. Return ORIG_MODE otherwise. We can also assume that the
10459	result of the shift is subject to operation OUTER_CODE with operand
10460	OUTER_CONST. */
10461
10462	static scalar_int_mode
10463	try_widen_shift_mode (enum rtx_code code, rtx op, int count,
10464	scalar_int_mode orig_mode, scalar_int_mode mode,
10465	enum rtx_code outer_code, HOST_WIDE_INT outer_const)
10466	{
10467	gcc_assert (GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (orig_mode));
10468
10469	/* In general we can't perform in wider mode for right shift and rotate. */
10470	switch (code)
10471	{
10472	case ASHIFTRT:
10473	/* We can still widen if the bits brought in from the left are identical
10474	to the sign bit of ORIG_MODE. */
10475	if (num_sign_bit_copies (op, mode)
10476	> (unsigned) (GET_MODE_PRECISION (mode)
10477	- GET_MODE_PRECISION (mode: orig_mode)))
10478	return mode;
10479	return orig_mode;
10480
10481	case LSHIFTRT:
10482	/* Similarly here but with zero bits. */
10483	if (HWI_COMPUTABLE_MODE_P (mode)
10484	&& (nonzero_bits (op, mode) & ~GET_MODE_MASK (orig_mode)) == 0)
10485	return mode;
10486
10487	/* We can also widen if the bits brought in will be masked off. This
10488	operation is performed in ORIG_MODE. */
10489	if (outer_code == AND)
10490	{
10491	int care_bits = low_bitmask_len (orig_mode, outer_const);
10492
10493	if (care_bits >= 0
10494	&& GET_MODE_PRECISION (mode: orig_mode) - care_bits >= count)
10495	return mode;
10496	}
10497	/* fall through */
10498
10499	case ROTATE:
10500	return orig_mode;
10501
10502	case ROTATERT:
10503	gcc_unreachable ();
10504
10505	default:
10506	return mode;
10507	}
10508	}
10509
10510	/* Simplify a shift of VAROP by ORIG_COUNT bits. CODE says what kind
10511	of shift. The result of the shift is RESULT_MODE. Return NULL_RTX
10512	if we cannot simplify it. Otherwise, return a simplified value.
10513
10514	The shift is normally computed in the widest mode we find in VAROP, as
10515	long as it isn't a different number of words than RESULT_MODE. Exceptions
10516	are ASHIFTRT and ROTATE, which are always done in their original mode. */
10517
10518	static rtx
10519	simplify_shift_const_1 (enum rtx_code code, machine_mode result_mode,
10520	rtx varop, int orig_count)
10521	{
10522	enum rtx_code orig_code = code;
10523	rtx orig_varop = varop;
10524	int count, log2;
10525	machine_mode mode = result_mode;
10526	machine_mode shift_mode;
10527	scalar_int_mode tmode, inner_mode, int_mode, int_varop_mode, int_result_mode;
10528	/* We form (outer_op (code varop count) (outer_const)). */
10529	enum rtx_code outer_op = UNKNOWN;
10530	HOST_WIDE_INT outer_const = 0;
10531	bool complement_p = false;
10532	rtx new_rtx, x;
10533
10534	/* Make sure and truncate the "natural" shift on the way in. We don't
10535	want to do this inside the loop as it makes it more difficult to
10536	combine shifts. */
10537	if (SHIFT_COUNT_TRUNCATED)
10538	orig_count &= GET_MODE_UNIT_BITSIZE (mode) - 1;
10539
10540	/* If we were given an invalid count, don't do anything except exactly
10541	what was requested. */
10542
10543	if (orig_count < 0 || orig_count >= (int) GET_MODE_UNIT_PRECISION (mode))
10544	return NULL_RTX;
10545
10546	count = orig_count;
10547
10548	/* Unless one of the branches of the `if' in this loop does a `continue',
10549	we will `break' the loop after the `if'. */
10550
10551	while (count != 0)
10552	{
10553	/* If we have an operand of (clobber (const_int 0)), fail. */
10554	if (GET_CODE (varop) == CLOBBER)
10555	return NULL_RTX;
10556
10557	/* Convert ROTATERT to ROTATE. */
10558	if (code == ROTATERT)
10559	{
10560	unsigned int bitsize = GET_MODE_UNIT_PRECISION (result_mode);
10561	code = ROTATE;
10562	count = bitsize - count;
10563	}
10564
10565	shift_mode = result_mode;
10566	if (shift_mode != mode)
10567	{
10568	/* We only change the modes of scalar shifts. */
10569	int_mode = as_a <scalar_int_mode> (m: mode);
10570	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
10571	shift_mode = try_widen_shift_mode (code, op: varop, count,
10572	orig_mode: int_result_mode, mode: int_mode,
10573	outer_code: outer_op, outer_const);
10574	}
10575
10576	scalar_int_mode shift_unit_mode
10577	= as_a <scalar_int_mode> (GET_MODE_INNER (shift_mode));
10578
10579	/* Handle cases where the count is greater than the size of the mode
10580	minus 1. For ASHIFT, use the size minus one as the count (this can
10581	occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
10582	take the count modulo the size. For other shifts, the result is
10583	zero.
10584
10585	Since these shifts are being produced by the compiler by combining
10586	multiple operations, each of which are defined, we know what the
10587	result is supposed to be. */
10588
10589	if (count > (GET_MODE_PRECISION (mode: shift_unit_mode) - 1))
10590	{
10591	if (code == ASHIFTRT)
10592	count = GET_MODE_PRECISION (mode: shift_unit_mode) - 1;
10593	else if (code == ROTATE || code == ROTATERT)
10594	count %= GET_MODE_PRECISION (mode: shift_unit_mode);
10595	else
10596	{
10597	/* We can't simply return zero because there may be an
10598	outer op. */
10599	varop = const0_rtx;
10600	count = 0;
10601	break;
10602	}
10603	}
10604
10605	/* If we discovered we had to complement VAROP, leave. Making a NOT
10606	here would cause an infinite loop. */
10607	if (complement_p)
10608	break;
10609
10610	if (shift_mode == shift_unit_mode)
10611	{
10612	/* An arithmetic right shift of a quantity known to be -1 or 0
10613	is a no-op. */
10614	if (code == ASHIFTRT
10615	&& (num_sign_bit_copies (varop, shift_unit_mode)
10616	== GET_MODE_PRECISION (mode: shift_unit_mode)))
10617	{
10618	count = 0;
10619	break;
10620	}
10621
10622	/* If we are doing an arithmetic right shift and discarding all but
10623	the sign bit copies, this is equivalent to doing a shift by the
10624	bitsize minus one. Convert it into that shift because it will
10625	often allow other simplifications. */
10626
10627	if (code == ASHIFTRT
10628	&& (count + num_sign_bit_copies (varop, shift_unit_mode)
10629	>= GET_MODE_PRECISION (mode: shift_unit_mode)))
10630	count = GET_MODE_PRECISION (mode: shift_unit_mode) - 1;
10631
10632	/* We simplify the tests below and elsewhere by converting
10633	ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
10634	`make_compound_operation' will convert it to an ASHIFTRT for
10635	those machines (such as VAX) that don't have an LSHIFTRT. */
10636	if (code == ASHIFTRT
10637	&& HWI_COMPUTABLE_MODE_P (mode: shift_unit_mode)
10638	&& val_signbit_known_clear_p (shift_unit_mode,
10639	nonzero_bits (varop,
10640	shift_unit_mode)))
10641	code = LSHIFTRT;
10642
10643	if (((code == LSHIFTRT
10644	&& HWI_COMPUTABLE_MODE_P (mode: shift_unit_mode)
10645	&& !(nonzero_bits (varop, shift_unit_mode) >> count))
10646	|| (code == ASHIFT
10647	&& HWI_COMPUTABLE_MODE_P (mode: shift_unit_mode)
10648	&& !((nonzero_bits (varop, shift_unit_mode) << count)
10649	& GET_MODE_MASK (shift_unit_mode))))
10650	&& !side_effects_p (varop))
10651	varop = const0_rtx;
10652	}
10653
10654	switch (GET_CODE (varop))
10655	{
10656	case SIGN_EXTEND:
10657	case ZERO_EXTEND:
10658	case SIGN_EXTRACT:
10659	case ZERO_EXTRACT:
10660	new_rtx = expand_compound_operation (x: varop);
10661	if (new_rtx != varop)
10662	{
10663	varop = new_rtx;
10664	continue;
10665	}
10666	break;
10667
10668	case MEM:
10669	/* The following rules apply only to scalars. */
10670	if (shift_mode != shift_unit_mode)
10671	break;
10672	int_mode = as_a <scalar_int_mode> (m: mode);
10673
10674	/* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
10675	minus the width of a smaller mode, we can do this with a
10676	SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
10677	if ((code == ASHIFTRT || code == LSHIFTRT)
10678	&& ! mode_dependent_address_p (XEXP (varop, 0),
10679	MEM_ADDR_SPACE (varop))
10680	&& ! MEM_VOLATILE_P (varop)
10681	&& (int_mode_for_size (size: GET_MODE_BITSIZE (mode: int_mode) - count, limit: 1)
10682	.exists (mode: &tmode)))
10683	{
10684	new_rtx = adjust_address_nv (varop, tmode,
10685	BYTES_BIG_ENDIAN ? 0
10686	: count / BITS_PER_UNIT);
10687
10688	varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
10689	: ZERO_EXTEND, int_mode, new_rtx);
10690	count = 0;
10691	continue;
10692	}
10693	break;
10694
10695	case SUBREG:
10696	/* The following rules apply only to scalars. */
10697	if (shift_mode != shift_unit_mode)
10698	break;
10699	int_mode = as_a <scalar_int_mode> (m: mode);
10700	int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10701
10702	/* If VAROP is a SUBREG, strip it as long as the inner operand has
10703	the same number of words as what we've seen so far. Then store
10704	the widest mode in MODE. */
10705	if (subreg_lowpart_p (varop)
10706	&& is_int_mode (GET_MODE (SUBREG_REG (varop)), int_mode: &inner_mode)
10707	&& GET_MODE_SIZE (mode: inner_mode) > GET_MODE_SIZE (mode: int_varop_mode)
10708	&& (CEIL (GET_MODE_SIZE (inner_mode), UNITS_PER_WORD)
10709	== CEIL (GET_MODE_SIZE (int_mode), UNITS_PER_WORD))
10710	&& GET_MODE_CLASS (int_varop_mode) == MODE_INT)
10711	{
10712	varop = SUBREG_REG (varop);
10713	if (GET_MODE_SIZE (mode: inner_mode) > GET_MODE_SIZE (mode: int_mode))
10714	mode = inner_mode;
10715	continue;
10716	}
10717	break;
10718
10719	case MULT:
10720	/* Some machines use MULT instead of ASHIFT because MULT
10721	is cheaper. But it is still better on those machines to
10722	merge two shifts into one. */
10723	if (CONST_INT_P (XEXP (varop, 1))
10724	&& (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10725	{
10726	rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10727	varop = simplify_gen_binary (code: ASHIFT, GET_MODE (varop),
10728	XEXP (varop, 0), op1: log2_rtx);
10729	continue;
10730	}
10731	break;
10732
10733	case UDIV:
10734	/* Similar, for when divides are cheaper. */
10735	if (CONST_INT_P (XEXP (varop, 1))
10736	&& (log2 = exact_log2 (UINTVAL (XEXP (varop, 1)))) >= 0)
10737	{
10738	rtx log2_rtx = gen_int_shift_amount (GET_MODE (varop), log2);
10739	varop = simplify_gen_binary (code: LSHIFTRT, GET_MODE (varop),
10740	XEXP (varop, 0), op1: log2_rtx);
10741	continue;
10742	}
10743	break;
10744
10745	case ASHIFTRT:
10746	/* If we are extracting just the sign bit of an arithmetic
10747	right shift, that shift is not needed. However, the sign
10748	bit of a wider mode may be different from what would be
10749	interpreted as the sign bit in a narrower mode, so, if
10750	the result is narrower, don't discard the shift. */
10751	if (code == LSHIFTRT
10752	&& count == (GET_MODE_UNIT_BITSIZE (result_mode) - 1)
10753	&& (GET_MODE_UNIT_BITSIZE (result_mode)
10754	>= GET_MODE_UNIT_BITSIZE (GET_MODE (varop))))
10755	{
10756	varop = XEXP (varop, 0);
10757	continue;
10758	}
10759
10760	/* fall through */
10761
10762	case LSHIFTRT:
10763	case ASHIFT:
10764	case ROTATE:
10765	/* The following rules apply only to scalars. */
10766	if (shift_mode != shift_unit_mode)
10767	break;
10768	int_mode = as_a <scalar_int_mode> (m: mode);
10769	int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10770	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
10771
10772	/* Here we have two nested shifts. The result is usually the
10773	AND of a new shift with a mask. We compute the result below. */
10774	if (CONST_INT_P (XEXP (varop, 1))
10775	&& INTVAL (XEXP (varop, 1)) >= 0
10776	&& INTVAL (XEXP (varop, 1)) < GET_MODE_PRECISION (mode: int_varop_mode)
10777	&& HWI_COMPUTABLE_MODE_P (mode: int_result_mode)
10778	&& HWI_COMPUTABLE_MODE_P (mode: int_mode))
10779	{
10780	enum rtx_code first_code = GET_CODE (varop);
10781	unsigned int first_count = INTVAL (XEXP (varop, 1));
10782	unsigned HOST_WIDE_INT mask;
10783	rtx mask_rtx;
10784
10785	/* We have one common special case. We can't do any merging if
10786	the inner code is an ASHIFTRT of a smaller mode. However, if
10787	we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
10788	with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
10789	we can convert it to
10790	(ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0) C3) C2) C1).
10791	This simplifies certain SIGN_EXTEND operations. */
10792	if (code == ASHIFT && first_code == ASHIFTRT
10793	&& count == (GET_MODE_PRECISION (mode: int_result_mode)
10794	- GET_MODE_PRECISION (mode: int_varop_mode)))
10795	{
10796	/* C3 has the low-order C1 bits zero. */
10797
10798	mask = GET_MODE_MASK (int_mode)
10799	& ~((HOST_WIDE_INT_1U << first_count) - 1);
10800
10801	varop = simplify_and_const_int (NULL_RTX, mode: int_result_mode,
10802	XEXP (varop, 0), constop: mask);
10803	varop = simplify_shift_const (NULL_RTX, ASHIFT,
10804	int_result_mode, varop, count);
10805	count = first_count;
10806	code = ASHIFTRT;
10807	continue;
10808	}
10809
10810	/* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
10811	than C1 high-order bits equal to the sign bit, we can convert
10812	this to either an ASHIFT or an ASHIFTRT depending on the
10813	two counts.
10814
10815	We cannot do this if VAROP's mode is not SHIFT_UNIT_MODE. */
10816
10817	if (code == ASHIFTRT && first_code == ASHIFT
10818	&& int_varop_mode == shift_unit_mode
10819	&& (num_sign_bit_copies (XEXP (varop, 0), shift_unit_mode)
10820	> first_count))
10821	{
10822	varop = XEXP (varop, 0);
10823	count -= first_count;
10824	if (count < 0)
10825	{
10826	count = -count;
10827	code = ASHIFT;
10828	}
10829
10830	continue;
10831	}
10832
10833	/* There are some cases we can't do. If CODE is ASHIFTRT,
10834	we can only do this if FIRST_CODE is also ASHIFTRT.
10835
10836	We can't do the case when CODE is ROTATE and FIRST_CODE is
10837	ASHIFTRT.
10838
10839	If the mode of this shift is not the mode of the outer shift,
10840	we can't do this if either shift is a right shift or ROTATE.
10841
10842	Finally, we can't do any of these if the mode is too wide
10843	unless the codes are the same.
10844
10845	Handle the case where the shift codes are the same
10846	first. */
10847
10848	if (code == first_code)
10849	{
10850	if (int_varop_mode != int_result_mode
10851	&& (code == ASHIFTRT || code == LSHIFTRT
10852	|| code == ROTATE))
10853	break;
10854
10855	count += first_count;
10856	varop = XEXP (varop, 0);
10857	continue;
10858	}
10859
10860	if (code == ASHIFTRT
10861	|| (code == ROTATE && first_code == ASHIFTRT)
10862	|| GET_MODE_PRECISION (mode: int_mode) > HOST_BITS_PER_WIDE_INT
10863	|| (int_varop_mode != int_result_mode
10864	&& (first_code == ASHIFTRT || first_code == LSHIFTRT
10865	|| first_code == ROTATE
10866	|| code == ROTATE)))
10867	break;
10868
10869	/* To compute the mask to apply after the shift, shift the
10870	nonzero bits of the inner shift the same way the
10871	outer shift will. */
10872
10873	mask_rtx = gen_int_mode (nonzero_bits (varop, int_varop_mode),
10874	int_result_mode);
10875	rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10876	mask_rtx
10877	= simplify_const_binary_operation (code, int_result_mode,
10878	mask_rtx, count_rtx);
10879
10880	/* Give up if we can't compute an outer operation to use. */
10881	if (mask_rtx == 0
10882	|| !CONST_INT_P (mask_rtx)
10883	|| ! merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: AND,
10884	INTVAL (mask_rtx),
10885	mode: int_result_mode, pcomp_p: &complement_p))
10886	break;
10887
10888	/* If the shifts are in the same direction, we add the
10889	counts. Otherwise, we subtract them. */
10890	if ((code == ASHIFTRT || code == LSHIFTRT)
10891	== (first_code == ASHIFTRT || first_code == LSHIFTRT))
10892	count += first_count;
10893	else
10894	count -= first_count;
10895
10896	/* If COUNT is positive, the new shift is usually CODE,
10897	except for the two exceptions below, in which case it is
10898	FIRST_CODE. If the count is negative, FIRST_CODE should
10899	always be used */
10900	if (count > 0
10901	&& ((first_code == ROTATE && code == ASHIFT)
10902	|| (first_code == ASHIFTRT && code == LSHIFTRT)))
10903	code = first_code;
10904	else if (count < 0)
10905	code = first_code, count = -count;
10906
10907	varop = XEXP (varop, 0);
10908	continue;
10909	}
10910
10911	/* If we have (A << B << C) for any shift, we can convert this to
10912	(A << C << B). This wins if A is a constant. Only try this if
10913	B is not a constant. */
10914
10915	else if (GET_CODE (varop) == code
10916	&& CONST_INT_P (XEXP (varop, 0))
10917	&& !CONST_INT_P (XEXP (varop, 1)))
10918	{
10919	/* For ((unsigned) (cstULL >> count)) >> cst2 we have to make
10920	sure the result will be masked. See PR70222. */
10921	if (code == LSHIFTRT
10922	&& int_mode != int_result_mode
10923	&& !merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: AND,
10924	GET_MODE_MASK (int_result_mode)
10925	>> orig_count, mode: int_result_mode,
10926	pcomp_p: &complement_p))
10927	break;
10928	/* For ((int) (cstLL >> count)) >> cst2 just give up. Queuing
10929	up outer sign extension (often left and right shift) is
10930	hardly more efficient than the original. See PR70429.
10931	Similarly punt for rotates with different modes.
10932	See PR97386. */
10933	if ((code == ASHIFTRT || code == ROTATE)
10934	&& int_mode != int_result_mode)
10935	break;
10936
10937	rtx count_rtx = gen_int_shift_amount (int_result_mode, count);
10938	rtx new_rtx = simplify_const_binary_operation (code, int_mode,
10939	XEXP (varop, 0),
10940	count_rtx);
10941	varop = gen_rtx_fmt_ee (code, int_mode, new_rtx, XEXP (varop, 1));
10942	count = 0;
10943	continue;
10944	}
10945	break;
10946
10947	case NOT:
10948	/* The following rules apply only to scalars. */
10949	if (shift_mode != shift_unit_mode)
10950	break;
10951
10952	/* Make this fit the case below. */
10953	varop = gen_rtx_XOR (mode, XEXP (varop, 0), constm1_rtx);
10954	continue;
10955
10956	case IOR:
10957	case AND:
10958	case XOR:
10959	/* The following rules apply only to scalars. */
10960	if (shift_mode != shift_unit_mode)
10961	break;
10962	int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
10963	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
10964
10965	/* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
10966	with C the size of VAROP - 1 and the shift is logical if
10967	STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
10968	we have an (le X 0) operation. If we have an arithmetic shift
10969	and STORE_FLAG_VALUE is 1 or we have a logical shift with
10970	STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
10971
10972	if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
10973	&& XEXP (XEXP (varop, 0), 1) == constm1_rtx
10974	&& (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
10975	&& (code == LSHIFTRT || code == ASHIFTRT)
10976	&& count == (GET_MODE_PRECISION (mode: int_varop_mode) - 1)
10977	&& rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
10978	{
10979	count = 0;
10980	varop = gen_rtx_LE (int_varop_mode, XEXP (varop, 1),
10981	const0_rtx);
10982
10983	if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
10984	varop = gen_rtx_NEG (int_varop_mode, varop);
10985
10986	continue;
10987	}
10988
10989	/* If we have (shift (logical)), move the logical to the outside
10990	to allow it to possibly combine with another logical and the
10991	shift to combine with another shift. This also canonicalizes to
10992	what a ZERO_EXTRACT looks like. Also, some machines have
10993	(and (shift)) insns. */
10994
10995	if (CONST_INT_P (XEXP (varop, 1))
10996	/* We can't do this if we have (ashiftrt (xor)) and the
10997	constant has its sign bit set in shift_unit_mode with
10998	shift_unit_mode wider than result_mode. */
10999	&& !(code == ASHIFTRT && GET_CODE (varop) == XOR
11000	&& int_result_mode != shift_unit_mode
11001	&& trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11002	shift_unit_mode) < 0)
11003	&& (new_rtx = simplify_const_binary_operation
11004	(code, int_result_mode,
11005	gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11006	gen_int_shift_amount (int_result_mode, count))) != 0
11007	&& CONST_INT_P (new_rtx)
11008	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, GET_CODE (varop),
11009	INTVAL (new_rtx), mode: int_result_mode,
11010	pcomp_p: &complement_p))
11011	{
11012	varop = XEXP (varop, 0);
11013	continue;
11014	}
11015
11016	/* If we can't do that, try to simplify the shift in each arm of the
11017	logical expression, make a new logical expression, and apply
11018	the inverse distributive law. This also can't be done for
11019	(ashiftrt (xor)) where we've widened the shift and the constant
11020	changes the sign bit. */
11021	if (CONST_INT_P (XEXP (varop, 1))
11022	&& !(code == ASHIFTRT && GET_CODE (varop) == XOR
11023	&& int_result_mode != shift_unit_mode
11024	&& trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
11025	shift_unit_mode) < 0))
11026	{
11027	rtx lhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11028	XEXP (varop, 0), count);
11029	rtx rhs = simplify_shift_const (NULL_RTX, code, shift_unit_mode,
11030	XEXP (varop, 1), count);
11031
11032	varop = simplify_gen_binary (GET_CODE (varop), mode: shift_unit_mode,
11033	op0: lhs, op1: rhs);
11034	varop = apply_distributive_law (x: varop);
11035
11036	count = 0;
11037	continue;
11038	}
11039	break;
11040
11041	case EQ:
11042	/* The following rules apply only to scalars. */
11043	if (shift_mode != shift_unit_mode)
11044	break;
11045	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
11046
11047	/* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
11048	says that the sign bit can be tested, FOO has mode MODE, C is
11049	GET_MODE_PRECISION (MODE) - 1, and FOO has only its low-order bit
11050	that may be nonzero. */
11051	if (code == LSHIFTRT
11052	&& XEXP (varop, 1) == const0_rtx
11053	&& GET_MODE (XEXP (varop, 0)) == int_result_mode
11054	&& count == (GET_MODE_PRECISION (mode: int_result_mode) - 1)
11055	&& HWI_COMPUTABLE_MODE_P (mode: int_result_mode)
11056	&& STORE_FLAG_VALUE == -1
11057	&& nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11058	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: XOR, const1: 1,
11059	mode: int_result_mode, pcomp_p: &complement_p))
11060	{
11061	varop = XEXP (varop, 0);
11062	count = 0;
11063	continue;
11064	}
11065	break;
11066
11067	case NEG:
11068	/* The following rules apply only to scalars. */
11069	if (shift_mode != shift_unit_mode)
11070	break;
11071	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
11072
11073	/* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
11074	than the number of bits in the mode is equivalent to A. */
11075	if (code == LSHIFTRT
11076	&& count == (GET_MODE_PRECISION (mode: int_result_mode) - 1)
11077	&& nonzero_bits (XEXP (varop, 0), int_result_mode) == 1)
11078	{
11079	varop = XEXP (varop, 0);
11080	count = 0;
11081	continue;
11082	}
11083
11084	/* NEG commutes with ASHIFT since it is multiplication. Move the
11085	NEG outside to allow shifts to combine. */
11086	if (code == ASHIFT
11087	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: NEG, const1: 0,
11088	mode: int_result_mode, pcomp_p: &complement_p))
11089	{
11090	varop = XEXP (varop, 0);
11091	continue;
11092	}
11093	break;
11094
11095	case PLUS:
11096	/* The following rules apply only to scalars. */
11097	if (shift_mode != shift_unit_mode)
11098	break;
11099	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
11100
11101	/* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
11102	is one less than the number of bits in the mode is
11103	equivalent to (xor A 1). */
11104	if (code == LSHIFTRT
11105	&& count == (GET_MODE_PRECISION (mode: int_result_mode) - 1)
11106	&& XEXP (varop, 1) == constm1_rtx
11107	&& nonzero_bits (XEXP (varop, 0), int_result_mode) == 1
11108	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: XOR, const1: 1,
11109	mode: int_result_mode, pcomp_p: &complement_p))
11110	{
11111	count = 0;
11112	varop = XEXP (varop, 0);
11113	continue;
11114	}
11115
11116	/* If we have (xshiftrt (plus FOO BAR) C), and the only bits
11117	that might be nonzero in BAR are those being shifted out and those
11118	bits are known zero in FOO, we can replace the PLUS with FOO.
11119	Similarly in the other operand order. This code occurs when
11120	we are computing the size of a variable-size array. */
11121
11122	if ((code == ASHIFTRT || code == LSHIFTRT)
11123	&& count < HOST_BITS_PER_WIDE_INT
11124	&& nonzero_bits (XEXP (varop, 1), int_result_mode) >> count == 0
11125	&& (nonzero_bits (XEXP (varop, 1), int_result_mode)
11126	& nonzero_bits (XEXP (varop, 0), int_result_mode)) == 0)
11127	{
11128	varop = XEXP (varop, 0);
11129	continue;
11130	}
11131	else if ((code == ASHIFTRT || code == LSHIFTRT)
11132	&& count < HOST_BITS_PER_WIDE_INT
11133	&& HWI_COMPUTABLE_MODE_P (mode: int_result_mode)
11134	&& (nonzero_bits (XEXP (varop, 0), int_result_mode)
11135	>> count) == 0
11136	&& (nonzero_bits (XEXP (varop, 0), int_result_mode)
11137	& nonzero_bits (XEXP (varop, 1), int_result_mode)) == 0)
11138	{
11139	varop = XEXP (varop, 1);
11140	continue;
11141	}
11142
11143	/* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
11144	if (code == ASHIFT
11145	&& CONST_INT_P (XEXP (varop, 1))
11146	&& (new_rtx = simplify_const_binary_operation
11147	(ASHIFT, int_result_mode,
11148	gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11149	gen_int_shift_amount (int_result_mode, count))) != 0
11150	&& CONST_INT_P (new_rtx)
11151	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: PLUS,
11152	INTVAL (new_rtx), mode: int_result_mode,
11153	pcomp_p: &complement_p))
11154	{
11155	varop = XEXP (varop, 0);
11156	continue;
11157	}
11158
11159	/* Check for 'PLUS signbit', which is the canonical form of 'XOR
11160	signbit', and attempt to change the PLUS to an XOR and move it to
11161	the outer operation as is done above in the AND/IOR/XOR case
11162	leg for shift(logical). See details in logical handling above
11163	for reasoning in doing so. */
11164	if (code == LSHIFTRT
11165	&& CONST_INT_P (XEXP (varop, 1))
11166	&& mode_signbit_p (int_result_mode, XEXP (varop, 1))
11167	&& (new_rtx = simplify_const_binary_operation
11168	(code, int_result_mode,
11169	gen_int_mode (INTVAL (XEXP (varop, 1)), int_result_mode),
11170	gen_int_shift_amount (int_result_mode, count))) != 0
11171	&& CONST_INT_P (new_rtx)
11172	&& merge_outer_ops (pop0: &outer_op, pconst0: &outer_const, op1: XOR,
11173	INTVAL (new_rtx), mode: int_result_mode,
11174	pcomp_p: &complement_p))
11175	{
11176	varop = XEXP (varop, 0);
11177	continue;
11178	}
11179
11180	break;
11181
11182	case MINUS:
11183	/* The following rules apply only to scalars. */
11184	if (shift_mode != shift_unit_mode)
11185	break;
11186	int_varop_mode = as_a <scalar_int_mode> (GET_MODE (varop));
11187
11188	/* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
11189	with C the size of VAROP - 1 and the shift is logical if
11190	STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
11191	we have a (gt X 0) operation. If the shift is arithmetic with
11192	STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
11193	we have a (neg (gt X 0)) operation. */
11194
11195	if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
11196	&& GET_CODE (XEXP (varop, 0)) == ASHIFTRT
11197	&& count == (GET_MODE_PRECISION (mode: int_varop_mode) - 1)
11198	&& (code == LSHIFTRT || code == ASHIFTRT)
11199	&& CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11200	&& INTVAL (XEXP (XEXP (varop, 0), 1)) == count
11201	&& rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
11202	{
11203	count = 0;
11204	varop = gen_rtx_GT (int_varop_mode, XEXP (varop, 1),
11205	const0_rtx);
11206
11207	if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
11208	varop = gen_rtx_NEG (int_varop_mode, varop);
11209
11210	continue;
11211	}
11212	break;
11213
11214	case TRUNCATE:
11215	/* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
11216	if the truncate does not affect the value. */
11217	if (code == LSHIFTRT
11218	&& GET_CODE (XEXP (varop, 0)) == LSHIFTRT
11219	&& CONST_INT_P (XEXP (XEXP (varop, 0), 1))
11220	&& (INTVAL (XEXP (XEXP (varop, 0), 1))
11221	>= (GET_MODE_UNIT_PRECISION (GET_MODE (XEXP (varop, 0)))
11222	- GET_MODE_UNIT_PRECISION (GET_MODE (varop)))))
11223	{
11224	rtx varop_inner = XEXP (varop, 0);
11225	int new_count = count + INTVAL (XEXP (varop_inner, 1));
11226	rtx new_count_rtx = gen_int_shift_amount (GET_MODE (varop_inner),
11227	new_count);
11228	varop_inner = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
11229	XEXP (varop_inner, 0),
11230	new_count_rtx);
11231	varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
11232	count = 0;
11233	continue;
11234	}
11235	break;
11236
11237	default:
11238	break;
11239	}
11240
11241	break;
11242	}
11243
11244	shift_mode = result_mode;
11245	if (shift_mode != mode)
11246	{
11247	/* We only change the modes of scalar shifts. */
11248	int_mode = as_a <scalar_int_mode> (m: mode);
11249	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
11250	shift_mode = try_widen_shift_mode (code, op: varop, count, orig_mode: int_result_mode,
11251	mode: int_mode, outer_code: outer_op, outer_const);
11252	}
11253
11254	/* We have now finished analyzing the shift. The result should be
11255	a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
11256	OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
11257	to the result of the shift. OUTER_CONST is the relevant constant,
11258	but we must turn off all bits turned off in the shift. */
11259
11260	if (outer_op == UNKNOWN
11261	&& orig_code == code && orig_count == count
11262	&& varop == orig_varop
11263	&& shift_mode == GET_MODE (varop))
11264	return NULL_RTX;
11265
11266	/* Make a SUBREG if necessary. If we can't make it, fail. */
11267	varop = gen_lowpart (shift_mode, varop);
11268	if (varop == NULL_RTX || GET_CODE (varop) == CLOBBER)
11269	return NULL_RTX;
11270
11271	/* If we have an outer operation and we just made a shift, it is
11272	possible that we could have simplified the shift were it not
11273	for the outer operation. So try to do the simplification
11274	recursively. */
11275
11276	if (outer_op != UNKNOWN)
11277	x = simplify_shift_const_1 (code, result_mode: shift_mode, varop, orig_count: count);
11278	else
11279	x = NULL_RTX;
11280
11281	if (x == NULL_RTX)
11282	x = simplify_gen_binary (code, mode: shift_mode, op0: varop,
11283	op1: gen_int_shift_amount (shift_mode, count));
11284
11285	/* If we were doing an LSHIFTRT in a wider mode than it was originally,
11286	turn off all the bits that the shift would have turned off. */
11287	if (orig_code == LSHIFTRT && result_mode != shift_mode)
11288	/* We only change the modes of scalar shifts. */
11289	x = simplify_and_const_int (NULL_RTX, mode: as_a <scalar_int_mode> (m: shift_mode),
11290	varop: x, GET_MODE_MASK (result_mode) >> orig_count);
11291
11292	/* Do the remainder of the processing in RESULT_MODE. */
11293	x = gen_lowpart_or_truncate (mode: result_mode, x);
11294
11295	/* If COMPLEMENT_P is set, we have to complement X before doing the outer
11296	operation. */
11297	if (complement_p)
11298	x = simplify_gen_unary (code: NOT, mode: result_mode, op: x, op_mode: result_mode);
11299
11300	if (outer_op != UNKNOWN)
11301	{
11302	int_result_mode = as_a <scalar_int_mode> (m: result_mode);
11303
11304	if (GET_RTX_CLASS (outer_op) != RTX_UNARY
11305	&& GET_MODE_PRECISION (mode: int_result_mode) < HOST_BITS_PER_WIDE_INT)
11306	outer_const = trunc_int_for_mode (outer_const, int_result_mode);
11307
11308	if (outer_op == AND)
11309	x = simplify_and_const_int (NULL_RTX, mode: int_result_mode, varop: x, constop: outer_const);
11310	else if (outer_op == SET)
11311	{
11312	/* This means that we have determined that the result is
11313	equivalent to a constant. This should be rare. */
11314	if (!side_effects_p (x))
11315	x = GEN_INT (outer_const);
11316	}
11317	else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
11318	x = simplify_gen_unary (code: outer_op, mode: int_result_mode, op: x, op_mode: int_result_mode);
11319	else
11320	x = simplify_gen_binary (code: outer_op, mode: int_result_mode, op0: x,
11321	GEN_INT (outer_const));
11322	}
11323
11324	return x;
11325	}
11326
11327	/* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
11328	The result of the shift is RESULT_MODE. If we cannot simplify it,
11329	return X or, if it is NULL, synthesize the expression with
11330	simplify_gen_binary. Otherwise, return a simplified value.
11331
11332	The shift is normally computed in the widest mode we find in VAROP, as
11333	long as it isn't a different number of words than RESULT_MODE. Exceptions
11334	are ASHIFTRT and ROTATE, which are always done in their original mode. */
11335
11336	static rtx
11337	simplify_shift_const (rtx x, enum rtx_code code, machine_mode result_mode,
11338	rtx varop, int count)
11339	{
11340	rtx tem = simplify_shift_const_1 (code, result_mode, varop, orig_count: count);
11341	if (tem)
11342	return tem;
11343
11344	if (!x)
11345	x = simplify_gen_binary (code, GET_MODE (varop), op0: varop,
11346	op1: gen_int_shift_amount (GET_MODE (varop), count));
11347	if (GET_MODE (x) != result_mode)
11348	x = gen_lowpart (result_mode, x);
11349	return x;
11350	}
11351
11352
11353	/* A subroutine of recog_for_combine. See there for arguments and
11354	return value. */
11355
11356	static int
11357	recog_for_combine_1 (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11358	{
11359	rtx pat = *pnewpat;
11360	rtx pat_without_clobbers;
11361	int insn_code_number;
11362	int num_clobbers_to_add = 0;
11363	int i;
11364	rtx notes = NULL_RTX;
11365	rtx old_notes, old_pat;
11366	int old_icode;
11367
11368	/* If PAT is a PARALLEL, check to see if it contains the CLOBBER
11369	we use to indicate that something didn't match. If we find such a
11370	thing, force rejection. */
11371	if (GET_CODE (pat) == PARALLEL)
11372	for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
11373	if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
11374	&& XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
11375	return -1;
11376
11377	old_pat = PATTERN (insn);
11378	old_notes = REG_NOTES (insn);
11379	PATTERN (insn) = pat;
11380	REG_NOTES (insn) = NULL_RTX;
11381
11382	insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11383	if (dump_file && (dump_flags & TDF_DETAILS))
11384	{
11385	if (insn_code_number < 0)
11386	fputs (s: "Failed to match this instruction:\n", stream: dump_file);
11387	else
11388	fputs (s: "Successfully matched this instruction:\n", stream: dump_file);
11389	print_rtl_single (dump_file, pat);
11390	}
11391
11392	/* If it isn't, there is the possibility that we previously had an insn
11393	that clobbered some register as a side effect, but the combined
11394	insn doesn't need to do that. So try once more without the clobbers
11395	unless this represents an ASM insn. */
11396
11397	if (insn_code_number < 0 && ! check_asm_operands (pat)
11398	&& GET_CODE (pat) == PARALLEL)
11399	{
11400	int pos;
11401
11402	for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
11403	if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
11404	{
11405	if (i != pos)
11406	SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
11407	pos++;
11408	}
11409
11410	SUBST_INT (XVECLEN (pat, 0), pos);
11411
11412	if (pos == 1)
11413	pat = XVECEXP (pat, 0, 0);
11414
11415	PATTERN (insn) = pat;
11416	insn_code_number = recog (pat, insn, &num_clobbers_to_add);
11417	if (dump_file && (dump_flags & TDF_DETAILS))
11418	{
11419	if (insn_code_number < 0)
11420	fputs (s: "Failed to match this instruction:\n", stream: dump_file);
11421	else
11422	fputs (s: "Successfully matched this instruction:\n", stream: dump_file);
11423	print_rtl_single (dump_file, pat);
11424	}
11425	}
11426
11427	pat_without_clobbers = pat;
11428
11429	PATTERN (insn) = old_pat;
11430	REG_NOTES (insn) = old_notes;
11431
11432	/* Recognize all noop sets, these will be killed by followup pass. */
11433	if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
11434	insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
11435
11436	/* If we had any clobbers to add, make a new pattern than contains
11437	them. Then check to make sure that all of them are dead. */
11438	if (num_clobbers_to_add)
11439	{
11440	rtx newpat = gen_rtx_PARALLEL (VOIDmode,
11441	rtvec_alloc (GET_CODE (pat) == PARALLEL
11442	? (XVECLEN (pat, 0)
11443	+ num_clobbers_to_add)
11444	: num_clobbers_to_add + 1));
11445
11446	if (GET_CODE (pat) == PARALLEL)
11447	for (i = 0; i < XVECLEN (pat, 0); i++)
11448	XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
11449	else
11450	XVECEXP (newpat, 0, 0) = pat;
11451
11452	add_clobbers (newpat, insn_code_number);
11453
11454	for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
11455	i < XVECLEN (newpat, 0); i++)
11456	{
11457	if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
11458	&& ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
11459	return -1;
11460	if (GET_CODE (XEXP (XVECEXP (newpat, 0, i), 0)) != SCRATCH)
11461	{
11462	gcc_assert (REG_P (XEXP (XVECEXP (newpat, 0, i), 0)));
11463	notes = alloc_reg_note (REG_UNUSED,
11464	XEXP (XVECEXP (newpat, 0, i), 0), notes);
11465	}
11466	}
11467	pat = newpat;
11468	}
11469
11470	if (insn_code_number >= 0
11471	&& insn_code_number != NOOP_MOVE_INSN_CODE)
11472	{
11473	old_pat = PATTERN (insn);
11474	old_notes = REG_NOTES (insn);
11475	old_icode = INSN_CODE (insn);
11476	PATTERN (insn) = pat;
11477	REG_NOTES (insn) = notes;
11478	INSN_CODE (insn) = insn_code_number;
11479
11480	/* Allow targets to reject combined insn. */
11481	if (!targetm.legitimate_combined_insn (insn))
11482	{
11483	if (dump_file && (dump_flags & TDF_DETAILS))
11484	fputs (s: "Instruction not appropriate for target.",
11485	stream: dump_file);
11486
11487	/* Callers expect recog_for_combine to strip
11488	clobbers from the pattern on failure. */
11489	pat = pat_without_clobbers;
11490	notes = NULL_RTX;
11491
11492	insn_code_number = -1;
11493	}
11494
11495	PATTERN (insn) = old_pat;
11496	REG_NOTES (insn) = old_notes;
11497	INSN_CODE (insn) = old_icode;
11498	}
11499
11500	*pnewpat = pat;
11501	*pnotes = notes;
11502
11503	return insn_code_number;
11504	}
11505
11506	/* Change every ZERO_EXTRACT and ZERO_EXTEND of a SUBREG that can be
11507	expressed as an AND and maybe an LSHIFTRT, to that formulation.
11508	Return whether anything was so changed. */
11509
11510	static bool
11511	change_zero_ext (rtx pat)
11512	{
11513	bool changed = false;
11514	rtx *src = &SET_SRC (pat);
11515
11516	subrtx_ptr_iterator::array_type array;
11517	FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11518	{
11519	rtx x = **iter;
11520	scalar_int_mode mode, inner_mode;
11521	if (!is_a <scalar_int_mode> (GET_MODE (x), result: &mode))
11522	continue;
11523	int size;
11524
11525	if (GET_CODE (x) == ZERO_EXTRACT
11526	&& CONST_INT_P (XEXP (x, 1))
11527	&& CONST_INT_P (XEXP (x, 2))
11528	&& is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), result: &inner_mode)
11529	&& GET_MODE_PRECISION (mode: inner_mode) <= GET_MODE_PRECISION (mode))
11530	{
11531	size = INTVAL (XEXP (x, 1));
11532
11533	int start = INTVAL (XEXP (x, 2));
11534	if (BITS_BIG_ENDIAN)
11535	start = GET_MODE_PRECISION (mode: inner_mode) - size - start;
11536
11537	if (start != 0)
11538	x = gen_rtx_LSHIFTRT (inner_mode, XEXP (x, 0),
11539	gen_int_shift_amount (inner_mode, start));
11540	else
11541	x = XEXP (x, 0);
11542
11543	if (mode != inner_mode)
11544	{
11545	if (REG_P (x) && HARD_REGISTER_P (x)
11546	&& !can_change_dest_mode (x, added_sets: 0, mode))
11547	continue;
11548
11549	x = gen_lowpart_SUBREG (mode, x);
11550	}
11551	}
11552	else if (GET_CODE (x) == ZERO_EXTEND
11553	&& GET_CODE (XEXP (x, 0)) == SUBREG
11554	&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
11555	&& !paradoxical_subreg_p (XEXP (x, 0))
11556	&& subreg_lowpart_p (XEXP (x, 0)))
11557	{
11558	inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11559	size = GET_MODE_PRECISION (mode: inner_mode);
11560	x = SUBREG_REG (XEXP (x, 0));
11561	if (GET_MODE (x) != mode)
11562	{
11563	if (REG_P (x) && HARD_REGISTER_P (x)
11564	&& !can_change_dest_mode (x, added_sets: 0, mode))
11565	continue;
11566
11567	x = gen_lowpart_SUBREG (mode, x);
11568	}
11569	}
11570	else if (GET_CODE (x) == ZERO_EXTEND
11571	&& REG_P (XEXP (x, 0))
11572	&& HARD_REGISTER_P (XEXP (x, 0))
11573	&& can_change_dest_mode (XEXP (x, 0), added_sets: 0, mode))
11574	{
11575	inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
11576	size = GET_MODE_PRECISION (mode: inner_mode);
11577	x = gen_rtx_REG (mode, REGNO (XEXP (x, 0)));
11578	}
11579	else
11580	continue;
11581
11582	if (!(GET_CODE (x) == LSHIFTRT
11583	&& CONST_INT_P (XEXP (x, 1))
11584	&& size + INTVAL (XEXP (x, 1)) == GET_MODE_PRECISION (mode)))
11585	{
11586	wide_int mask = wi::mask (width: size, negate_p: false, precision: GET_MODE_PRECISION (mode));
11587	x = gen_rtx_AND (mode, x, immed_wide_int_const (mask, mode));
11588	}
11589
11590	SUBST (**iter, x);
11591	changed = true;
11592	}
11593
11594	if (changed)
11595	FOR_EACH_SUBRTX_PTR (iter, array, src, NONCONST)
11596	maybe_swap_commutative_operands (x: **iter);
11597
11598	rtx *dst = &SET_DEST (pat);
11599	scalar_int_mode mode;
11600	if (GET_CODE (*dst) == ZERO_EXTRACT
11601	&& REG_P (XEXP (*dst, 0))
11602	&& is_a <scalar_int_mode> (GET_MODE (XEXP (*dst, 0)), result: &mode)
11603	&& CONST_INT_P (XEXP (*dst, 1))
11604	&& CONST_INT_P (XEXP (*dst, 2)))
11605	{
11606	rtx reg = XEXP (*dst, 0);
11607	int width = INTVAL (XEXP (*dst, 1));
11608	int offset = INTVAL (XEXP (*dst, 2));
11609	int reg_width = GET_MODE_PRECISION (mode);
11610	if (BITS_BIG_ENDIAN)
11611	offset = reg_width - width - offset;
11612
11613	rtx x, y, z, w;
11614	wide_int mask = wi::shifted_mask (start: offset, width, negate_p: true, precision: reg_width);
11615	wide_int mask2 = wi::shifted_mask (start: offset, width, negate_p: false, precision: reg_width);
11616	x = gen_rtx_AND (mode, reg, immed_wide_int_const (mask, mode));
11617	if (offset)
11618	y = gen_rtx_ASHIFT (mode, SET_SRC (pat), GEN_INT (offset));
11619	else
11620	y = SET_SRC (pat);
11621	z = gen_rtx_AND (mode, y, immed_wide_int_const (mask2, mode));
11622	w = gen_rtx_IOR (mode, x, z);
11623	SUBST (SET_DEST (pat), reg);
11624	SUBST (SET_SRC (pat), w);
11625
11626	changed = true;
11627	}
11628
11629	return changed;
11630	}
11631
11632	/* Like recog, but we receive the address of a pointer to a new pattern.
11633	We try to match the rtx that the pointer points to.
11634	If that fails, we may try to modify or replace the pattern,
11635	storing the replacement into the same pointer object.
11636
11637	Modifications include deletion or addition of CLOBBERs. If the
11638	instruction will still not match, we change ZERO_EXTEND and ZERO_EXTRACT
11639	to the equivalent AND and perhaps LSHIFTRT patterns, and try with that
11640	(and undo if that fails).
11641
11642	PNOTES is a pointer to a location where any REG_UNUSED notes added for
11643	the CLOBBERs are placed.
11644
11645	The value is the final insn code from the pattern ultimately matched,
11646	or -1. */
11647
11648	static int
11649	recog_for_combine (rtx *pnewpat, rtx_insn *insn, rtx *pnotes)
11650	{
11651	rtx pat = *pnewpat;
11652	int insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11653	if (insn_code_number >= 0 || check_asm_operands (pat))
11654	return insn_code_number;
11655
11656	void *marker = get_undo_marker ();
11657	bool changed = false;
11658
11659	if (GET_CODE (pat) == SET)
11660	{
11661	/* For an unrecognized single set of a constant, try placing it in
11662	the constant pool, if this function already uses one. */
11663	rtx src = SET_SRC (pat);
11664	if (CONSTANT_P (src)
11665	&& !CONST_INT_P (src)
11666	&& crtl->uses_const_pool)
11667	{
11668	machine_mode mode = GET_MODE (src);
11669	if (mode == VOIDmode)
11670	mode = GET_MODE (SET_DEST (pat));
11671	src = force_const_mem (mode, src);
11672	if (src)
11673	{
11674	SUBST (SET_SRC (pat), src);
11675	changed = true;
11676	}
11677	}
11678	else
11679	changed = change_zero_ext (pat);
11680	}
11681	else if (GET_CODE (pat) == PARALLEL)
11682	{
11683	int i;
11684	for (i = 0; i < XVECLEN (pat, 0); i++)
11685	{
11686	rtx set = XVECEXP (pat, 0, i);
11687	if (GET_CODE (set) == SET)
11688	changed |= change_zero_ext (pat: set);
11689	}
11690	}
11691
11692	if (changed)
11693	{
11694	insn_code_number = recog_for_combine_1 (pnewpat, insn, pnotes);
11695
11696	if (insn_code_number < 0)
11697	undo_to_marker (marker);
11698	}
11699
11700	return insn_code_number;
11701	}
11702
11703	/* Like gen_lowpart_general but for use by combine. In combine it
11704	is not possible to create any new pseudoregs. However, it is
11705	safe to create invalid memory addresses, because combine will
11706	try to recognize them and all they will do is make the combine
11707	attempt fail.
11708
11709	If for some reason this cannot do its job, an rtx
11710	(clobber (const_int 0)) is returned.
11711	An insn containing that will not be recognized. */
11712
11713	static rtx
11714	gen_lowpart_for_combine (machine_mode omode, rtx x)
11715	{
11716	machine_mode imode = GET_MODE (x);
11717	rtx result;
11718
11719	if (omode == imode)
11720	return x;
11721
11722	/* We can only support MODE being wider than a word if X is a
11723	constant integer or has a mode the same size. */
11724	if (maybe_gt (GET_MODE_SIZE (omode), UNITS_PER_WORD)
11725	&& ! (CONST_SCALAR_INT_P (x)
11726	|| known_eq (GET_MODE_SIZE (imode), GET_MODE_SIZE (omode))))
11727	goto fail;
11728
11729	/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
11730	won't know what to do. So we will strip off the SUBREG here and
11731	process normally. */
11732	if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
11733	{
11734	x = SUBREG_REG (x);
11735
11736	/* For use in case we fall down into the address adjustments
11737	further below, we need to adjust the known mode and size of
11738	x; imode and isize, since we just adjusted x. */
11739	imode = GET_MODE (x);
11740
11741	if (imode == omode)
11742	return x;
11743	}
11744
11745	result = gen_lowpart_common (omode, x);
11746
11747	if (result)
11748	return result;
11749
11750	if (MEM_P (x))
11751	{
11752	/* Refuse to work on a volatile memory ref or one with a mode-dependent
11753	address. */
11754	if (MEM_VOLATILE_P (x)
11755	|| mode_dependent_address_p (XEXP (x, 0), MEM_ADDR_SPACE (x)))
11756	goto fail;
11757
11758	/* If we want to refer to something bigger than the original memref,
11759	generate a paradoxical subreg instead. That will force a reload
11760	of the original memref X. */
11761	if (paradoxical_subreg_p (outermode: omode, innermode: imode))
11762	return gen_rtx_SUBREG (omode, x, 0);
11763
11764	poly_int64 offset = byte_lowpart_offset (omode, imode);
11765	return adjust_address_nv (x, omode, offset);
11766	}
11767
11768	/* If X is a comparison operator, rewrite it in a new mode. This
11769	probably won't match, but may allow further simplifications. */
11770	else if (COMPARISON_P (x)
11771	&& SCALAR_INT_MODE_P (imode)
11772	&& SCALAR_INT_MODE_P (omode))
11773	return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
11774
11775	/* If we couldn't simplify X any other way, just enclose it in a
11776	SUBREG. Normally, this SUBREG won't match, but some patterns may
11777	include an explicit SUBREG or we may simplify it further in combine. */
11778	else
11779	{
11780	rtx res;
11781
11782	if (imode == VOIDmode)
11783	{
11784	imode = int_mode_for_mode (omode).require ();
11785	x = gen_lowpart_common (imode, x);
11786	if (x == NULL)
11787	goto fail;
11788	}
11789	res = lowpart_subreg (outermode: omode, op: x, innermode: imode);
11790	if (res)
11791	return res;
11792	}
11793
11794	fail:
11795	return gen_rtx_CLOBBER (omode, const0_rtx);
11796	}
11797
11798	/* Try to simplify a comparison between OP0 and a constant OP1,
11799	where CODE is the comparison code that will be tested, into a
11800	(CODE OP0 const0_rtx) form.
11801
11802	The result is a possibly different comparison code to use.
11803	*POP0 and *POP1 may be updated. */
11804
11805	static enum rtx_code
11806	simplify_compare_const (enum rtx_code code, machine_mode mode,
11807	rtx *pop0, rtx *pop1)
11808	{
11809	scalar_int_mode int_mode;
11810	rtx op0 = *pop0;
11811	HOST_WIDE_INT const_op = INTVAL (*pop1);
11812
11813	/* Get the constant we are comparing against and turn off all bits
11814	not on in our mode. */
11815	if (mode != VOIDmode)
11816	const_op = trunc_int_for_mode (const_op, mode);
11817
11818	/* If we are comparing against a constant power of two and the value
11819	being compared can only have that single bit nonzero (e.g., it was
11820	`and'ed with that bit), we can replace this with a comparison
11821	with zero. */
11822	if (const_op
11823	&& (code == EQ || code == NE || code == GE || code == GEU
11824	|| code == LT || code == LTU)
11825	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
11826	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11827	&& pow2p_hwi (x: const_op & GET_MODE_MASK (int_mode))
11828	&& (nonzero_bits (op0, int_mode)
11829	== (unsigned HOST_WIDE_INT) (const_op & GET_MODE_MASK (int_mode))))
11830	{
11831	code = (code == EQ || code == GE || code == GEU ? NE : EQ);
11832	const_op = 0;
11833	}
11834
11835	/* Similarly, if we are comparing a value known to be either -1 or
11836	0 with -1, change it to the opposite comparison against zero. */
11837	if (const_op == -1
11838	&& (code == EQ || code == NE || code == GT || code == LE
11839	|| code == GEU || code == LTU)
11840	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
11841	&& num_sign_bit_copies (op0, int_mode) == GET_MODE_PRECISION (mode: int_mode))
11842	{
11843	code = (code == EQ || code == LE || code == GEU ? NE : EQ);
11844	const_op = 0;
11845	}
11846
11847	/* Do some canonicalizations based on the comparison code. We prefer
11848	comparisons against zero and then prefer equality comparisons.
11849	If we can reduce the size of a constant, we will do that too. */
11850	switch (code)
11851	{
11852	case LT:
11853	/* < C is equivalent to <= (C - 1) */
11854	if (const_op > 0)
11855	{
11856	const_op -= 1;
11857	code = LE;
11858	/* ... fall through to LE case below. */
11859	gcc_fallthrough ();
11860	}
11861	else
11862	break;
11863
11864	case LE:
11865	/* <= C is equivalent to < (C + 1); we do this for C < 0 */
11866	if (const_op < 0)
11867	{
11868	const_op += 1;
11869	code = LT;
11870	}
11871
11872	/* If we are doing a <= 0 comparison on a value known to have
11873	a zero sign bit, we can replace this with == 0. */
11874	else if (const_op == 0
11875	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
11876	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11877	&& (nonzero_bits (op0, int_mode)
11878	& (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (mode: int_mode) - 1)))
11879	== 0)
11880	code = EQ;
11881	break;
11882
11883	case GE:
11884	/* >= C is equivalent to > (C - 1). */
11885	if (const_op > 0)
11886	{
11887	const_op -= 1;
11888	code = GT;
11889	/* ... fall through to GT below. */
11890	gcc_fallthrough ();
11891	}
11892	else
11893	break;
11894
11895	case GT:
11896	/* > C is equivalent to >= (C + 1); we do this for C < 0. */
11897	if (const_op < 0)
11898	{
11899	const_op += 1;
11900	code = GE;
11901	}
11902
11903	/* If we are doing a > 0 comparison on a value known to have
11904	a zero sign bit, we can replace this with != 0. */
11905	else if (const_op == 0
11906	&& is_a <scalar_int_mode> (m: mode, result: &int_mode)
11907	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11908	&& (nonzero_bits (op0, int_mode)
11909	& (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (mode: int_mode) - 1)))
11910	== 0)
11911	code = NE;
11912	break;
11913
11914	case LTU:
11915	/* < C is equivalent to <= (C - 1). */
11916	if (const_op > 0)
11917	{
11918	const_op -= 1;
11919	code = LEU;
11920	/* ... fall through ... */
11921	gcc_fallthrough ();
11922	}
11923	/* (unsigned) < 0x80000000 is equivalent to >= 0. */
11924	else if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
11925	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11926	&& (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
11927	== HOST_WIDE_INT_1U << (GET_MODE_PRECISION (mode: int_mode) - 1)))
11928	{
11929	const_op = 0;
11930	code = GE;
11931	break;
11932	}
11933	else
11934	break;
11935
11936	case LEU:
11937	/* unsigned <= 0 is equivalent to == 0 */
11938	if (const_op == 0)
11939	code = EQ;
11940	/* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
11941	else if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
11942	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11943	&& ((unsigned HOST_WIDE_INT) const_op
11944	== ((HOST_WIDE_INT_1U
11945	<< (GET_MODE_PRECISION (mode: int_mode) - 1)) - 1)))
11946	{
11947	const_op = 0;
11948	code = GE;
11949	}
11950	break;
11951
11952	case GEU:
11953	/* >= C is equivalent to > (C - 1). */
11954	if (const_op > 1)
11955	{
11956	const_op -= 1;
11957	code = GTU;
11958	/* ... fall through ... */
11959	gcc_fallthrough ();
11960	}
11961
11962	/* (unsigned) >= 0x80000000 is equivalent to < 0. */
11963	else if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
11964	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11965	&& (((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
11966	== HOST_WIDE_INT_1U << (GET_MODE_PRECISION (mode: int_mode) - 1)))
11967	{
11968	const_op = 0;
11969	code = LT;
11970	break;
11971	}
11972	else
11973	break;
11974
11975	case GTU:
11976	/* unsigned > 0 is equivalent to != 0 */
11977	if (const_op == 0)
11978	code = NE;
11979	/* (unsigned) > 0x7fffffff is equivalent to < 0. */
11980	else if (is_a <scalar_int_mode> (m: mode, result: &int_mode)
11981	&& GET_MODE_PRECISION (mode: int_mode) - 1 < HOST_BITS_PER_WIDE_INT
11982	&& ((unsigned HOST_WIDE_INT) const_op
11983	== (HOST_WIDE_INT_1U
11984	<< (GET_MODE_PRECISION (mode: int_mode) - 1)) - 1))
11985	{
11986	const_op = 0;
11987	code = LT;
11988	}
11989	break;
11990
11991	default:
11992	break;
11993	}
11994
11995	/* Narrow non-symmetric comparison of memory and constant as e.g.
11996	x0...x7 <= 0x3fffffffffffffff into x0 <= 0x3f where x0 is the most
11997	significant byte. Likewise, transform x0...x7 >= 0x4000000000000000 into
11998	x0 >= 0x40. */
11999	if ((code == LEU || code == LTU || code == GEU || code == GTU)
12000	&& is_a <scalar_int_mode> (GET_MODE (op0), result: &int_mode)
12001	&& HWI_COMPUTABLE_MODE_P (mode: int_mode)
12002	&& MEM_P (op0)
12003	&& !MEM_VOLATILE_P (op0)
12004	/* The optimization makes only sense for constants which are big enough
12005	so that we have a chance to chop off something at all. */
12006	&& ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode)) > 0xff
12007	/* Ensure that we do not overflow during normalization. */
12008	&& (code != GTU
12009	|| ((unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode))
12010	< HOST_WIDE_INT_M1U)
12011	&& trunc_int_for_mode (const_op, int_mode) == const_op)
12012	{
12013	unsigned HOST_WIDE_INT n
12014	= (unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode);
12015	enum rtx_code adjusted_code;
12016
12017	/* Normalize code to either LEU or GEU. */
12018	if (code == LTU)
12019	{
12020	--n;
12021	adjusted_code = LEU;
12022	}
12023	else if (code == GTU)
12024	{
12025	++n;
12026	adjusted_code = GEU;
12027	}
12028	else
12029	adjusted_code = code;
12030
12031	scalar_int_mode narrow_mode_iter;
12032	FOR_EACH_MODE_UNTIL (narrow_mode_iter, int_mode)
12033	{
12034	unsigned nbits = GET_MODE_PRECISION (mode: int_mode)
12035	- GET_MODE_PRECISION (mode: narrow_mode_iter);
12036	unsigned HOST_WIDE_INT mask = (HOST_WIDE_INT_1U << nbits) - 1;
12037	unsigned HOST_WIDE_INT lower_bits = n & mask;
12038	if ((adjusted_code == LEU && lower_bits == mask)
12039	|| (adjusted_code == GEU && lower_bits == 0))
12040	{
12041	n >>= nbits;
12042	break;
12043	}
12044	}
12045
12046	if (narrow_mode_iter < int_mode)
12047	{
12048	if (dump_file && (dump_flags & TDF_DETAILS))
12049	{
12050	fprintf (
12051	stream: dump_file, format: "narrow comparison from mode %s to %s: (MEM %s "
12052	HOST_WIDE_INT_PRINT_HEX ") to (MEM %s "
12053	HOST_WIDE_INT_PRINT_HEX ").\n", GET_MODE_NAME (int_mode),
12054	GET_MODE_NAME (narrow_mode_iter), GET_RTX_NAME (code),
12055	(unsigned HOST_WIDE_INT) const_op & GET_MODE_MASK (int_mode),
12056	GET_RTX_NAME (adjusted_code), n);
12057	}
12058	poly_int64 offset = (BYTES_BIG_ENDIAN
12059	? 0
12060	: (GET_MODE_SIZE (mode: int_mode)
12061	- GET_MODE_SIZE (mode: narrow_mode_iter)));
12062	*pop0 = adjust_address_nv (op0, narrow_mode_iter, offset);
12063	*pop1 = gen_int_mode (n, narrow_mode_iter);
12064	return adjusted_code;
12065	}
12066	}
12067
12068	*pop1 = GEN_INT (const_op);
12069	return code;
12070	}
12071
12072	/* Simplify a comparison between *POP0 and *POP1 where CODE is the
12073	comparison code that will be tested.
12074
12075	The result is a possibly different comparison code to use. *POP0 and
12076	*POP1 may be updated.
12077
12078	It is possible that we might detect that a comparison is either always
12079	true or always false. However, we do not perform general constant
12080	folding in combine, so this knowledge isn't useful. Such tautologies
12081	should have been detected earlier. Hence we ignore all such cases. */
12082
12083	static enum rtx_code
12084	simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
12085	{
12086	rtx op0 = *pop0;
12087	rtx op1 = *pop1;
12088	rtx tem, tem1;
12089	int i;
12090	scalar_int_mode mode, inner_mode, tmode;
12091	opt_scalar_int_mode tmode_iter;
12092
12093	/* Try a few ways of applying the same transformation to both operands. */
12094	while (1)
12095	{
12096	/* The test below this one won't handle SIGN_EXTENDs on these machines,
12097	so check specially. */
12098	if (!WORD_REGISTER_OPERATIONS
12099	&& code != GTU && code != GEU && code != LTU && code != LEU
12100	&& GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
12101	&& GET_CODE (XEXP (op0, 0)) == ASHIFT
12102	&& GET_CODE (XEXP (op1, 0)) == ASHIFT
12103	&& GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
12104	&& GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
12105	&& is_a <scalar_int_mode> (GET_MODE (op0), result: &mode)
12106	&& (is_a <scalar_int_mode>
12107	(GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), result: &inner_mode))
12108	&& inner_mode == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0)))
12109	&& CONST_INT_P (XEXP (op0, 1))
12110	&& XEXP (op0, 1) == XEXP (op1, 1)
12111	&& XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12112	&& XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
12113	&& (INTVAL (XEXP (op0, 1))
12114	== (GET_MODE_PRECISION (mode)
12115	- GET_MODE_PRECISION (mode: inner_mode))))
12116	{
12117	op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
12118	op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
12119	}
12120
12121	/* If both operands are the same constant shift, see if we can ignore the
12122	shift. We can if the shift is a rotate or if the bits shifted out of
12123	this shift are known to be zero for both inputs and if the type of
12124	comparison is compatible with the shift. */
12125	if (GET_CODE (op0) == GET_CODE (op1)
12126	&& HWI_COMPUTABLE_MODE_P (GET_MODE (op0))
12127	&& ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
12128	|| ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
12129	&& (code != GT && code != LT && code != GE && code != LE))
12130	|| (GET_CODE (op0) == ASHIFTRT
12131	&& (code != GTU && code != LTU
12132	&& code != GEU && code != LEU)))
12133	&& CONST_INT_P (XEXP (op0, 1))
12134	&& INTVAL (XEXP (op0, 1)) >= 0
12135	&& INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12136	&& XEXP (op0, 1) == XEXP (op1, 1))
12137	{
12138	machine_mode mode = GET_MODE (op0);
12139	unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12140	int shift_count = INTVAL (XEXP (op0, 1));
12141
12142	if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
12143	mask &= (mask >> shift_count) << shift_count;
12144	else if (GET_CODE (op0) == ASHIFT)
12145	mask = (mask & (mask << shift_count)) >> shift_count;
12146
12147	if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
12148	&& (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
12149	op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
12150	else
12151	break;
12152	}
12153
12154	/* If both operands are AND's of a paradoxical SUBREG by constant, the
12155	SUBREGs are of the same mode, and, in both cases, the AND would
12156	be redundant if the comparison was done in the narrower mode,
12157	do the comparison in the narrower mode (e.g., we are AND'ing with 1
12158	and the operand's possibly nonzero bits are 0xffffff01; in that case
12159	if we only care about QImode, we don't need the AND). This case
12160	occurs if the output mode of an scc insn is not SImode and
12161	STORE_FLAG_VALUE == 1 (e.g., the 386).
12162
12163	Similarly, check for a case where the AND's are ZERO_EXTEND
12164	operations from some narrower mode even though a SUBREG is not
12165	present. */
12166
12167	else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
12168	&& CONST_INT_P (XEXP (op0, 1))
12169	&& CONST_INT_P (XEXP (op1, 1)))
12170	{
12171	rtx inner_op0 = XEXP (op0, 0);
12172	rtx inner_op1 = XEXP (op1, 0);
12173	HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
12174	HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
12175	bool changed = false;
12176
12177	if (paradoxical_subreg_p (x: inner_op0)
12178	&& GET_CODE (inner_op1) == SUBREG
12179	&& HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
12180	&& (GET_MODE (SUBREG_REG (inner_op0))
12181	== GET_MODE (SUBREG_REG (inner_op1)))
12182	&& ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
12183	GET_MODE (SUBREG_REG (inner_op0)))) == 0
12184	&& ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
12185	GET_MODE (SUBREG_REG (inner_op1)))) == 0)
12186	{
12187	op0 = SUBREG_REG (inner_op0);
12188	op1 = SUBREG_REG (inner_op1);
12189
12190	/* The resulting comparison is always unsigned since we masked
12191	off the original sign bit. */
12192	code = unsigned_condition (code);
12193
12194	changed = true;
12195	}
12196
12197	else if (c0 == c1)
12198	FOR_EACH_MODE_UNTIL (tmode,
12199	as_a <scalar_int_mode> (GET_MODE (op0)))
12200	if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
12201	{
12202	op0 = gen_lowpart_or_truncate (mode: tmode, x: inner_op0);
12203	op1 = gen_lowpart_or_truncate (mode: tmode, x: inner_op1);
12204	code = unsigned_condition (code);
12205	changed = true;
12206	break;
12207	}
12208
12209	if (! changed)
12210	break;
12211	}
12212
12213	/* If both operands are NOT, we can strip off the outer operation
12214	and adjust the comparison code for swapped operands; similarly for
12215	NEG, except that this must be an equality comparison. */
12216	else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
12217	|| (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
12218	&& (code == EQ || code == NE)))
12219	op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
12220
12221	else
12222	break;
12223	}
12224
12225	/* If the first operand is a constant, swap the operands and adjust the
12226	comparison code appropriately, but don't do this if the second operand
12227	is already a constant integer. */
12228	if (swap_commutative_operands_p (op0, op1))
12229	{
12230	std::swap (a&: op0, b&: op1);
12231	code = swap_condition (code);
12232	}
12233
12234	/* We now enter a loop during which we will try to simplify the comparison.
12235	For the most part, we only are concerned with comparisons with zero,
12236	but some things may really be comparisons with zero but not start
12237	out looking that way. */
12238
12239	while (CONST_INT_P (op1))
12240	{
12241	machine_mode raw_mode = GET_MODE (op0);
12242	scalar_int_mode int_mode;
12243	int equality_comparison_p;
12244	int sign_bit_comparison_p;
12245	int unsigned_comparison_p;
12246	HOST_WIDE_INT const_op;
12247
12248	/* We only want to handle integral modes. This catches VOIDmode,
12249	CCmode, and the floating-point modes. An exception is that we
12250	can handle VOIDmode if OP0 is a COMPARE or a comparison
12251	operation. */
12252
12253	if (GET_MODE_CLASS (raw_mode) != MODE_INT
12254	&& ! (raw_mode == VOIDmode
12255	&& (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
12256	break;
12257
12258	/* Try to simplify the compare to constant, possibly changing the
12259	comparison op, and/or changing op1 to zero. */
12260	code = simplify_compare_const (code, mode: raw_mode, pop0: &op0, pop1: &op1);
12261	const_op = INTVAL (op1);
12262
12263	/* Compute some predicates to simplify code below. */
12264
12265	equality_comparison_p = (code == EQ || code == NE);
12266	sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
12267	unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
12268	|| code == GEU);
12269
12270	/* If this is a sign bit comparison and we can do arithmetic in
12271	MODE, say that we will only be needing the sign bit of OP0. */
12272	if (sign_bit_comparison_p
12273	&& is_a <scalar_int_mode> (m: raw_mode, result: &int_mode)
12274	&& HWI_COMPUTABLE_MODE_P (mode: int_mode))
12275	op0 = force_to_mode (x: op0, mode: int_mode,
12276	HOST_WIDE_INT_1U
12277	<< (GET_MODE_PRECISION (mode: int_mode) - 1), just_select: false);
12278
12279	if (COMPARISON_P (op0))
12280	{
12281	/* We can't do anything if OP0 is a condition code value, rather
12282	than an actual data value. */
12283	if (const_op != 0
12284	|| GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
12285	break;
12286
12287	/* Get the two operands being compared. */
12288	if (GET_CODE (XEXP (op0, 0)) == COMPARE)
12289	tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
12290	else
12291	tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
12292
12293	/* Check for the cases where we simply want the result of the
12294	earlier test or the opposite of that result. */
12295	if (code == NE || code == EQ
12296	|| (val_signbit_known_set_p (raw_mode, STORE_FLAG_VALUE)
12297	&& (code == LT || code == GE)))
12298	{
12299	enum rtx_code new_code;
12300	if (code == LT || code == NE)
12301	new_code = GET_CODE (op0);
12302	else
12303	new_code = reversed_comparison_code (op0, NULL);
12304
12305	if (new_code != UNKNOWN)
12306	{
12307	code = new_code;
12308	op0 = tem;
12309	op1 = tem1;
12310	continue;
12311	}
12312	}
12313	break;
12314	}
12315
12316	if (raw_mode == VOIDmode)
12317	break;
12318	scalar_int_mode mode = as_a <scalar_int_mode> (m: raw_mode);
12319
12320	/* Now try cases based on the opcode of OP0. If none of the cases
12321	does a "continue", we exit this loop immediately after the
12322	switch. */
12323
12324	unsigned int mode_width = GET_MODE_PRECISION (mode);
12325	unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
12326	switch (GET_CODE (op0))
12327	{
12328	case ZERO_EXTRACT:
12329	/* If we are extracting a single bit from a variable position in
12330	a constant that has only a single bit set and are comparing it
12331	with zero, we can convert this into an equality comparison
12332	between the position and the location of the single bit. */
12333	/* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
12334	have already reduced the shift count modulo the word size. */
12335	if (!SHIFT_COUNT_TRUNCATED
12336	&& CONST_INT_P (XEXP (op0, 0))
12337	&& XEXP (op0, 1) == const1_rtx
12338	&& equality_comparison_p && const_op == 0
12339	&& (i = exact_log2 (UINTVAL (XEXP (op0, 0)))) >= 0)
12340	{
12341	if (BITS_BIG_ENDIAN)
12342	i = BITS_PER_WORD - 1 - i;
12343
12344	op0 = XEXP (op0, 2);
12345	op1 = GEN_INT (i);
12346	const_op = i;
12347
12348	/* Result is nonzero iff shift count is equal to I. */
12349	code = reverse_condition (code);
12350	continue;
12351	}
12352
12353	/* fall through */
12354
12355	case SIGN_EXTRACT:
12356	tem = expand_compound_operation (x: op0);
12357	if (tem != op0)
12358	{
12359	op0 = tem;
12360	continue;
12361	}
12362	break;
12363
12364	case NOT:
12365	/* If testing for equality, we can take the NOT of the constant. */
12366	if (equality_comparison_p
12367	&& (tem = simplify_unary_operation (code: NOT, mode, op: op1, op_mode: mode)) != 0)
12368	{
12369	op0 = XEXP (op0, 0);
12370	op1 = tem;
12371	continue;
12372	}
12373
12374	/* If just looking at the sign bit, reverse the sense of the
12375	comparison. */
12376	if (sign_bit_comparison_p)
12377	{
12378	op0 = XEXP (op0, 0);
12379	code = (code == GE ? LT : GE);
12380	continue;
12381	}
12382	break;
12383
12384	case NEG:
12385	/* If testing for equality, we can take the NEG of the constant. */
12386	if (equality_comparison_p
12387	&& (tem = simplify_unary_operation (code: NEG, mode, op: op1, op_mode: mode)) != 0)
12388	{
12389	op0 = XEXP (op0, 0);
12390	op1 = tem;
12391	continue;
12392	}
12393
12394	/* The remaining cases only apply to comparisons with zero. */
12395	if (const_op != 0)
12396	break;
12397
12398	/* When X is ABS or is known positive,
12399	(neg X) is < 0 if and only if X != 0. */
12400
12401	if (sign_bit_comparison_p
12402	&& (GET_CODE (XEXP (op0, 0)) == ABS
12403	|| (mode_width <= HOST_BITS_PER_WIDE_INT
12404	&& (nonzero_bits (XEXP (op0, 0), mode)
12405	& (HOST_WIDE_INT_1U << (mode_width - 1)))
12406	== 0)))
12407	{
12408	op0 = XEXP (op0, 0);
12409	code = (code == LT ? NE : EQ);
12410	continue;
12411	}
12412
12413	/* If we have NEG of something whose two high-order bits are the
12414	same, we know that "(-a) < 0" is equivalent to "a > 0". */
12415	if (num_sign_bit_copies (op0, mode) >= 2)
12416	{
12417	op0 = XEXP (op0, 0);
12418	code = swap_condition (code);
12419	continue;
12420	}
12421	break;
12422
12423	case ROTATE:
12424	/* If we are testing equality and our count is a constant, we
12425	can perform the inverse operation on our RHS. */
12426	if (equality_comparison_p && CONST_INT_P (XEXP (op0, 1))
12427	&& (tem = simplify_binary_operation (code: ROTATERT, mode,
12428	op0: op1, XEXP (op0, 1))) != 0)
12429	{
12430	op0 = XEXP (op0, 0);
12431	op1 = tem;
12432	continue;
12433	}
12434
12435	/* If we are doing a < 0 or >= 0 comparison, it means we are testing
12436	a particular bit. Convert it to an AND of a constant of that
12437	bit. This will be converted into a ZERO_EXTRACT. */
12438	if (const_op == 0 && sign_bit_comparison_p
12439	&& CONST_INT_P (XEXP (op0, 1))
12440	&& mode_width <= HOST_BITS_PER_WIDE_INT
12441	&& UINTVAL (XEXP (op0, 1)) < mode_width)
12442	{
12443	op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12444	constop: (HOST_WIDE_INT_1U
12445	<< (mode_width - 1
12446	- INTVAL (XEXP (op0, 1)))));
12447	code = (code == LT ? NE : EQ);
12448	continue;
12449	}
12450
12451	/* Fall through. */
12452
12453	case ABS:
12454	/* ABS is ignorable inside an equality comparison with zero. */
12455	if (const_op == 0 && equality_comparison_p)
12456	{
12457	op0 = XEXP (op0, 0);
12458	continue;
12459	}
12460	break;
12461
12462	case SIGN_EXTEND:
12463	/* Can simplify (compare (zero/sign_extend FOO) CONST) to
12464	(compare FOO CONST) if CONST fits in FOO's mode and we
12465	are either testing inequality or have an unsigned
12466	comparison with ZERO_EXTEND or a signed comparison with
12467	SIGN_EXTEND. But don't do it if we don't have a compare
12468	insn of the given mode, since we'd have to revert it
12469	later on, and then we wouldn't know whether to sign- or
12470	zero-extend. */
12471	if (is_int_mode (GET_MODE (XEXP (op0, 0)), int_mode: &mode)
12472	&& ! unsigned_comparison_p
12473	&& HWI_COMPUTABLE_MODE_P (mode)
12474	&& trunc_int_for_mode (const_op, mode) == const_op
12475	&& have_insn_for (COMPARE, mode))
12476	{
12477	op0 = XEXP (op0, 0);
12478	continue;
12479	}
12480	break;
12481
12482	case SUBREG:
12483	/* Check for the case where we are comparing A - C1 with C2, that is
12484
12485	(subreg:MODE (plus (A) (-C1))) op (C2)
12486
12487	with C1 a constant, and try to lift the SUBREG, i.e. to do the
12488	comparison in the wider mode. One of the following two conditions
12489	must be true in order for this to be valid:
12490
12491	1. The mode extension results in the same bit pattern being added
12492	on both sides and the comparison is equality or unsigned. As
12493	C2 has been truncated to fit in MODE, the pattern can only be
12494	all 0s or all 1s.
12495
12496	2. The mode extension results in the sign bit being copied on
12497	each side.
12498
12499	The difficulty here is that we have predicates for A but not for
12500	(A - C1) so we need to check that C1 is within proper bounds so
12501	as to perturbate A as little as possible. */
12502
12503	if (mode_width <= HOST_BITS_PER_WIDE_INT
12504	&& subreg_lowpart_p (op0)
12505	&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op0)),
12506	result: &inner_mode)
12507	&& GET_MODE_PRECISION (mode: inner_mode) > mode_width
12508	&& GET_CODE (SUBREG_REG (op0)) == PLUS
12509	&& CONST_INT_P (XEXP (SUBREG_REG (op0), 1)))
12510	{
12511	rtx a = XEXP (SUBREG_REG (op0), 0);
12512	HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
12513
12514	if ((c1 > 0
12515	&& (unsigned HOST_WIDE_INT) c1
12516	< HOST_WIDE_INT_1U << (mode_width - 1)
12517	&& (equality_comparison_p || unsigned_comparison_p)
12518	/* (A - C1) zero-extends if it is positive and sign-extends
12519	if it is negative, C2 both zero- and sign-extends. */
12520	&& (((nonzero_bits (a, inner_mode)
12521	& ~GET_MODE_MASK (mode)) == 0
12522	&& const_op >= 0)
12523	/* (A - C1) sign-extends if it is positive and 1-extends
12524	if it is negative, C2 both sign- and 1-extends. */
12525	|| (num_sign_bit_copies (a, inner_mode)
12526	> (unsigned int) (GET_MODE_PRECISION (mode: inner_mode)
12527	- mode_width)
12528	&& const_op < 0)))
12529	|| ((unsigned HOST_WIDE_INT) c1
12530	< HOST_WIDE_INT_1U << (mode_width - 2)
12531	/* (A - C1) always sign-extends, like C2. */
12532	&& num_sign_bit_copies (a, inner_mode)
12533	> (unsigned int) (GET_MODE_PRECISION (mode: inner_mode)
12534	- (mode_width - 1))))
12535	{
12536	op0 = SUBREG_REG (op0);
12537	continue;
12538	}
12539	}
12540
12541	/* If the inner mode is narrower and we are extracting the low part,
12542	we can treat the SUBREG as if it were a ZERO_EXTEND. */
12543	if (paradoxical_subreg_p (x: op0))
12544	;
12545	else if (subreg_lowpart_p (op0)
12546	&& GET_MODE_CLASS (mode) == MODE_INT
12547	&& is_int_mode (GET_MODE (SUBREG_REG (op0)), int_mode: &inner_mode)
12548	&& (code == NE || code == EQ)
12549	&& GET_MODE_PRECISION (mode: inner_mode) <= HOST_BITS_PER_WIDE_INT
12550	&& !paradoxical_subreg_p (x: op0)
12551	&& (nonzero_bits (SUBREG_REG (op0), inner_mode)
12552	& ~GET_MODE_MASK (mode)) == 0)
12553	{
12554	/* Remove outer subregs that don't do anything. */
12555	tem = gen_lowpart (inner_mode, op1);
12556
12557	if ((nonzero_bits (tem, inner_mode)
12558	& ~GET_MODE_MASK (mode)) == 0)
12559	{
12560	op0 = SUBREG_REG (op0);
12561	op1 = tem;
12562	continue;
12563	}
12564	break;
12565	}
12566	else
12567	break;
12568
12569	/* FALLTHROUGH */
12570
12571	case ZERO_EXTEND:
12572	if (is_int_mode (GET_MODE (XEXP (op0, 0)), int_mode: &mode)
12573	&& (unsigned_comparison_p || equality_comparison_p)
12574	&& HWI_COMPUTABLE_MODE_P (mode)
12575	&& (unsigned HOST_WIDE_INT) const_op <= GET_MODE_MASK (mode)
12576	&& const_op >= 0
12577	&& have_insn_for (COMPARE, mode))
12578	{
12579	op0 = XEXP (op0, 0);
12580	continue;
12581	}
12582	break;
12583
12584	case PLUS:
12585	/* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
12586	this for equality comparisons due to pathological cases involving
12587	overflows. */
12588	if (equality_comparison_p
12589	&& (tem = simplify_binary_operation (code: MINUS, mode,
12590	op0: op1, XEXP (op0, 1))) != 0)
12591	{
12592	op0 = XEXP (op0, 0);
12593	op1 = tem;
12594	continue;
12595	}
12596
12597	/* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
12598	if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
12599	&& GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
12600	{
12601	op0 = XEXP (XEXP (op0, 0), 0);
12602	code = (code == LT ? EQ : NE);
12603	continue;
12604	}
12605	break;
12606
12607	case MINUS:
12608	/* We used to optimize signed comparisons against zero, but that
12609	was incorrect. Unsigned comparisons against zero (GTU, LEU)
12610	arrive here as equality comparisons, or (GEU, LTU) are
12611	optimized away. No need to special-case them. */
12612
12613	/* (eq (minus A B) C) -> (eq A (plus B C)) or
12614	(eq B (minus A C)), whichever simplifies. We can only do
12615	this for equality comparisons due to pathological cases involving
12616	overflows. */
12617	if (equality_comparison_p
12618	&& (tem = simplify_binary_operation (code: PLUS, mode,
12619	XEXP (op0, 1), op1)) != 0)
12620	{
12621	op0 = XEXP (op0, 0);
12622	op1 = tem;
12623	continue;
12624	}
12625
12626	if (equality_comparison_p
12627	&& (tem = simplify_binary_operation (code: MINUS, mode,
12628	XEXP (op0, 0), op1)) != 0)
12629	{
12630	op0 = XEXP (op0, 1);
12631	op1 = tem;
12632	continue;
12633	}
12634
12635	/* The sign bit of (minus (ashiftrt X C) X), where C is the number
12636	of bits in X minus 1, is one iff X > 0. */
12637	if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
12638	&& CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12639	&& UINTVAL (XEXP (XEXP (op0, 0), 1)) == mode_width - 1
12640	&& rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12641	{
12642	op0 = XEXP (op0, 1);
12643	code = (code == GE ? LE : GT);
12644	continue;
12645	}
12646	break;
12647
12648	case XOR:
12649	/* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
12650	if C is zero or B is a constant. */
12651	if (equality_comparison_p
12652	&& (tem = simplify_binary_operation (code: XOR, mode,
12653	XEXP (op0, 1), op1)) != 0)
12654	{
12655	op0 = XEXP (op0, 0);
12656	op1 = tem;
12657	continue;
12658	}
12659	break;
12660
12661
12662	case IOR:
12663	/* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
12664	iff X <= 0. */
12665	if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
12666	&& XEXP (XEXP (op0, 0), 1) == constm1_rtx
12667	&& rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
12668	{
12669	op0 = XEXP (op0, 1);
12670	code = (code == GE ? GT : LE);
12671	continue;
12672	}
12673	break;
12674
12675	case AND:
12676	/* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
12677	will be converted to a ZERO_EXTRACT later. */
12678	if (const_op == 0 && equality_comparison_p
12679	&& GET_CODE (XEXP (op0, 0)) == ASHIFT
12680	&& XEXP (XEXP (op0, 0), 0) == const1_rtx)
12681	{
12682	op0 = gen_rtx_LSHIFTRT (mode, XEXP (op0, 1),
12683	XEXP (XEXP (op0, 0), 1));
12684	op0 = simplify_and_const_int (NULL_RTX, mode, varop: op0, constop: 1);
12685	continue;
12686	}
12687
12688	/* If we are comparing (and (lshiftrt X C1) C2) for equality with
12689	zero and X is a comparison and C1 and C2 describe only bits set
12690	in STORE_FLAG_VALUE, we can compare with X. */
12691	if (const_op == 0 && equality_comparison_p
12692	&& mode_width <= HOST_BITS_PER_WIDE_INT
12693	&& CONST_INT_P (XEXP (op0, 1))
12694	&& GET_CODE (XEXP (op0, 0)) == LSHIFTRT
12695	&& CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12696	&& INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
12697	&& INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
12698	{
12699	mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12700	<< INTVAL (XEXP (XEXP (op0, 0), 1)));
12701	if ((~STORE_FLAG_VALUE & mask) == 0
12702	&& (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
12703	|| ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
12704	&& COMPARISON_P (tem))))
12705	{
12706	op0 = XEXP (XEXP (op0, 0), 0);
12707	continue;
12708	}
12709	}
12710
12711	/* If we are doing an equality comparison of an AND of a bit equal
12712	to the sign bit, replace this with a LT or GE comparison of
12713	the underlying value. */
12714	if (equality_comparison_p
12715	&& const_op == 0
12716	&& CONST_INT_P (XEXP (op0, 1))
12717	&& mode_width <= HOST_BITS_PER_WIDE_INT
12718	&& ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
12719	== HOST_WIDE_INT_1U << (mode_width - 1)))
12720	{
12721	op0 = XEXP (op0, 0);
12722	code = (code == EQ ? GE : LT);
12723	continue;
12724	}
12725
12726	/* If this AND operation is really a ZERO_EXTEND from a narrower
12727	mode, the constant fits within that mode, and this is either an
12728	equality or unsigned comparison, try to do this comparison in
12729	the narrower mode.
12730
12731	Note that in:
12732
12733	(ne:DI (and:DI (reg:DI 4) (const_int 0xffffffff)) (const_int 0))
12734	-> (ne:DI (reg:SI 4) (const_int 0))
12735
12736	unless TARGET_TRULY_NOOP_TRUNCATION allows it or the register is
12737	known to hold a value of the required mode the
12738	transformation is invalid. */
12739	if ((equality_comparison_p || unsigned_comparison_p)
12740	&& CONST_INT_P (XEXP (op0, 1))
12741	&& (i = exact_log2 (x: (UINTVAL (XEXP (op0, 1))
12742	& GET_MODE_MASK (mode))
12743	+ 1)) >= 0
12744	&& const_op >> i == 0
12745	&& int_mode_for_size (size: i, limit: 1).exists (mode: &tmode))
12746	{
12747	op0 = gen_lowpart_or_truncate (mode: tmode, XEXP (op0, 0));
12748	continue;
12749	}
12750
12751	/* If this is (and:M1 (subreg:M1 X:M2 0) (const_int C1)) where C1
12752	fits in both M1 and M2 and the SUBREG is either paradoxical
12753	or represents the low part, permute the SUBREG and the AND
12754	and try again. */
12755	if (GET_CODE (XEXP (op0, 0)) == SUBREG
12756	&& CONST_INT_P (XEXP (op0, 1)))
12757	{
12758	unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
12759	/* Require an integral mode, to avoid creating something like
12760	(AND:SF ...). */
12761	if ((is_a <scalar_int_mode>
12762	(GET_MODE (SUBREG_REG (XEXP (op0, 0))), result: &tmode))
12763	/* It is unsafe to commute the AND into the SUBREG if the
12764	SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
12765	not defined. As originally written the upper bits
12766	have a defined value due to the AND operation.
12767	However, if we commute the AND inside the SUBREG then
12768	they no longer have defined values and the meaning of
12769	the code has been changed.
12770	Also C1 should not change value in the smaller mode,
12771	see PR67028 (a positive C1 can become negative in the
12772	smaller mode, so that the AND does no longer mask the
12773	upper bits). */
12774	&& ((WORD_REGISTER_OPERATIONS
12775	&& mode_width > GET_MODE_PRECISION (mode: tmode)
12776	&& mode_width <= BITS_PER_WORD
12777	&& trunc_int_for_mode (c1, tmode) == (HOST_WIDE_INT) c1)
12778	|| (mode_width <= GET_MODE_PRECISION (mode: tmode)
12779	&& subreg_lowpart_p (XEXP (op0, 0))))
12780	&& mode_width <= HOST_BITS_PER_WIDE_INT
12781	&& HWI_COMPUTABLE_MODE_P (mode: tmode)
12782	&& (c1 & ~mask) == 0
12783	&& (c1 & ~GET_MODE_MASK (tmode)) == 0
12784	&& c1 != mask
12785	&& c1 != GET_MODE_MASK (tmode))
12786	{
12787	op0 = simplify_gen_binary (code: AND, mode: tmode,
12788	SUBREG_REG (XEXP (op0, 0)),
12789	op1: gen_int_mode (c1, tmode));
12790	op0 = gen_lowpart (mode, op0);
12791	continue;
12792	}
12793	}
12794
12795	/* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
12796	if (const_op == 0 && equality_comparison_p
12797	&& XEXP (op0, 1) == const1_rtx
12798	&& GET_CODE (XEXP (op0, 0)) == NOT)
12799	{
12800	op0 = simplify_and_const_int (NULL_RTX, mode,
12801	XEXP (XEXP (op0, 0), 0), constop: 1);
12802	code = (code == NE ? EQ : NE);
12803	continue;
12804	}
12805
12806	/* Convert (ne (and (lshiftrt (not X)) 1) 0) to
12807	(eq (and (lshiftrt X) 1) 0).
12808	Also handle the case where (not X) is expressed using xor. */
12809	if (const_op == 0 && equality_comparison_p
12810	&& XEXP (op0, 1) == const1_rtx
12811	&& GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
12812	{
12813	rtx shift_op = XEXP (XEXP (op0, 0), 0);
12814	rtx shift_count = XEXP (XEXP (op0, 0), 1);
12815
12816	if (GET_CODE (shift_op) == NOT
12817	|| (GET_CODE (shift_op) == XOR
12818	&& CONST_INT_P (XEXP (shift_op, 1))
12819	&& CONST_INT_P (shift_count)
12820	&& HWI_COMPUTABLE_MODE_P (mode)
12821	&& (UINTVAL (XEXP (shift_op, 1))
12822	== HOST_WIDE_INT_1U
12823	<< INTVAL (shift_count))))
12824	{
12825	op0
12826	= gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count);
12827	op0 = simplify_and_const_int (NULL_RTX, mode, varop: op0, constop: 1);
12828	code = (code == NE ? EQ : NE);
12829	continue;
12830	}
12831	}
12832	break;
12833
12834	case ASHIFT:
12835	/* If we have (compare (ashift FOO N) (const_int C)) and
12836	the high order N bits of FOO (N+1 if an inequality comparison)
12837	are known to be zero, we can do this by comparing FOO with C
12838	shifted right N bits so long as the low-order N bits of C are
12839	zero. */
12840	if (CONST_INT_P (XEXP (op0, 1))
12841	&& INTVAL (XEXP (op0, 1)) >= 0
12842	&& ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
12843	< HOST_BITS_PER_WIDE_INT)
12844	&& (((unsigned HOST_WIDE_INT) const_op
12845	& ((HOST_WIDE_INT_1U << INTVAL (XEXP (op0, 1)))
12846	- 1)) == 0)
12847	&& mode_width <= HOST_BITS_PER_WIDE_INT
12848	&& (nonzero_bits (XEXP (op0, 0), mode)
12849	& ~(mask >> (INTVAL (XEXP (op0, 1))
12850	+ ! equality_comparison_p))) == 0)
12851	{
12852	/* We must perform a logical shift, not an arithmetic one,
12853	as we want the top N bits of C to be zero. */
12854	unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
12855
12856	temp >>= INTVAL (XEXP (op0, 1));
12857	op1 = gen_int_mode (temp, mode);
12858	op0 = XEXP (op0, 0);
12859	continue;
12860	}
12861
12862	/* If we are doing a sign bit comparison, it means we are testing
12863	a particular bit. Convert it to the appropriate AND. */
12864	if (sign_bit_comparison_p && CONST_INT_P (XEXP (op0, 1))
12865	&& mode_width <= HOST_BITS_PER_WIDE_INT)
12866	{
12867	op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
12868	constop: (HOST_WIDE_INT_1U
12869	<< (mode_width - 1
12870	- INTVAL (XEXP (op0, 1)))));
12871	code = (code == LT ? NE : EQ);
12872	continue;
12873	}
12874
12875	/* If this an equality comparison with zero and we are shifting
12876	the low bit to the sign bit, we can convert this to an AND of the
12877	low-order bit. */
12878	if (const_op == 0 && equality_comparison_p
12879	&& CONST_INT_P (XEXP (op0, 1))
12880	&& UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12881	{
12882	op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0), constop: 1);
12883	continue;
12884	}
12885	break;
12886
12887	case ASHIFTRT:
12888	/* If this is an equality comparison with zero, we can do this
12889	as a logical shift, which might be much simpler. */
12890	if (equality_comparison_p && const_op == 0
12891	&& CONST_INT_P (XEXP (op0, 1)))
12892	{
12893	op0 = simplify_shift_const (NULL_RTX, code: LSHIFTRT, result_mode: mode,
12894	XEXP (op0, 0),
12895	INTVAL (XEXP (op0, 1)));
12896	continue;
12897	}
12898
12899	/* If OP0 is a sign extension and CODE is not an unsigned comparison,
12900	do the comparison in a narrower mode. */
12901	if (! unsigned_comparison_p
12902	&& CONST_INT_P (XEXP (op0, 1))
12903	&& GET_CODE (XEXP (op0, 0)) == ASHIFT
12904	&& XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
12905	&& (int_mode_for_size (size: mode_width - INTVAL (XEXP (op0, 1)), limit: 1)
12906	.exists (mode: &tmode))
12907	&& (((unsigned HOST_WIDE_INT) const_op
12908	+ (GET_MODE_MASK (tmode) >> 1) + 1)
12909	<= GET_MODE_MASK (tmode)))
12910	{
12911	op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
12912	continue;
12913	}
12914
12915	/* Likewise if OP0 is a PLUS of a sign extension with a
12916	constant, which is usually represented with the PLUS
12917	between the shifts. */
12918	if (! unsigned_comparison_p
12919	&& CONST_INT_P (XEXP (op0, 1))
12920	&& GET_CODE (XEXP (op0, 0)) == PLUS
12921	&& CONST_INT_P (XEXP (XEXP (op0, 0), 1))
12922	&& GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
12923	&& XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
12924	&& (int_mode_for_size (size: mode_width - INTVAL (XEXP (op0, 1)), limit: 1)
12925	.exists (mode: &tmode))
12926	&& (((unsigned HOST_WIDE_INT) const_op
12927	+ (GET_MODE_MASK (tmode) >> 1) + 1)
12928	<= GET_MODE_MASK (tmode)))
12929	{
12930	rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
12931	rtx add_const = XEXP (XEXP (op0, 0), 1);
12932	rtx new_const = simplify_gen_binary (code: ASHIFTRT, mode,
12933	op0: add_const, XEXP (op0, 1));
12934
12935	op0 = simplify_gen_binary (code: PLUS, mode: tmode,
12936	gen_lowpart (tmode, inner),
12937	op1: new_const);
12938	continue;
12939	}
12940
12941	/* FALLTHROUGH */
12942	case LSHIFTRT:
12943	/* If we have (compare (xshiftrt FOO N) (const_int C)) and
12944	the low order N bits of FOO are known to be zero, we can do this
12945	by comparing FOO with C shifted left N bits so long as no
12946	overflow occurs. Even if the low order N bits of FOO aren't known
12947	to be zero, if the comparison is >= or < we can use the same
12948	optimization and for > or <= by setting all the low
12949	order N bits in the comparison constant. */
12950	if (CONST_INT_P (XEXP (op0, 1))
12951	&& INTVAL (XEXP (op0, 1)) > 0
12952	&& INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
12953	&& mode_width <= HOST_BITS_PER_WIDE_INT
12954	&& (((unsigned HOST_WIDE_INT) const_op
12955	+ (GET_CODE (op0) != LSHIFTRT
12956	? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
12957	+ 1)
12958	: 0))
12959	<= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
12960	{
12961	unsigned HOST_WIDE_INT low_bits
12962	= (nonzero_bits (XEXP (op0, 0), mode)
12963	& ((HOST_WIDE_INT_1U
12964	<< INTVAL (XEXP (op0, 1))) - 1));
12965	if (low_bits == 0 || !equality_comparison_p)
12966	{
12967	/* If the shift was logical, then we must make the condition
12968	unsigned. */
12969	if (GET_CODE (op0) == LSHIFTRT)
12970	code = unsigned_condition (code);
12971
12972	const_op = (unsigned HOST_WIDE_INT) const_op
12973	<< INTVAL (XEXP (op0, 1));
12974	if (low_bits != 0
12975	&& (code == GT || code == GTU
12976	|| code == LE || code == LEU))
12977	const_op
12978	|= ((HOST_WIDE_INT_1 << INTVAL (XEXP (op0, 1))) - 1);
12979	op1 = GEN_INT (const_op);
12980	op0 = XEXP (op0, 0);
12981	continue;
12982	}
12983	}
12984
12985	/* If we are using this shift to extract just the sign bit, we
12986	can replace this with an LT or GE comparison. */
12987	if (const_op == 0
12988	&& (equality_comparison_p || sign_bit_comparison_p)
12989	&& CONST_INT_P (XEXP (op0, 1))
12990	&& UINTVAL (XEXP (op0, 1)) == mode_width - 1)
12991	{
12992	op0 = XEXP (op0, 0);
12993	code = (code == NE || code == GT ? LT : GE);
12994	continue;
12995	}
12996	break;
12997
12998	default:
12999	break;
13000	}
13001
13002	break;
13003	}
13004
13005	/* Now make any compound operations involved in this comparison. Then,
13006	check for an outmost SUBREG on OP0 that is not doing anything or is
13007	paradoxical. The latter transformation must only be performed when
13008	it is known that the "extra" bits will be the same in op0 and op1 or
13009	that they don't matter. There are three cases to consider:
13010
13011	1. SUBREG_REG (op0) is a register. In this case the bits are don't
13012	care bits and we can assume they have any convenient value. So
13013	making the transformation is safe.
13014
13015	2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is UNKNOWN.
13016	In this case the upper bits of op0 are undefined. We should not make
13017	the simplification in that case as we do not know the contents of
13018	those bits.
13019
13020	3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not UNKNOWN.
13021	In that case we know those bits are zeros or ones. We must also be
13022	sure that they are the same as the upper bits of op1.
13023
13024	We can never remove a SUBREG for a non-equality comparison because
13025	the sign bit is in a different place in the underlying object. */
13026
13027	rtx_code op0_mco_code = SET;
13028	if (op1 == const0_rtx)
13029	op0_mco_code = code == NE || code == EQ ? EQ : COMPARE;
13030
13031	op0 = make_compound_operation (x: op0, in_code: op0_mco_code);
13032	op1 = make_compound_operation (x: op1, in_code: SET);
13033
13034	if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
13035	&& is_int_mode (GET_MODE (op0), int_mode: &mode)
13036	&& is_int_mode (GET_MODE (SUBREG_REG (op0)), int_mode: &inner_mode)
13037	&& (code == NE || code == EQ))
13038	{
13039	if (paradoxical_subreg_p (x: op0))
13040	{
13041	/* For paradoxical subregs, allow case 1 as above. Case 3 isn't
13042	implemented. */
13043	if (REG_P (SUBREG_REG (op0)))
13044	{
13045	op0 = SUBREG_REG (op0);
13046	op1 = gen_lowpart (inner_mode, op1);
13047	}
13048	}
13049	else if (GET_MODE_PRECISION (mode: inner_mode) <= HOST_BITS_PER_WIDE_INT
13050	&& (nonzero_bits (SUBREG_REG (op0), inner_mode)
13051	& ~GET_MODE_MASK (mode)) == 0)
13052	{
13053	tem = gen_lowpart (inner_mode, op1);
13054
13055	if ((nonzero_bits (tem, inner_mode) & ~GET_MODE_MASK (mode)) == 0)
13056	op0 = SUBREG_REG (op0), op1 = tem;
13057	}
13058	}
13059
13060	/* We now do the opposite procedure: Some machines don't have compare
13061	insns in all modes. If OP0's mode is an integer mode smaller than a
13062	word and we can't do a compare in that mode, see if there is a larger
13063	mode for which we can do the compare. There are a number of cases in
13064	which we can use the wider mode. */
13065
13066	if (is_int_mode (GET_MODE (op0), int_mode: &mode)
13067	&& GET_MODE_SIZE (mode) < UNITS_PER_WORD
13068	&& ! have_insn_for (COMPARE, mode))
13069	FOR_EACH_WIDER_MODE (tmode_iter, mode)
13070	{
13071	tmode = tmode_iter.require ();
13072	if (!HWI_COMPUTABLE_MODE_P (mode: tmode))
13073	break;
13074	if (have_insn_for (COMPARE, tmode))
13075	{
13076	int zero_extended;
13077
13078	/* If this is a test for negative, we can make an explicit
13079	test of the sign bit. Test this first so we can use
13080	a paradoxical subreg to extend OP0. */
13081
13082	if (op1 == const0_rtx && (code == LT || code == GE)
13083	&& HWI_COMPUTABLE_MODE_P (mode))
13084	{
13085	unsigned HOST_WIDE_INT sign
13086	= HOST_WIDE_INT_1U << (GET_MODE_BITSIZE (mode) - 1);
13087	op0 = simplify_gen_binary (code: AND, mode: tmode,
13088	gen_lowpart (tmode, op0),
13089	op1: gen_int_mode (sign, tmode));
13090	code = (code == LT) ? NE : EQ;
13091	break;
13092	}
13093
13094	/* If the only nonzero bits in OP0 and OP1 are those in the
13095	narrower mode and this is an equality or unsigned comparison,
13096	we can use the wider mode. Similarly for sign-extended
13097	values, in which case it is true for all comparisons. */
13098	zero_extended = ((code == EQ || code == NE
13099	|| code == GEU || code == GTU
13100	|| code == LEU || code == LTU)
13101	&& (nonzero_bits (op0, tmode)
13102	& ~GET_MODE_MASK (mode)) == 0
13103	&& ((CONST_INT_P (op1)
13104	|| (nonzero_bits (op1, tmode)
13105	& ~GET_MODE_MASK (mode)) == 0)));
13106
13107	if (zero_extended
13108	|| ((num_sign_bit_copies (op0, tmode)
13109	> (unsigned int) (GET_MODE_PRECISION (mode: tmode)
13110	- GET_MODE_PRECISION (mode)))
13111	&& (num_sign_bit_copies (op1, tmode)
13112	> (unsigned int) (GET_MODE_PRECISION (mode: tmode)
13113	- GET_MODE_PRECISION (mode)))))
13114	{
13115	/* If OP0 is an AND and we don't have an AND in MODE either,
13116	make a new AND in the proper mode. */
13117	if (GET_CODE (op0) == AND
13118	&& !have_insn_for (AND, mode))
13119	op0 = simplify_gen_binary (code: AND, mode: tmode,
13120	gen_lowpart (tmode,
13121	XEXP (op0, 0)),
13122	gen_lowpart (tmode,
13123	XEXP (op0, 1)));
13124	else
13125	{
13126	if (zero_extended)
13127	{
13128	op0 = simplify_gen_unary (code: ZERO_EXTEND, mode: tmode,
13129	op: op0, op_mode: mode);
13130	op1 = simplify_gen_unary (code: ZERO_EXTEND, mode: tmode,
13131	op: op1, op_mode: mode);
13132	}
13133	else
13134	{
13135	op0 = simplify_gen_unary (code: SIGN_EXTEND, mode: tmode,
13136	op: op0, op_mode: mode);
13137	op1 = simplify_gen_unary (code: SIGN_EXTEND, mode: tmode,
13138	op: op1, op_mode: mode);
13139	}
13140	break;
13141	}
13142	}
13143	}
13144	}
13145
13146	/* We may have changed the comparison operands. Re-canonicalize. */
13147	if (swap_commutative_operands_p (op0, op1))
13148	{
13149	std::swap (a&: op0, b&: op1);
13150	code = swap_condition (code);
13151	}
13152
13153	/* If this machine only supports a subset of valid comparisons, see if we
13154	can convert an unsupported one into a supported one. */
13155	target_canonicalize_comparison (code: &code, op0: &op0, op1: &op1, op0_preserve_value: 0);
13156
13157	*pop0 = op0;
13158	*pop1 = op1;
13159
13160	return code;
13161	}
13162
13163	/* Utility function for record_value_for_reg. Count number of
13164	rtxs in X. */
13165	static int
13166	count_rtxs (rtx x)
13167	{
13168	enum rtx_code code = GET_CODE (x);
13169	const char *fmt;
13170	int i, j, ret = 1;
13171
13172	if (GET_RTX_CLASS (code) == RTX_BIN_ARITH
13173	|| GET_RTX_CLASS (code) == RTX_COMM_ARITH)
13174	{
13175	rtx x0 = XEXP (x, 0);
13176	rtx x1 = XEXP (x, 1);
13177
13178	if (x0 == x1)
13179	return 1 + 2 * count_rtxs (x: x0);
13180
13181	if ((GET_RTX_CLASS (GET_CODE (x1)) == RTX_BIN_ARITH
13182	|| GET_RTX_CLASS (GET_CODE (x1)) == RTX_COMM_ARITH)
13183	&& (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13184	return 2 + 2 * count_rtxs (x: x0)
13185	+ count_rtxs (x: x == XEXP (x1, 0)
13186	? XEXP (x1, 1) : XEXP (x1, 0));
13187
13188	if ((GET_RTX_CLASS (GET_CODE (x0)) == RTX_BIN_ARITH
13189	|| GET_RTX_CLASS (GET_CODE (x0)) == RTX_COMM_ARITH)
13190	&& (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13191	return 2 + 2 * count_rtxs (x: x1)
13192	+ count_rtxs (x: x == XEXP (x0, 0)
13193	? XEXP (x0, 1) : XEXP (x0, 0));
13194	}
13195
13196	fmt = GET_RTX_FORMAT (code);
13197	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13198	if (fmt[i] == 'e')
13199	ret += count_rtxs (XEXP (x, i));
13200	else if (fmt[i] == 'E')
13201	for (j = 0; j < XVECLEN (x, i); j++)
13202	ret += count_rtxs (XVECEXP (x, i, j));
13203
13204	return ret;
13205	}
13206
13207	/* Utility function for following routine. Called when X is part of a value
13208	being stored into last_set_value. Sets last_set_table_tick
13209	for each register mentioned. Similar to mention_regs in cse.cc */
13210
13211	static void
13212	update_table_tick (rtx x)
13213	{
13214	enum rtx_code code = GET_CODE (x);
13215	const char *fmt = GET_RTX_FORMAT (code);
13216	int i, j;
13217
13218	if (code == REG)
13219	{
13220	unsigned int regno = REGNO (x);
13221	unsigned int endregno = END_REGNO (x);
13222	unsigned int r;
13223
13224	for (r = regno; r < endregno; r++)
13225	{
13226	reg_stat_type *rsp = &reg_stat[r];
13227	rsp->last_set_table_tick = label_tick;
13228	}
13229
13230	return;
13231	}
13232
13233	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
13234	if (fmt[i] == 'e')
13235	{
13236	/* Check for identical subexpressions. If x contains
13237	identical subexpression we only have to traverse one of
13238	them. */
13239	if (i == 0 && ARITHMETIC_P (x))
13240	{
13241	/* Note that at this point x1 has already been
13242	processed. */
13243	rtx x0 = XEXP (x, 0);
13244	rtx x1 = XEXP (x, 1);
13245
13246	/* If x0 and x1 are identical then there is no need to
13247	process x0. */
13248	if (x0 == x1)
13249	break;
13250
13251	/* If x0 is identical to a subexpression of x1 then while
13252	processing x1, x0 has already been processed. Thus we
13253	are done with x. */
13254	if (ARITHMETIC_P (x1)
13255	&& (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13256	break;
13257
13258	/* If x1 is identical to a subexpression of x0 then we
13259	still have to process the rest of x0. */
13260	if (ARITHMETIC_P (x0)
13261	&& (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13262	{
13263	update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
13264	break;
13265	}
13266	}
13267
13268	update_table_tick (XEXP (x, i));
13269	}
13270	else if (fmt[i] == 'E')
13271	for (j = 0; j < XVECLEN (x, i); j++)
13272	update_table_tick (XVECEXP (x, i, j));
13273	}
13274
13275	/* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
13276	are saying that the register is clobbered and we no longer know its
13277	value. If INSN is zero, don't update reg_stat[].last_set; this is
13278	only permitted with VALUE also zero and is used to invalidate the
13279	register. */
13280
13281	static void
13282	record_value_for_reg (rtx reg, rtx_insn *insn, rtx value)
13283	{
13284	unsigned int regno = REGNO (reg);
13285	unsigned int endregno = END_REGNO (x: reg);
13286	unsigned int i;
13287	reg_stat_type *rsp;
13288
13289	/* If VALUE contains REG and we have a previous value for REG, substitute
13290	the previous value. */
13291	if (value && insn && reg_overlap_mentioned_p (reg, value))
13292	{
13293	rtx tem;
13294
13295	/* Set things up so get_last_value is allowed to see anything set up to
13296	our insn. */
13297	subst_low_luid = DF_INSN_LUID (insn);
13298	tem = get_last_value (reg);
13299
13300	/* If TEM is simply a binary operation with two CLOBBERs as operands,
13301	it isn't going to be useful and will take a lot of time to process,
13302	so just use the CLOBBER. */
13303
13304	if (tem)
13305	{
13306	if (ARITHMETIC_P (tem)
13307	&& GET_CODE (XEXP (tem, 0)) == CLOBBER
13308	&& GET_CODE (XEXP (tem, 1)) == CLOBBER)
13309	tem = XEXP (tem, 0);
13310	else if (count_occurrences (value, reg, 1) >= 2)
13311	{
13312	/* If there are two or more occurrences of REG in VALUE,
13313	prevent the value from growing too much. */
13314	if (count_rtxs (x: tem) > param_max_last_value_rtl)
13315	tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
13316	}
13317
13318	value = replace_rtx (copy_rtx (value), reg, tem);
13319	}
13320	}
13321
13322	/* For each register modified, show we don't know its value, that
13323	we don't know about its bitwise content, that its value has been
13324	updated, and that we don't know the location of the death of the
13325	register. */
13326	for (i = regno; i < endregno; i++)
13327	{
13328	rsp = &reg_stat[i];
13329
13330	if (insn)
13331	rsp->last_set = insn;
13332
13333	rsp->last_set_value = 0;
13334	rsp->last_set_mode = VOIDmode;
13335	rsp->last_set_nonzero_bits = 0;
13336	rsp->last_set_sign_bit_copies = 0;
13337	rsp->last_death = 0;
13338	rsp->truncated_to_mode = VOIDmode;
13339	}
13340
13341	/* Mark registers that are being referenced in this value. */
13342	if (value)
13343	update_table_tick (x: value);
13344
13345	/* Now update the status of each register being set.
13346	If someone is using this register in this block, set this register
13347	to invalid since we will get confused between the two lives in this
13348	basic block. This makes using this register always invalid. In cse, we
13349	scan the table to invalidate all entries using this register, but this
13350	is too much work for us. */
13351
13352	for (i = regno; i < endregno; i++)
13353	{
13354	rsp = &reg_stat[i];
13355	rsp->last_set_label = label_tick;
13356	if (!insn
13357	|| (value && rsp->last_set_table_tick >= label_tick_ebb_start))
13358	rsp->last_set_invalid = true;
13359	else
13360	rsp->last_set_invalid = false;
13361	}
13362
13363	/* The value being assigned might refer to X (like in "x++;"). In that
13364	case, we must replace it with (clobber (const_int 0)) to prevent
13365	infinite loops. */
13366	rsp = &reg_stat[regno];
13367	if (value && !get_last_value_validate (&value, insn, label_tick, false))
13368	{
13369	value = copy_rtx (value);
13370	if (!get_last_value_validate (&value, insn, label_tick, true))
13371	value = 0;
13372	}
13373
13374	/* For the main register being modified, update the value, the mode, the
13375	nonzero bits, and the number of sign bit copies. */
13376
13377	rsp->last_set_value = value;
13378
13379	if (value)
13380	{
13381	machine_mode mode = GET_MODE (reg);
13382	subst_low_luid = DF_INSN_LUID (insn);
13383	rsp->last_set_mode = mode;
13384	if (GET_MODE_CLASS (mode) == MODE_INT
13385	&& HWI_COMPUTABLE_MODE_P (mode))
13386	mode = nonzero_bits_mode;
13387	rsp->last_set_nonzero_bits = nonzero_bits (value, mode);
13388	rsp->last_set_sign_bit_copies
13389	= num_sign_bit_copies (value, GET_MODE (reg));
13390	}
13391	}
13392
13393	/* Called via note_stores from record_dead_and_set_regs to handle one
13394	SET or CLOBBER in an insn. DATA is the instruction in which the
13395	set is occurring. */
13396
13397	static void
13398	record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
13399	{
13400	rtx_insn *record_dead_insn = (rtx_insn *) data;
13401
13402	if (GET_CODE (dest) == SUBREG)
13403	dest = SUBREG_REG (dest);
13404
13405	if (!record_dead_insn)
13406	{
13407	if (REG_P (dest))
13408	record_value_for_reg (reg: dest, NULL, NULL_RTX);
13409	return;
13410	}
13411
13412	if (REG_P (dest))
13413	{
13414	/* If we are setting the whole register, we know its value. */
13415	if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
13416	record_value_for_reg (reg: dest, insn: record_dead_insn, SET_SRC (setter));
13417	/* We can handle a SUBREG if it's the low part, but we must be
13418	careful with paradoxical SUBREGs on RISC architectures because
13419	we cannot strip e.g. an extension around a load and record the
13420	naked load since the RTL middle-end considers that the upper bits
13421	are defined according to LOAD_EXTEND_OP. */
13422	else if (GET_CODE (setter) == SET
13423	&& GET_CODE (SET_DEST (setter)) == SUBREG
13424	&& SUBREG_REG (SET_DEST (setter)) == dest
13425	&& known_le (GET_MODE_PRECISION (GET_MODE (dest)),
13426	BITS_PER_WORD)
13427	&& subreg_lowpart_p (SET_DEST (setter)))
13428	{
13429	if (WORD_REGISTER_OPERATIONS
13430	&& word_register_operation_p (SET_SRC (setter))
13431	&& paradoxical_subreg_p (SET_DEST (setter)))
13432	record_value_for_reg (reg: dest, insn: record_dead_insn, SET_SRC (setter));
13433	else if (!partial_subreg_p (SET_DEST (setter)))
13434	record_value_for_reg (reg: dest, insn: record_dead_insn,
13435	gen_lowpart (GET_MODE (dest),
13436	SET_SRC (setter)));
13437	else
13438	{
13439	record_value_for_reg (reg: dest, insn: record_dead_insn,
13440	gen_lowpart (GET_MODE (dest),
13441	SET_SRC (setter)));
13442
13443	unsigned HOST_WIDE_INT mask;
13444	reg_stat_type *rsp = &reg_stat[REGNO (dest)];
13445	mask = GET_MODE_MASK (GET_MODE (SET_DEST (setter)));
13446	rsp->last_set_nonzero_bits |= ~mask;
13447	rsp->last_set_sign_bit_copies = 1;
13448	}
13449	}
13450	/* Otherwise show that we don't know the value. */
13451	else
13452	record_value_for_reg (reg: dest, insn: record_dead_insn, NULL_RTX);
13453	}
13454	else if (MEM_P (dest)
13455	/* Ignore pushes, they clobber nothing. */
13456	&& ! push_operand (dest, GET_MODE (dest)))
13457	mem_last_set = DF_INSN_LUID (record_dead_insn);
13458	}
13459
13460	/* Update the records of when each REG was most recently set or killed
13461	for the things done by INSN. This is the last thing done in processing
13462	INSN in the combiner loop.
13463
13464	We update reg_stat[], in particular fields last_set, last_set_value,
13465	last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
13466	last_death, and also the similar information mem_last_set (which insn
13467	most recently modified memory) and last_call_luid (which insn was the
13468	most recent subroutine call). */
13469
13470	static void
13471	record_dead_and_set_regs (rtx_insn *insn)
13472	{
13473	rtx link;
13474	unsigned int i;
13475
13476	for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
13477	{
13478	if (REG_NOTE_KIND (link) == REG_DEAD
13479	&& REG_P (XEXP (link, 0)))
13480	{
13481	unsigned int regno = REGNO (XEXP (link, 0));
13482	unsigned int endregno = END_REGNO (XEXP (link, 0));
13483
13484	for (i = regno; i < endregno; i++)
13485	{
13486	reg_stat_type *rsp;
13487
13488	rsp = &reg_stat[i];
13489	rsp->last_death = insn;
13490	}
13491	}
13492	else if (REG_NOTE_KIND (link) == REG_INC)
13493	record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
13494	}
13495
13496	if (CALL_P (insn))
13497	{
13498	HARD_REG_SET callee_clobbers
13499	= insn_callee_abi (insn).full_and_partial_reg_clobbers ();
13500	hard_reg_set_iterator hrsi;
13501	EXECUTE_IF_SET_IN_HARD_REG_SET (callee_clobbers, 0, i, hrsi)
13502	{
13503	reg_stat_type *rsp;
13504
13505	/* ??? We could try to preserve some information from the last
13506	set of register I if the call doesn't actually clobber
13507	(reg:last_set_mode I), which might be true for ABIs with
13508	partial clobbers. However, it would be difficult to
13509	update last_set_nonzero_bits and last_sign_bit_copies
13510	to account for the part of I that actually was clobbered.
13511	It wouldn't help much anyway, since we rarely see this
13512	situation before RA. */
13513	rsp = &reg_stat[i];
13514	rsp->last_set_invalid = true;
13515	rsp->last_set = insn;
13516	rsp->last_set_value = 0;
13517	rsp->last_set_mode = VOIDmode;
13518	rsp->last_set_nonzero_bits = 0;
13519	rsp->last_set_sign_bit_copies = 0;
13520	rsp->last_death = 0;
13521	rsp->truncated_to_mode = VOIDmode;
13522	}
13523
13524	last_call_luid = mem_last_set = DF_INSN_LUID (insn);
13525
13526	/* We can't combine into a call pattern. Remember, though, that
13527	the return value register is set at this LUID. We could
13528	still replace a register with the return value from the
13529	wrong subroutine call! */
13530	note_stores (insn, record_dead_and_set_regs_1, NULL_RTX);
13531	}
13532	else
13533	note_stores (insn, record_dead_and_set_regs_1, insn);
13534	}
13535
13536	/* If a SUBREG has the promoted bit set, it is in fact a property of the
13537	register present in the SUBREG, so for each such SUBREG go back and
13538	adjust nonzero and sign bit information of the registers that are
13539	known to have some zero/sign bits set.
13540
13541	This is needed because when combine blows the SUBREGs away, the
13542	information on zero/sign bits is lost and further combines can be
13543	missed because of that. */
13544
13545	static void
13546	record_promoted_value (rtx_insn *insn, rtx subreg)
13547	{
13548	struct insn_link *links;
13549	rtx set;
13550	unsigned int regno = REGNO (SUBREG_REG (subreg));
13551	machine_mode mode = GET_MODE (subreg);
13552
13553	if (!HWI_COMPUTABLE_MODE_P (mode))
13554	return;
13555
13556	for (links = LOG_LINKS (insn); links;)
13557	{
13558	reg_stat_type *rsp;
13559
13560	insn = links->insn;
13561	set = single_set (insn);
13562
13563	if (! set || !REG_P (SET_DEST (set))
13564	|| REGNO (SET_DEST (set)) != regno
13565	|| GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
13566	{
13567	links = links->next;
13568	continue;
13569	}
13570
13571	rsp = &reg_stat[regno];
13572	if (rsp->last_set == insn)
13573	{
13574	if (SUBREG_PROMOTED_UNSIGNED_P (subreg))
13575	rsp->last_set_nonzero_bits &= GET_MODE_MASK (mode);
13576	}
13577
13578	if (REG_P (SET_SRC (set)))
13579	{
13580	regno = REGNO (SET_SRC (set));
13581	links = LOG_LINKS (insn);
13582	}
13583	else
13584	break;
13585	}
13586	}
13587
13588	/* Check if X, a register, is known to contain a value already
13589	truncated to MODE. In this case we can use a subreg to refer to
13590	the truncated value even though in the generic case we would need
13591	an explicit truncation. */
13592
13593	static bool
13594	reg_truncated_to_mode (machine_mode mode, const_rtx x)
13595	{
13596	reg_stat_type *rsp = &reg_stat[REGNO (x)];
13597	machine_mode truncated = rsp->truncated_to_mode;
13598
13599	if (truncated == 0
13600	|| rsp->truncation_label < label_tick_ebb_start)
13601	return false;
13602	if (!partial_subreg_p (outermode: mode, innermode: truncated))
13603	return true;
13604	if (TRULY_NOOP_TRUNCATION_MODES_P (mode, truncated))
13605	return true;
13606	return false;
13607	}
13608
13609	/* If X is a hard reg or a subreg record the mode that the register is
13610	accessed in. For non-TARGET_TRULY_NOOP_TRUNCATION targets we might be
13611	able to turn a truncate into a subreg using this information. Return true
13612	if traversing X is complete. */
13613
13614	static bool
13615	record_truncated_value (rtx x)
13616	{
13617	machine_mode truncated_mode;
13618	reg_stat_type *rsp;
13619
13620	if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
13621	{
13622	machine_mode original_mode = GET_MODE (SUBREG_REG (x));
13623	truncated_mode = GET_MODE (x);
13624
13625	if (!partial_subreg_p (outermode: truncated_mode, innermode: original_mode))
13626	return true;
13627
13628	truncated_mode = GET_MODE (x);
13629	if (TRULY_NOOP_TRUNCATION_MODES_P (truncated_mode, original_mode))
13630	return true;
13631
13632	x = SUBREG_REG (x);
13633	}
13634	/* ??? For hard-regs we now record everything. We might be able to
13635	optimize this using last_set_mode. */
13636	else if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
13637	truncated_mode = GET_MODE (x);
13638	else
13639	return false;
13640
13641	rsp = &reg_stat[REGNO (x)];
13642	if (rsp->truncated_to_mode == 0
13643	|| rsp->truncation_label < label_tick_ebb_start
13644	|| partial_subreg_p (outermode: truncated_mode, innermode: rsp->truncated_to_mode))
13645	{
13646	rsp->truncated_to_mode = truncated_mode;
13647	rsp->truncation_label = label_tick;
13648	}
13649
13650	return true;
13651	}
13652
13653	/* Callback for note_uses. Find hardregs and subregs of pseudos and
13654	the modes they are used in. This can help truning TRUNCATEs into
13655	SUBREGs. */
13656
13657	static void
13658	record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
13659	{
13660	subrtx_var_iterator::array_type array;
13661	FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
13662	if (record_truncated_value (x: *iter))
13663	iter.skip_subrtxes ();
13664	}
13665
13666	/* Scan X for promoted SUBREGs. For each one found,
13667	note what it implies to the registers used in it. */
13668
13669	static void
13670	check_promoted_subreg (rtx_insn *insn, rtx x)
13671	{
13672	if (GET_CODE (x) == SUBREG
13673	&& SUBREG_PROMOTED_VAR_P (x)
13674	&& REG_P (SUBREG_REG (x)))
13675	record_promoted_value (insn, subreg: x);
13676	else
13677	{
13678	const char *format = GET_RTX_FORMAT (GET_CODE (x));
13679	int i, j;
13680
13681	for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
13682	switch (format[i])
13683	{
13684	case 'e':
13685	check_promoted_subreg (insn, XEXP (x, i));
13686	break;
13687	case 'V':
13688	case 'E':
13689	if (XVEC (x, i) != 0)
13690	for (j = 0; j < XVECLEN (x, i); j++)
13691	check_promoted_subreg (insn, XVECEXP (x, i, j));
13692	break;
13693	}
13694	}
13695	}
13696
13697	/* Verify that all the registers and memory references mentioned in *LOC are
13698	still valid. *LOC was part of a value set in INSN when label_tick was
13699	equal to TICK. Return false if some are not. If REPLACE is true, replace
13700	the invalid references with (clobber (const_int 0)) and return true. This
13701	replacement is useful because we often can get useful information about
13702	the form of a value (e.g., if it was produced by a shift that always
13703	produces -1 or 0) even though we don't know exactly what registers it
13704	was produced from. */
13705
13706	static bool
13707	get_last_value_validate (rtx *loc, rtx_insn *insn, int tick, bool replace)
13708	{
13709	rtx x = *loc;
13710	const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
13711	int len = GET_RTX_LENGTH (GET_CODE (x));
13712	int i, j;
13713
13714	if (REG_P (x))
13715	{
13716	unsigned int regno = REGNO (x);
13717	unsigned int endregno = END_REGNO (x);
13718	unsigned int j;
13719
13720	for (j = regno; j < endregno; j++)
13721	{
13722	reg_stat_type *rsp = &reg_stat[j];
13723	if (rsp->last_set_invalid
13724	/* If this is a pseudo-register that was only set once and not
13725	live at the beginning of the function, it is always valid. */
13726	|| (! (regno >= FIRST_PSEUDO_REGISTER
13727	&& regno < reg_n_sets_max
13728	&& REG_N_SETS (regno) == 1
13729	&& (!REGNO_REG_SET_P
13730	(DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb),
13731	regno)))
13732	&& rsp->last_set_label > tick))
13733	{
13734	if (replace)
13735	*loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13736	return replace;
13737	}
13738	}
13739
13740	return true;
13741	}
13742	/* If this is a memory reference, make sure that there were no stores after
13743	it that might have clobbered the value. We don't have alias info, so we
13744	assume any store invalidates it. Moreover, we only have local UIDs, so
13745	we also assume that there were stores in the intervening basic blocks. */
13746	else if (MEM_P (x) && !MEM_READONLY_P (x)
13747	&& (tick != label_tick || DF_INSN_LUID (insn) <= mem_last_set))
13748	{
13749	if (replace)
13750	*loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
13751	return replace;
13752	}
13753
13754	for (i = 0; i < len; i++)
13755	{
13756	if (fmt[i] == 'e')
13757	{
13758	/* Check for identical subexpressions. If x contains
13759	identical subexpression we only have to traverse one of
13760	them. */
13761	if (i == 1 && ARITHMETIC_P (x))
13762	{
13763	/* Note that at this point x0 has already been checked
13764	and found valid. */
13765	rtx x0 = XEXP (x, 0);
13766	rtx x1 = XEXP (x, 1);
13767
13768	/* If x0 and x1 are identical then x is also valid. */
13769	if (x0 == x1)
13770	return true;
13771
13772	/* If x1 is identical to a subexpression of x0 then
13773	while checking x0, x1 has already been checked. Thus
13774	it is valid and so as x. */
13775	if (ARITHMETIC_P (x0)
13776	&& (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
13777	return true;
13778
13779	/* If x0 is identical to a subexpression of x1 then x is
13780	valid iff the rest of x1 is valid. */
13781	if (ARITHMETIC_P (x1)
13782	&& (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
13783	return
13784	get_last_value_validate (loc: &XEXP (x1,
13785	x0 == XEXP (x1, 0) ? 1 : 0),
13786	insn, tick, replace);
13787	}
13788
13789	if (!get_last_value_validate (loc: &XEXP (x, i), insn, tick, replace))
13790	return false;
13791	}
13792	else if (fmt[i] == 'E')
13793	for (j = 0; j < XVECLEN (x, i); j++)
13794	if (!get_last_value_validate (loc: &XVECEXP (x, i, j),
13795	insn, tick, replace))
13796	return false;
13797	}
13798
13799	/* If we haven't found a reason for it to be invalid, it is valid. */
13800	return true;
13801	}
13802
13803	/* Get the last value assigned to X, if known. Some registers
13804	in the value may be replaced with (clobber (const_int 0)) if their value
13805	is known longer known reliably. */
13806
13807	static rtx
13808	get_last_value (const_rtx x)
13809	{
13810	unsigned int regno;
13811	rtx value;
13812	reg_stat_type *rsp;
13813
13814	/* If this is a non-paradoxical SUBREG, get the value of its operand and
13815	then convert it to the desired mode. If this is a paradoxical SUBREG,
13816	we cannot predict what values the "extra" bits might have. */
13817	if (GET_CODE (x) == SUBREG
13818	&& subreg_lowpart_p (x)
13819	&& !paradoxical_subreg_p (x)
13820	&& (value = get_last_value (SUBREG_REG (x))) != 0)
13821	return gen_lowpart (GET_MODE (x), value);
13822
13823	if (!REG_P (x))
13824	return 0;
13825
13826	regno = REGNO (x);
13827	rsp = &reg_stat[regno];
13828	value = rsp->last_set_value;
13829
13830	/* If we don't have a value, or if it isn't for this basic block and
13831	it's either a hard register, set more than once, or it's a live
13832	at the beginning of the function, return 0.
13833
13834	Because if it's not live at the beginning of the function then the reg
13835	is always set before being used (is never used without being set).
13836	And, if it's set only once, and it's always set before use, then all
13837	uses must have the same last value, even if it's not from this basic
13838	block. */
13839
13840	if (value == 0
13841	|| (rsp->last_set_label < label_tick_ebb_start
13842	&& (regno < FIRST_PSEUDO_REGISTER
13843	|| regno >= reg_n_sets_max
13844	|| REG_N_SETS (regno) != 1
13845	|| REGNO_REG_SET_P
13846	(DF_LR_IN (ENTRY_BLOCK_PTR_FOR_FN (cfun)->next_bb), regno))))
13847	return 0;
13848
13849	/* If the value was set in a later insn than the ones we are processing,
13850	we can't use it even if the register was only set once. */
13851	if (rsp->last_set_label == label_tick
13852	&& DF_INSN_LUID (rsp->last_set) >= subst_low_luid)
13853	return 0;
13854
13855	/* If fewer bits were set than what we are asked for now, we cannot use
13856	the value. */
13857	if (maybe_lt (a: GET_MODE_PRECISION (mode: rsp->last_set_mode),
13858	b: GET_MODE_PRECISION (GET_MODE (x))))
13859	return 0;
13860
13861	/* If the value has all its registers valid, return it. */
13862	if (get_last_value_validate (loc: &value, insn: rsp->last_set,
13863	tick: rsp->last_set_label, replace: false))
13864	return value;
13865
13866	/* Otherwise, make a copy and replace any invalid register with
13867	(clobber (const_int 0)). If that fails for some reason, return 0. */
13868
13869	value = copy_rtx (value);
13870	if (get_last_value_validate (loc: &value, insn: rsp->last_set,
13871	tick: rsp->last_set_label, replace: true))
13872	return value;
13873
13874	return 0;
13875	}
13876
13877	/* Define three variables used for communication between the following
13878	routines. */
13879
13880	static unsigned int reg_dead_regno, reg_dead_endregno;
13881	static int reg_dead_flag;
13882	rtx reg_dead_reg;
13883
13884	/* Function called via note_stores from reg_dead_at_p.
13885
13886	If DEST is within [reg_dead_regno, reg_dead_endregno), set
13887	reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
13888
13889	static void
13890	reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
13891	{
13892	unsigned int regno, endregno;
13893
13894	if (!REG_P (dest))
13895	return;
13896
13897	regno = REGNO (dest);
13898	endregno = END_REGNO (x: dest);
13899	if (reg_dead_endregno > regno && reg_dead_regno < endregno)
13900	reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
13901	}
13902
13903	/* Return true if REG is known to be dead at INSN.
13904
13905	We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
13906	referencing REG, it is dead. If we hit a SET referencing REG, it is
13907	live. Otherwise, see if it is live or dead at the start of the basic
13908	block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
13909	must be assumed to be always live. */
13910
13911	static bool
13912	reg_dead_at_p (rtx reg, rtx_insn *insn)
13913	{
13914	basic_block block;
13915	unsigned int i;
13916
13917	/* Set variables for reg_dead_at_p_1. */
13918	reg_dead_regno = REGNO (reg);
13919	reg_dead_endregno = END_REGNO (x: reg);
13920	reg_dead_reg = reg;
13921
13922	reg_dead_flag = 0;
13923
13924	/* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
13925	we allow the machine description to decide whether use-and-clobber
13926	patterns are OK. */
13927	if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
13928	{
13929	for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13930	if (!fixed_regs[i] && TEST_HARD_REG_BIT (set: newpat_used_regs, bit: i))
13931	return false;
13932	}
13933
13934	/* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, or
13935	beginning of basic block. */
13936	block = BLOCK_FOR_INSN (insn);
13937	for (;;)
13938	{
13939	if (INSN_P (insn))
13940	{
13941	if (find_regno_note (insn, REG_UNUSED, reg_dead_regno))
13942	return true;
13943
13944	note_stores (insn, reg_dead_at_p_1, NULL);
13945	if (reg_dead_flag)
13946	return reg_dead_flag == 1 ? 1 : 0;
13947
13948	if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
13949	return true;
13950	}
13951
13952	if (insn == BB_HEAD (block))
13953	break;
13954
13955	insn = PREV_INSN (insn);
13956	}
13957
13958	/* Look at live-in sets for the basic block that we were in. */
13959	for (i = reg_dead_regno; i < reg_dead_endregno; i++)
13960	if (REGNO_REG_SET_P (df_get_live_in (block), i))
13961	return false;
13962
13963	return true;
13964	}
13965
13966	/* Note hard registers in X that are used. */
13967
13968	static void
13969	mark_used_regs_combine (rtx x)
13970	{
13971	RTX_CODE code = GET_CODE (x);
13972	unsigned int regno;
13973	int i;
13974
13975	switch (code)
13976	{
13977	case LABEL_REF:
13978	case SYMBOL_REF:
13979	case CONST:
13980	CASE_CONST_ANY:
13981	case PC:
13982	case ADDR_VEC:
13983	case ADDR_DIFF_VEC:
13984	case ASM_INPUT:
13985	return;
13986
13987	case CLOBBER:
13988	/* If we are clobbering a MEM, mark any hard registers inside the
13989	address as used. */
13990	if (MEM_P (XEXP (x, 0)))
13991	mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
13992	return;
13993
13994	case REG:
13995	regno = REGNO (x);
13996	/* A hard reg in a wide mode may really be multiple registers.
13997	If so, mark all of them just like the first. */
13998	if (regno < FIRST_PSEUDO_REGISTER)
13999	{
14000	/* None of this applies to the stack, frame or arg pointers. */
14001	if (regno == STACK_POINTER_REGNUM
14002	|| (!HARD_FRAME_POINTER_IS_FRAME_POINTER
14003	&& regno == HARD_FRAME_POINTER_REGNUM)
14004	|| (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
14005	&& regno == ARG_POINTER_REGNUM && fixed_regs[regno])
14006	|| regno == FRAME_POINTER_REGNUM)
14007	return;
14008
14009	add_to_hard_reg_set (regs: &newpat_used_regs, GET_MODE (x), regno);
14010	}
14011	return;
14012
14013	case SET:
14014	{
14015	/* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
14016	the address. */
14017	rtx testreg = SET_DEST (x);
14018
14019	while (GET_CODE (testreg) == SUBREG
14020	|| GET_CODE (testreg) == ZERO_EXTRACT
14021	|| GET_CODE (testreg) == STRICT_LOW_PART)
14022	testreg = XEXP (testreg, 0);
14023
14024	if (MEM_P (testreg))
14025	mark_used_regs_combine (XEXP (testreg, 0));
14026
14027	mark_used_regs_combine (SET_SRC (x));
14028	}
14029	return;
14030
14031	default:
14032	break;
14033	}
14034
14035	/* Recursively scan the operands of this expression. */
14036
14037	{
14038	const char *fmt = GET_RTX_FORMAT (code);
14039
14040	for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
14041	{
14042	if (fmt[i] == 'e')
14043	mark_used_regs_combine (XEXP (x, i));
14044	else if (fmt[i] == 'E')
14045	{
14046	int j;
14047
14048	for (j = 0; j < XVECLEN (x, i); j++)
14049	mark_used_regs_combine (XVECEXP (x, i, j));
14050	}
14051	}
14052	}
14053	}
14054
14055	/* Remove register number REGNO from the dead registers list of INSN.
14056
14057	Return the note used to record the death, if there was one. */
14058
14059	rtx
14060	remove_death (unsigned int regno, rtx_insn *insn)
14061	{
14062	rtx note = find_regno_note (insn, REG_DEAD, regno);
14063
14064	if (note)
14065	remove_note (insn, note);
14066
14067	return note;
14068	}
14069
14070	/* For each register (hardware or pseudo) used within expression X, if its
14071	death is in an instruction with luid between FROM_LUID (inclusive) and
14072	TO_INSN (exclusive), put a REG_DEAD note for that register in the
14073	list headed by PNOTES.
14074
14075	That said, don't move registers killed by maybe_kill_insn.
14076
14077	This is done when X is being merged by combination into TO_INSN. These
14078	notes will then be distributed as needed. */
14079
14080	static void
14081	move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
14082	rtx *pnotes)
14083	{
14084	const char *fmt;
14085	int len, i;
14086	enum rtx_code code = GET_CODE (x);
14087
14088	if (code == REG)
14089	{
14090	unsigned int regno = REGNO (x);
14091	rtx_insn *where_dead = reg_stat[regno].last_death;
14092
14093	/* If we do not know where the register died, it may still die between
14094	FROM_LUID and TO_INSN. If so, find it. This is PR83304. */
14095	if (!where_dead || DF_INSN_LUID (where_dead) >= DF_INSN_LUID (to_insn))
14096	{
14097	rtx_insn *insn = prev_real_nondebug_insn (to_insn);
14098	while (insn
14099	&& BLOCK_FOR_INSN (insn) == BLOCK_FOR_INSN (insn: to_insn)
14100	&& DF_INSN_LUID (insn) >= from_luid)
14101	{
14102	if (dead_or_set_regno_p (insn, regno))
14103	{
14104	if (find_regno_note (insn, REG_DEAD, regno))
14105	where_dead = insn;
14106	break;
14107	}
14108
14109	insn = prev_real_nondebug_insn (insn);
14110	}
14111	}
14112
14113	/* Don't move the register if it gets killed in between from and to. */
14114	if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
14115	&& ! reg_referenced_p (x, maybe_kill_insn))
14116	return;
14117
14118	if (where_dead
14119	&& BLOCK_FOR_INSN (insn: where_dead) == BLOCK_FOR_INSN (insn: to_insn)
14120	&& DF_INSN_LUID (where_dead) >= from_luid
14121	&& DF_INSN_LUID (where_dead) < DF_INSN_LUID (to_insn))
14122	{
14123	rtx note = remove_death (regno, insn: where_dead);
14124
14125	/* It is possible for the call above to return 0. This can occur
14126	when last_death points to I2 or I1 that we combined with.
14127	In that case make a new note.
14128
14129	We must also check for the case where X is a hard register
14130	and NOTE is a death note for a range of hard registers
14131	including X. In that case, we must put REG_DEAD notes for
14132	the remaining registers in place of NOTE. */
14133
14134	if (note != 0 && regno < FIRST_PSEUDO_REGISTER
14135	&& partial_subreg_p (GET_MODE (x), GET_MODE (XEXP (note, 0))))
14136	{
14137	unsigned int deadregno = REGNO (XEXP (note, 0));
14138	unsigned int deadend = END_REGNO (XEXP (note, 0));
14139	unsigned int ourend = END_REGNO (x);
14140	unsigned int i;
14141
14142	for (i = deadregno; i < deadend; i++)
14143	if (i < regno || i >= ourend)
14144	add_reg_note (where_dead, REG_DEAD, regno_reg_rtx[i]);
14145	}
14146
14147	/* If we didn't find any note, or if we found a REG_DEAD note that
14148	covers only part of the given reg, and we have a multi-reg hard
14149	register, then to be safe we must check for REG_DEAD notes
14150	for each register other than the first. They could have
14151	their own REG_DEAD notes lying around. */
14152	else if ((note == 0
14153	|| (note != 0
14154	&& partial_subreg_p (GET_MODE (XEXP (note, 0)),
14155	GET_MODE (x))))
14156	&& regno < FIRST_PSEUDO_REGISTER
14157	&& REG_NREGS (x) > 1)
14158	{
14159	unsigned int ourend = END_REGNO (x);
14160	unsigned int i, offset;
14161	rtx oldnotes = 0;
14162
14163	if (note)
14164	offset = hard_regno_nregs (regno, GET_MODE (XEXP (note, 0)));
14165	else
14166	offset = 1;
14167
14168	for (i = regno + offset; i < ourend; i++)
14169	move_deaths (x: regno_reg_rtx[i],
14170	maybe_kill_insn, from_luid, to_insn, pnotes: &oldnotes);
14171	}
14172
14173	if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
14174	{
14175	XEXP (note, 1) = *pnotes;
14176	*pnotes = note;
14177	}
14178	else
14179	*pnotes = alloc_reg_note (REG_DEAD, x, *pnotes);
14180	}
14181
14182	return;
14183	}
14184
14185	else if (GET_CODE (x) == SET)
14186	{
14187	rtx dest = SET_DEST (x);
14188
14189	move_deaths (SET_SRC (x), maybe_kill_insn, from_luid, to_insn, pnotes);
14190
14191	/* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
14192	that accesses one word of a multi-word item, some
14193	piece of everything register in the expression is used by
14194	this insn, so remove any old death. */
14195	/* ??? So why do we test for equality of the sizes? */
14196
14197	if (GET_CODE (dest) == ZERO_EXTRACT
14198	|| GET_CODE (dest) == STRICT_LOW_PART
14199	|| (GET_CODE (dest) == SUBREG
14200	&& !read_modify_subreg_p (dest)))
14201	{
14202	move_deaths (x: dest, maybe_kill_insn, from_luid, to_insn, pnotes);
14203	return;
14204	}
14205
14206	/* If this is some other SUBREG, we know it replaces the entire
14207	value, so use that as the destination. */
14208	if (GET_CODE (dest) == SUBREG)
14209	dest = SUBREG_REG (dest);
14210
14211	/* If this is a MEM, adjust deaths of anything used in the address.
14212	For a REG (the only other possibility), the entire value is
14213	being replaced so the old value is not used in this insn. */
14214
14215	if (MEM_P (dest))
14216	move_deaths (XEXP (dest, 0), maybe_kill_insn, from_luid,
14217	to_insn, pnotes);
14218	return;
14219	}
14220
14221	else if (GET_CODE (x) == CLOBBER)
14222	return;
14223
14224	len = GET_RTX_LENGTH (code);
14225	fmt = GET_RTX_FORMAT (code);
14226
14227	for (i = 0; i < len; i++)
14228	{
14229	if (fmt[i] == 'E')
14230	{
14231	int j;
14232	for (j = XVECLEN (x, i) - 1; j >= 0; j--)
14233	move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_luid,
14234	to_insn, pnotes);
14235	}
14236	else if (fmt[i] == 'e')
14237	move_deaths (XEXP (x, i), maybe_kill_insn, from_luid, to_insn, pnotes);
14238	}
14239	}
14240
14241	/* Return true if X is the target of a bit-field assignment in BODY, the
14242	pattern of an insn. X must be a REG. */
14243
14244	static bool
14245	reg_bitfield_target_p (rtx x, rtx body)
14246	{
14247	int i;
14248
14249	if (GET_CODE (body) == SET)
14250	{
14251	rtx dest = SET_DEST (body);
14252	rtx target;
14253	unsigned int regno, tregno, endregno, endtregno;
14254
14255	if (GET_CODE (dest) == ZERO_EXTRACT)
14256	target = XEXP (dest, 0);
14257	else if (GET_CODE (dest) == STRICT_LOW_PART)
14258	target = SUBREG_REG (XEXP (dest, 0));
14259	else
14260	return false;
14261
14262	if (GET_CODE (target) == SUBREG)
14263	target = SUBREG_REG (target);
14264
14265	if (!REG_P (target))
14266	return false;
14267
14268	tregno = REGNO (target), regno = REGNO (x);
14269	if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
14270	return target == x;
14271
14272	endtregno = end_hard_regno (GET_MODE (target), regno: tregno);
14273	endregno = end_hard_regno (GET_MODE (x), regno);
14274
14275	return endregno > tregno && regno < endtregno;
14276	}
14277
14278	else if (GET_CODE (body) == PARALLEL)
14279	for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
14280	if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
14281	return true;
14282
14283	return false;
14284	}
14285
14286	/* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
14287	as appropriate. I3 and I2 are the insns resulting from the combination
14288	insns including FROM (I2 may be zero).
14289
14290	ELIM_I2 and ELIM_I1 are either zero or registers that we know will
14291	not need REG_DEAD notes because they are being substituted for. This
14292	saves searching in the most common cases.
14293
14294	Each note in the list is either ignored or placed on some insns, depending
14295	on the type of note. */
14296
14297	static void
14298	distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
14299	rtx elim_i2, rtx elim_i1, rtx elim_i0)
14300	{
14301	rtx note, next_note;
14302	rtx tem_note;
14303	rtx_insn *tem_insn;
14304
14305	for (note = notes; note; note = next_note)
14306	{
14307	rtx_insn *place = 0, *place2 = 0;
14308
14309	next_note = XEXP (note, 1);
14310	switch (REG_NOTE_KIND (note))
14311	{
14312	case REG_BR_PROB:
14313	case REG_BR_PRED:
14314	/* Doesn't matter much where we put this, as long as it's somewhere.
14315	It is preferable to keep these notes on branches, which is most
14316	likely to be i3. */
14317	place = i3;
14318	break;
14319
14320	case REG_NON_LOCAL_GOTO:
14321	if (JUMP_P (i3))
14322	place = i3;
14323	else
14324	{
14325	gcc_assert (i2 && JUMP_P (i2));
14326	place = i2;
14327	}
14328	break;
14329
14330	case REG_EH_REGION:
14331	{
14332	/* The landing pad handling needs to be kept in sync with the
14333	prerequisite checking in try_combine. */
14334	int lp_nr = INTVAL (XEXP (note, 0));
14335	/* A REG_EH_REGION note transfering control can only ever come
14336	from i3. */
14337	if (lp_nr > 0)
14338	gcc_assert (from_insn == i3);
14339	/* We are making sure there is a single effective REG_EH_REGION
14340	note and it's valid to put it on i3. */
14341	if (!insn_could_throw_p (from_insn)
14342	&& !(lp_nr == INT_MIN && can_nonlocal_goto (from_insn)))
14343	/* Throw away stray notes on insns that can never throw or
14344	make a nonlocal goto. */
14345	;
14346	else
14347	{
14348	if (CALL_P (i3))
14349	place = i3;
14350	else
14351	{
14352	gcc_assert (cfun->can_throw_non_call_exceptions);
14353	/* If i3 can still trap preserve the note, otherwise we've
14354	combined things such that we can now prove that the
14355	instructions can't trap. Drop the note in this case. */
14356	if (may_trap_p (i3))
14357	place = i3;
14358	}
14359	}
14360	break;
14361	}
14362
14363	case REG_ARGS_SIZE:
14364	/* ??? How to distribute between i3-i1. Assume i3 contains the
14365	entire adjustment. Assert i3 contains at least some adjust. */
14366	if (!noop_move_p (i3))
14367	{
14368	poly_int64 old_size, args_size = get_args_size (note);
14369	/* fixup_args_size_notes looks at REG_NORETURN note,
14370	so ensure the note is placed there first. */
14371	if (CALL_P (i3))
14372	{
14373	rtx *np;
14374	for (np = &next_note; *np; np = &XEXP (*np, 1))
14375	if (REG_NOTE_KIND (*np) == REG_NORETURN)
14376	{
14377	rtx n = *np;
14378	*np = XEXP (n, 1);
14379	XEXP (n, 1) = REG_NOTES (i3);
14380	REG_NOTES (i3) = n;
14381	break;
14382	}
14383	}
14384	old_size = fixup_args_size_notes (PREV_INSN (insn: i3), i3, args_size);
14385	/* emit_call_1 adds for !ACCUMULATE_OUTGOING_ARGS
14386	REG_ARGS_SIZE note to all noreturn calls, allow that here. */
14387	gcc_assert (maybe_ne (old_size, args_size)
14388	|| (CALL_P (i3)
14389	&& !ACCUMULATE_OUTGOING_ARGS
14390	&& find_reg_note (i3, REG_NORETURN, NULL_RTX)));
14391	}
14392	break;
14393
14394	case REG_NORETURN:
14395	case REG_SETJMP:
14396	case REG_TM:
14397	case REG_CALL_DECL:
14398	case REG_UNTYPED_CALL:
14399	case REG_CALL_NOCF_CHECK:
14400	/* These notes must remain with the call. It should not be
14401	possible for both I2 and I3 to be a call. */
14402	if (CALL_P (i3))
14403	place = i3;
14404	else
14405	{
14406	gcc_assert (i2 && CALL_P (i2));
14407	place = i2;
14408	}
14409	break;
14410
14411	case REG_UNUSED:
14412	/* Any clobbers for i3 may still exist, and so we must process
14413	REG_UNUSED notes from that insn.
14414
14415	Any clobbers from i2 or i1 can only exist if they were added by
14416	recog_for_combine. In that case, recog_for_combine created the
14417	necessary REG_UNUSED notes. Trying to keep any original
14418	REG_UNUSED notes from these insns can cause incorrect output
14419	if it is for the same register as the original i3 dest.
14420	In that case, we will notice that the register is set in i3,
14421	and then add a REG_UNUSED note for the destination of i3, which
14422	is wrong. However, it is possible to have REG_UNUSED notes from
14423	i2 or i1 for register which were both used and clobbered, so
14424	we keep notes from i2 or i1 if they will turn into REG_DEAD
14425	notes. */
14426
14427	/* If this register is set or clobbered between FROM_INSN and I3,
14428	we should not create a note for it. */
14429	if (reg_set_between_p (XEXP (note, 0), from_insn, i3))
14430	break;
14431
14432	/* If this register is set or clobbered in I3, put the note there
14433	unless there is one already. */
14434	if (reg_set_p (XEXP (note, 0), PATTERN (insn: i3)))
14435	{
14436	if (from_insn != i3)
14437	break;
14438
14439	if (! (REG_P (XEXP (note, 0))
14440	? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
14441	: find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
14442	place = i3;
14443	}
14444	/* Otherwise, if this register is used by I3, then this register
14445	now dies here, so we must put a REG_DEAD note here unless there
14446	is one already. */
14447	else if (reg_referenced_p (XEXP (note, 0), PATTERN (insn: i3))
14448	&& ! (REG_P (XEXP (note, 0))
14449	? find_regno_note (i3, REG_DEAD,
14450	REGNO (XEXP (note, 0)))
14451	: find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
14452	{
14453	PUT_REG_NOTE_KIND (note, REG_DEAD);
14454	place = i3;
14455	}
14456
14457	/* A SET or CLOBBER of the REG_UNUSED reg has been removed,
14458	but we can't tell which at this point. We must reset any
14459	expectations we had about the value that was previously
14460	stored in the reg. ??? Ideally, we'd adjust REG_N_SETS
14461	and, if appropriate, restore its previous value, but we
14462	don't have enough information for that at this point. */
14463	else
14464	{
14465	record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14466
14467	/* Otherwise, if this register is now referenced in i2
14468	then the register used to be modified in one of the
14469	original insns. If it was i3 (say, in an unused
14470	parallel), it's now completely gone, so the note can
14471	be discarded. But if it was modified in i2, i1 or i0
14472	and we still reference it in i2, then we're
14473	referencing the previous value, and since the
14474	register was modified and REG_UNUSED, we know that
14475	the previous value is now dead. So, if we only
14476	reference the register in i2, we change the note to
14477	REG_DEAD, to reflect the previous value. However, if
14478	we're also setting or clobbering the register as
14479	scratch, we know (because the register was not
14480	referenced in i3) that it's unused, just as it was
14481	unused before, and we place the note in i2. */
14482	if (from_insn != i3 && i2 && INSN_P (i2)
14483	&& reg_referenced_p (XEXP (note, 0), PATTERN (insn: i2)))
14484	{
14485	if (!reg_set_p (XEXP (note, 0), PATTERN (insn: i2)))
14486	PUT_REG_NOTE_KIND (note, REG_DEAD);
14487	if (! (REG_P (XEXP (note, 0))
14488	? find_regno_note (i2, REG_NOTE_KIND (note),
14489	REGNO (XEXP (note, 0)))
14490	: find_reg_note (i2, REG_NOTE_KIND (note),
14491	XEXP (note, 0))))
14492	place = i2;
14493	}
14494	}
14495
14496	break;
14497
14498	case REG_EQUAL:
14499	case REG_EQUIV:
14500	case REG_NOALIAS:
14501	/* These notes say something about results of an insn. We can
14502	only support them if they used to be on I3 in which case they
14503	remain on I3. Otherwise they are ignored.
14504
14505	If the note refers to an expression that is not a constant, we
14506	must also ignore the note since we cannot tell whether the
14507	equivalence is still true. It might be possible to do
14508	slightly better than this (we only have a problem if I2DEST
14509	or I1DEST is present in the expression), but it doesn't
14510	seem worth the trouble. */
14511
14512	if (from_insn == i3
14513	&& (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
14514	place = i3;
14515	break;
14516
14517	case REG_INC:
14518	/* These notes say something about how a register is used. They must
14519	be present on any use of the register in I2 or I3. */
14520	if (reg_mentioned_p (XEXP (note, 0), PATTERN (insn: i3)))
14521	place = i3;
14522
14523	if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (insn: i2)))
14524	{
14525	if (place)
14526	place2 = i2;
14527	else
14528	place = i2;
14529	}
14530	break;
14531
14532	case REG_LABEL_TARGET:
14533	case REG_LABEL_OPERAND:
14534	/* This can show up in several ways -- either directly in the
14535	pattern, or hidden off in the constant pool with (or without?)
14536	a REG_EQUAL note. */
14537	/* ??? Ignore the without-reg_equal-note problem for now. */
14538	if (reg_mentioned_p (XEXP (note, 0), PATTERN (insn: i3))
14539	|| ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
14540	&& GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14541	&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
14542	place = i3;
14543
14544	if (i2
14545	&& (reg_mentioned_p (XEXP (note, 0), PATTERN (insn: i2))
14546	|| ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
14547	&& GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
14548	&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
14549	{
14550	if (place)
14551	place2 = i2;
14552	else
14553	place = i2;
14554	}
14555
14556	/* For REG_LABEL_TARGET on a JUMP_P, we prefer to put the note
14557	as a JUMP_LABEL or decrement LABEL_NUSES if it's already
14558	there. */
14559	if (place && JUMP_P (place)
14560	&& REG_NOTE_KIND (note) == REG_LABEL_TARGET
14561	&& (JUMP_LABEL (place) == NULL
14562	|| JUMP_LABEL (place) == XEXP (note, 0)))
14563	{
14564	rtx label = JUMP_LABEL (place);
14565
14566	if (!label)
14567	JUMP_LABEL (place) = XEXP (note, 0);
14568	else if (LABEL_P (label))
14569	LABEL_NUSES (label)--;
14570	}
14571
14572	if (place2 && JUMP_P (place2)
14573	&& REG_NOTE_KIND (note) == REG_LABEL_TARGET
14574	&& (JUMP_LABEL (place2) == NULL
14575	|| JUMP_LABEL (place2) == XEXP (note, 0)))
14576	{
14577	rtx label = JUMP_LABEL (place2);
14578
14579	if (!label)
14580	JUMP_LABEL (place2) = XEXP (note, 0);
14581	else if (LABEL_P (label))
14582	LABEL_NUSES (label)--;
14583	place2 = 0;
14584	}
14585	break;
14586
14587	case REG_NONNEG:
14588	/* This note says something about the value of a register prior
14589	to the execution of an insn. It is too much trouble to see
14590	if the note is still correct in all situations. It is better
14591	to simply delete it. */
14592	break;
14593
14594	case REG_DEAD:
14595	/* If we replaced the right hand side of FROM_INSN with a
14596	REG_EQUAL note, the original use of the dying register
14597	will not have been combined into I3 and I2. In such cases,
14598	FROM_INSN is guaranteed to be the first of the combined
14599	instructions, so we simply need to search back before
14600	FROM_INSN for the previous use or set of this register,
14601	then alter the notes there appropriately.
14602
14603	If the register is used as an input in I3, it dies there.
14604	Similarly for I2, if it is nonzero and adjacent to I3.
14605
14606	If the register is not used as an input in either I3 or I2
14607	and it is not one of the registers we were supposed to eliminate,
14608	there are two possibilities. We might have a non-adjacent I2
14609	or we might have somehow eliminated an additional register
14610	from a computation. For example, we might have had A & B where
14611	we discover that B will always be zero. In this case we will
14612	eliminate the reference to A.
14613
14614	In both cases, we must search to see if we can find a previous
14615	use of A and put the death note there. */
14616
14617	if (from_insn
14618	&& from_insn == i2mod
14619	&& !reg_overlap_mentioned_p (XEXP (note, 0), i2mod_new_rhs))
14620	tem_insn = from_insn;
14621	else
14622	{
14623	if (from_insn
14624	&& CALL_P (from_insn)
14625	&& find_reg_fusage (from_insn, USE, XEXP (note, 0)))
14626	place = from_insn;
14627	else if (i2 && reg_set_p (XEXP (note, 0), PATTERN (insn: i2)))
14628	{
14629	/* If the new I2 sets the same register that is marked
14630	dead in the note, we do not in general know where to
14631	put the note. One important case we _can_ handle is
14632	when the note comes from I3. */
14633	if (from_insn == i3)
14634	place = i3;
14635	else
14636	break;
14637	}
14638	else if (reg_referenced_p (XEXP (note, 0), PATTERN (insn: i3)))
14639	place = i3;
14640	else if (i2 != 0 && next_nonnote_nondebug_insn (i2) == i3
14641	&& reg_referenced_p (XEXP (note, 0), PATTERN (insn: i2)))
14642	place = i2;
14643	else if ((rtx_equal_p (XEXP (note, 0), elim_i2)
14644	&& !(i2mod
14645	&& reg_overlap_mentioned_p (XEXP (note, 0),
14646	i2mod_old_rhs)))
14647	|| rtx_equal_p (XEXP (note, 0), elim_i1)
14648	|| rtx_equal_p (XEXP (note, 0), elim_i0))
14649	break;
14650	tem_insn = i3;
14651	}
14652
14653	if (place == 0)
14654	{
14655	basic_block bb = this_basic_block;
14656
14657	for (tem_insn = PREV_INSN (insn: tem_insn); place == 0; tem_insn = PREV_INSN (insn: tem_insn))
14658	{
14659	if (!NONDEBUG_INSN_P (tem_insn))
14660	{
14661	if (tem_insn == BB_HEAD (bb))
14662	break;
14663	continue;
14664	}
14665
14666	/* If the register is being set at TEM_INSN, see if that is all
14667	TEM_INSN is doing. If so, delete TEM_INSN. Otherwise, make this
14668	into a REG_UNUSED note instead. Don't delete sets to
14669	global register vars. */
14670	if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
14671	|| !global_regs[REGNO (XEXP (note, 0))])
14672	&& reg_set_p (XEXP (note, 0), PATTERN (insn: tem_insn)))
14673	{
14674	rtx set = single_set (insn: tem_insn);
14675	rtx inner_dest = 0;
14676
14677	if (set != 0)
14678	for (inner_dest = SET_DEST (set);
14679	(GET_CODE (inner_dest) == STRICT_LOW_PART
14680	|| GET_CODE (inner_dest) == SUBREG
14681	|| GET_CODE (inner_dest) == ZERO_EXTRACT);
14682	inner_dest = XEXP (inner_dest, 0))
14683	;
14684
14685	/* Verify that it was the set, and not a clobber that
14686	modified the register.
14687
14688	If we cannot delete the setter due to side
14689	effects, mark the user with an UNUSED note instead
14690	of deleting it. */
14691
14692	if (set != 0 && ! side_effects_p (SET_SRC (set))
14693	&& rtx_equal_p (XEXP (note, 0), inner_dest))
14694	{
14695	/* Move the notes and links of TEM_INSN elsewhere.
14696	This might delete other dead insns recursively.
14697	First set the pattern to something that won't use
14698	any register. */
14699	rtx old_notes = REG_NOTES (tem_insn);
14700
14701	PATTERN (insn: tem_insn) = pc_rtx;
14702	REG_NOTES (tem_insn) = NULL;
14703
14704	distribute_notes (notes: old_notes, from_insn: tem_insn, i3: tem_insn, NULL,
14705	NULL_RTX, NULL_RTX, NULL_RTX);
14706	distribute_links (LOG_LINKS (tem_insn));
14707
14708	unsigned int regno = REGNO (XEXP (note, 0));
14709	reg_stat_type *rsp = &reg_stat[regno];
14710	if (rsp->last_set == tem_insn)
14711	record_value_for_reg (XEXP (note, 0), NULL, NULL_RTX);
14712
14713	SET_INSN_DELETED (tem_insn);
14714	if (tem_insn == i2)
14715	i2 = NULL;
14716	}
14717	else
14718	{
14719	PUT_REG_NOTE_KIND (note, REG_UNUSED);
14720
14721	/* If there isn't already a REG_UNUSED note, put one
14722	here. Do not place a REG_DEAD note, even if
14723	the register is also used here; that would not
14724	match the algorithm used in lifetime analysis
14725	and can cause the consistency check in the
14726	scheduler to fail. */
14727	if (! find_regno_note (tem_insn, REG_UNUSED,
14728	REGNO (XEXP (note, 0))))
14729	place = tem_insn;
14730	break;
14731	}
14732	}
14733	else if (reg_referenced_p (XEXP (note, 0), PATTERN (insn: tem_insn))
14734	|| (CALL_P (tem_insn)
14735	&& find_reg_fusage (tem_insn, USE, XEXP (note, 0))))
14736	{
14737	place = tem_insn;
14738
14739	/* If we are doing a 3->2 combination, and we have a
14740	register which formerly died in i3 and was not used
14741	by i2, which now no longer dies in i3 and is used in
14742	i2 but does not die in i2, and place is between i2
14743	and i3, then we may need to move a link from place to
14744	i2. */
14745	if (i2 && DF_INSN_LUID (place) > DF_INSN_LUID (i2)
14746	&& from_insn
14747	&& DF_INSN_LUID (from_insn) > DF_INSN_LUID (i2)
14748	&& reg_referenced_p (XEXP (note, 0), PATTERN (insn: i2)))
14749	{
14750	struct insn_link *links = LOG_LINKS (place);
14751	LOG_LINKS (place) = NULL;
14752	distribute_links (links);
14753	}
14754	break;
14755	}
14756
14757	if (tem_insn == BB_HEAD (bb))
14758	break;
14759	}
14760
14761	}
14762
14763	/* If the register is set or already dead at PLACE, we needn't do
14764	anything with this note if it is still a REG_DEAD note.
14765	We check here if it is set at all, not if is it totally replaced,
14766	which is what `dead_or_set_p' checks, so also check for it being
14767	set partially. */
14768
14769	if (place && REG_NOTE_KIND (note) == REG_DEAD)
14770	{
14771	unsigned int regno = REGNO (XEXP (note, 0));
14772	reg_stat_type *rsp = &reg_stat[regno];
14773
14774	if (dead_or_set_p (place, XEXP (note, 0))
14775	|| reg_bitfield_target_p (XEXP (note, 0), body: PATTERN (insn: place)))
14776	{
14777	/* Unless the register previously died in PLACE, clear
14778	last_death. [I no longer understand why this is
14779	being done.] */
14780	if (rsp->last_death != place)
14781	rsp->last_death = 0;
14782	place = 0;
14783	}
14784	else
14785	rsp->last_death = place;
14786
14787	/* If this is a death note for a hard reg that is occupying
14788	multiple registers, ensure that we are still using all
14789	parts of the object. If we find a piece of the object
14790	that is unused, we must arrange for an appropriate REG_DEAD
14791	note to be added for it. However, we can't just emit a USE
14792	and tag the note to it, since the register might actually
14793	be dead; so we recourse, and the recursive call then finds
14794	the previous insn that used this register. */
14795
14796	if (place && REG_NREGS (XEXP (note, 0)) > 1)
14797	{
14798	unsigned int endregno = END_REGNO (XEXP (note, 0));
14799	bool all_used = true;
14800	unsigned int i;
14801
14802	for (i = regno; i < endregno; i++)
14803	if ((! refers_to_regno_p (regnum: i, x: PATTERN (insn: place))
14804	&& ! find_regno_fusage (place, USE, i))
14805	|| dead_or_set_regno_p (place, i))
14806	{
14807	all_used = false;
14808	break;
14809	}
14810
14811	if (! all_used)
14812	{
14813	/* Put only REG_DEAD notes for pieces that are
14814	not already dead or set. */
14815
14816	for (i = regno; i < endregno;
14817	i += hard_regno_nregs (regno: i, reg_raw_mode[i]))
14818	{
14819	rtx piece = regno_reg_rtx[i];
14820	basic_block bb = this_basic_block;
14821
14822	if (! dead_or_set_p (place, piece)
14823	&& ! reg_bitfield_target_p (x: piece,
14824	body: PATTERN (insn: place)))
14825	{
14826	rtx new_note = alloc_reg_note (REG_DEAD, piece,
14827	NULL_RTX);
14828
14829	distribute_notes (notes: new_note, from_insn: place, i3: place,
14830	NULL, NULL_RTX, NULL_RTX,
14831	NULL_RTX);
14832	}
14833	else if (! refers_to_regno_p (regnum: i, x: PATTERN (insn: place))
14834	&& ! find_regno_fusage (place, USE, i))
14835	for (tem_insn = PREV_INSN (insn: place); ;
14836	tem_insn = PREV_INSN (insn: tem_insn))
14837	{
14838	if (!NONDEBUG_INSN_P (tem_insn))
14839	{
14840	if (tem_insn == BB_HEAD (bb))
14841	break;
14842	continue;
14843	}
14844	if (dead_or_set_p (tem_insn, piece)
14845	|| reg_bitfield_target_p (x: piece,
14846	body: PATTERN (insn: tem_insn)))
14847	{
14848	add_reg_note (tem_insn, REG_UNUSED, piece);
14849	break;
14850	}
14851	}
14852	}
14853
14854	place = 0;
14855	}
14856	}
14857	}
14858	break;
14859
14860	default:
14861	/* Any other notes should not be present at this point in the
14862	compilation. */
14863	gcc_unreachable ();
14864	}
14865
14866	if (place)
14867	{
14868	XEXP (note, 1) = REG_NOTES (place);
14869	REG_NOTES (place) = note;
14870
14871	/* Set added_notes_insn to the earliest insn we added a note to. */
14872	if (added_notes_insn == 0
14873	|| DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place))
14874	added_notes_insn = place;
14875	}
14876
14877	if (place2)
14878	{
14879	add_shallow_copy_of_reg_note (place2, note);
14880
14881	/* Set added_notes_insn to the earliest insn we added a note to. */
14882	if (added_notes_insn == 0
14883	|| DF_INSN_LUID (added_notes_insn) > DF_INSN_LUID (place2))
14884	added_notes_insn = place2;
14885	}
14886	}
14887	}
14888
14889	/* Similarly to above, distribute the LOG_LINKS that used to be present on
14890	I3, I2, and I1 to new locations. This is also called to add a link
14891	pointing at I3 when I3's destination is changed. */
14892
14893	static void
14894	distribute_links (struct insn_link *links)
14895	{
14896	struct insn_link *link, *next_link;
14897
14898	for (link = links; link; link = next_link)
14899	{
14900	rtx_insn *place = 0;
14901	rtx_insn *insn;
14902	rtx set, reg;
14903
14904	next_link = link->next;
14905
14906	/* If the insn that this link points to is a NOTE, ignore it. */
14907	if (NOTE_P (link->insn))
14908	continue;
14909
14910	set = 0;
14911	rtx pat = PATTERN (insn: link->insn);
14912	if (GET_CODE (pat) == SET)
14913	set = pat;
14914	else if (GET_CODE (pat) == PARALLEL)
14915	{
14916	int i;
14917	for (i = 0; i < XVECLEN (pat, 0); i++)
14918	{
14919	set = XVECEXP (pat, 0, i);
14920	if (GET_CODE (set) != SET)
14921	continue;
14922
14923	reg = SET_DEST (set);
14924	while (GET_CODE (reg) == ZERO_EXTRACT
14925	|| GET_CODE (reg) == STRICT_LOW_PART
14926	|| GET_CODE (reg) == SUBREG)
14927	reg = XEXP (reg, 0);
14928
14929	if (!REG_P (reg))
14930	continue;
14931
14932	if (REGNO (reg) == link->regno)
14933	break;
14934	}
14935	if (i == XVECLEN (pat, 0))
14936	continue;
14937	}
14938	else
14939	continue;
14940
14941	reg = SET_DEST (set);
14942
14943	while (GET_CODE (reg) == ZERO_EXTRACT
14944	|| GET_CODE (reg) == STRICT_LOW_PART
14945	|| GET_CODE (reg) == SUBREG)
14946	reg = XEXP (reg, 0);
14947
14948	if (reg == pc_rtx)
14949	continue;
14950
14951	/* A LOG_LINK is defined as being placed on the first insn that uses
14952	a register and points to the insn that sets the register. Start
14953	searching at the next insn after the target of the link and stop
14954	when we reach a set of the register or the end of the basic block.
14955
14956	Note that this correctly handles the link that used to point from
14957	I3 to I2. Also note that not much searching is typically done here
14958	since most links don't point very far away. */
14959
14960	for (insn = NEXT_INSN (insn: link->insn);
14961	(insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun)
14962	|| BB_HEAD (this_basic_block->next_bb) != insn));
14963	insn = NEXT_INSN (insn))
14964	if (DEBUG_INSN_P (insn))
14965	continue;
14966	else if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
14967	{
14968	if (reg_referenced_p (reg, PATTERN (insn)))
14969	place = insn;
14970	break;
14971	}
14972	else if (CALL_P (insn)
14973	&& find_reg_fusage (insn, USE, reg))
14974	{
14975	place = insn;
14976	break;
14977	}
14978	else if (INSN_P (insn) && reg_set_p (reg, insn))
14979	break;
14980
14981	/* If we found a place to put the link, place it there unless there
14982	is already a link to the same insn as LINK at that point. */
14983
14984	if (place)
14985	{
14986	struct insn_link *link2;
14987
14988	FOR_EACH_LOG_LINK (link2, place)
14989	if (link2->insn == link->insn && link2->regno == link->regno)
14990	break;
14991
14992	if (link2 == NULL)
14993	{
14994	link->next = LOG_LINKS (place);
14995	LOG_LINKS (place) = link;
14996
14997	/* Set added_links_insn to the earliest insn we added a
14998	link to. */
14999	if (added_links_insn == 0
15000	|| DF_INSN_LUID (added_links_insn) > DF_INSN_LUID (place))
15001	added_links_insn = place;
15002	}
15003	}
15004	}
15005	}
15006
15007	/* Check for any register or memory mentioned in EQUIV that is not
15008	mentioned in EXPR. This is used to restrict EQUIV to "specializations"
15009	of EXPR where some registers may have been replaced by constants. */
15010
15011	static bool
15012	unmentioned_reg_p (rtx equiv, rtx expr)
15013	{
15014	subrtx_iterator::array_type array;
15015	FOR_EACH_SUBRTX (iter, array, equiv, NONCONST)
15016	{
15017	const_rtx x = *iter;
15018	if ((REG_P (x) || MEM_P (x))
15019	&& !reg_mentioned_p (x, expr))
15020	return true;
15021	}
15022	return false;
15023	}
15024
15025	/* Make pseudo-to-pseudo copies after every hard-reg-to-pseudo-copy, because
15026	the reg-to-reg copy can usefully combine with later instructions, but we
15027	do not want to combine the hard reg into later instructions, for that
15028	restricts register allocation. */
15029	static void
15030	make_more_copies (void)
15031	{
15032	basic_block bb;
15033
15034	FOR_EACH_BB_FN (bb, cfun)
15035	{
15036	rtx_insn *insn;
15037
15038	FOR_BB_INSNS (bb, insn)
15039	{
15040	if (!NONDEBUG_INSN_P (insn))
15041	continue;
15042
15043	rtx set = single_set (insn);
15044	if (!set)
15045	continue;
15046
15047	rtx dest = SET_DEST (set);
15048	if (!(REG_P (dest) && !HARD_REGISTER_P (dest)))
15049	continue;
15050
15051	rtx src = SET_SRC (set);
15052	if (!(REG_P (src) && HARD_REGISTER_P (src)))
15053	continue;
15054	if (TEST_HARD_REG_BIT (fixed_reg_set, REGNO (src)))
15055	continue;
15056
15057	rtx new_reg = gen_reg_rtx (GET_MODE (dest));
15058	rtx_insn *new_insn = gen_move_insn (new_reg, src);
15059	SET_SRC (set) = new_reg;
15060	emit_insn_before (new_insn, insn);
15061	df_insn_rescan (insn);
15062	}
15063	}
15064	}
15065
15066	/* Try combining insns through substitution. */
15067	static void
15068	rest_of_handle_combine (void)
15069	{
15070	make_more_copies ();
15071
15072	df_set_flags (DF_LR_RUN_DCE + DF_DEFER_INSN_RESCAN);
15073	df_note_add_problem ();
15074	df_analyze ();
15075
15076	regstat_init_n_sets_and_refs ();
15077	reg_n_sets_max = max_reg_num ();
15078
15079	bool rebuild_jump_labels_after_combine
15080	= combine_instructions (f: get_insns (), nregs: max_reg_num ());
15081
15082	/* Combining insns may have turned an indirect jump into a
15083	direct jump. Rebuild the JUMP_LABEL fields of jumping
15084	instructions. */
15085	if (rebuild_jump_labels_after_combine)
15086	{
15087	if (dom_info_available_p (CDI_DOMINATORS))
15088	free_dominance_info (CDI_DOMINATORS);
15089	timevar_push (tv: TV_JUMP);
15090	rebuild_jump_labels (get_insns ());
15091	cleanup_cfg (0);
15092	timevar_pop (tv: TV_JUMP);
15093	}
15094
15095	regstat_free_n_sets_and_refs ();
15096	}
15097
15098	namespace {
15099
15100	const pass_data pass_data_combine =
15101	{
15102	.type: RTL_PASS, /* type */
15103	.name: "combine", /* name */
15104	.optinfo_flags: OPTGROUP_NONE, /* optinfo_flags */
15105	.tv_id: TV_COMBINE, /* tv_id */
15106	PROP_cfglayout, /* properties_required */
15107	.properties_provided: 0, /* properties_provided */
15108	.properties_destroyed: 0, /* properties_destroyed */
15109	.todo_flags_start: 0, /* todo_flags_start */
15110	TODO_df_finish, /* todo_flags_finish */
15111	};
15112
15113	class pass_combine : public rtl_opt_pass
15114	{
15115	public:
15116	pass_combine (gcc::context *ctxt)
15117	: rtl_opt_pass (pass_data_combine, ctxt)
15118	{}
15119
15120	/* opt_pass methods: */
15121	bool gate (function *) final override { return (optimize > 0); }
15122	unsigned int execute (function *) final override
15123	{
15124	rest_of_handle_combine ();
15125	return 0;
15126	}
15127
15128	}; // class pass_combine
15129
15130	} // anon namespace
15131
15132	rtl_opt_pass *
15133	make_pass_combine (gcc::context *ctxt)
15134	{
15135	return new pass_combine (ctxt);
15136	}
15137