| 1 | /* Get CPU type and Features for x86 processors. |
| 2 | Copyright (C) 2012-2026 Free Software Foundation, Inc. |
| 3 | Contributed by Sriraman Tallam (tmsriram@google.com) |
| 4 | |
| 5 | This file is part of GCC. |
| 6 | |
| 7 | GCC is free software; you can redistribute it and/or modify it under |
| 8 | the terms of the GNU General Public License as published by the Free |
| 9 | Software Foundation; either version 3, or (at your option) any later |
| 10 | version. |
| 11 | |
| 12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
| 13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
| 15 | for more details. |
| 16 | |
| 17 | Under Section 7 of GPL version 3, you are granted additional |
| 18 | permissions described in the GCC Runtime Library Exception, version |
| 19 | 3.1, as published by the Free Software Foundation. |
| 20 | |
| 21 | You should have received a copy of the GNU General Public License and |
| 22 | a copy of the GCC Runtime Library Exception along with this program; |
| 23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
| 24 | <http://www.gnu.org/licenses/>. */ |
| 25 | |
| 26 | /* Processor Vendor and Models. */ |
| 27 | |
| 28 | enum processor_vendor |
| 29 | { |
| 30 | VENDOR_INTEL = 1, |
| 31 | VENDOR_AMD, |
| 32 | VENDOR_ZHAOXIN, |
| 33 | VENDOR_OTHER, |
| 34 | VENDOR_CENTAUR, |
| 35 | VENDOR_CYRIX, |
| 36 | VENDOR_NSC, |
| 37 | |
| 38 | /* Maximum values must be at the end of this enum. */ |
| 39 | VENDOR_MAX, |
| 40 | BUILTIN_VENDOR_MAX = VENDOR_OTHER |
| 41 | }; |
| 42 | |
| 43 | /* Any new types or subtypes have to be inserted at the end. */ |
| 44 | |
| 45 | enum processor_types |
| 46 | { |
| 47 | INTEL_BONNELL = 1, |
| 48 | INTEL_CORE2, |
| 49 | INTEL_COREI7, |
| 50 | AMDFAM10H, |
| 51 | AMDFAM15H, |
| 52 | INTEL_SILVERMONT, |
| 53 | AMD_BTVER1 = 8, |
| 54 | AMD_BTVER2, |
| 55 | AMDFAM17H, |
| 56 | INTEL_GOLDMONT = 12, |
| 57 | INTEL_GOLDMONT_PLUS, |
| 58 | INTEL_TREMONT, |
| 59 | AMDFAM19H, |
| 60 | ZHAOXIN_FAM7H, |
| 61 | INTEL_SIERRAFOREST, |
| 62 | INTEL_GRANDRIDGE, |
| 63 | INTEL_CLEARWATERFOREST, |
| 64 | AMDFAM1AH, |
| 65 | CPU_TYPE_MAX, |
| 66 | BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX |
| 67 | }; |
| 68 | |
| 69 | enum processor_subtypes |
| 70 | { |
| 71 | INTEL_COREI7_NEHALEM = 1, |
| 72 | INTEL_COREI7_WESTMERE, |
| 73 | INTEL_COREI7_SANDYBRIDGE, |
| 74 | AMDFAM10H_BARCELONA, |
| 75 | AMDFAM10H_SHANGHAI, |
| 76 | AMDFAM10H_ISTANBUL, |
| 77 | AMDFAM15H_BDVER1, |
| 78 | AMDFAM15H_BDVER2, |
| 79 | AMDFAM15H_BDVER3, |
| 80 | AMDFAM15H_BDVER4, |
| 81 | AMDFAM17H_ZNVER1, |
| 82 | INTEL_COREI7_IVYBRIDGE, |
| 83 | INTEL_COREI7_HASWELL, |
| 84 | INTEL_COREI7_BROADWELL, |
| 85 | INTEL_COREI7_SKYLAKE, |
| 86 | INTEL_COREI7_SKYLAKE_AVX512, |
| 87 | INTEL_COREI7_CANNONLAKE, |
| 88 | INTEL_COREI7_ICELAKE_CLIENT, |
| 89 | INTEL_COREI7_ICELAKE_SERVER, |
| 90 | AMDFAM17H_ZNVER2, |
| 91 | INTEL_COREI7_CASCADELAKE, |
| 92 | INTEL_COREI7_TIGERLAKE, |
| 93 | INTEL_COREI7_COOPERLAKE, |
| 94 | INTEL_COREI7_SAPPHIRERAPIDS, |
| 95 | INTEL_COREI7_ALDERLAKE, |
| 96 | AMDFAM19H_ZNVER3, |
| 97 | INTEL_COREI7_ROCKETLAKE, |
| 98 | ZHAOXIN_FAM7H_LUJIAZUI, |
| 99 | AMDFAM19H_ZNVER4, |
| 100 | INTEL_COREI7_GRANITERAPIDS, |
| 101 | INTEL_COREI7_GRANITERAPIDS_D, |
| 102 | INTEL_COREI7_ARROWLAKE, |
| 103 | INTEL_COREI7_ARROWLAKE_S, |
| 104 | INTEL_COREI7_PANTHERLAKE, |
| 105 | ZHAOXIN_FAM7H_YONGFENG, |
| 106 | AMDFAM1AH_ZNVER5, |
| 107 | ZHAOXIN_FAM7H_SHIJIDADAO, |
| 108 | INTEL_COREI7_DIAMONDRAPIDS, |
| 109 | INTEL_COREI7_NOVALAKE, |
| 110 | AMDFAM1AH_ZNVER6, |
| 111 | CPU_SUBTYPE_MAX |
| 112 | }; |
| 113 | |
| 114 | /* Priority of i386 features, greater value is higher priority. This is |
| 115 | used to decide the order in which function dispatch must happen. For |
| 116 | instance, a version specialized for SSE4.2 should be checked for dispatch |
| 117 | before a version for SSE3. */ |
| 118 | enum feature_priority |
| 119 | { |
| 120 | P_NONE = 0, |
| 121 | P_MMX, |
| 122 | P_SSE, |
| 123 | P_SSE2, |
| 124 | P_X86_64_BASELINE, |
| 125 | P_SSE3, |
| 126 | P_SSSE3, |
| 127 | P_PROC_SSSE3, |
| 128 | P_SSE4_A, |
| 129 | P_PROC_SSE4_A, |
| 130 | P_SSE4_1, |
| 131 | P_SSE4_2, |
| 132 | P_PROC_SSE4_2, |
| 133 | P_POPCNT, |
| 134 | P_X86_64_V2, |
| 135 | P_AES, |
| 136 | P_PCLMUL, |
| 137 | P_AVX, |
| 138 | P_PROC_AVX, |
| 139 | P_BMI, |
| 140 | P_PROC_BMI, |
| 141 | P_FMA4, |
| 142 | P_XOP, |
| 143 | P_PROC_XOP, |
| 144 | P_FMA, |
| 145 | P_PROC_FMA, |
| 146 | P_BMI2, |
| 147 | P_AVX2, |
| 148 | P_PROC_AVX2, |
| 149 | P_X86_64_V3, |
| 150 | P_AVX512F, |
| 151 | P_PROC_AVX512F, |
| 152 | P_X86_64_V4, |
| 153 | P_AVX10_1 = 34, |
| 154 | P_PROC_AVX10_1, |
| 155 | P_PROC_DYNAMIC |
| 156 | }; |
| 157 | |
| 158 | /* ISA Features supported. New features have to be inserted at the end. */ |
| 159 | |
| 160 | enum processor_features |
| 161 | { |
| 162 | FEATURE_CMOV = 0, |
| 163 | FEATURE_MMX, |
| 164 | FEATURE_POPCNT, |
| 165 | FEATURE_SSE, |
| 166 | FEATURE_SSE2, |
| 167 | FEATURE_SSE3, |
| 168 | FEATURE_SSSE3, |
| 169 | FEATURE_SSE4_1, |
| 170 | FEATURE_SSE4_2, |
| 171 | FEATURE_AVX, |
| 172 | FEATURE_AVX2, |
| 173 | FEATURE_SSE4_A, |
| 174 | FEATURE_FMA4, |
| 175 | FEATURE_XOP, |
| 176 | FEATURE_FMA, |
| 177 | FEATURE_AVX512F, |
| 178 | FEATURE_BMI, |
| 179 | FEATURE_BMI2, |
| 180 | FEATURE_AES, |
| 181 | FEATURE_PCLMUL, |
| 182 | FEATURE_AVX512VL, |
| 183 | FEATURE_AVX512BW, |
| 184 | FEATURE_AVX512DQ, |
| 185 | FEATURE_AVX512CD, |
| 186 | FEATURE_AVX512VBMI = 26, |
| 187 | FEATURE_AVX512IFMA, |
| 188 | FEATURE_AVX512VPOPCNTDQ = 30, |
| 189 | FEATURE_AVX512VBMI2, |
| 190 | FEATURE_GFNI, |
| 191 | FEATURE_VPCLMULQDQ, |
| 192 | FEATURE_AVX512VNNI, |
| 193 | FEATURE_AVX512BITALG, |
| 194 | FEATURE_AVX512BF16, |
| 195 | FEATURE_AVX512VP2INTERSECT, |
| 196 | FEATURE_3DNOW, |
| 197 | FEATURE_3DNOWP, |
| 198 | FEATURE_ADX, |
| 199 | FEATURE_ABM, |
| 200 | FEATURE_CLDEMOTE, |
| 201 | FEATURE_CLFLUSHOPT, |
| 202 | FEATURE_CLWB, |
| 203 | FEATURE_CLZERO, |
| 204 | FEATURE_CMPXCHG16B, |
| 205 | FEATURE_CMPXCHG8B, |
| 206 | FEATURE_ENQCMD, |
| 207 | FEATURE_F16C, |
| 208 | FEATURE_FSGSBASE, |
| 209 | FEATURE_FXSAVE, |
| 210 | FEATURE_HLE, |
| 211 | FEATURE_IBT, |
| 212 | FEATURE_LAHF_LM, |
| 213 | FEATURE_LM, |
| 214 | FEATURE_LWP, |
| 215 | FEATURE_LZCNT, |
| 216 | FEATURE_MOVBE, |
| 217 | FEATURE_MOVDIR64B, |
| 218 | FEATURE_MOVDIRI, |
| 219 | FEATURE_MWAITX, |
| 220 | FEATURE_OSXSAVE, |
| 221 | FEATURE_PCONFIG, |
| 222 | FEATURE_PKU, |
| 223 | FEATURE_PRFCHW = 66, |
| 224 | FEATURE_PTWRITE, |
| 225 | FEATURE_RDPID, |
| 226 | FEATURE_RDRND, |
| 227 | FEATURE_RDSEED, |
| 228 | FEATURE_RTM, |
| 229 | FEATURE_SERIALIZE, |
| 230 | FEATURE_SGX, |
| 231 | FEATURE_SHA, |
| 232 | FEATURE_SHSTK, |
| 233 | FEATURE_TBM, |
| 234 | FEATURE_TSXLDTRK, |
| 235 | FEATURE_VAES, |
| 236 | FEATURE_WAITPKG, |
| 237 | FEATURE_WBNOINVD, |
| 238 | FEATURE_XSAVE, |
| 239 | FEATURE_XSAVEC, |
| 240 | FEATURE_XSAVEOPT, |
| 241 | FEATURE_XSAVES, |
| 242 | FEATURE_AMX_TILE, |
| 243 | FEATURE_AMX_INT8, |
| 244 | FEATURE_AMX_BF16, |
| 245 | FEATURE_UINTR, |
| 246 | FEATURE_HRESET, |
| 247 | FEATURE_KL, |
| 248 | FEATURE_AESKLE, |
| 249 | FEATURE_WIDEKL, |
| 250 | FEATURE_AVXVNNI, |
| 251 | FEATURE_AVX512FP16, |
| 252 | FEATURE_X86_64_BASELINE, |
| 253 | FEATURE_X86_64_V2, |
| 254 | FEATURE_X86_64_V3, |
| 255 | FEATURE_X86_64_V4, |
| 256 | FEATURE_AVXIFMA, |
| 257 | FEATURE_AVXVNNIINT8, |
| 258 | FEATURE_AVXNECONVERT, |
| 259 | FEATURE_CMPCCXADD, |
| 260 | FEATURE_AMX_FP16, |
| 261 | FEATURE_PREFETCHI, |
| 262 | FEATURE_RAOINT, |
| 263 | FEATURE_AMX_COMPLEX, |
| 264 | FEATURE_AVXVNNIINT16, |
| 265 | FEATURE_SM3, |
| 266 | FEATURE_SHA512, |
| 267 | FEATURE_SM4, |
| 268 | FEATURE_APX_F, |
| 269 | FEATURE_USER_MSR, |
| 270 | FEATURE_AVX10_1 = 114, |
| 271 | FEATURE_AVX10_2 = 116, |
| 272 | FEATURE_AMX_AVX512, |
| 273 | FEATURE_AMX_TF32, |
| 274 | FEATURE_AMX_FP8 = 120, |
| 275 | FEATURE_MOVRS, |
| 276 | FEATURE_AMX_MOVRS, |
| 277 | FEATURE_AVX512BMM, |
| 278 | CPU_FEATURE_MAX |
| 279 | }; |
| 280 | |
| 281 | /* Size of __cpu_features2 array in libgcc/config/i386/cpuinfo.c. */ |
| 282 | #define SIZE_OF_CPU_FEATURES ((CPU_FEATURE_MAX - 1) / 32) |
| 283 | |
| 284 | /* These are the values for vendor types, cpu types and subtypes. Cpu |
| 285 | types and subtypes should be subtracted by the corresponding start |
| 286 | value. */ |
| 287 | |
| 288 | #define M_CPU_TYPE_START (BUILTIN_VENDOR_MAX) |
| 289 | #define M_CPU_SUBTYPE_START \ |
| 290 | (M_CPU_TYPE_START + int (BUILTIN_CPU_TYPE_MAX)) |
| 291 | #define M_VENDOR(a) (a) |
| 292 | #define M_CPU_TYPE(a) (M_CPU_TYPE_START + int (a)) |
| 293 | #define M_CPU_SUBTYPE(a) (M_CPU_SUBTYPE_START + a) |
| 294 | |