1 | /* Get CPU type and Features for x86 processors. |
2 | Copyright (C) 2012-2023 Free Software Foundation, Inc. |
3 | Contributed by Sriraman Tallam (tmsriram@google.com) |
4 | |
5 | This file is part of GCC. |
6 | |
7 | GCC is free software; you can redistribute it and/or modify it under |
8 | the terms of the GNU General Public License as published by the Free |
9 | Software Foundation; either version 3, or (at your option) any later |
10 | version. |
11 | |
12 | GCC is distributed in the hope that it will be useful, but WITHOUT ANY |
13 | WARRANTY; without even the implied warranty of MERCHANTABILITY or |
14 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License |
15 | for more details. |
16 | |
17 | Under Section 7 of GPL version 3, you are granted additional |
18 | permissions described in the GCC Runtime Library Exception, version |
19 | 3.1, as published by the Free Software Foundation. |
20 | |
21 | You should have received a copy of the GNU General Public License and |
22 | a copy of the GCC Runtime Library Exception along with this program; |
23 | see the files COPYING3 and COPYING.RUNTIME respectively. If not, see |
24 | <http://www.gnu.org/licenses/>. */ |
25 | |
26 | /* Processor Vendor and Models. */ |
27 | |
28 | enum processor_vendor |
29 | { |
30 | VENDOR_INTEL = 1, |
31 | VENDOR_AMD, |
32 | VENDOR_ZHAOXIN, |
33 | VENDOR_OTHER, |
34 | VENDOR_CENTAUR, |
35 | VENDOR_CYRIX, |
36 | VENDOR_NSC, |
37 | |
38 | /* Maximum values must be at the end of this enum. */ |
39 | VENDOR_MAX, |
40 | BUILTIN_VENDOR_MAX = VENDOR_OTHER |
41 | }; |
42 | |
43 | /* Any new types or subtypes have to be inserted at the end. */ |
44 | |
45 | enum processor_types |
46 | { |
47 | INTEL_BONNELL = 1, |
48 | INTEL_CORE2, |
49 | INTEL_COREI7, |
50 | AMDFAM10H, |
51 | AMDFAM15H, |
52 | INTEL_SILVERMONT, |
53 | INTEL_KNL, |
54 | AMD_BTVER1, |
55 | AMD_BTVER2, |
56 | AMDFAM17H, |
57 | INTEL_KNM, |
58 | INTEL_GOLDMONT, |
59 | INTEL_GOLDMONT_PLUS, |
60 | INTEL_TREMONT, |
61 | AMDFAM19H, |
62 | ZHAOXIN_FAM7H, |
63 | INTEL_SIERRAFOREST, |
64 | INTEL_GRANDRIDGE, |
65 | INTEL_CLEARWATERFOREST, |
66 | CPU_TYPE_MAX, |
67 | BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX |
68 | }; |
69 | |
70 | enum processor_subtypes |
71 | { |
72 | INTEL_COREI7_NEHALEM = 1, |
73 | INTEL_COREI7_WESTMERE, |
74 | INTEL_COREI7_SANDYBRIDGE, |
75 | AMDFAM10H_BARCELONA, |
76 | AMDFAM10H_SHANGHAI, |
77 | AMDFAM10H_ISTANBUL, |
78 | AMDFAM15H_BDVER1, |
79 | AMDFAM15H_BDVER2, |
80 | AMDFAM15H_BDVER3, |
81 | AMDFAM15H_BDVER4, |
82 | AMDFAM17H_ZNVER1, |
83 | INTEL_COREI7_IVYBRIDGE, |
84 | INTEL_COREI7_HASWELL, |
85 | INTEL_COREI7_BROADWELL, |
86 | INTEL_COREI7_SKYLAKE, |
87 | INTEL_COREI7_SKYLAKE_AVX512, |
88 | INTEL_COREI7_CANNONLAKE, |
89 | INTEL_COREI7_ICELAKE_CLIENT, |
90 | INTEL_COREI7_ICELAKE_SERVER, |
91 | AMDFAM17H_ZNVER2, |
92 | INTEL_COREI7_CASCADELAKE, |
93 | INTEL_COREI7_TIGERLAKE, |
94 | INTEL_COREI7_COOPERLAKE, |
95 | INTEL_COREI7_SAPPHIRERAPIDS, |
96 | INTEL_COREI7_ALDERLAKE, |
97 | AMDFAM19H_ZNVER3, |
98 | INTEL_COREI7_ROCKETLAKE, |
99 | ZHAOXIN_FAM7H_LUJIAZUI, |
100 | AMDFAM19H_ZNVER4, |
101 | INTEL_COREI7_GRANITERAPIDS, |
102 | INTEL_COREI7_GRANITERAPIDS_D, |
103 | INTEL_COREI7_ARROWLAKE, |
104 | INTEL_COREI7_ARROWLAKE_S, |
105 | INTEL_COREI7_PANTHERLAKE, |
106 | ZHAOXIN_FAM7H_YONGFENG, |
107 | CPU_SUBTYPE_MAX |
108 | }; |
109 | |
110 | /* Priority of i386 features, greater value is higher priority. This is |
111 | used to decide the order in which function dispatch must happen. For |
112 | instance, a version specialized for SSE4.2 should be checked for dispatch |
113 | before a version for SSE3, as SSE4.2 implies SSE3. */ |
114 | enum feature_priority |
115 | { |
116 | P_NONE = 0, |
117 | P_MMX, |
118 | P_SSE, |
119 | P_SSE2, |
120 | P_X86_64_BASELINE, |
121 | P_SSE3, |
122 | P_SSSE3, |
123 | P_PROC_SSSE3, |
124 | P_SSE4_A, |
125 | P_PROC_SSE4_A, |
126 | P_SSE4_1, |
127 | P_SSE4_2, |
128 | P_PROC_SSE4_2, |
129 | P_POPCNT, |
130 | P_X86_64_V2, |
131 | P_AES, |
132 | P_PCLMUL, |
133 | P_AVX, |
134 | P_PROC_AVX, |
135 | P_BMI, |
136 | P_PROC_BMI, |
137 | P_FMA4, |
138 | P_XOP, |
139 | P_PROC_XOP, |
140 | P_FMA, |
141 | P_PROC_FMA, |
142 | P_BMI2, |
143 | P_AVX2, |
144 | P_PROC_AVX2, |
145 | P_X86_64_V3, |
146 | P_AVX512F, |
147 | P_PROC_AVX512F, |
148 | P_X86_64_V4, |
149 | P_PROC_DYNAMIC |
150 | }; |
151 | |
152 | /* ISA Features supported. New features have to be inserted at the end. */ |
153 | |
154 | enum processor_features |
155 | { |
156 | FEATURE_CMOV = 0, |
157 | FEATURE_MMX, |
158 | FEATURE_POPCNT, |
159 | FEATURE_SSE, |
160 | FEATURE_SSE2, |
161 | FEATURE_SSE3, |
162 | FEATURE_SSSE3, |
163 | FEATURE_SSE4_1, |
164 | FEATURE_SSE4_2, |
165 | FEATURE_AVX, |
166 | FEATURE_AVX2, |
167 | FEATURE_SSE4_A, |
168 | FEATURE_FMA4, |
169 | FEATURE_XOP, |
170 | FEATURE_FMA, |
171 | FEATURE_AVX512F, |
172 | FEATURE_BMI, |
173 | FEATURE_BMI2, |
174 | FEATURE_AES, |
175 | FEATURE_PCLMUL, |
176 | FEATURE_AVX512VL, |
177 | FEATURE_AVX512BW, |
178 | FEATURE_AVX512DQ, |
179 | FEATURE_AVX512CD, |
180 | FEATURE_AVX512ER, |
181 | FEATURE_AVX512PF, |
182 | FEATURE_AVX512VBMI, |
183 | FEATURE_AVX512IFMA, |
184 | FEATURE_AVX5124VNNIW, |
185 | FEATURE_AVX5124FMAPS, |
186 | FEATURE_AVX512VPOPCNTDQ, |
187 | FEATURE_AVX512VBMI2, |
188 | FEATURE_GFNI, |
189 | FEATURE_VPCLMULQDQ, |
190 | FEATURE_AVX512VNNI, |
191 | FEATURE_AVX512BITALG, |
192 | FEATURE_AVX512BF16, |
193 | FEATURE_AVX512VP2INTERSECT, |
194 | FEATURE_3DNOW, |
195 | FEATURE_3DNOWP, |
196 | FEATURE_ADX, |
197 | FEATURE_ABM, |
198 | FEATURE_CLDEMOTE, |
199 | FEATURE_CLFLUSHOPT, |
200 | FEATURE_CLWB, |
201 | FEATURE_CLZERO, |
202 | FEATURE_CMPXCHG16B, |
203 | FEATURE_CMPXCHG8B, |
204 | FEATURE_ENQCMD, |
205 | FEATURE_F16C, |
206 | FEATURE_FSGSBASE, |
207 | FEATURE_FXSAVE, |
208 | FEATURE_HLE, |
209 | FEATURE_IBT, |
210 | FEATURE_LAHF_LM, |
211 | FEATURE_LM, |
212 | FEATURE_LWP, |
213 | FEATURE_LZCNT, |
214 | FEATURE_MOVBE, |
215 | FEATURE_MOVDIR64B, |
216 | FEATURE_MOVDIRI, |
217 | FEATURE_MWAITX, |
218 | FEATURE_OSXSAVE, |
219 | FEATURE_PCONFIG, |
220 | FEATURE_PKU, |
221 | FEATURE_PREFETCHWT1, |
222 | FEATURE_PRFCHW, |
223 | FEATURE_PTWRITE, |
224 | FEATURE_RDPID, |
225 | FEATURE_RDRND, |
226 | FEATURE_RDSEED, |
227 | FEATURE_RTM, |
228 | FEATURE_SERIALIZE, |
229 | FEATURE_SGX, |
230 | FEATURE_SHA, |
231 | FEATURE_SHSTK, |
232 | FEATURE_TBM, |
233 | FEATURE_TSXLDTRK, |
234 | FEATURE_VAES, |
235 | FEATURE_WAITPKG, |
236 | FEATURE_WBNOINVD, |
237 | FEATURE_XSAVE, |
238 | FEATURE_XSAVEC, |
239 | FEATURE_XSAVEOPT, |
240 | FEATURE_XSAVES, |
241 | FEATURE_AMX_TILE, |
242 | FEATURE_AMX_INT8, |
243 | FEATURE_AMX_BF16, |
244 | FEATURE_UINTR, |
245 | FEATURE_HRESET, |
246 | FEATURE_KL, |
247 | FEATURE_AESKLE, |
248 | FEATURE_WIDEKL, |
249 | FEATURE_AVXVNNI, |
250 | FEATURE_AVX512FP16, |
251 | FEATURE_X86_64_BASELINE, |
252 | FEATURE_X86_64_V2, |
253 | FEATURE_X86_64_V3, |
254 | FEATURE_X86_64_V4, |
255 | FEATURE_AVXIFMA, |
256 | FEATURE_AVXVNNIINT8, |
257 | FEATURE_AVXNECONVERT, |
258 | FEATURE_CMPCCXADD, |
259 | FEATURE_AMX_FP16, |
260 | FEATURE_PREFETCHI, |
261 | FEATURE_RAOINT, |
262 | FEATURE_AMX_COMPLEX, |
263 | FEATURE_AVXVNNIINT16, |
264 | FEATURE_SM3, |
265 | FEATURE_SHA512, |
266 | FEATURE_SM4, |
267 | FEATURE_APX_F, |
268 | FEATURE_USER_MSR, |
269 | CPU_FEATURE_MAX |
270 | }; |
271 | |
272 | /* Size of __cpu_features2 array in libgcc/config/i386/cpuinfo.c. */ |
273 | #define SIZE_OF_CPU_FEATURES ((CPU_FEATURE_MAX - 1) / 32) |
274 | |
275 | /* These are the values for vendor types, cpu types and subtypes. Cpu |
276 | types and subtypes should be subtracted by the corresponding start |
277 | value. */ |
278 | |
279 | #define M_CPU_TYPE_START (BUILTIN_VENDOR_MAX) |
280 | #define M_CPU_SUBTYPE_START \ |
281 | (M_CPU_TYPE_START + BUILTIN_CPU_TYPE_MAX) |
282 | #define M_VENDOR(a) (a) |
283 | #define M_CPU_TYPE(a) (M_CPU_TYPE_START + a) |
284 | #define M_CPU_SUBTYPE(a) (M_CPU_SUBTYPE_START + a) |
285 | |