1/* Definitions of x86 tunable features.
2 Copyright (C) 2013-2026 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify
7it under the terms of the GNU General Public License as published by
8the Free Software Foundation; either version 3, or (at your option)
9any later version.
10
11GCC is distributed in the hope that it will be useful,
12but WITHOUT ANY WARRANTY; without even the implied warranty of
13MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14GNU General Public License for more details.
15
16You should have received a copy of the GNU General Public License and
17a copy of the GCC Runtime Library Exception along with this program;
18see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
19<http://www.gnu.org/licenses/>. */
20
21/* Tuning for a given CPU XXXX consists of:
22 - adding new CPU into:
23 - adding PROCESSOR_XXX to processor_type (in i386.h)
24 - possibly adding XXX into CPU attribute in i386.md
25 - adding XXX to processor_alias_table (in i386.cc)
26 - introducing ix86_XXX_cost in i386.cc
27 - Stringop generation table can be build based on test_stringop
28 - script (once rest of tuning is complete)
29 - designing a scheduler model in
30 - XXXX.md file
31 - Updating ix86_issue_rate and ix86_adjust_cost in i386.md
32 - possibly updating ia32_multipass_dfa_lookahead, ix86_sched_reorder
33 and ix86_sched_init_global if those tricks are needed.
34 - tuning flags below; those are split into sections and each
35 section is very roughly ordered by importance. */
36
37/*****************************************************************************/
38/* Scheduling flags. */
39/*****************************************************************************/
40
41/* X86_TUNE_SCHEDULE: Enable scheduling. */
42DEF_TUNE (X86_TUNE_SCHEDULE, "schedule",
43 m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT
44 | m_INTEL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
45 | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
46 | m_GENERIC)
47
48/* X86_TUNE_PARTIAL_REG_DEPENDENCY: Enable more register renaming
49 on modern chips. Prefer stores affecting whole integer register
50 over partial stores. For example prefer MOVZBL or MOVQ to load 8bit
51 value over movb. */
52DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency",
53 m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2
54 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL
55 | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
56 | m_CORE_ATOM | m_GENERIC)
57
58/* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store
59 destinations to be 128bit to allow register renaming on 128bit SSE units,
60 but usually results in one extra microop on 64bit SSE units.
61 Experimental results shows that disabling this option on P4 brings over 20%
62 SPECfp regression, while enabling it on K8 brings roughly 2.4% regression
63 that can be partly masked by careful scheduling of moves. */
64DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, "sse_partial_reg_dependency",
65 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
66 | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
67 | m_CORE_ATOM | m_GENERIC)
68
69/* X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY: This knob avoids
70 partial write to the destination in scalar SSE conversion from FP
71 to FP. */
72DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY,
73 "sse_partial_reg_fp_converts_dependency",
74 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
75 | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
76 | m_GENERIC)
77
78/* X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY: This knob avoids partial
79 write to the destination in scalar SSE conversion from integer to FP. */
80DEF_TUNE (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY,
81 "sse_partial_reg_converts_dependency",
82 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_AMDFAM10
83 | m_BDVER | m_ZNVER | m_ZHAOXIN | m_CORE_HYBRID | m_CORE_ATOM
84 | m_GENERIC)
85
86/* X86_TUNE_DEST_FALSE_DEP_FOR_GLC: This knob inserts zero-idiom before
87 several insns to break false dependency on the dest register for GLC
88 micro-architecture. */
89DEF_TUNE (X86_TUNE_DEST_FALSE_DEP_FOR_GLC,
90 "dest_false_dep_for_glc", m_SAPPHIRERAPIDS | m_ALDERLAKE)
91
92/* X86_TUNE_SSE_SPLIT_REGS: Set for machines where the type and dependencies
93 are resolved on SSE register parts instead of whole registers, so we may
94 maintain just lower part of scalar values in proper format leaving the
95 upper part undefined. */
96DEF_TUNE (X86_TUNE_SSE_SPLIT_REGS, "sse_split_regs", m_ATHLON_K8)
97
98/* X86_TUNE_PARTIAL_FLAG_REG_STALL: this flag disables use of flags
99 set by instructions affecting just some flags (in particular shifts).
100 This is because Core2 resolves dependencies on whole flags register
101 and such sequences introduce false dependency on previous instruction
102 setting full flags.
103
104 The flags does not affect generation of INC and DEC that is controlled
105 by X86_TUNE_USE_INCDEC. */
106
107DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall",
108 m_CORE2)
109
110/* X86_TUNE_MOVX: Enable to zero extend integer registers to avoid
111 partial dependencies. */
112DEF_TUNE (X86_TUNE_MOVX, "movx",
113 m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
114 | m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_INTEL
115 | m_GOLDMONT_PLUS | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
116 | m_CORE_AVX2 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
117
118/* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by
119 full sized loads. */
120DEF_TUNE (X86_TUNE_MEMORY_MISMATCH_STALL, "memory_mismatch_stall",
121 m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL
122 | m_GOLDMONT | m_GOLDMONT_PLUS | m_AMD_MULTIPLE | m_ZHAOXIN
123 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
124
125/* X86_TUNE_FUSE_CMP_AND_BRANCH_32: Fuse compare with a subsequent
126 conditional jump instruction for 32 bit TARGET. */
127DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_32, "fuse_cmp_and_branch_32",
128 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
129
130/* X86_TUNE_FUSE_CMP_AND_BRANCH_64: Fuse compare with a subsequent
131 conditional jump instruction for TARGET_64BIT. */
132DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_64, "fuse_cmp_and_branch_64",
133 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
134 | m_ZNVER | m_ZHAOXIN | m_GENERIC)
135
136/* X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS: Fuse compare with a
137 subsequent conditional jump instruction when the condition jump
138 check sign flag (SF) or overflow flag (OF). */
139DEF_TUNE (X86_TUNE_FUSE_CMP_AND_BRANCH_SOFLAGS, "fuse_cmp_and_branch_soflags",
140 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_BDVER
141 | m_ZNVER | m_ZHAOXIN | m_GENERIC)
142
143/* X86_TUNE_FUSE_ALU_AND_BRANCH: Fuse alu with a subsequent conditional
144 jump instruction when the alu instruction produces the CCFLAG consumed by
145 the conditional jump instruction.
146
147 TODO: znver5 supports fusing with SUB, ADD, INC, DEC, OR, AND,
148 There is also limitation for immediate and displacement supported. */
149DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH, "fuse_alu_and_branch",
150 m_SANDYBRIDGE | m_CORE_AVX2 | m_ZHAOXIN | m_GENERIC | m_ZNVER3 | m_ZNVER4 | m_ZNVER5
151 | m_ZNVER6)
152
153/* X86_TUNE_FUSE_MOV_AND_ALU: mov and alu in case mov is reg-reg mov
154 and the destination is used by alu. alu must be one of
155 ADD, ADC, AND, XOR, OR, SUB, SBB, INC, DEC, NOT, SAL, SHL, SHR, SAR. */
156DEF_TUNE (X86_TUNE_FUSE_MOV_AND_ALU, "fuse_mov_and_alu",
157 m_ZNVER5 | m_ZNVER6 | m_GRANITERAPIDS | m_GRANITERAPIDS_D)
158
159/* X86_TUNE_FUSE_AND_BRANCH_MEM: Fuse alu with a subsequent conditional
160 jump instruction when alu contains memory operand.
161 TODO: Not suported by TIGERLAKE and COPERLAKE, so m_CORE_AVX2 is wrong. */
162DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM, "fuse_alu_and_branch_mem",
163 m_SANDYBRIDGE | m_CORE_AVX2 | m_ZHAOXIN | m_GENERIC | m_ZNVER3 | m_ZNVER4 | m_ZNVER5)
164
165/* X86_TUNE_FUSE_AND_BRANCH_MEM_IMM: Fuse alu with a subsequent conditional
166 jump instruction when alu contains both immediate and displacement. */
167DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_MEM_IMM, "fuse_alu_and_branch_mem_imm",
168 m_GENERIC | m_ZNVER4 | m_ZNVER5)
169
170/* X86_TUNE_FUSE_AND_BRANCH_RIP_RELATIVE: Fuse alu with a subsequent
171 conditional jump instruction when alu contains IP relative address. */
172DEF_TUNE (X86_TUNE_FUSE_ALU_AND_BRANCH_RIP_RELATIVE,
173 "fuse_alu_and_branch_rip_relative", 0)
174
175/*****************************************************************************/
176/* Function prologue, epilogue and function calling sequences. */
177/*****************************************************************************/
178
179/* X86_TUNE_ACCUMULATE_OUTGOING_ARGS: Allocate stack space for outgoing
180 arguments in prologue/epilogue instead of separately for each call
181 by push/pop instructions.
182 This increase code size by about 5% in 32bit mode, less so in 64bit mode
183 because parameters are passed in registers. It is considerable
184 win for targets without stack engine that prevents multiple push operations
185 to happen in parallel. */
186
187DEF_TUNE (X86_TUNE_ACCUMULATE_OUTGOING_ARGS, "accumulate_outgoing_args",
188 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_INTEL
189 | m_GOLDMONT | m_GOLDMONT_PLUS | m_ATHLON_K8 | m_ZHAOXIN)
190
191/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in prologues that are
192 considered on critical path. */
193DEF_TUNE (X86_TUNE_PROLOGUE_USING_MOVE, "prologue_using_move",
194 m_PPRO | m_ATHLON_K8)
195
196/* X86_TUNE_PROLOGUE_USING_MOVE: Do not use push/pop in epilogues that are
197 considered on critical path. */
198DEF_TUNE (X86_TUNE_EPILOGUE_USING_MOVE, "epilogue_using_move",
199 m_PPRO | m_ATHLON_K8)
200
201/* X86_TUNE_USE_LEAVE: Use "leave" instruction in epilogues where it fits. */
202DEF_TUNE (X86_TUNE_USE_LEAVE, "use_leave",
203 m_386 | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN
204 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
205
206/* X86_TUNE_PUSH_MEMORY: Enable generation of "push mem" instructions.
207 Some chips, like 486 and Pentium works faster with separate load
208 and push instructions. */
209DEF_TUNE (X86_TUNE_PUSH_MEMORY, "push_memory",
210 m_386 | m_P4_NOCONA | m_CORE_ALL | m_K6_GEODE | m_AMD_MULTIPLE
211 | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
212
213/* X86_TUNE_SINGLE_PUSH: Enable if single push insn is preferred
214 over esp subtraction. */
215DEF_TUNE (X86_TUNE_SINGLE_PUSH, "single_push", m_386 | m_486 | m_PENT
216 | m_LAKEMONT | m_K6_GEODE)
217
218/* X86_TUNE_DOUBLE_PUSH. Enable if double push insn is preferred
219 over esp subtraction. */
220DEF_TUNE (X86_TUNE_DOUBLE_PUSH, "double_push", m_PENT | m_LAKEMONT
221 | m_K6_GEODE)
222
223/* X86_TUNE_SINGLE_POP: Enable if single pop insn is preferred
224 over esp addition. */
225DEF_TUNE (X86_TUNE_SINGLE_POP, "single_pop", m_386 | m_486 | m_PENT
226 | m_LAKEMONT | m_PPRO)
227
228/* X86_TUNE_DOUBLE_POP: Enable if double pop insn is preferred
229 over esp addition. */
230DEF_TUNE (X86_TUNE_DOUBLE_POP, "double_pop", m_PENT | m_LAKEMONT)
231
232/*****************************************************************************/
233/* Branch predictor tuning and Front-end tuning */
234/*****************************************************************************/
235
236/* X86_TUNE_PAD_SHORT_FUNCTION: Make every function to be at least 4
237 instructions long. */
238DEF_TUNE (X86_TUNE_PAD_SHORT_FUNCTION, "pad_short_function", m_BONNELL)
239
240/* X86_TUNE_PAD_RETURNS: Place NOP before every RET that is a destination
241 of conditional jump or directly preceded by other jump instruction.
242 This is important for AND K8-AMDFAM10 because the branch prediction
243 architecture expect at most one jump per 2 byte window. Failing to
244 pad returns leads to misaligned return stack. */
245DEF_TUNE (X86_TUNE_PAD_RETURNS, "pad_returns",
246 m_ATHLON_K8 | m_AMDFAM10)
247
248/* X86_TUNE_FOUR_JUMP_LIMIT: Some CPU cores are not able to predict more
249 than 4 branch instructions in the 16 byte window. */
250DEF_TUNE (X86_TUNE_FOUR_JUMP_LIMIT, "four_jump_limit",
251 m_PPRO | m_P4_NOCONA | m_BONNELL | m_SILVERMONT | m_GOLDMONT
252 | m_GOLDMONT_PLUS | m_INTEL | m_ATHLON_K8 | m_AMDFAM10)
253
254/* X86_TUNE_ALIGN_TIGHT_LOOPS: if false, tight loops are not aligned. */
255DEF_TUNE (X86_TUNE_ALIGN_TIGHT_LOOPS, "align_tight_loops",
256 ~(m_ZHAOXIN | m_CASCADELAKE | m_SKYLAKE_AVX512
257 | m_CORE_ATOM))
258
259/*****************************************************************************/
260/* Integer instruction selection tuning */
261/*****************************************************************************/
262
263/* X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL: Enable software prefetching
264 at -O3. For the moment, the prefetching seems badly tuned for Intel
265 chips. */
266DEF_TUNE (X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, "software_prefetching_beneficial",
267 m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER)
268
269/* X86_TUNE_LCP_STALL: Avoid an expensive length-changing prefix stall
270 on 16-bit immediate moves into memory on Core2 and Corei7. */
271DEF_TUNE (X86_TUNE_LCP_STALL, "lcp_stall", m_CORE_ALL | m_ZHAOXIN | m_GENERIC)
272
273/* X86_TUNE_READ_MODIFY: Enable use of read-modify instructions such
274 as "add mem, reg". */
275DEF_TUNE (X86_TUNE_READ_MODIFY, "read_modify", ~(m_PENT | m_LAKEMONT | m_PPRO))
276
277/* X86_TUNE_USE_INCDEC: Enable use of inc/dec instructions.
278
279 Core2 and nehalem has stall of 7 cycles for partial flag register stalls.
280 Sandy bridge and Ivy bridge generate extra uop. On Haswell this extra uop
281 is output only when the values needs to be really merged, which is not
282 done by GCC generated code. */
283DEF_TUNE (X86_TUNE_USE_INCDEC, "use_incdec",
284 ~(m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE
285 | m_BONNELL | m_SILVERMONT | m_INTEL | m_GOLDMONT
286 | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
287 | m_ZHAOXIN | m_GENERIC))
288
289/* X86_TUNE_INTEGER_DFMODE_MOVES: Enable if integer moves are preferred
290 for DFmode copies */
291DEF_TUNE (X86_TUNE_INTEGER_DFMODE_MOVES, "integer_dfmode_moves",
292 ~(m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
293 | m_INTEL | m_GEODE | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
294 | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
295 | m_GENERIC))
296
297/* X86_TUNE_OPT_AGU: Optimize for Address Generation Unit. This flag
298 will impact LEA instruction selection. */
299DEF_TUNE (X86_TUNE_OPT_AGU, "opt_agu", m_BONNELL | m_SILVERMONT | m_GOLDMONT
300 | m_GOLDMONT_PLUS | m_INTEL | m_ZHAOXIN)
301
302/* X86_TUNE_AVOID_LEA_FOR_ADDR: Avoid lea for address computation. */
303DEF_TUNE (X86_TUNE_AVOID_LEA_FOR_ADDR, "avoid_lea_for_addr",
304 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS)
305
306/* X86_TUNE_SLOW_IMUL_IMM32_MEM: Imul of 32-bit constant and memory is
307 vector path on AMD machines.
308 FIXME: Do we need to enable this for core? */
309DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM32_MEM, "slow_imul_imm32_mem",
310 m_K8 | m_AMDFAM10)
311
312/* X86_TUNE_SLOW_IMUL_IMM8: Imul of 8-bit constant is vector path on AMD
313 machines.
314 FIXME: Do we need to enable this for core? */
315DEF_TUNE (X86_TUNE_SLOW_IMUL_IMM8, "slow_imul_imm8",
316 m_K8 | m_AMDFAM10)
317
318/* X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE: Try to avoid memory operands for
319 a conditional move. */
320DEF_TUNE (X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, "avoid_mem_opnd_for_cmove",
321 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
322
323/* X86_TUNE_SINGLE_STRINGOP: Enable use of single string operations, such
324 as MOVS and STOS (without a REP prefix) to move/set sequences of bytes. */
325DEF_TUNE (X86_TUNE_SINGLE_STRINGOP, "single_stringop", m_386 | m_P4_NOCONA)
326
327/* X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB: Enable use of REP MOVSB/STOSB to
328 move/set sequences of bytes with known size. */
329DEF_TUNE (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB,
330 "prefer_known_rep_movsb_stosb",
331 m_SKYLAKE | m_CORE_HYBRID | m_CORE_ATOM | m_TREMONT | m_CORE_AVX512
332 | m_ZHAOXIN)
333
334/* X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES: Enable generation of
335 compact prologues and epilogues by issuing a misaligned moves. This
336 requires target to handle misaligned moves and partial memory stalls
337 reasonably well.
338 FIXME: This may actualy be a win on more targets than listed here. */
339DEF_TUNE (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES,
340 "misaligned_move_string_pro_epilogues",
341 m_386 | m_486 | m_CORE_ALL | m_AMD_MULTIPLE | m_ZHAOXIN | m_TREMONT
342 | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
343
344/* X86_TUNE_USE_SAHF: Controls use of SAHF. */
345DEF_TUNE (X86_TUNE_USE_SAHF, "use_sahf",
346 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
347 | m_INTEL | m_K6_GEODE | m_K8 | m_AMDFAM10 | m_BDVER | m_BTVER
348 | m_ZNVER | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
349 | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
350
351/* X86_TUNE_USE_CLTD: Controls use of CLTD and CTQO instructions. */
352DEF_TUNE (X86_TUNE_USE_CLTD, "use_cltd",
353 ~(m_PENT | m_LAKEMONT | m_BONNELL | m_SILVERMONT | m_INTEL
354 | m_K6 | m_GOLDMONT | m_GOLDMONT_PLUS))
355
356/* X86_TUNE_USE_BT: Enable use of BT (bit test) instructions. */
357DEF_TUNE (X86_TUNE_USE_BT, "use_bt",
358 m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_INTEL | m_LAKEMONT
359 | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT | m_GOLDMONT_PLUS
360 | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
361
362/* X86_TUNE_AVOID_FALSE_DEP_FOR_BMI: Avoid false dependency
363 for bit-manipulation instructions. */
364DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI, "avoid_false_dep_for_bmi",
365 m_SANDYBRIDGE | m_HASWELL | m_SKYLAKE | m_SKYLAKE_AVX512
366 | m_CANNONLAKE | m_CASCADELAKE | m_COOPERLAKE
367 | m_ZHAOXIN | m_GENERIC)
368
369/* X86_TUNE_AVOID_FALSE_DEP_FOR_TZCNT: Avoid false dependency
370 for tzcnt instruction (also included in X86_TUNE_AVOID_FALSE_DEP_FOR_BMI). */
371DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_TZCNT, "avoid_false_dep_for_tzcnt",
372 m_ZNVER5)
373
374/* X86_TUNE_AVOID_FALSE_DEP_FOR_BLS: Avoid false dependency
375 for blsi, blsr and blsmsk instructions. */
376DEF_TUNE (X86_TUNE_AVOID_FALSE_DEP_FOR_BLS, "avoid_false_dep_for_bls",
377 m_ZNVER5)
378
379/* X86_TUNE_ADJUST_UNROLL: This enables adjusting the unroll factor based
380 on hardware capabilities. Bdver3 hardware has a loop buffer which makes
381 unrolling small loop less important. For, such architectures we adjust
382 the unroll factor so that the unrolled loop fits the loop buffer. */
383DEF_TUNE (X86_TUNE_ADJUST_UNROLL, "adjust_unroll_factor", m_BDVER3 | m_BDVER4)
384
385/* X86_TUNE_ONE_IF_CONV_INSNS: Restrict a number of cmov insns in
386 if-converted sequence to one. */
387DEF_TUNE (X86_TUNE_ONE_IF_CONV_INSN, "one_if_conv_insn",
388 m_SILVERMONT | m_HASWELL | m_SKYLAKE | m_GOLDMONT | m_GOLDMONT_PLUS
389 | m_TREMONT | m_ZHAOXIN)
390
391/* X86_TUNE_AVOID_MFENCE: Use lock prefixed instructions instead of mfence. */
392DEF_TUNE (X86_TUNE_AVOID_MFENCE, "avoid_mfence",
393 m_CORE_ALL | m_BDVER | m_ZNVER | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID
394 | m_CORE_ATOM | m_GENERIC)
395
396/* X86_TUNE_EXPAND_ABS: This enables a new abs pattern by
397 generating instructions for abs (x) = (((signed) x >> (W-1) ^ x) -
398 (signed) x >> (W-1)) instead of cmove or SSE max/abs instructions. */
399DEF_TUNE (X86_TUNE_EXPAND_ABS, "expand_abs",
400 m_CORE_ALL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_ZHAOXIN)
401
402/*****************************************************************************/
403/* 387 instruction selection tuning */
404/*****************************************************************************/
405
406/* X86_TUNE_USE_HIMODE_FIOP: Enables use of x87 instructions with 16bit
407 integer operand.
408 FIXME: Why this is disabled for modern chips? */
409DEF_TUNE (X86_TUNE_USE_HIMODE_FIOP, "use_himode_fiop",
410 m_386 | m_486 | m_K6_GEODE)
411
412/* X86_TUNE_USE_SIMODE_FIOP: Enables use of x87 instructions with 32bit
413 integer operand. */
414DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop",
415 ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL
416 | m_SILVERMONT | m_INTEL | m_AMD_MULTIPLE | m_ZHAOXIN | m_GOLDMONT
417 | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
418 | m_GENERIC))
419
420/* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */
421DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_ZHAOXIN)
422
423/* X86_TUNE_EXT_80387_CONSTANTS: Use fancy 80387 constants, such as PI. */
424DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants",
425 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT
426 | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_ZHAOXIN | m_GOLDMONT
427 | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM
428 | m_GENERIC)
429
430/*****************************************************************************/
431/* SSE instruction selection tuning */
432/*****************************************************************************/
433
434/* X86_TUNE_GENERAL_REGS_SSE_SPILL: Try to spill general regs to SSE
435 regs instead of memory. */
436DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill",
437 m_CORE_ALL)
438
439/* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL: Use movups for misaligned loads instead
440 of a sequence loading registers by parts. */
441DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal",
442 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_INTEL
443 | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
444 | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_ZHAOXIN
445 | m_GENERIC)
446
447/* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores
448 instead of a sequence loading registers by parts. */
449DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal",
450 m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT
451 | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
452 | m_CORE_ATOM | m_BDVER | m_ZNVER | m_ZHAOXIN | m_GENERIC)
453
454/* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single
455 precision 128bit instructions instead of double where possible. */
456DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optimal",
457 m_BDVER | m_ZNVER)
458
459/* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */
460DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores",
461 m_AMD_MULTIPLE | m_ZHAOXIN | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID
462 | m_CORE_ATOM | m_GENERIC)
463
464/* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to
465 xorps/xorpd and other variants. */
466DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor",
467 m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER
468 | m_ZHAOXIN | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)
469
470/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer
471 to SSE registers. If disabled, the moves will be done by storing
472 the value to memory and reloading.
473 Enable this flag for generic - the only relevant architecture preferring
474 no inter-unit moves is Buldozer. While this makes small regression on SPECfp
475 scores (sub 0.3%), disabling inter-unit moves penalizes noticeably hand
476 written vectorized code which use i.e. _mm_set_epi16. */
477DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_TO_VEC, "inter_unit_moves_to_vec",
478 ~(m_ATHLON_K8 | m_AMDFAM10 | m_BDVER | m_BTVER))
479
480/* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from SSE
481 to integer registers. If disabled, the moves will be done by storing
482 the value to memory and reloading. */
483DEF_TUNE (X86_TUNE_INTER_UNIT_MOVES_FROM_VEC, "inter_unit_moves_from_vec",
484 ~m_ATHLON_K8)
485
486/* X86_TUNE_INTER_UNIT_CONVERSIONS: Enable float<->integer conversions
487 to use both SSE and integer registers at a same time. */
488DEF_TUNE (X86_TUNE_INTER_UNIT_CONVERSIONS, "inter_unit_conversions",
489 ~(m_AMDFAM10 | m_BDVER))
490
491/* X86_TUNE_PREFER_BCST_FROM_INTEGER: Enable broadcast from integer for
492 128/256/512-bit vector, if disabled, the move will be done by
493 broadcast/load from constant pool
494
495 broadcast from integer:
496 mov $0xa,%eax
497 vmovd %eax,%xmm0
498 vpbroadcastd %xmm0,%xmm0
499
500 broadcast/load from constant pool:
501 vpbroadcastd CST.0(%rip), %xmm0 */
502
503DEF_TUNE (X86_TUNE_PREFER_BCST_FROM_INTEGER, "prefer_bcst_from_integer",
504 m_ALL)
505
506/* X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS: Try to split memory operand for
507 fp converts to destination register. */
508DEF_TUNE (X86_TUNE_SPLIT_MEM_OPND_FOR_FP_CONVERTS, "split_mem_opnd_for_fp_converts",
509 m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
510
511/* X86_TUNE_USE_VECTOR_FP_CONVERTS: Prefer vector packed SSE conversion
512 from FP to FP. This form of instructions avoids partial write to the
513 destination. */
514DEF_TUNE (X86_TUNE_USE_VECTOR_FP_CONVERTS, "use_vector_fp_converts",
515 m_AMDFAM10)
516
517/* X86_TUNE_USE_VECTOR_CONVERTS: Prefer vector packed SSE conversion
518 from integer to FP. */
519DEF_TUNE (X86_TUNE_USE_VECTOR_CONVERTS, "use_vector_converts", m_AMDFAM10)
520
521/* X86_TUNE_SLOW_SHUFB: Indicates tunings with slow pshufb instruction. */
522DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb",
523 m_BONNELL | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_INTEL)
524
525/* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */
526DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes",
527 m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID
528 | m_CORE_ATOM | m_INTEL)
529
530/* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2
531 elements. */
532DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts",
533 ~(m_ZNVER | m_CORE_HYBRID
534 | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
535
536/* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2
537 elements. */
538DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts",
539 ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
540
541/* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4
542 elements. */
543DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts",
544 ~(m_ZNVER | m_CORE_HYBRID
545 | m_YONGFENG | m_SHIJIDADAO | m_CORE_ATOM | m_GENERIC | m_GDS))
546
547/* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4
548 elements. */
549DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts",
550 ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
551
552/* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more
553 elements. */
554DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts",
555 ~(m_ZNVER | m_CORE_HYBRID | m_CORE_ATOM
556 | m_YONGFENG | m_SHIJIDADAO | m_GENERIC | m_GDS))
557
558/* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more
559 elements. */
560DEF_TUNE (X86_TUNE_USE_SCATTER_8PARTS, "use_scatter_8parts",
561 ~(m_ZNVER4 | m_ZNVER5 | m_ZNVER6))
562
563/* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or
564 smaller FMA chain. */
565DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER
566 | m_YONGFENG | m_SHIJIDADAO | m_GENERIC)
567
568/* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or
569 smaller FMA chain. */
570DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains",
571 m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ZNVER5 | m_ZNVER6 | m_CORE_HYBRID
572 | m_SAPPHIRERAPIDS | m_GRANITERAPIDS | m_GRANITERAPIDS_D
573 | m_DIAMONDRAPIDS | m_CORE_ATOM | m_GENERIC)
574
575/* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or
576 smaller FMA chain. */
577DEF_TUNE (X86_TUNE_AVOID_512FMA_CHAINS, "avoid_fma512_chains", m_ZNVER5
578 | m_ZNVER6)
579
580/* X86_TUNE_V2DF_REDUCTION_PREFER_PHADDPD: Prefer haddpd
581 for v2df vector reduction. */
582DEF_TUNE (X86_TUNE_V2DF_REDUCTION_PREFER_HADDPD,
583 "v2df_reduction_prefer_haddpd", m_NONE)
584
585/* X86_TUNE_SSE_MOVCC_USE_BLENDV: Prefer blendv instructions to
586 3-instruction sequence (op1 & mask) | (op2 & ~mask)
587 for vector condition move.
588 For Crestmont, 4-operand vex blendv instructions come from MSROM
589 which is slow. */
590DEF_TUNE (X86_TUNE_SSE_MOVCC_USE_BLENDV,
591 "sse_movcc_use_blendv", ~m_CORE_ATOM)
592
593/* X86_TUNE_V4SI_REDUCTION_PREFER_SHUFD: Prefer pshuf to reduce V16QI,
594 V8HI, V8HI, V4SI, V4FI, V2DI modes when lshr are costlier. */
595DEF_TUNE (X86_TUNE_SSE_REDUCTION_PREFER_PSHUF,
596 "sse_reduction_prefer_pshuf", m_ZNVER4 | m_ZNVER5)
597
598/*****************************************************************************/
599/* AVX instruction selection tuning (some of SSE flags affects AVX, too) */
600/*****************************************************************************/
601
602/* X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL: if false, unaligned loads are
603 split. */
604DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL, "256_unaligned_load_optimal",
605 ~(m_NEHALEM | m_SANDYBRIDGE))
606
607/* X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL: if false, unaligned stores are
608 split. */
609DEF_TUNE (X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL, "256_unaligned_store_optimal",
610 ~(m_NEHALEM | m_SANDYBRIDGE | m_BDVER | m_ZNVER1))
611
612/* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX256 ops are split into two AVX128 ops. */
613DEF_TUNE (X86_TUNE_AVX256_SPLIT_REGS, "avx256_split_regs",m_BDVER | m_BTVER2
614 | m_ZNVER1 | m_CORE_ATOM)
615
616/* X86_TUNE_AVX128_OPTIMAL: Enable 128-bit AVX instruction generation for
617 the auto-vectorizer. */
618DEF_TUNE (X86_TUNE_AVX128_OPTIMAL, "avx128_optimal", m_BDVER | m_BTVER2
619 | m_ZNVER1)
620
621/* X86_TUNE_AVX256_OPTIMAL: Use 256-bit AVX instructions instead of 512-bit AVX
622 instructions in the auto-vectorizer. */
623DEF_TUNE (X86_TUNE_AVX256_OPTIMAL, "avx256_optimal", m_CORE_AVX512 | m_NOVALAKE)
624
625/* X86_TUNE_AVX256_AVOID_VEC_PERM: Avoid using 256-bit cross-lane
626 vector permutation instructions in the auto-vectorizer. */
627DEF_TUNE (X86_TUNE_AVX256_AVOID_VEC_PERM,
628 "avx256_avoid_vec_perm", m_CORE_ATOM)
629
630/* X86_TUNE_AVX256_SPLIT_REGS: if true, AVX512 ops are split into two AVX256 ops. */
631DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4)
632
633/* It's better to align MOVE_MAX with prefer_vector_width to reduce
634 risk of STLF stalls(small store followed by big load.) */
635/* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit
636 AVX instructions. */
637DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces",
638 m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3)
639
640/* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit
641 AVX instructions. */
642DEF_TUNE (X86_TUNE_AVX512_MOVE_BY_PIECES, "avx512_move_by_pieces",
643 m_ZNVER4 | m_ZNVER5 | m_ZNVER6)
644
645/* X86_TUNE_AVX512_TWO_EPILOGUES: Use two vector epilogues for 512-bit
646 vectorized loops. */
647DEF_TUNE (X86_TUNE_AVX512_TWO_EPILOGUES, "avx512_two_epilogues",
648 m_ZNVER4 | m_ZNVER5)
649
650/* X86_TUNE_AVX512_MAKED_EPILOGUES: Use two masked vector epilogues
651 when fit. */
652DEF_TUNE (X86_TUNE_AVX512_MASKED_EPILOGUES, "avx512_masked_epilogues",
653 m_ZNVER4 | m_ZNVER5)
654
655/*****************************************************************************/
656/*****************************************************************************/
657/* Historical relics: tuning flags that helps a specific old CPU designs */
658/*****************************************************************************/
659
660/* X86_TUNE_DOUBLE_WITH_ADD: Use add instead of sal to double value in
661 an integer register. */
662DEF_TUNE (X86_TUNE_DOUBLE_WITH_ADD, "double_with_add", ~m_386)
663
664/* X86_TUNE_ALWAYS_FANCY_MATH_387: controls use of fancy 387 operations,
665 such as fsqrt, fprem, fsin, fcos, fsincos etc.
666 Should be enabled for all targets that always has coprocesor. */
667DEF_TUNE (X86_TUNE_ALWAYS_FANCY_MATH_387, "always_fancy_math_387",
668 ~(m_386 | m_486 | m_LAKEMONT))
669
670/* X86_TUNE_UNROLL_STRLEN: Produce (quite lame) unrolled sequence for
671 inline strlen. This affects only -minline-all-stringops mode. By
672 default we always dispatch to a library since our internal strlen
673 is bad. */
674DEF_TUNE (X86_TUNE_UNROLL_STRLEN, "unroll_strlen", ~m_386)
675
676/* X86_TUNE_SHIFT1: Enables use of short encoding of "sal reg" instead of
677 longer "sal $1, reg". */
678DEF_TUNE (X86_TUNE_SHIFT1, "shift1", ~m_486)
679
680/* X86_TUNE_ZERO_EXTEND_WITH_AND: Use AND instruction instead
681 of mozbl/movwl. */
682DEF_TUNE (X86_TUNE_ZERO_EXTEND_WITH_AND, "zero_extend_with_and",
683 m_486 | m_PENT)
684
685/* X86_TUNE_PROMOTE_HIMODE_IMUL: Modern CPUs have same latency for HImode
686 and SImode multiply, but 386 and 486 do HImode multiply faster. */
687DEF_TUNE (X86_TUNE_PROMOTE_HIMODE_IMUL, "promote_himode_imul",
688 ~(m_386 | m_486))
689
690/* X86_TUNE_FAST_PREFIX: Enable demoting some 32bit or 64bit arithmetic
691 into 16bit/8bit when resulting sequence is shorter. For example
692 for "and $-65536, reg" to 16bit store of 0. */
693DEF_TUNE (X86_TUNE_FAST_PREFIX, "fast_prefix",
694 ~(m_386 | m_486 | m_PENT | m_LAKEMONT))
695
696/* X86_TUNE_READ_MODIFY_WRITE: Enable use of read modify write instructions
697 such as "add $1, mem". */
698DEF_TUNE (X86_TUNE_READ_MODIFY_WRITE, "read_modify_write",
699 ~(m_PENT | m_LAKEMONT))
700
701/* X86_TUNE_MOVE_M1_VIA_OR: On pentiums, it is faster to load -1 via OR
702 than a MOV. */
703DEF_TUNE (X86_TUNE_MOVE_M1_VIA_OR, "move_m1_via_or", m_PENT | m_LAKEMONT)
704
705/* X86_TUNE_NOT_UNPAIRABLE: NOT is not pairable on Pentium, while XOR is,
706 but one byte longer. */
707DEF_TUNE (X86_TUNE_NOT_UNPAIRABLE, "not_unpairable", m_PENT | m_LAKEMONT)
708
709/* X86_TUNE_PARTIAL_REG_STALL: Pentium pro, unlike later chips, handled
710 use of partial registers by renaming. This improved performance of 16bit
711 code where upper halves of registers are not used. It also leads to
712 an penalty whenever a 16bit store is followed by 32bit use. This flag
713 disables production of such sequences in common cases.
714 See also X86_TUNE_HIMODE_MATH.
715
716 In current implementation the partial register stalls are not eliminated
717 very well - they can be introduced via subregs synthesized by combine
718 and can happen in caller/callee saving sequences. */
719DEF_TUNE (X86_TUNE_PARTIAL_REG_STALL, "partial_reg_stall", m_PPRO)
720
721/* X86_TUNE_PARTIAL_MEMORY_READ_STALL: Reading (possible unaligned) part of
722 memory location after a large write to the same address causes
723 store-to-load forwarding stall. */
724DEF_TUNE (X86_TUNE_PARTIAL_MEMORY_READ_STALL, "partial_memory_read_stall",
725 m_386 | m_486 | m_PENT | m_LAKEMONT | m_PPRO | m_P4_NOCONA | m_CORE2
726 | m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT
727 | m_K6_GEODE | m_ATHLON_K8 | m_AMDFAM10)
728
729/* X86_TUNE_PROMOTE_QIMODE: When it is cheap, turn 8bit arithmetic to
730 corresponding 32bit arithmetic. */
731DEF_TUNE (X86_TUNE_PROMOTE_QIMODE, "promote_qimode",
732 ~m_PPRO)
733
734/* X86_TUNE_PROMOTE_HI_REGS: Same, but for 16bit artihmetic. Again we avoid
735 partial register stalls on PentiumPro targets. */
736DEF_TUNE (X86_TUNE_PROMOTE_HI_REGS, "promote_hi_regs", m_PPRO)
737
738/* X86_TUNE_HIMODE_MATH: Enable use of 16bit arithmetic.
739 On PPro this flag is meant to avoid partial register stalls. */
740DEF_TUNE (X86_TUNE_HIMODE_MATH, "himode_math", ~m_PPRO)
741
742/* X86_TUNE_SPLIT_LONG_MOVES: Avoid instructions moving immediates
743 directly to memory. */
744DEF_TUNE (X86_TUNE_SPLIT_LONG_MOVES, "split_long_moves", m_PPRO)
745
746/* X86_TUNE_USE_XCHGB: Use xchgb %rh,%rl instead of rolw/rorw $8,rx. */
747DEF_TUNE (X86_TUNE_USE_XCHGB, "use_xchgb", m_PENT4)
748
749/* X86_TUNE_USE_MOV0: Use "mov $0, reg" instead of "xor reg, reg" to clear
750 integer register. */
751DEF_TUNE (X86_TUNE_USE_MOV0, "use_mov0", m_K6)
752
753/* X86_TUNE_NOT_VECTORMODE: On AMD K6, NOT is vector decoded with memory
754 operand that cannot be represented using a modRM byte. The XOR
755 replacement is long decoded, so this split helps here as well. */
756DEF_TUNE (X86_TUNE_NOT_VECTORMODE, "not_vectormode", m_K6)
757
758/* X86_TUNE_AVOID_VECTOR_DECODE: Enable splitters that avoid vector decoded
759 forms of instructions on K8 targets. */
760DEF_TUNE (X86_TUNE_AVOID_VECTOR_DECODE, "avoid_vector_decode",
761 m_K8)
762
763/* X86_TUNE_BRANCH_PREDICTION_HINTS_TAKEN, starting with the Redwood Cove
764 microarchitecture, if the predictor has no stored information about a branch,
765 the branch has the Intel® SSE2 branch taken hint
766 (i.e., instruction prefix 3EH), When the codec decodes the branch, it flips
767 the branch’s prediction from not-taken to taken. It then flushes the pipeline
768 in front of it and steers this pipeline to fetch the taken path of the
769 branch. */
770DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS_TAKEN, "branch_prediction_hints_taken", m_NONE)
771
772/*****************************************************************************/
773/* This never worked well before. */
774/*****************************************************************************/
775
776/* X86_TUNE_BRANCH_PREDICTION_HINTS_NOT_TAKEN: Branch hints were put in P4 based
777 on simulation result. But after P4 was made, no performance benefit
778 was observed with branch hints. It also increases the code size.
779 As a result, icc never generates branch hints. */
780DEF_TUNE (X86_TUNE_BRANCH_PREDICTION_HINTS_NOT_TAKEN, "branch_prediction_hints_not_taken", m_NONE)
781
782/* X86_TUNE_QIMODE_MATH: Enable use of 8bit arithmetic. */
783DEF_TUNE (X86_TUNE_QIMODE_MATH, "qimode_math", m_ALL)
784
785/* X86_TUNE_PROMOTE_QI_REGS: This enables generic code that promotes all 8bit
786 arithmetic to 32bit via PROMOTE_MODE macro. This code generation scheme
787 is usually used for RISC targets. */
788DEF_TUNE (X86_TUNE_PROMOTE_QI_REGS, "promote_qi_regs", m_NONE)
789
790/* X86_TUNE_SLOW_STC: This disables use of stc, clc and cmc carry flag
791 modifications on architectures where theses operations are slow. */
792DEF_TUNE (X86_TUNE_SLOW_STC, "slow_stc", m_PENT4)
793
794/* X86_TUNE_USE_RCR: Controls use of rcr 1 instruction instead of shrd. */
795DEF_TUNE (X86_TUNE_USE_RCR, "use_rcr", m_AMD_MULTIPLE)
796

source code of gcc/config/i386/x86-tune.def