1/* Local Register Allocator (LRA) intercommunication header file.
2 Copyright (C) 2010-2023 Free Software Foundation, Inc.
3 Contributed by Vladimir Makarov <vmakarov@redhat.com>.
4
5This file is part of GCC.
6
7GCC is free software; you can redistribute it and/or modify it under
8the terms of the GNU General Public License as published by the Free
9Software Foundation; either version 3, or (at your option) any later
10version.
11
12GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13WARRANTY; without even the implied warranty of MERCHANTABILITY or
14FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15for more details.
16
17You should have received a copy of the GNU General Public License
18along with GCC; see the file COPYING3. If not see
19<http://www.gnu.org/licenses/>. */
20
21#ifndef GCC_LRA_INT_H
22#define GCC_LRA_INT_H
23
24#define lra_assert(c) gcc_checking_assert (c)
25
26/* The parameter used to prevent infinite reloading for an insn. Each
27 insn operands might require a reload and, if it is a memory, its
28 base and index registers might require a reload too. */
29#define LRA_MAX_INSN_RELOADS (MAX_RECOG_OPERANDS * 3)
30
31typedef struct lra_live_range *lra_live_range_t;
32
33/* The structure describes program points where a given pseudo lives.
34 The live ranges can be used to find conflicts with other pseudos.
35 If the live ranges of two pseudos are intersected, the pseudos are
36 in conflict. */
37struct lra_live_range
38{
39 /* Pseudo regno whose live range is described by given
40 structure. */
41 int regno;
42 /* Program point range. */
43 int start, finish;
44 /* Next structure describing program points where the pseudo
45 lives. */
46 lra_live_range_t next;
47 /* Pointer to structures with the same start. */
48 lra_live_range_t start_next;
49};
50
51typedef struct lra_copy *lra_copy_t;
52
53/* Copy between pseudos which affects assigning hard registers. */
54struct lra_copy
55{
56 /* True if regno1 is the destination of the copy. */
57 bool regno1_dest_p;
58 /* Execution frequency of the copy. */
59 int freq;
60 /* Pseudos connected by the copy. REGNO1 < REGNO2. */
61 int regno1, regno2;
62 /* Next copy with correspondingly REGNO1 and REGNO2. */
63 lra_copy_t regno1_next, regno2_next;
64};
65
66/* Common info about a register (pseudo or hard register). */
67class lra_reg
68{
69public:
70 /* Bitmap of UIDs of insns (including debug insns) referring the
71 reg. */
72 bitmap_head insn_bitmap;
73 /* The following fields are defined only for pseudos. */
74 /* Hard registers with which the pseudo conflicts. */
75 HARD_REG_SET conflict_hard_regs;
76 /* Pseudo allocno class hard registers which cannot be a start hard register
77 of the pseudo. */
78 HARD_REG_SET exclude_start_hard_regs;
79 /* We assign hard registers to reload pseudos which can occur in few
80 places. So two hard register preferences are enough for them.
81 The following fields define the preferred hard registers. If
82 there are no such hard registers the first field value is
83 negative. If there is only one preferred hard register, the 2nd
84 field is negative. */
85 int preferred_hard_regno1, preferred_hard_regno2;
86 /* Profits to use the corresponding preferred hard registers. If
87 the both hard registers defined, the first hard register has not
88 less profit than the second one. */
89 int preferred_hard_regno_profit1, preferred_hard_regno_profit2;
90#ifdef STACK_REGS
91 /* True if the pseudo should not be assigned to a stack register. */
92 bool no_stack_p;
93#endif
94 /* Number of references and execution frequencies of the register in
95 *non-debug* insns. */
96 int nrefs, freq;
97 int last_reload;
98 /* rtx used to undo the inheritance. It can be non-null only
99 between subsequent inheritance and undo inheritance passes. */
100 rtx restore_rtx;
101 /* Value holding by register. If the pseudos have the same value
102 they do not conflict. */
103 int val;
104 /* Offset from relative eliminate register to pesudo reg. */
105 poly_int64 offset;
106 /* These members are set up in lra-lives.cc and updated in
107 lra-coalesce.cc. */
108 /* The biggest size mode in which each pseudo reg is referred in
109 whole function (possibly via subreg). */
110 machine_mode biggest_mode;
111 /* Live ranges of the pseudo. */
112 lra_live_range_t live_ranges;
113 /* This member is set up in lra-lives.cc for subsequent
114 assignments. */
115 lra_copy_t copies;
116};
117
118/* References to the common info about each register. */
119extern class lra_reg *lra_reg_info;
120
121extern HARD_REG_SET hard_regs_spilled_into;
122
123/* Static info about each insn operand (common for all insns with the
124 same ICODE). Warning: if the structure definition is changed, the
125 initializer for debug_operand_data in lra.cc should be changed
126 too. */
127struct lra_operand_data
128{
129 /* The machine description constraint string of the operand. */
130 const char *constraint;
131 /* Alternatives for which early_clobber can be true. */
132 alternative_mask early_clobber_alts;
133 /* It is taken only from machine description (which is different
134 from recog_data.operand_mode) and can be of VOIDmode. */
135 ENUM_BITFIELD(machine_mode) mode : 16;
136 /* The type of the operand (in/out/inout). */
137 ENUM_BITFIELD (op_type) type : 8;
138 /* Through if accessed through STRICT_LOW. */
139 unsigned int strict_low : 1;
140 /* True if the operand is an operator. */
141 unsigned int is_operator : 1;
142 /* True if the operand is an address. */
143 unsigned int is_address : 1;
144};
145
146/* Info about register occurrence in an insn. */
147struct lra_insn_reg
148{
149 /* Alternatives for which early_clobber can be true. */
150 alternative_mask early_clobber_alts;
151 /* The biggest mode through which the insn refers to the register
152 occurrence (remember the register can be accessed through a
153 subreg in the insn). */
154 ENUM_BITFIELD(machine_mode) biggest_mode : 16;
155 /* The type of the corresponding operand which is the register. */
156 ENUM_BITFIELD (op_type) type : 8;
157 /* True if the reg is accessed through a subreg and the subreg is
158 just a part of the register. */
159 unsigned int subreg_p : 1;
160 /* The corresponding regno of the register. */
161 int regno;
162 /* Next reg info of the same insn. */
163 struct lra_insn_reg *next;
164};
165
166/* Static part (common info for insns with the same ICODE) of LRA
167 internal insn info. It exists in at most one exemplar for each
168 non-negative ICODE. There is only one exception. Each asm insn has
169 own structure. Warning: if the structure definition is changed,
170 the initializer for debug_insn_static_data in lra.cc should be
171 changed too. */
172struct lra_static_insn_data
173{
174 /* Static info about each insn operand. */
175 struct lra_operand_data *operand;
176 /* Each duplication refers to the number of the corresponding
177 operand which is duplicated. */
178 int *dup_num;
179 /* The number of an operand marked as commutative, -1 otherwise. */
180 int commutative;
181 /* Number of operands, duplications, and alternatives of the
182 insn. */
183 char n_operands;
184 char n_dups;
185 char n_alternatives;
186 /* Insns in machine description (or clobbers in asm) may contain
187 explicit hard regs which are not operands. The following list
188 describes such hard registers. */
189 struct lra_insn_reg *hard_regs;
190 /* Array [n_alternatives][n_operand] of static constraint info for
191 given operand in given alternative. This info can be changed if
192 the target reg info is changed. */
193 const struct operand_alternative *operand_alternative;
194};
195
196/* Negative insn alternative numbers used for special cases. */
197#define LRA_UNKNOWN_ALT -1
198#define LRA_NON_CLOBBERED_ALT -2
199
200/* LRA internal info about an insn (LRA internal insn
201 representation). */
202class lra_insn_recog_data
203{
204public:
205 /* The insn code. */
206 int icode;
207 /* The alternative should be used for the insn, LRA_UNKNOWN_ALT if
208 unknown, or we should assume any alternative, or the insn is a
209 debug insn. LRA_NON_CLOBBERED_ALT means ignoring any earlier
210 clobbers for the insn. */
211 int used_insn_alternative;
212 /* Defined for asm insn and it is how many times we already generated reloads
213 for the asm insn. */
214 int asm_reloads_num;
215 /* SP offset before the insn relative to one at the func start. */
216 poly_int64 sp_offset;
217 /* The insn itself. */
218 rtx_insn *insn;
219 /* Common data for insns with the same ICODE. Asm insns (their
220 ICODE is negative) do not share such structures. */
221 struct lra_static_insn_data *insn_static_data;
222 /* Two arrays of size correspondingly equal to the operand and the
223 duplication numbers: */
224 rtx **operand_loc; /* The operand locations, NULL if no operands. */
225 rtx **dup_loc; /* The dup locations, NULL if no dups. */
226 /* Number of hard registers implicitly used/clobbered in given call
227 insn. The value can be NULL or points to array of the hard
228 register numbers ending with a negative value. To differ
229 clobbered and used hard regs, clobbered hard regs are incremented
230 by FIRST_PSEUDO_REGISTER. */
231 int *arg_hard_regs;
232 /* Cached value of get_preferred_alternatives. */
233 alternative_mask preferred_alternatives;
234 /* The following member value is always NULL for a debug insn. */
235 struct lra_insn_reg *regs;
236};
237
238typedef class lra_insn_recog_data *lra_insn_recog_data_t;
239
240/* Whether the clobber is used temporary in LRA. */
241#define LRA_TEMP_CLOBBER_P(x) \
242 (RTL_FLAG_CHECK1 ("TEMP_CLOBBER_P", (x), CLOBBER)->unchanging)
243
244/* Cost factor for each additional reload and maximal cost reject for
245 insn reloads. One might ask about such strange numbers. Their
246 values occurred historically from former reload pass. */
247#define LRA_LOSER_COST_FACTOR 6
248#define LRA_MAX_REJECT 600
249
250/* Maximum allowed number of assignment pass iterations after the
251 latest spill pass when any former reload pseudo was spilled. It is
252 for preventing LRA cycling in a bug case. */
253#define LRA_MAX_ASSIGNMENT_ITERATION_NUMBER 30
254
255/* The maximal number of inheritance/split passes in LRA. It should
256 be more 1 in order to perform caller saves transformations and much
257 less MAX_CONSTRAINT_ITERATION_NUMBER to prevent LRA to do as many
258 as permitted constraint passes in some complicated cases. The
259 first inheritance/split pass has a biggest impact on generated code
260 quality. Each subsequent affects generated code in less degree.
261 For example, the 3rd pass does not change generated SPEC2000 code
262 at all on x86-64. */
263#define LRA_MAX_INHERITANCE_PASSES 2
264
265#if LRA_MAX_INHERITANCE_PASSES <= 0 \
266 || LRA_MAX_INHERITANCE_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
267#error wrong LRA_MAX_INHERITANCE_PASSES value
268#endif
269
270/* Analogous macro to the above one but for rematerialization. */
271#define LRA_MAX_REMATERIALIZATION_PASSES 2
272
273#if LRA_MAX_REMATERIALIZATION_PASSES <= 0 \
274 || LRA_MAX_REMATERIALIZATION_PASSES >= LRA_MAX_ASSIGNMENT_ITERATION_NUMBER - 8
275#error wrong LRA_MAX_REMATERIALIZATION_PASSES value
276#endif
277
278/* lra.cc: */
279
280extern FILE *lra_dump_file;
281
282extern bool lra_hard_reg_split_p;
283extern bool lra_asm_error_p;
284extern bool lra_reg_spill_p;
285
286extern HARD_REG_SET lra_no_alloc_regs;
287
288extern int lra_insn_recog_data_len;
289extern lra_insn_recog_data_t *lra_insn_recog_data;
290
291extern int lra_curr_reload_num;
292
293extern void lra_dump_bitmap_with_title (const char *, bitmap, int);
294extern hashval_t lra_rtx_hash (rtx x);
295extern void lra_push_insn (rtx_insn *);
296extern void lra_push_insn_by_uid (unsigned int);
297extern void lra_push_insn_and_update_insn_regno_info (rtx_insn *);
298extern rtx_insn *lra_pop_insn (void);
299extern unsigned int lra_insn_stack_length (void);
300
301extern rtx lra_create_new_reg (machine_mode, rtx, enum reg_class, HARD_REG_SET *,
302 const char *);
303extern rtx lra_create_new_reg_with_unique_value (machine_mode, rtx,
304 enum reg_class, HARD_REG_SET *,
305 const char *);
306extern void lra_set_regno_unique_value (int);
307extern void lra_invalidate_insn_data (rtx_insn *);
308extern void lra_set_insn_deleted (rtx_insn *);
309extern void lra_delete_dead_insn (rtx_insn *);
310extern void lra_emit_add (rtx, rtx, rtx);
311extern void lra_emit_move (rtx, rtx);
312extern void lra_update_dups (lra_insn_recog_data_t, signed char *);
313extern void lra_asm_insn_error (rtx_insn *insn);
314
315extern void lra_process_new_insns (rtx_insn *, rtx_insn *, rtx_insn *,
316 const char *);
317
318extern bool lra_substitute_pseudo (rtx *, int, rtx, bool, bool);
319extern bool lra_substitute_pseudo_within_insn (rtx_insn *, int, rtx, bool);
320
321extern lra_insn_recog_data_t lra_set_insn_recog_data (rtx_insn *);
322extern lra_insn_recog_data_t lra_update_insn_recog_data (rtx_insn *);
323extern void lra_set_used_insn_alternative (rtx_insn *, int);
324extern void lra_set_used_insn_alternative_by_uid (int, int);
325
326extern void lra_invalidate_insn_regno_info (rtx_insn *);
327extern void lra_update_insn_regno_info (rtx_insn *);
328extern struct lra_insn_reg *lra_get_insn_regs (int);
329
330extern void lra_free_copies (void);
331extern void lra_create_copy (int, int, int);
332extern lra_copy_t lra_get_copy (int);
333
334extern int lra_new_regno_start;
335extern int lra_constraint_new_regno_start;
336extern int lra_bad_spill_regno_start;
337extern rtx lra_pmode_pseudo;
338extern bitmap_head lra_inheritance_pseudos;
339extern bitmap_head lra_split_regs;
340extern bitmap_head lra_subreg_reload_pseudos;
341extern bitmap_head lra_optional_reload_pseudos;
342
343/* lra-constraints.cc: */
344
345extern void lra_init_equiv (void);
346extern int lra_constraint_offset (int, machine_mode);
347
348extern int lra_constraint_iter;
349extern bool check_and_force_assignment_correctness_p;
350extern int lra_inheritance_iter;
351extern int lra_undo_inheritance_iter;
352extern bool lra_constrain_insn (rtx_insn *);
353extern bool lra_constraints (bool);
354extern void lra_constraints_init (void);
355extern void lra_constraints_finish (void);
356extern bool spill_hard_reg_in_range (int, enum reg_class, rtx_insn *, rtx_insn *);
357extern void lra_inheritance (void);
358extern bool lra_undo_inheritance (void);
359
360/* lra-lives.cc: */
361
362extern int lra_live_max_point;
363extern int *lra_point_freq;
364
365extern int lra_hard_reg_usage[FIRST_PSEUDO_REGISTER];
366
367extern int lra_live_range_iter;
368extern void lra_create_live_ranges (bool, bool);
369extern lra_live_range_t lra_copy_live_range_list (lra_live_range_t);
370extern lra_live_range_t lra_merge_live_ranges (lra_live_range_t,
371 lra_live_range_t);
372extern bool lra_intersected_live_ranges_p (lra_live_range_t,
373 lra_live_range_t);
374extern void lra_print_live_range_list (FILE *, lra_live_range_t);
375extern void debug (lra_live_range &ref);
376extern void debug (lra_live_range *ptr);
377extern void lra_debug_live_range_list (lra_live_range_t);
378extern void lra_debug_pseudo_live_ranges (int);
379extern void lra_debug_live_ranges (void);
380extern void lra_clear_live_ranges (void);
381extern void lra_live_ranges_init (void);
382extern void lra_live_ranges_finish (void);
383extern void lra_setup_reload_pseudo_preferenced_hard_reg (int, int, int);
384
385/* lra-assigns.cc: */
386
387extern int lra_assignment_iter;
388extern int lra_assignment_iter_after_spill;
389extern void lra_setup_reg_renumber (int, int, bool);
390extern bool lra_assign (bool &);
391extern bool lra_split_hard_reg_for (void);
392
393/* lra-coalesce.cc: */
394
395extern int lra_coalesce_iter;
396extern bool lra_coalesce (void);
397
398/* lra-spills.cc: */
399
400extern bool lra_need_for_scratch_reg_p (void);
401extern bool lra_need_for_spills_p (void);
402extern void lra_spill (void);
403extern void lra_final_code_change (void);
404
405/* lra-remat.cc: */
406
407extern int lra_rematerialization_iter;
408extern bool lra_remat (void);
409
410/* lra-elimination.c: */
411
412extern void lra_debug_elim_table (void);
413extern int lra_get_elimination_hard_regno (int);
414extern rtx lra_eliminate_regs_1 (rtx_insn *, rtx, machine_mode,
415 bool, bool, poly_int64, bool);
416extern void eliminate_regs_in_insn (rtx_insn *insn, bool, bool, poly_int64);
417extern int lra_update_fp2sp_elimination (int *spilled_pseudos);
418extern void lra_eliminate (bool, bool);
419
420extern poly_int64 lra_update_sp_offset (rtx, poly_int64);
421extern void lra_eliminate_reg_if_possible (rtx *);
422
423
424
425/* Return the hard register which given pseudo REGNO assigned to.
426 Negative value means that the register got memory or we don't know
427 allocation yet. */
428inline int
429lra_get_regno_hard_regno (int regno)
430{
431 resize_reg_info ();
432 return reg_renumber[regno];
433}
434
435/* Change class of pseudo REGNO to NEW_CLASS. Print info about it
436 using TITLE. Output a new line if NL_P. */
437inline void
438lra_change_class (int regno, enum reg_class new_class,
439 const char *title, bool nl_p)
440{
441 lra_assert (regno >= FIRST_PSEUDO_REGISTER);
442 if (lra_dump_file != NULL)
443 fprintf (stream: lra_dump_file, format: "%s class %s for r%d",
444 title, reg_class_names[new_class], regno);
445 setup_reg_classes (regno, new_class, NO_REGS, new_class);
446 if (lra_dump_file != NULL && nl_p)
447 fprintf (stream: lra_dump_file, format: "\n");
448}
449
450/* Update insn operands which are duplication of NOP operand. The
451 insn is represented by its LRA internal representation ID. */
452inline void
453lra_update_dup (lra_insn_recog_data_t id, int nop)
454{
455 int i;
456 struct lra_static_insn_data *static_id = id->insn_static_data;
457
458 for (i = 0; i < static_id->n_dups; i++)
459 if (static_id->dup_num[i] == nop)
460 *id->dup_loc[i] = *id->operand_loc[nop];
461}
462
463/* Process operator duplications in insn with ID. We do it after the
464 operands processing. Generally speaking, we could do this probably
465 simultaneously with operands processing because a common practice
466 is to enumerate the operators after their operands. */
467inline void
468lra_update_operator_dups (lra_insn_recog_data_t id)
469{
470 int i;
471 struct lra_static_insn_data *static_id = id->insn_static_data;
472
473 for (i = 0; i < static_id->n_dups; i++)
474 {
475 int ndup = static_id->dup_num[i];
476
477 if (static_id->operand[ndup].is_operator)
478 *id->dup_loc[i] = *id->operand_loc[ndup];
479 }
480}
481
482/* Return info about INSN. Set up the info if it is not done yet. */
483inline lra_insn_recog_data_t
484lra_get_insn_recog_data (rtx_insn *insn)
485{
486 lra_insn_recog_data_t data;
487 unsigned int uid = INSN_UID (insn);
488
489 if (lra_insn_recog_data_len > (int) uid
490 && (data = lra_insn_recog_data[uid]) != NULL)
491 {
492 /* Check that we did not change insn without updating the insn
493 info. */
494 lra_assert (data->insn == insn
495 && (INSN_CODE (insn) < 0
496 || data->icode == INSN_CODE (insn)));
497 return data;
498 }
499 return lra_set_insn_recog_data (insn);
500}
501
502/* Update offset from pseudos with VAL by INCR. */
503inline void
504lra_update_reg_val_offset (int val, poly_int64 incr)
505{
506 int i;
507
508 for (i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++)
509 {
510 if (lra_reg_info[i].val == val)
511 lra_reg_info[i].offset += incr;
512 }
513}
514
515/* Return true if register content is equal to VAL with OFFSET. */
516inline bool
517lra_reg_val_equal_p (int regno, int val, poly_int64 offset)
518{
519 if (lra_reg_info[regno].val == val
520 && known_eq (lra_reg_info[regno].offset, offset))
521 return true;
522
523 return false;
524}
525
526/* Assign value of register FROM to TO. */
527inline void
528lra_assign_reg_val (int from, int to)
529{
530 lra_reg_info[to].val = lra_reg_info[from].val;
531 lra_reg_info[to].offset = lra_reg_info[from].offset;
532}
533
534#endif /* GCC_LRA_INT_H */
535

source code of gcc/lra-int.h