1/* Analyze RTL for GNU compiler.
2 Copyright (C) 1987-2023 Free Software Foundation, Inc.
3
4This file is part of GCC.
5
6GCC is free software; you can redistribute it and/or modify it under
7the terms of the GNU General Public License as published by the Free
8Software Foundation; either version 3, or (at your option) any later
9version.
10
11GCC is distributed in the hope that it will be useful, but WITHOUT ANY
12WARRANTY; without even the implied warranty of MERCHANTABILITY or
13FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14for more details.
15
16You should have received a copy of the GNU General Public License
17along with GCC; see the file COPYING3. If not see
18<http://www.gnu.org/licenses/>. */
19
20
21#include "config.h"
22#include "system.h"
23#include "coretypes.h"
24#include "backend.h"
25#include "target.h"
26#include "rtl.h"
27#include "rtlanal.h"
28#include "tree.h"
29#include "predict.h"
30#include "df.h"
31#include "memmodel.h"
32#include "tm_p.h"
33#include "insn-config.h"
34#include "regs.h"
35#include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */
36#include "recog.h"
37#include "addresses.h"
38#include "rtl-iter.h"
39#include "hard-reg-set.h"
40#include "function-abi.h"
41
42/* Forward declarations */
43static void set_of_1 (rtx, const_rtx, void *);
44static bool covers_regno_p (const_rtx, unsigned int);
45static bool covers_regno_no_parallel_p (const_rtx, unsigned int);
46static bool computed_jump_p_1 (const_rtx);
47static void parms_set (rtx, const_rtx, void *);
48
49static unsigned HOST_WIDE_INT cached_nonzero_bits (const_rtx, scalar_int_mode,
50 const_rtx, machine_mode,
51 unsigned HOST_WIDE_INT);
52static unsigned HOST_WIDE_INT nonzero_bits1 (const_rtx, scalar_int_mode,
53 const_rtx, machine_mode,
54 unsigned HOST_WIDE_INT);
55static unsigned int cached_num_sign_bit_copies (const_rtx, scalar_int_mode,
56 const_rtx, machine_mode,
57 unsigned int);
58static unsigned int num_sign_bit_copies1 (const_rtx, scalar_int_mode,
59 const_rtx, machine_mode,
60 unsigned int);
61
62rtx_subrtx_bound_info rtx_all_subrtx_bounds[NUM_RTX_CODE];
63rtx_subrtx_bound_info rtx_nonconst_subrtx_bounds[NUM_RTX_CODE];
64
65/* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
66 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
67 SIGN_EXTEND then while narrowing we also have to enforce the
68 representation and sign-extend the value to mode DESTINATION_REP.
69
70 If the value is already sign-extended to DESTINATION_REP mode we
71 can just switch to DESTINATION mode on it. For each pair of
72 integral modes SOURCE and DESTINATION, when truncating from SOURCE
73 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION]
74 contains the number of high-order bits in SOURCE that have to be
75 copies of the sign-bit so that we can do this mode-switch to
76 DESTINATION. */
77
78static unsigned int
79num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1];
80
81/* Store X into index I of ARRAY. ARRAY is known to have at least I
82 elements. Return the new base of ARRAY. */
83
84template <typename T>
85typename T::value_type *
86generic_subrtx_iterator <T>::add_single_to_queue (array_type &array,
87 value_type *base,
88 size_t i, value_type x)
89{
90 if (base == array.stack)
91 {
92 if (i < LOCAL_ELEMS)
93 {
94 base[i] = x;
95 return base;
96 }
97 gcc_checking_assert (i == LOCAL_ELEMS);
98 /* A previous iteration might also have moved from the stack to the
99 heap, in which case the heap array will already be big enough. */
100 if (vec_safe_length (array.heap) <= i)
101 vec_safe_grow (array.heap, i + 1, true);
102 base = array.heap->address ();
103 memcpy (base, array.stack, sizeof (array.stack));
104 base[LOCAL_ELEMS] = x;
105 return base;
106 }
107 unsigned int length = array.heap->length ();
108 if (length > i)
109 {
110 gcc_checking_assert (base == array.heap->address ());
111 base[i] = x;
112 return base;
113 }
114 else
115 {
116 gcc_checking_assert (i == length);
117 vec_safe_push (array.heap, x);
118 return array.heap->address ();
119 }
120}
121
122/* Add the subrtxes of X to worklist ARRAY, starting at END. Return the
123 number of elements added to the worklist. */
124
125template <typename T>
126size_t
127generic_subrtx_iterator <T>::add_subrtxes_to_queue (array_type &array,
128 value_type *base,
129 size_t end, rtx_type x)
130{
131 enum rtx_code code = GET_CODE (x);
132 const char *format = GET_RTX_FORMAT (code);
133 size_t orig_end = end;
134 if (UNLIKELY (INSN_P (x)))
135 {
136 /* Put the pattern at the top of the queue, since that's what
137 we're likely to want most. It also allows for the SEQUENCE
138 code below. */
139 for (int i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; --i)
140 if (format[i] == 'e')
141 {
142 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
143 if (LIKELY (end < LOCAL_ELEMS))
144 base[end++] = subx;
145 else
146 base = add_single_to_queue (array, base, i: end++, x: subx);
147 }
148 }
149 else
150 for (int i = 0; format[i]; ++i)
151 if (format[i] == 'e')
152 {
153 value_type subx = T::get_value (x->u.fld[i].rt_rtx);
154 if (LIKELY (end < LOCAL_ELEMS))
155 base[end++] = subx;
156 else
157 base = add_single_to_queue (array, base, i: end++, x: subx);
158 }
159 else if (format[i] == 'E')
160 {
161 unsigned int length = GET_NUM_ELEM (x->u.fld[i].rt_rtvec);
162 rtx *vec = x->u.fld[i].rt_rtvec->elem;
163 if (LIKELY (end + length <= LOCAL_ELEMS))
164 for (unsigned int j = 0; j < length; j++)
165 base[end++] = T::get_value (vec[j]);
166 else
167 for (unsigned int j = 0; j < length; j++)
168 base = add_single_to_queue (array, base, i: end++,
169 x: T::get_value (vec[j]));
170 if (code == SEQUENCE && end == length)
171 /* If the subrtxes of the sequence fill the entire array then
172 we know that no other parts of a containing insn are queued.
173 The caller is therefore iterating over the sequence as a
174 PATTERN (...), so we also want the patterns of the
175 subinstructions. */
176 for (unsigned int j = 0; j < length; j++)
177 {
178 typename T::rtx_type x = T::get_rtx (base[j]);
179 if (INSN_P (x))
180 base[j] = T::get_value (PATTERN (x));
181 }
182 }
183 return end - orig_end;
184}
185
186template <typename T>
187void
188generic_subrtx_iterator <T>::free_array (array_type &array)
189{
190 vec_free (array.heap);
191}
192
193template <typename T>
194const size_t generic_subrtx_iterator <T>::LOCAL_ELEMS;
195
196template class generic_subrtx_iterator <const_rtx_accessor>;
197template class generic_subrtx_iterator <rtx_var_accessor>;
198template class generic_subrtx_iterator <rtx_ptr_accessor>;
199
200/* Return true if the value of X is unstable
201 (would be different at a different point in the program).
202 The frame pointer, arg pointer, etc. are considered stable
203 (within one function) and so is anything marked `unchanging'. */
204
205bool
206rtx_unstable_p (const_rtx x)
207{
208 const RTX_CODE code = GET_CODE (x);
209 int i;
210 const char *fmt;
211
212 switch (code)
213 {
214 case MEM:
215 return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0));
216
217 case CONST:
218 CASE_CONST_ANY:
219 case SYMBOL_REF:
220 case LABEL_REF:
221 return false;
222
223 case REG:
224 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
225 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
226 /* The arg pointer varies if it is not a fixed register. */
227 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
228 return false;
229 /* ??? When call-clobbered, the value is stable modulo the restore
230 that must happen after a call. This currently screws up local-alloc
231 into believing that the restore is not needed. */
232 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED && x == pic_offset_table_rtx)
233 return false;
234 return true;
235
236 case ASM_OPERANDS:
237 if (MEM_VOLATILE_P (x))
238 return true;
239
240 /* Fall through. */
241
242 default:
243 break;
244 }
245
246 fmt = GET_RTX_FORMAT (code);
247 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
248 if (fmt[i] == 'e')
249 {
250 if (rtx_unstable_p (XEXP (x, i)))
251 return true;
252 }
253 else if (fmt[i] == 'E')
254 {
255 int j;
256 for (j = 0; j < XVECLEN (x, i); j++)
257 if (rtx_unstable_p (XVECEXP (x, i, j)))
258 return true;
259 }
260
261 return false;
262}
263
264/* Return true if X has a value that can vary even between two
265 executions of the program. false means X can be compared reliably
266 against certain constants or near-constants.
267 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
268 zero, we are slightly more conservative.
269 The frame pointer and the arg pointer are considered constant. */
270
271bool
272rtx_varies_p (const_rtx x, bool for_alias)
273{
274 RTX_CODE code;
275 int i;
276 const char *fmt;
277
278 if (!x)
279 return false;
280
281 code = GET_CODE (x);
282 switch (code)
283 {
284 case MEM:
285 return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias);
286
287 case CONST:
288 CASE_CONST_ANY:
289 case SYMBOL_REF:
290 case LABEL_REF:
291 return false;
292
293 case REG:
294 /* Note that we have to test for the actual rtx used for the frame
295 and arg pointers and not just the register number in case we have
296 eliminated the frame and/or arg pointer and are using it
297 for pseudos. */
298 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
299 /* The arg pointer varies if it is not a fixed register. */
300 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
301 return false;
302 if (x == pic_offset_table_rtx
303 /* ??? When call-clobbered, the value is stable modulo the restore
304 that must happen after a call. This currently screws up
305 local-alloc into believing that the restore is not needed, so we
306 must return 0 only if we are called from alias analysis. */
307 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED || for_alias))
308 return false;
309 return true;
310
311 case LO_SUM:
312 /* The operand 0 of a LO_SUM is considered constant
313 (in fact it is related specifically to operand 1)
314 during alias analysis. */
315 return (! for_alias && rtx_varies_p (XEXP (x, 0), for_alias))
316 || rtx_varies_p (XEXP (x, 1), for_alias);
317
318 case ASM_OPERANDS:
319 if (MEM_VOLATILE_P (x))
320 return true;
321
322 /* Fall through. */
323
324 default:
325 break;
326 }
327
328 fmt = GET_RTX_FORMAT (code);
329 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
330 if (fmt[i] == 'e')
331 {
332 if (rtx_varies_p (XEXP (x, i), for_alias))
333 return true;
334 }
335 else if (fmt[i] == 'E')
336 {
337 int j;
338 for (j = 0; j < XVECLEN (x, i); j++)
339 if (rtx_varies_p (XVECEXP (x, i, j), for_alias))
340 return true;
341 }
342
343 return false;
344}
345
346/* Compute an approximation for the offset between the register
347 FROM and TO for the current function, as it was at the start
348 of the routine. */
349
350static poly_int64
351get_initial_register_offset (int from, int to)
352{
353 static const struct elim_table_t
354 {
355 const int from;
356 const int to;
357 } table[] = ELIMINABLE_REGS;
358 poly_int64 offset1, offset2;
359 unsigned int i, j;
360
361 if (to == from)
362 return 0;
363
364 /* It is not safe to call INITIAL_ELIMINATION_OFFSET before the epilogue
365 is completed, but we need to give at least an estimate for the stack
366 pointer based on the frame size. */
367 if (!epilogue_completed)
368 {
369 offset1 = crtl->outgoing_args_size + get_frame_size ();
370#if !STACK_GROWS_DOWNWARD
371 offset1 = - offset1;
372#endif
373 if (to == STACK_POINTER_REGNUM)
374 return offset1;
375 else if (from == STACK_POINTER_REGNUM)
376 return - offset1;
377 else
378 return 0;
379 }
380
381 for (i = 0; i < ARRAY_SIZE (table); i++)
382 if (table[i].from == from)
383 {
384 if (table[i].to == to)
385 {
386 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
387 offset1);
388 return offset1;
389 }
390 for (j = 0; j < ARRAY_SIZE (table); j++)
391 {
392 if (table[j].to == to
393 && table[j].from == table[i].to)
394 {
395 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
396 offset1);
397 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,
398 offset2);
399 return offset1 + offset2;
400 }
401 if (table[j].from == to
402 && table[j].to == table[i].to)
403 {
404 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
405 offset1);
406 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,
407 offset2);
408 return offset1 - offset2;
409 }
410 }
411 }
412 else if (table[i].to == from)
413 {
414 if (table[i].from == to)
415 {
416 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
417 offset1);
418 return - offset1;
419 }
420 for (j = 0; j < ARRAY_SIZE (table); j++)
421 {
422 if (table[j].to == to
423 && table[j].from == table[i].from)
424 {
425 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
426 offset1);
427 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,
428 offset2);
429 return - offset1 + offset2;
430 }
431 if (table[j].from == to
432 && table[j].to == table[i].from)
433 {
434 INITIAL_ELIMINATION_OFFSET (table[i].from, table[i].to,
435 offset1);
436 INITIAL_ELIMINATION_OFFSET (table[j].from, table[j].to,
437 offset2);
438 return - offset1 - offset2;
439 }
440 }
441 }
442
443 /* If the requested register combination was not found,
444 try a different more simple combination. */
445 if (from == ARG_POINTER_REGNUM)
446 return get_initial_register_offset (HARD_FRAME_POINTER_REGNUM, to);
447 else if (to == ARG_POINTER_REGNUM)
448 return get_initial_register_offset (from, HARD_FRAME_POINTER_REGNUM);
449 else if (from == HARD_FRAME_POINTER_REGNUM)
450 return get_initial_register_offset (FRAME_POINTER_REGNUM, to);
451 else if (to == HARD_FRAME_POINTER_REGNUM)
452 return get_initial_register_offset (from, FRAME_POINTER_REGNUM);
453 else
454 return 0;
455}
456
457/* Return true if the use of X+OFFSET as an address in a MEM with SIZE
458 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and
459 UNALIGNED_MEMS controls whether true is returned for unaligned memory
460 references on strict alignment machines. */
461
462static bool
463rtx_addr_can_trap_p_1 (const_rtx x, poly_int64 offset, poly_int64 size,
464 machine_mode mode, bool unaligned_mems)
465{
466 enum rtx_code code = GET_CODE (x);
467 gcc_checking_assert (mode == BLKmode
468 || mode == VOIDmode
469 || known_size_p (size));
470 poly_int64 const_x1;
471
472 /* The offset must be a multiple of the mode size if we are considering
473 unaligned memory references on strict alignment machines. */
474 if (STRICT_ALIGNMENT
475 && unaligned_mems
476 && mode != BLKmode
477 && mode != VOIDmode)
478 {
479 poly_int64 actual_offset = offset;
480
481#ifdef SPARC_STACK_BOUNDARY_HACK
482 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than
483 the real alignment of %sp. However, when it does this, the
484 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */
485 if (SPARC_STACK_BOUNDARY_HACK
486 && (x == stack_pointer_rtx || x == hard_frame_pointer_rtx))
487 actual_offset -= STACK_POINTER_OFFSET;
488#endif
489
490 if (!multiple_p (a: actual_offset, b: GET_MODE_SIZE (mode)))
491 return true;
492 }
493
494 switch (code)
495 {
496 case SYMBOL_REF:
497 if (SYMBOL_REF_WEAK (x))
498 return true;
499 if (!CONSTANT_POOL_ADDRESS_P (x) && !SYMBOL_REF_FUNCTION_P (x))
500 {
501 tree decl;
502 poly_int64 decl_size;
503
504 if (maybe_lt (a: offset, b: 0))
505 return true;
506 if (!known_size_p (a: size))
507 return maybe_ne (a: offset, b: 0);
508
509 /* If the size of the access or of the symbol is unknown,
510 assume the worst. */
511 decl = SYMBOL_REF_DECL (x);
512
513 /* Else check that the access is in bounds. TODO: restructure
514 expr_size/tree_expr_size/int_expr_size and just use the latter. */
515 if (!decl)
516 decl_size = -1;
517 else if (DECL_P (decl) && DECL_SIZE_UNIT (decl))
518 {
519 if (!poly_int_tree_p (DECL_SIZE_UNIT (decl), value: &decl_size))
520 decl_size = -1;
521 }
522 else if (TREE_CODE (decl) == STRING_CST)
523 decl_size = TREE_STRING_LENGTH (decl);
524 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl)))
525 decl_size = int_size_in_bytes (TREE_TYPE (decl));
526 else
527 decl_size = -1;
528
529 return (!known_size_p (a: decl_size) || known_eq (decl_size, 0)
530 ? maybe_ne (a: offset, b: 0)
531 : !known_subrange_p (pos1: offset, size1: size, pos2: 0, size2: decl_size));
532 }
533
534 return false;
535
536 case LABEL_REF:
537 return false;
538
539 case REG:
540 /* Stack references are assumed not to trap, but we need to deal with
541 nonsensical offsets. */
542 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
543 || x == stack_pointer_rtx
544 /* The arg pointer varies if it is not a fixed register. */
545 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
546 {
547#ifdef RED_ZONE_SIZE
548 poly_int64 red_zone_size = RED_ZONE_SIZE;
549#else
550 poly_int64 red_zone_size = 0;
551#endif
552 poly_int64 stack_boundary = PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT;
553 poly_int64 low_bound, high_bound;
554
555 if (!known_size_p (a: size))
556 return true;
557
558 if (x == frame_pointer_rtx)
559 {
560 if (FRAME_GROWS_DOWNWARD)
561 {
562 high_bound = targetm.starting_frame_offset ();
563 low_bound = high_bound - get_frame_size ();
564 }
565 else
566 {
567 low_bound = targetm.starting_frame_offset ();
568 high_bound = low_bound + get_frame_size ();
569 }
570 }
571 else if (x == hard_frame_pointer_rtx)
572 {
573 poly_int64 sp_offset
574 = get_initial_register_offset (STACK_POINTER_REGNUM,
575 HARD_FRAME_POINTER_REGNUM);
576 poly_int64 ap_offset
577 = get_initial_register_offset (ARG_POINTER_REGNUM,
578 HARD_FRAME_POINTER_REGNUM);
579
580#if STACK_GROWS_DOWNWARD
581 low_bound = sp_offset - red_zone_size - stack_boundary;
582 high_bound = ap_offset
583 + FIRST_PARM_OFFSET (current_function_decl)
584#if !ARGS_GROW_DOWNWARD
585 + crtl->args.size
586#endif
587 + stack_boundary;
588#else
589 high_bound = sp_offset + red_zone_size + stack_boundary;
590 low_bound = ap_offset
591 + FIRST_PARM_OFFSET (current_function_decl)
592#if ARGS_GROW_DOWNWARD
593 - crtl->args.size
594#endif
595 - stack_boundary;
596#endif
597 }
598 else if (x == stack_pointer_rtx)
599 {
600 poly_int64 ap_offset
601 = get_initial_register_offset (ARG_POINTER_REGNUM,
602 STACK_POINTER_REGNUM);
603
604#if STACK_GROWS_DOWNWARD
605 low_bound = - red_zone_size - stack_boundary;
606 high_bound = ap_offset
607 + FIRST_PARM_OFFSET (current_function_decl)
608#if !ARGS_GROW_DOWNWARD
609 + crtl->args.size
610#endif
611 + stack_boundary;
612#else
613 high_bound = red_zone_size + stack_boundary;
614 low_bound = ap_offset
615 + FIRST_PARM_OFFSET (current_function_decl)
616#if ARGS_GROW_DOWNWARD
617 - crtl->args.size
618#endif
619 - stack_boundary;
620#endif
621 }
622 else
623 {
624 /* We assume that accesses are safe to at least the
625 next stack boundary.
626 Examples are varargs and __builtin_return_address. */
627#if ARGS_GROW_DOWNWARD
628 high_bound = FIRST_PARM_OFFSET (current_function_decl)
629 + stack_boundary;
630 low_bound = FIRST_PARM_OFFSET (current_function_decl)
631 - crtl->args.size - stack_boundary;
632#else
633 low_bound = FIRST_PARM_OFFSET (current_function_decl)
634 - stack_boundary;
635 high_bound = FIRST_PARM_OFFSET (current_function_decl)
636 + crtl->args.size + stack_boundary;
637#endif
638 }
639
640 if (known_ge (offset, low_bound)
641 && known_le (offset, high_bound - size))
642 return false;
643 return true;
644 }
645 /* All of the virtual frame registers are stack references. */
646 if (VIRTUAL_REGISTER_P (x))
647 return false;
648 return true;
649
650 case CONST:
651 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size,
652 mode, unaligned_mems);
653
654 case PLUS:
655 /* An address is assumed not to trap if:
656 - it is the pic register plus a const unspec without offset. */
657 if (XEXP (x, 0) == pic_offset_table_rtx
658 && GET_CODE (XEXP (x, 1)) == CONST
659 && GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
660 && known_eq (offset, 0))
661 return false;
662
663 /* - or it is an address that can't trap plus a constant integer. */
664 if (poly_int_rtx_p (XEXP (x, 1), res: &const_x1)
665 && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset: offset + const_x1,
666 size, mode, unaligned_mems))
667 return false;
668
669 return true;
670
671 case LO_SUM:
672 case PRE_MODIFY:
673 return rtx_addr_can_trap_p_1 (XEXP (x, 1), offset, size,
674 mode, unaligned_mems);
675
676 case PRE_DEC:
677 case PRE_INC:
678 case POST_DEC:
679 case POST_INC:
680 case POST_MODIFY:
681 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size,
682 mode, unaligned_mems);
683
684 default:
685 break;
686 }
687
688 /* If it isn't one of the case above, it can cause a trap. */
689 return true;
690}
691
692/* Return true if the use of X as an address in a MEM can cause a trap. */
693
694bool
695rtx_addr_can_trap_p (const_rtx x)
696{
697 return rtx_addr_can_trap_p_1 (x, offset: 0, size: -1, BLKmode, unaligned_mems: false);
698}
699
700/* Return true if X contains a MEM subrtx. */
701
702bool
703contains_mem_rtx_p (rtx x)
704{
705 subrtx_iterator::array_type array;
706 FOR_EACH_SUBRTX (iter, array, x, ALL)
707 if (MEM_P (*iter))
708 return true;
709
710 return false;
711}
712
713/* Return true if X is an address that is known to not be zero. */
714
715bool
716nonzero_address_p (const_rtx x)
717{
718 const enum rtx_code code = GET_CODE (x);
719
720 switch (code)
721 {
722 case SYMBOL_REF:
723 return flag_delete_null_pointer_checks && !SYMBOL_REF_WEAK (x);
724
725 case LABEL_REF:
726 return true;
727
728 case REG:
729 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */
730 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx
731 || x == stack_pointer_rtx
732 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM]))
733 return true;
734 /* All of the virtual frame registers are stack references. */
735 if (VIRTUAL_REGISTER_P (x))
736 return true;
737 return false;
738
739 case CONST:
740 return nonzero_address_p (XEXP (x, 0));
741
742 case PLUS:
743 /* Handle PIC references. */
744 if (XEXP (x, 0) == pic_offset_table_rtx
745 && CONSTANT_P (XEXP (x, 1)))
746 return true;
747 return false;
748
749 case PRE_MODIFY:
750 /* Similar to the above; allow positive offsets. Further, since
751 auto-inc is only allowed in memories, the register must be a
752 pointer. */
753 if (CONST_INT_P (XEXP (x, 1))
754 && INTVAL (XEXP (x, 1)) > 0)
755 return true;
756 return nonzero_address_p (XEXP (x, 0));
757
758 case PRE_INC:
759 /* Similarly. Further, the offset is always positive. */
760 return true;
761
762 case PRE_DEC:
763 case POST_DEC:
764 case POST_INC:
765 case POST_MODIFY:
766 return nonzero_address_p (XEXP (x, 0));
767
768 case LO_SUM:
769 return nonzero_address_p (XEXP (x, 1));
770
771 default:
772 break;
773 }
774
775 /* If it isn't one of the case above, might be zero. */
776 return false;
777}
778
779/* Return true if X refers to a memory location whose address
780 cannot be compared reliably with constant addresses,
781 or if X refers to a BLKmode memory object.
782 FOR_ALIAS is nonzero if we are called from alias analysis; if it is
783 zero, we are slightly more conservative. */
784
785bool
786rtx_addr_varies_p (const_rtx x, bool for_alias)
787{
788 enum rtx_code code;
789 int i;
790 const char *fmt;
791
792 if (x == 0)
793 return false;
794
795 code = GET_CODE (x);
796 if (code == MEM)
797 return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0), for_alias);
798
799 fmt = GET_RTX_FORMAT (code);
800 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
801 if (fmt[i] == 'e')
802 {
803 if (rtx_addr_varies_p (XEXP (x, i), for_alias))
804 return true;
805 }
806 else if (fmt[i] == 'E')
807 {
808 int j;
809 for (j = 0; j < XVECLEN (x, i); j++)
810 if (rtx_addr_varies_p (XVECEXP (x, i, j), for_alias))
811 return true;
812 }
813 return false;
814}
815
816/* Return the CALL in X if there is one. */
817
818rtx
819get_call_rtx_from (const rtx_insn *insn)
820{
821 rtx x = PATTERN (insn);
822 if (GET_CODE (x) == PARALLEL)
823 x = XVECEXP (x, 0, 0);
824 if (GET_CODE (x) == SET)
825 x = SET_SRC (x);
826 if (GET_CODE (x) == CALL && MEM_P (XEXP (x, 0)))
827 return x;
828 return NULL_RTX;
829}
830
831/* Get the declaration of the function called by INSN. */
832
833tree
834get_call_fndecl (const rtx_insn *insn)
835{
836 rtx note, datum;
837
838 note = find_reg_note (insn, REG_CALL_DECL, NULL_RTX);
839 if (note == NULL_RTX)
840 return NULL_TREE;
841
842 datum = XEXP (note, 0);
843 if (datum != NULL_RTX)
844 return SYMBOL_REF_DECL (datum);
845
846 return NULL_TREE;
847}
848
849/* Return the value of the integer term in X, if one is apparent;
850 otherwise return 0.
851 Only obvious integer terms are detected.
852 This is used in cse.cc with the `related_value' field. */
853
854HOST_WIDE_INT
855get_integer_term (const_rtx x)
856{
857 if (GET_CODE (x) == CONST)
858 x = XEXP (x, 0);
859
860 if (GET_CODE (x) == MINUS
861 && CONST_INT_P (XEXP (x, 1)))
862 return - INTVAL (XEXP (x, 1));
863 if (GET_CODE (x) == PLUS
864 && CONST_INT_P (XEXP (x, 1)))
865 return INTVAL (XEXP (x, 1));
866 return 0;
867}
868
869/* If X is a constant, return the value sans apparent integer term;
870 otherwise return 0.
871 Only obvious integer terms are detected. */
872
873rtx
874get_related_value (const_rtx x)
875{
876 if (GET_CODE (x) != CONST)
877 return 0;
878 x = XEXP (x, 0);
879 if (GET_CODE (x) == PLUS
880 && CONST_INT_P (XEXP (x, 1)))
881 return XEXP (x, 0);
882 else if (GET_CODE (x) == MINUS
883 && CONST_INT_P (XEXP (x, 1)))
884 return XEXP (x, 0);
885 return 0;
886}
887
888/* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points
889 to somewhere in the same object or object_block as SYMBOL. */
890
891bool
892offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
893{
894 tree decl;
895
896 if (GET_CODE (symbol) != SYMBOL_REF)
897 return false;
898
899 if (offset == 0)
900 return true;
901
902 if (offset > 0)
903 {
904 if (CONSTANT_POOL_ADDRESS_P (symbol)
905 && offset < (int) GET_MODE_SIZE (mode: get_pool_mode (symbol)))
906 return true;
907
908 decl = SYMBOL_REF_DECL (symbol);
909 if (decl && offset < int_size_in_bytes (TREE_TYPE (decl)))
910 return true;
911 }
912
913 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol)
914 && SYMBOL_REF_BLOCK (symbol)
915 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0
916 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol)
917 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size))
918 return true;
919
920 return false;
921}
922
923/* Split X into a base and a constant offset, storing them in *BASE_OUT
924 and *OFFSET_OUT respectively. */
925
926void
927split_const (rtx x, rtx *base_out, rtx *offset_out)
928{
929 if (GET_CODE (x) == CONST)
930 {
931 x = XEXP (x, 0);
932 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
933 {
934 *base_out = XEXP (x, 0);
935 *offset_out = XEXP (x, 1);
936 return;
937 }
938 }
939 *base_out = x;
940 *offset_out = const0_rtx;
941}
942
943/* Express integer value X as some value Y plus a polynomial offset,
944 where Y is either const0_rtx, X or something within X (as opposed
945 to a new rtx). Return the Y and store the offset in *OFFSET_OUT. */
946
947rtx
948strip_offset (rtx x, poly_int64 *offset_out)
949{
950 rtx base = const0_rtx;
951 rtx test = x;
952 if (GET_CODE (test) == CONST)
953 test = XEXP (test, 0);
954 if (GET_CODE (test) == PLUS)
955 {
956 base = XEXP (test, 0);
957 test = XEXP (test, 1);
958 }
959 if (poly_int_rtx_p (x: test, res: offset_out))
960 return base;
961 *offset_out = 0;
962 return x;
963}
964
965/* Return the argument size in REG_ARGS_SIZE note X. */
966
967poly_int64
968get_args_size (const_rtx x)
969{
970 gcc_checking_assert (REG_NOTE_KIND (x) == REG_ARGS_SIZE);
971 return rtx_to_poly_int64 (XEXP (x, 0));
972}
973
974/* Return the number of places FIND appears within X. If COUNT_DEST is
975 zero, we do not count occurrences inside the destination of a SET. */
976
977int
978count_occurrences (const_rtx x, const_rtx find, int count_dest)
979{
980 int i, j;
981 enum rtx_code code;
982 const char *format_ptr;
983 int count;
984
985 if (x == find)
986 return 1;
987
988 code = GET_CODE (x);
989
990 switch (code)
991 {
992 case REG:
993 CASE_CONST_ANY:
994 case SYMBOL_REF:
995 case CODE_LABEL:
996 case PC:
997 return 0;
998
999 case EXPR_LIST:
1000 count = count_occurrences (XEXP (x, 0), find, count_dest);
1001 if (XEXP (x, 1))
1002 count += count_occurrences (XEXP (x, 1), find, count_dest);
1003 return count;
1004
1005 case MEM:
1006 if (MEM_P (find) && rtx_equal_p (x, find))
1007 return 1;
1008 break;
1009
1010 case SET:
1011 if (SET_DEST (x) == find && ! count_dest)
1012 return count_occurrences (SET_SRC (x), find, count_dest);
1013 break;
1014
1015 default:
1016 break;
1017 }
1018
1019 format_ptr = GET_RTX_FORMAT (code);
1020 count = 0;
1021
1022 for (i = 0; i < GET_RTX_LENGTH (code); i++)
1023 {
1024 switch (*format_ptr++)
1025 {
1026 case 'e':
1027 count += count_occurrences (XEXP (x, i), find, count_dest);
1028 break;
1029
1030 case 'E':
1031 for (j = 0; j < XVECLEN (x, i); j++)
1032 count += count_occurrences (XVECEXP (x, i, j), find, count_dest);
1033 break;
1034 }
1035 }
1036 return count;
1037}
1038
1039
1040/* Return TRUE if OP is a register or subreg of a register that
1041 holds an unsigned quantity. Otherwise, return FALSE. */
1042
1043bool
1044unsigned_reg_p (rtx op)
1045{
1046 if (REG_P (op)
1047 && REG_EXPR (op)
1048 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
1049 return true;
1050
1051 if (GET_CODE (op) == SUBREG
1052 && SUBREG_PROMOTED_SIGN (op))
1053 return true;
1054
1055 return false;
1056}
1057
1058
1059/* Return true if register REG appears somewhere within IN.
1060 Also works if REG is not a register; in this case it checks
1061 for a subexpression of IN that is Lisp "equal" to REG. */
1062
1063bool
1064reg_mentioned_p (const_rtx reg, const_rtx in)
1065{
1066 const char *fmt;
1067 int i;
1068 enum rtx_code code;
1069
1070 if (in == 0)
1071 return false;
1072
1073 if (reg == in)
1074 return true;
1075
1076 if (GET_CODE (in) == LABEL_REF)
1077 return reg == label_ref_label (ref: in);
1078
1079 code = GET_CODE (in);
1080
1081 switch (code)
1082 {
1083 /* Compare registers by number. */
1084 case REG:
1085 return REG_P (reg) && REGNO (in) == REGNO (reg);
1086
1087 /* These codes have no constituent expressions
1088 and are unique. */
1089 case SCRATCH:
1090 case PC:
1091 return false;
1092
1093 CASE_CONST_ANY:
1094 /* These are kept unique for a given value. */
1095 return false;
1096
1097 default:
1098 break;
1099 }
1100
1101 if (GET_CODE (reg) == code && rtx_equal_p (reg, in))
1102 return true;
1103
1104 fmt = GET_RTX_FORMAT (code);
1105
1106 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1107 {
1108 if (fmt[i] == 'E')
1109 {
1110 int j;
1111 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
1112 if (reg_mentioned_p (reg, XVECEXP (in, i, j)))
1113 return true;
1114 }
1115 else if (fmt[i] == 'e'
1116 && reg_mentioned_p (reg, XEXP (in, i)))
1117 return true;
1118 }
1119 return false;
1120}
1121
1122/* Return true if in between BEG and END, exclusive of BEG and END, there is
1123 no CODE_LABEL insn. */
1124
1125bool
1126no_labels_between_p (const rtx_insn *beg, const rtx_insn *end)
1127{
1128 rtx_insn *p;
1129 if (beg == end)
1130 return false;
1131 for (p = NEXT_INSN (insn: beg); p != end; p = NEXT_INSN (insn: p))
1132 if (LABEL_P (p))
1133 return false;
1134 return true;
1135}
1136
1137/* Return true if register REG is used in an insn between
1138 FROM_INSN and TO_INSN (exclusive of those two). */
1139
1140bool
1141reg_used_between_p (const_rtx reg, const rtx_insn *from_insn,
1142 const rtx_insn *to_insn)
1143{
1144 rtx_insn *insn;
1145
1146 if (from_insn == to_insn)
1147 return false;
1148
1149 for (insn = NEXT_INSN (insn: from_insn); insn != to_insn; insn = NEXT_INSN (insn))
1150 if (NONDEBUG_INSN_P (insn)
1151 && (reg_overlap_mentioned_p (reg, PATTERN (insn))
1152 || (CALL_P (insn) && find_reg_fusage (insn, USE, reg))))
1153 return true;
1154 return false;
1155}
1156
1157/* Return true if the old value of X, a register, is referenced in BODY. If X
1158 is entirely replaced by a new value and the only use is as a SET_DEST,
1159 we do not consider it a reference. */
1160
1161bool
1162reg_referenced_p (const_rtx x, const_rtx body)
1163{
1164 int i;
1165
1166 switch (GET_CODE (body))
1167 {
1168 case SET:
1169 if (reg_overlap_mentioned_p (x, SET_SRC (body)))
1170 return true;
1171
1172 /* If the destination is anything other than PC, a REG or a SUBREG
1173 of a REG that occupies all of the REG, the insn references X if
1174 it is mentioned in the destination. */
1175 if (GET_CODE (SET_DEST (body)) != PC
1176 && !REG_P (SET_DEST (body))
1177 && ! (GET_CODE (SET_DEST (body)) == SUBREG
1178 && REG_P (SUBREG_REG (SET_DEST (body)))
1179 && !read_modify_subreg_p (SET_DEST (body)))
1180 && reg_overlap_mentioned_p (x, SET_DEST (body)))
1181 return true;
1182 return false;
1183
1184 case ASM_OPERANDS:
1185 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
1186 if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i)))
1187 return true;
1188 return false;
1189
1190 case CALL:
1191 case USE:
1192 case IF_THEN_ELSE:
1193 return reg_overlap_mentioned_p (x, body);
1194
1195 case TRAP_IF:
1196 return reg_overlap_mentioned_p (x, TRAP_CONDITION (body));
1197
1198 case PREFETCH:
1199 return reg_overlap_mentioned_p (x, XEXP (body, 0));
1200
1201 case UNSPEC:
1202 case UNSPEC_VOLATILE:
1203 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1204 if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i)))
1205 return true;
1206 return false;
1207
1208 case PARALLEL:
1209 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
1210 if (reg_referenced_p (x, XVECEXP (body, 0, i)))
1211 return true;
1212 return false;
1213
1214 case CLOBBER:
1215 if (MEM_P (XEXP (body, 0)))
1216 if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0)))
1217 return true;
1218 return false;
1219
1220 case COND_EXEC:
1221 if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body)))
1222 return true;
1223 return reg_referenced_p (x, COND_EXEC_CODE (body));
1224
1225 default:
1226 return false;
1227 }
1228}
1229
1230/* Return true if register REG is set or clobbered in an insn between
1231 FROM_INSN and TO_INSN (exclusive of those two). */
1232
1233bool
1234reg_set_between_p (const_rtx reg, const rtx_insn *from_insn,
1235 const rtx_insn *to_insn)
1236{
1237 const rtx_insn *insn;
1238
1239 if (from_insn == to_insn)
1240 return false;
1241
1242 for (insn = NEXT_INSN (insn: from_insn); insn != to_insn; insn = NEXT_INSN (insn))
1243 if (INSN_P (insn) && reg_set_p (reg, insn))
1244 return true;
1245 return false;
1246}
1247
1248/* Return true if REG is set or clobbered inside INSN. */
1249
1250bool
1251reg_set_p (const_rtx reg, const_rtx insn)
1252{
1253 /* After delay slot handling, call and branch insns might be in a
1254 sequence. Check all the elements there. */
1255 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE)
1256 {
1257 for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i)
1258 if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i)))
1259 return true;
1260
1261 return false;
1262 }
1263
1264 /* We can be passed an insn or part of one. If we are passed an insn,
1265 check if a side-effect of the insn clobbers REG. */
1266 if (INSN_P (insn)
1267 && (FIND_REG_INC_NOTE (insn, reg)
1268 || (CALL_P (insn)
1269 && ((REG_P (reg)
1270 && REGNO (reg) < FIRST_PSEUDO_REGISTER
1271 && (insn_callee_abi (as_a<const rtx_insn *> (p: insn))
1272 .clobbers_reg_p (GET_MODE (reg), REGNO (reg))))
1273 || MEM_P (reg)
1274 || find_reg_fusage (insn, CLOBBER, reg)))))
1275 return true;
1276
1277 /* There are no REG_INC notes for SP autoinc. */
1278 if (reg == stack_pointer_rtx && INSN_P (insn))
1279 {
1280 subrtx_var_iterator::array_type array;
1281 FOR_EACH_SUBRTX_VAR (iter, array, PATTERN (insn), NONCONST)
1282 {
1283 rtx mem = *iter;
1284 if (mem
1285 && MEM_P (mem)
1286 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC)
1287 {
1288 if (XEXP (XEXP (mem, 0), 0) == stack_pointer_rtx)
1289 return true;
1290 iter.skip_subrtxes ();
1291 }
1292 }
1293 }
1294
1295 return set_of (reg, insn) != NULL_RTX;
1296}
1297
1298/* Similar to reg_set_between_p, but check all registers in X. Return false
1299 only if none of them are modified between START and END. Return true if
1300 X contains a MEM; this routine does use memory aliasing. */
1301
1302bool
1303modified_between_p (const_rtx x, const rtx_insn *start, const rtx_insn *end)
1304{
1305 const enum rtx_code code = GET_CODE (x);
1306 const char *fmt;
1307 int i, j;
1308 rtx_insn *insn;
1309
1310 if (start == end)
1311 return false;
1312
1313 switch (code)
1314 {
1315 CASE_CONST_ANY:
1316 case CONST:
1317 case SYMBOL_REF:
1318 case LABEL_REF:
1319 return false;
1320
1321 case PC:
1322 return true;
1323
1324 case MEM:
1325 if (modified_between_p (XEXP (x, 0), start, end))
1326 return true;
1327 if (MEM_READONLY_P (x))
1328 return false;
1329 for (insn = NEXT_INSN (insn: start); insn != end; insn = NEXT_INSN (insn))
1330 if (memory_modified_in_insn_p (x, insn))
1331 return true;
1332 return false;
1333
1334 case REG:
1335 return reg_set_between_p (reg: x, from_insn: start, to_insn: end);
1336
1337 default:
1338 break;
1339 }
1340
1341 fmt = GET_RTX_FORMAT (code);
1342 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1343 {
1344 if (fmt[i] == 'e' && modified_between_p (XEXP (x, i), start, end))
1345 return true;
1346
1347 else if (fmt[i] == 'E')
1348 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1349 if (modified_between_p (XVECEXP (x, i, j), start, end))
1350 return true;
1351 }
1352
1353 return false;
1354}
1355
1356/* Similar to reg_set_p, but check all registers in X. Return false only if
1357 none of them are modified in INSN. Return true if X contains a MEM; this
1358 routine does use memory aliasing. */
1359
1360bool
1361modified_in_p (const_rtx x, const_rtx insn)
1362{
1363 const enum rtx_code code = GET_CODE (x);
1364 const char *fmt;
1365 int i, j;
1366
1367 switch (code)
1368 {
1369 CASE_CONST_ANY:
1370 case CONST:
1371 case SYMBOL_REF:
1372 case LABEL_REF:
1373 return false;
1374
1375 case PC:
1376 return true;
1377
1378 case MEM:
1379 if (modified_in_p (XEXP (x, 0), insn))
1380 return true;
1381 if (MEM_READONLY_P (x))
1382 return false;
1383 if (memory_modified_in_insn_p (x, insn))
1384 return true;
1385 return false;
1386
1387 case REG:
1388 return reg_set_p (reg: x, insn);
1389
1390 default:
1391 break;
1392 }
1393
1394 fmt = GET_RTX_FORMAT (code);
1395 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1396 {
1397 if (fmt[i] == 'e' && modified_in_p (XEXP (x, i), insn))
1398 return true;
1399
1400 else if (fmt[i] == 'E')
1401 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1402 if (modified_in_p (XVECEXP (x, i, j), insn))
1403 return true;
1404 }
1405
1406 return false;
1407}
1408
1409/* Return true if X is a SUBREG and if storing a value to X would
1410 preserve some of its SUBREG_REG. For example, on a normal 32-bit
1411 target, using a SUBREG to store to one half of a DImode REG would
1412 preserve the other half. */
1413
1414bool
1415read_modify_subreg_p (const_rtx x)
1416{
1417 if (GET_CODE (x) != SUBREG)
1418 return false;
1419 poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
1420 poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x));
1421 poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (SUBREG_REG (x)));
1422 /* The inner and outer modes of a subreg must be ordered, so that we
1423 can tell whether they're paradoxical or partial. */
1424 gcc_checking_assert (ordered_p (isize, osize));
1425 return (maybe_gt (isize, osize) && maybe_gt (isize, regsize));
1426}
1427
1428/* Helper function for set_of. */
1429struct set_of_data
1430 {
1431 const_rtx found;
1432 const_rtx pat;
1433 };
1434
1435static void
1436set_of_1 (rtx x, const_rtx pat, void *data1)
1437{
1438 struct set_of_data *const data = (struct set_of_data *) (data1);
1439 if (rtx_equal_p (x, data->pat)
1440 || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x)))
1441 data->found = pat;
1442}
1443
1444/* Give an INSN, return a SET or CLOBBER expression that does modify PAT
1445 (either directly or via STRICT_LOW_PART and similar modifiers). */
1446const_rtx
1447set_of (const_rtx pat, const_rtx insn)
1448{
1449 struct set_of_data data;
1450 data.found = NULL_RTX;
1451 data.pat = pat;
1452 note_pattern_stores (INSN_P (insn) ? PATTERN (insn) : insn, set_of_1, &data);
1453 return data.found;
1454}
1455
1456/* Check whether instruction pattern PAT contains a SET with the following
1457 properties:
1458
1459 - the SET is executed unconditionally; and
1460 - either:
1461 - the destination of the SET is a REG that contains REGNO; or
1462 - both:
1463 - the destination of the SET is a SUBREG of such a REG; and
1464 - writing to the subreg clobbers all of the SUBREG_REG
1465 (in other words, read_modify_subreg_p is false).
1466
1467 If PAT does have a SET like that, return the set, otherwise return null.
1468
1469 This is intended to be an alternative to single_set for passes that
1470 can handle patterns with multiple_sets. */
1471rtx
1472simple_regno_set (rtx pat, unsigned int regno)
1473{
1474 if (GET_CODE (pat) == PARALLEL)
1475 {
1476 int last = XVECLEN (pat, 0) - 1;
1477 for (int i = 0; i < last; ++i)
1478 if (rtx set = simple_regno_set (XVECEXP (pat, 0, i), regno))
1479 return set;
1480
1481 pat = XVECEXP (pat, 0, last);
1482 }
1483
1484 if (GET_CODE (pat) == SET
1485 && covers_regno_no_parallel_p (SET_DEST (pat), regno))
1486 return pat;
1487
1488 return nullptr;
1489}
1490
1491/* Add all hard register in X to *PSET. */
1492void
1493find_all_hard_regs (const_rtx x, HARD_REG_SET *pset)
1494{
1495 subrtx_iterator::array_type array;
1496 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
1497 {
1498 const_rtx x = *iter;
1499 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
1500 add_to_hard_reg_set (regs: pset, GET_MODE (x), REGNO (x));
1501 }
1502}
1503
1504/* This function, called through note_stores, collects sets and
1505 clobbers of hard registers in a HARD_REG_SET, which is pointed to
1506 by DATA. */
1507void
1508record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
1509{
1510 HARD_REG_SET *pset = (HARD_REG_SET *)data;
1511 if (REG_P (x) && HARD_REGISTER_P (x))
1512 add_to_hard_reg_set (regs: pset, GET_MODE (x), REGNO (x));
1513}
1514
1515/* Examine INSN, and compute the set of hard registers written by it.
1516 Store it in *PSET. Should only be called after reload.
1517
1518 IMPLICIT is true if we should include registers that are fully-clobbered
1519 by calls. This should be used with caution, since it doesn't include
1520 partially-clobbered registers. */
1521void
1522find_all_hard_reg_sets (const rtx_insn *insn, HARD_REG_SET *pset, bool implicit)
1523{
1524 rtx link;
1525
1526 CLEAR_HARD_REG_SET (set&: *pset);
1527 note_stores (insn, record_hard_reg_sets, pset);
1528 if (CALL_P (insn) && implicit)
1529 *pset |= insn_callee_abi (insn).full_reg_clobbers ();
1530 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1531 if (REG_NOTE_KIND (link) == REG_INC)
1532 record_hard_reg_sets (XEXP (link, 0), NULL, data: pset);
1533}
1534
1535/* Like record_hard_reg_sets, but called through note_uses. */
1536void
1537record_hard_reg_uses (rtx *px, void *data)
1538{
1539 find_all_hard_regs (x: *px, pset: (HARD_REG_SET *) data);
1540}
1541
1542/* Given an INSN, return a SET expression if this insn has only a single SET.
1543 It may also have CLOBBERs, USEs, or SET whose output
1544 will not be used, which we ignore. */
1545
1546rtx
1547single_set_2 (const rtx_insn *insn, const_rtx pat)
1548{
1549 rtx set = NULL;
1550 int set_verified = 1;
1551 int i;
1552
1553 if (GET_CODE (pat) == PARALLEL)
1554 {
1555 for (i = 0; i < XVECLEN (pat, 0); i++)
1556 {
1557 rtx sub = XVECEXP (pat, 0, i);
1558 switch (GET_CODE (sub))
1559 {
1560 case USE:
1561 case CLOBBER:
1562 break;
1563
1564 case SET:
1565 /* We can consider insns having multiple sets, where all
1566 but one are dead as single set insns. In common case
1567 only single set is present in the pattern so we want
1568 to avoid checking for REG_UNUSED notes unless necessary.
1569
1570 When we reach set first time, we just expect this is
1571 the single set we are looking for and only when more
1572 sets are found in the insn, we check them. */
1573 if (!set_verified)
1574 {
1575 if (find_reg_note (insn, REG_UNUSED, SET_DEST (set))
1576 && !side_effects_p (set))
1577 set = NULL;
1578 else
1579 set_verified = 1;
1580 }
1581 if (!set)
1582 set = sub, set_verified = 0;
1583 else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub))
1584 || side_effects_p (sub))
1585 return NULL_RTX;
1586 break;
1587
1588 default:
1589 return NULL_RTX;
1590 }
1591 }
1592 }
1593 return set;
1594}
1595
1596/* Given an INSN, return true if it has more than one SET, else return
1597 false. */
1598
1599bool
1600multiple_sets (const_rtx insn)
1601{
1602 bool found;
1603 int i;
1604
1605 /* INSN must be an insn. */
1606 if (! INSN_P (insn))
1607 return false;
1608
1609 /* Only a PARALLEL can have multiple SETs. */
1610 if (GET_CODE (PATTERN (insn)) == PARALLEL)
1611 {
1612 for (i = 0, found = false; i < XVECLEN (PATTERN (insn), 0); i++)
1613 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET)
1614 {
1615 /* If we have already found a SET, then return now. */
1616 if (found)
1617 return true;
1618 else
1619 found = true;
1620 }
1621 }
1622
1623 /* Either zero or one SET. */
1624 return false;
1625}
1626
1627/* Return true if the destination of SET equals the source
1628 and there are no side effects. */
1629
1630bool
1631set_noop_p (const_rtx set)
1632{
1633 rtx src = SET_SRC (set);
1634 rtx dst = SET_DEST (set);
1635
1636 if (dst == pc_rtx && src == pc_rtx)
1637 return true;
1638
1639 if (MEM_P (dst) && MEM_P (src))
1640 return rtx_equal_p (dst, src) && !side_effects_p (dst);
1641
1642 if (GET_CODE (dst) == ZERO_EXTRACT)
1643 return rtx_equal_p (XEXP (dst, 0), src)
1644 && !BITS_BIG_ENDIAN && XEXP (dst, 2) == const0_rtx
1645 && !side_effects_p (src);
1646
1647 if (GET_CODE (dst) == STRICT_LOW_PART)
1648 dst = XEXP (dst, 0);
1649
1650 if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
1651 {
1652 if (maybe_ne (SUBREG_BYTE (src), SUBREG_BYTE (dst)))
1653 return false;
1654 src = SUBREG_REG (src);
1655 dst = SUBREG_REG (dst);
1656 if (GET_MODE (src) != GET_MODE (dst))
1657 /* It is hard to tell whether subregs refer to the same bits, so act
1658 conservatively and return false. */
1659 return false;
1660 }
1661
1662 /* It is a NOOP if destination overlaps with selected src vector
1663 elements. */
1664 if (GET_CODE (src) == VEC_SELECT
1665 && REG_P (XEXP (src, 0)) && REG_P (dst)
1666 && HARD_REGISTER_P (XEXP (src, 0))
1667 && HARD_REGISTER_P (dst))
1668 {
1669 int i;
1670 rtx par = XEXP (src, 1);
1671 rtx src0 = XEXP (src, 0);
1672 poly_int64 c0;
1673 if (!poly_int_rtx_p (XVECEXP (par, 0, 0), res: &c0))
1674 return false;
1675 poly_int64 offset = GET_MODE_UNIT_SIZE (GET_MODE (src0)) * c0;
1676
1677 for (i = 1; i < XVECLEN (par, 0); i++)
1678 {
1679 poly_int64 c0i;
1680 if (!poly_int_rtx_p (XVECEXP (par, 0, i), res: &c0i)
1681 || maybe_ne (a: c0i, b: c0 + i))
1682 return false;
1683 }
1684 return
1685 REG_CAN_CHANGE_MODE_P (REGNO (dst), GET_MODE (src0), GET_MODE (dst))
1686 && simplify_subreg_regno (REGNO (src0), GET_MODE (src0),
1687 offset, GET_MODE (dst)) == (int) REGNO (dst);
1688 }
1689
1690 return (REG_P (src) && REG_P (dst)
1691 && REGNO (src) == REGNO (dst));
1692}
1693
1694/* Return true if an insn consists only of SETs, each of which only sets a
1695 value to itself. */
1696
1697bool
1698noop_move_p (const rtx_insn *insn)
1699{
1700 rtx pat = PATTERN (insn);
1701
1702 if (INSN_CODE (insn) == NOOP_MOVE_INSN_CODE)
1703 return true;
1704
1705 /* Check the code to be executed for COND_EXEC. */
1706 if (GET_CODE (pat) == COND_EXEC)
1707 pat = COND_EXEC_CODE (pat);
1708
1709 if (GET_CODE (pat) == SET && set_noop_p (pat))
1710 return true;
1711
1712 if (GET_CODE (pat) == PARALLEL)
1713 {
1714 int i;
1715 /* If nothing but SETs of registers to themselves,
1716 this insn can also be deleted. */
1717 for (i = 0; i < XVECLEN (pat, 0); i++)
1718 {
1719 rtx tem = XVECEXP (pat, 0, i);
1720
1721 if (GET_CODE (tem) == USE || GET_CODE (tem) == CLOBBER)
1722 continue;
1723
1724 if (GET_CODE (tem) != SET || ! set_noop_p (tem))
1725 return false;
1726 }
1727
1728 return true;
1729 }
1730 return false;
1731}
1732
1733
1734/* Return true if register in range [REGNO, ENDREGNO)
1735 appears either explicitly or implicitly in X
1736 other than being stored into.
1737
1738 References contained within the substructure at LOC do not count.
1739 LOC may be zero, meaning don't ignore anything. */
1740
1741bool
1742refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
1743 rtx *loc)
1744{
1745 int i;
1746 unsigned int x_regno;
1747 RTX_CODE code;
1748 const char *fmt;
1749
1750 repeat:
1751 /* The contents of a REG_NONNEG note is always zero, so we must come here
1752 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */
1753 if (x == 0)
1754 return false;
1755
1756 code = GET_CODE (x);
1757
1758 switch (code)
1759 {
1760 case REG:
1761 x_regno = REGNO (x);
1762
1763 /* If we modifying the stack, frame, or argument pointer, it will
1764 clobber a virtual register. In fact, we could be more precise,
1765 but it isn't worth it. */
1766 if ((x_regno == STACK_POINTER_REGNUM
1767 || (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
1768 && x_regno == ARG_POINTER_REGNUM)
1769 || x_regno == FRAME_POINTER_REGNUM)
1770 && VIRTUAL_REGISTER_NUM_P (regno))
1771 return true;
1772
1773 return endregno > x_regno && regno < END_REGNO (x);
1774
1775 case SUBREG:
1776 /* If this is a SUBREG of a hard reg, we can see exactly which
1777 registers are being modified. Otherwise, handle normally. */
1778 if (REG_P (SUBREG_REG (x))
1779 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER)
1780 {
1781 unsigned int inner_regno = subreg_regno (x);
1782 unsigned int inner_endregno
1783 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER
1784 ? subreg_nregs (x) : 1);
1785
1786 return endregno > inner_regno && regno < inner_endregno;
1787 }
1788 break;
1789
1790 case CLOBBER:
1791 case SET:
1792 if (&SET_DEST (x) != loc
1793 /* Note setting a SUBREG counts as referring to the REG it is in for
1794 a pseudo but not for hard registers since we can
1795 treat each word individually. */
1796 && ((GET_CODE (SET_DEST (x)) == SUBREG
1797 && loc != &SUBREG_REG (SET_DEST (x))
1798 && REG_P (SUBREG_REG (SET_DEST (x)))
1799 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
1800 && refers_to_regno_p (regno, endregno,
1801 SUBREG_REG (SET_DEST (x)), loc))
1802 || (!REG_P (SET_DEST (x))
1803 && refers_to_regno_p (regno, endregno, SET_DEST (x), loc))))
1804 return true;
1805
1806 if (code == CLOBBER || loc == &SET_SRC (x))
1807 return false;
1808 x = SET_SRC (x);
1809 goto repeat;
1810
1811 default:
1812 break;
1813 }
1814
1815 /* X does not match, so try its subexpressions. */
1816
1817 fmt = GET_RTX_FORMAT (code);
1818 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
1819 {
1820 if (fmt[i] == 'e' && loc != &XEXP (x, i))
1821 {
1822 if (i == 0)
1823 {
1824 x = XEXP (x, 0);
1825 goto repeat;
1826 }
1827 else
1828 if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc))
1829 return true;
1830 }
1831 else if (fmt[i] == 'E')
1832 {
1833 int j;
1834 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1835 if (loc != &XVECEXP (x, i, j)
1836 && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc))
1837 return true;
1838 }
1839 }
1840 return false;
1841}
1842
1843/* Rreturn true if modifying X will affect IN. If X is a register or a SUBREG,
1844 we check if any register number in X conflicts with the relevant register
1845 numbers. If X is a constant, return false. If X is a MEM, return true iff
1846 IN contains a MEM (we don't bother checking for memory addresses that can't
1847 conflict because we expect this to be a rare case. */
1848
1849bool
1850reg_overlap_mentioned_p (const_rtx x, const_rtx in)
1851{
1852 unsigned int regno, endregno;
1853
1854 /* If either argument is a constant, then modifying X cannot
1855 affect IN. Here we look at IN, we can profitably combine
1856 CONSTANT_P (x) with the switch statement below. */
1857 if (CONSTANT_P (in))
1858 return false;
1859
1860 recurse:
1861 switch (GET_CODE (x))
1862 {
1863 case CLOBBER:
1864 case STRICT_LOW_PART:
1865 case ZERO_EXTRACT:
1866 case SIGN_EXTRACT:
1867 /* Overly conservative. */
1868 x = XEXP (x, 0);
1869 goto recurse;
1870
1871 case SUBREG:
1872 regno = REGNO (SUBREG_REG (x));
1873 if (regno < FIRST_PSEUDO_REGISTER)
1874 regno = subreg_regno (x);
1875 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
1876 ? subreg_nregs (x) : 1);
1877 goto do_reg;
1878
1879 case REG:
1880 regno = REGNO (x);
1881 endregno = END_REGNO (x);
1882 do_reg:
1883 return refers_to_regno_p (regno, endregno, x: in, loc: (rtx*) 0);
1884
1885 case MEM:
1886 {
1887 const char *fmt;
1888 int i;
1889
1890 if (MEM_P (in))
1891 return true;
1892
1893 fmt = GET_RTX_FORMAT (GET_CODE (in));
1894 for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--)
1895 if (fmt[i] == 'e')
1896 {
1897 if (reg_overlap_mentioned_p (x, XEXP (in, i)))
1898 return true;
1899 }
1900 else if (fmt[i] == 'E')
1901 {
1902 int j;
1903 for (j = XVECLEN (in, i) - 1; j >= 0; --j)
1904 if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j)))
1905 return true;
1906 }
1907
1908 return false;
1909 }
1910
1911 case SCRATCH:
1912 case PC:
1913 return reg_mentioned_p (reg: x, in);
1914
1915 case PARALLEL:
1916 {
1917 int i;
1918
1919 /* If any register in here refers to it we return true. */
1920 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1921 if (XEXP (XVECEXP (x, 0, i), 0) != 0
1922 && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0), in))
1923 return true;
1924 return false;
1925 }
1926
1927 default:
1928 gcc_assert (CONSTANT_P (x));
1929 return false;
1930 }
1931}
1932
1933/* Call FUN on each register or MEM that is stored into or clobbered by X.
1934 (X would be the pattern of an insn). DATA is an arbitrary pointer,
1935 ignored by note_stores, but passed to FUN.
1936
1937 FUN receives three arguments:
1938 1. the REG, MEM or PC being stored in or clobbered,
1939 2. the SET or CLOBBER rtx that does the store,
1940 3. the pointer DATA provided to note_stores.
1941
1942 If the item being stored in or clobbered is a SUBREG of a hard register,
1943 the SUBREG will be passed. */
1944
1945void
1946note_pattern_stores (const_rtx x,
1947 void (*fun) (rtx, const_rtx, void *), void *data)
1948{
1949 int i;
1950
1951 if (GET_CODE (x) == COND_EXEC)
1952 x = COND_EXEC_CODE (x);
1953
1954 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER)
1955 {
1956 rtx dest = SET_DEST (x);
1957
1958 while ((GET_CODE (dest) == SUBREG
1959 && (!REG_P (SUBREG_REG (dest))
1960 || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
1961 || GET_CODE (dest) == ZERO_EXTRACT
1962 || GET_CODE (dest) == STRICT_LOW_PART)
1963 dest = XEXP (dest, 0);
1964
1965 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
1966 each of whose first operand is a register. */
1967 if (GET_CODE (dest) == PARALLEL)
1968 {
1969 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
1970 if (XEXP (XVECEXP (dest, 0, i), 0) != 0)
1971 (*fun) (XEXP (XVECEXP (dest, 0, i), 0), x, data);
1972 }
1973 else
1974 (*fun) (dest, x, data);
1975 }
1976
1977 else if (GET_CODE (x) == PARALLEL)
1978 for (i = XVECLEN (x, 0) - 1; i >= 0; i--)
1979 note_pattern_stores (XVECEXP (x, 0, i), fun, data);
1980}
1981
1982/* Same, but for an instruction. If the instruction is a call, include
1983 any CLOBBERs in its CALL_INSN_FUNCTION_USAGE. */
1984
1985void
1986note_stores (const rtx_insn *insn,
1987 void (*fun) (rtx, const_rtx, void *), void *data)
1988{
1989 if (CALL_P (insn))
1990 for (rtx link = CALL_INSN_FUNCTION_USAGE (insn);
1991 link; link = XEXP (link, 1))
1992 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
1993 note_pattern_stores (XEXP (link, 0), fun, data);
1994 note_pattern_stores (x: PATTERN (insn), fun, data);
1995}
1996
1997/* Like notes_stores, but call FUN for each expression that is being
1998 referenced in PBODY, a pointer to the PATTERN of an insn. We only call
1999 FUN for each expression, not any interior subexpressions. FUN receives a
2000 pointer to the expression and the DATA passed to this function.
2001
2002 Note that this is not quite the same test as that done in reg_referenced_p
2003 since that considers something as being referenced if it is being
2004 partially set, while we do not. */
2005
2006void
2007note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
2008{
2009 rtx body = *pbody;
2010 int i;
2011
2012 switch (GET_CODE (body))
2013 {
2014 case COND_EXEC:
2015 (*fun) (&COND_EXEC_TEST (body), data);
2016 note_uses (pbody: &COND_EXEC_CODE (body), fun, data);
2017 return;
2018
2019 case PARALLEL:
2020 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
2021 note_uses (pbody: &XVECEXP (body, 0, i), fun, data);
2022 return;
2023
2024 case SEQUENCE:
2025 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
2026 note_uses (pbody: &PATTERN (XVECEXP (body, 0, i)), fun, data);
2027 return;
2028
2029 case USE:
2030 (*fun) (&XEXP (body, 0), data);
2031 return;
2032
2033 case ASM_OPERANDS:
2034 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--)
2035 (*fun) (&ASM_OPERANDS_INPUT (body, i), data);
2036 return;
2037
2038 case TRAP_IF:
2039 (*fun) (&TRAP_CONDITION (body), data);
2040 return;
2041
2042 case PREFETCH:
2043 (*fun) (&XEXP (body, 0), data);
2044 return;
2045
2046 case UNSPEC:
2047 case UNSPEC_VOLATILE:
2048 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
2049 (*fun) (&XVECEXP (body, 0, i), data);
2050 return;
2051
2052 case CLOBBER:
2053 if (MEM_P (XEXP (body, 0)))
2054 (*fun) (&XEXP (XEXP (body, 0), 0), data);
2055 return;
2056
2057 case SET:
2058 {
2059 rtx dest = SET_DEST (body);
2060
2061 /* For sets we replace everything in source plus registers in memory
2062 expression in store and operands of a ZERO_EXTRACT. */
2063 (*fun) (&SET_SRC (body), data);
2064
2065 if (GET_CODE (dest) == ZERO_EXTRACT)
2066 {
2067 (*fun) (&XEXP (dest, 1), data);
2068 (*fun) (&XEXP (dest, 2), data);
2069 }
2070
2071 while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
2072 dest = XEXP (dest, 0);
2073
2074 if (MEM_P (dest))
2075 (*fun) (&XEXP (dest, 0), data);
2076 }
2077 return;
2078
2079 default:
2080 /* All the other possibilities never store. */
2081 (*fun) (pbody, data);
2082 return;
2083 }
2084}
2085
2086/* Try to add a description of REG X to this object, stopping once
2087 the REF_END limit has been reached. FLAGS is a bitmask of
2088 rtx_obj_reference flags that describe the context. */
2089
2090void
2091rtx_properties::try_to_add_reg (const_rtx x, unsigned int flags)
2092{
2093 if (REG_NREGS (x) != 1)
2094 flags |= rtx_obj_flags::IS_MULTIREG;
2095 machine_mode mode = GET_MODE (x);
2096 unsigned int start_regno = REGNO (x);
2097 unsigned int end_regno = END_REGNO (x);
2098 for (unsigned int regno = start_regno; regno < end_regno; ++regno)
2099 if (ref_iter != ref_end)
2100 *ref_iter++ = rtx_obj_reference (regno, flags, mode,
2101 regno - start_regno);
2102}
2103
2104/* Add a description of destination X to this object. FLAGS is a bitmask
2105 of rtx_obj_reference flags that describe the context.
2106
2107 This routine accepts all rtxes that can legitimately appear in a
2108 SET_DEST. */
2109
2110void
2111rtx_properties::try_to_add_dest (const_rtx x, unsigned int flags)
2112{
2113 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions,
2114 each of whose first operand is a register. */
2115 if (UNLIKELY (GET_CODE (x) == PARALLEL))
2116 {
2117 for (int i = XVECLEN (x, 0) - 1; i >= 0; --i)
2118 if (rtx dest = XEXP (XVECEXP (x, 0, i), 0))
2119 try_to_add_dest (x: dest, flags);
2120 return;
2121 }
2122
2123 unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
2124 flags |= rtx_obj_flags::IS_WRITE;
2125 for (;;)
2126 if (GET_CODE (x) == ZERO_EXTRACT)
2127 {
2128 try_to_add_src (XEXP (x, 1), flags: base_flags);
2129 try_to_add_src (XEXP (x, 2), flags: base_flags);
2130 flags |= rtx_obj_flags::IS_READ;
2131 x = XEXP (x, 0);
2132 }
2133 else if (GET_CODE (x) == STRICT_LOW_PART)
2134 {
2135 flags |= rtx_obj_flags::IS_READ;
2136 x = XEXP (x, 0);
2137 }
2138 else if (GET_CODE (x) == SUBREG)
2139 {
2140 flags |= rtx_obj_flags::IN_SUBREG;
2141 if (read_modify_subreg_p (x))
2142 flags |= rtx_obj_flags::IS_READ;
2143 x = SUBREG_REG (x);
2144 }
2145 else
2146 break;
2147
2148 if (MEM_P (x))
2149 {
2150 if (ref_iter != ref_end)
2151 *ref_iter++ = rtx_obj_reference (MEM_REGNO, flags, GET_MODE (x));
2152
2153 unsigned int addr_flags = base_flags | rtx_obj_flags::IN_MEM_STORE;
2154 if (flags & rtx_obj_flags::IS_READ)
2155 addr_flags |= rtx_obj_flags::IN_MEM_LOAD;
2156 try_to_add_src (XEXP (x, 0), flags: addr_flags);
2157 return;
2158 }
2159
2160 if (LIKELY (REG_P (x)))
2161 {
2162 /* We want to keep sp alive everywhere - by making all
2163 writes to sp also use sp. */
2164 if (REGNO (x) == STACK_POINTER_REGNUM)
2165 flags |= rtx_obj_flags::IS_READ;
2166 try_to_add_reg (x, flags);
2167 return;
2168 }
2169}
2170
2171/* Try to add a description of source X to this object, stopping once
2172 the REF_END limit has been reached. FLAGS is a bitmask of
2173 rtx_obj_reference flags that describe the context.
2174
2175 This routine accepts all rtxes that can legitimately appear in a SET_SRC. */
2176
2177void
2178rtx_properties::try_to_add_src (const_rtx x, unsigned int flags)
2179{
2180 unsigned int base_flags = flags & rtx_obj_flags::STICKY_FLAGS;
2181 subrtx_iterator::array_type array;
2182 FOR_EACH_SUBRTX (iter, array, x, NONCONST)
2183 {
2184 const_rtx x = *iter;
2185 rtx_code code = GET_CODE (x);
2186 if (code == REG)
2187 try_to_add_reg (x, flags: flags | rtx_obj_flags::IS_READ);
2188 else if (code == MEM)
2189 {
2190 if (MEM_VOLATILE_P (x))
2191 has_volatile_refs = true;
2192
2193 if (!MEM_READONLY_P (x) && ref_iter != ref_end)
2194 {
2195 auto mem_flags = flags | rtx_obj_flags::IS_READ;
2196 *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags,
2197 GET_MODE (x));
2198 }
2199
2200 try_to_add_src (XEXP (x, 0),
2201 flags: base_flags | rtx_obj_flags::IN_MEM_LOAD);
2202 iter.skip_subrtxes ();
2203 }
2204 else if (code == SUBREG)
2205 {
2206 try_to_add_src (SUBREG_REG (x), flags: flags | rtx_obj_flags::IN_SUBREG);
2207 iter.skip_subrtxes ();
2208 }
2209 else if (code == UNSPEC_VOLATILE)
2210 has_volatile_refs = true;
2211 else if (code == ASM_INPUT || code == ASM_OPERANDS)
2212 {
2213 has_asm = true;
2214 if (MEM_VOLATILE_P (x))
2215 has_volatile_refs = true;
2216 }
2217 else if (code == PRE_INC
2218 || code == PRE_DEC
2219 || code == POST_INC
2220 || code == POST_DEC
2221 || code == PRE_MODIFY
2222 || code == POST_MODIFY)
2223 {
2224 has_pre_post_modify = true;
2225
2226 unsigned int addr_flags = (base_flags
2227 | rtx_obj_flags::IS_PRE_POST_MODIFY
2228 | rtx_obj_flags::IS_READ);
2229 try_to_add_dest (XEXP (x, 0), flags: addr_flags);
2230 if (code == PRE_MODIFY || code == POST_MODIFY)
2231 iter.substitute (XEXP (XEXP (x, 1), 1));
2232 else
2233 iter.skip_subrtxes ();
2234 }
2235 else if (code == CALL)
2236 has_call = true;
2237 }
2238}
2239
2240/* Try to add a description of instruction pattern PAT to this object,
2241 stopping once the REF_END limit has been reached. */
2242
2243void
2244rtx_properties::try_to_add_pattern (const_rtx pat)
2245{
2246 switch (GET_CODE (pat))
2247 {
2248 case COND_EXEC:
2249 try_to_add_src (COND_EXEC_TEST (pat));
2250 try_to_add_pattern (COND_EXEC_CODE (pat));
2251 break;
2252
2253 case PARALLEL:
2254 {
2255 int last = XVECLEN (pat, 0) - 1;
2256 for (int i = 0; i < last; ++i)
2257 try_to_add_pattern (XVECEXP (pat, 0, i));
2258 try_to_add_pattern (XVECEXP (pat, 0, last));
2259 break;
2260 }
2261
2262 case ASM_OPERANDS:
2263 for (int i = 0, len = ASM_OPERANDS_INPUT_LENGTH (pat); i < len; ++i)
2264 try_to_add_src (ASM_OPERANDS_INPUT (pat, i));
2265 break;
2266
2267 case CLOBBER:
2268 try_to_add_dest (XEXP (pat, 0), flags: rtx_obj_flags::IS_CLOBBER);
2269 break;
2270
2271 case SET:
2272 try_to_add_dest (SET_DEST (pat));
2273 try_to_add_src (SET_SRC (pat));
2274 break;
2275
2276 default:
2277 /* All the other possibilities never store and can use a normal
2278 rtx walk. This includes:
2279
2280 - USE
2281 - TRAP_IF
2282 - PREFETCH
2283 - UNSPEC
2284 - UNSPEC_VOLATILE. */
2285 try_to_add_src (x: pat);
2286 break;
2287 }
2288}
2289
2290/* Try to add a description of INSN to this object, stopping once
2291 the REF_END limit has been reached. INCLUDE_NOTES is true if the
2292 description should include REG_EQUAL and REG_EQUIV notes; all such
2293 references will then be marked with rtx_obj_flags::IN_NOTE.
2294
2295 For calls, this description includes all accesses in
2296 CALL_INSN_FUNCTION_USAGE. It also include all implicit accesses
2297 to global registers by the target function. However, it does not
2298 include clobbers performed by the target function; callers that want
2299 this information should instead use the function_abi interface. */
2300
2301void
2302rtx_properties::try_to_add_insn (const rtx_insn *insn, bool include_notes)
2303{
2304 if (CALL_P (insn))
2305 {
2306 /* Non-const functions can read from global registers. Impure
2307 functions can also set them.
2308
2309 Adding the global registers first removes a situation in which
2310 a fixed-form clobber of register R could come before a real set
2311 of register R. */
2312 if (!hard_reg_set_empty_p (x: global_reg_set)
2313 && !RTL_CONST_CALL_P (insn))
2314 {
2315 unsigned int flags = rtx_obj_flags::IS_READ;
2316 if (!RTL_PURE_CALL_P (insn))
2317 flags |= rtx_obj_flags::IS_WRITE;
2318 for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
2319 /* As a special case, the stack pointer is invariant across calls
2320 even if it has been marked global; see the corresponding
2321 handling in df_get_call_refs. */
2322 if (regno != STACK_POINTER_REGNUM
2323 && global_regs[regno]
2324 && ref_iter != ref_end)
2325 *ref_iter++ = rtx_obj_reference (regno, flags,
2326 reg_raw_mode[regno], 0);
2327 }
2328 /* Untyped calls implicitly set all function value registers.
2329 Again, we add them first in case the main pattern contains
2330 a fixed-form clobber. */
2331 if (find_reg_note (insn, REG_UNTYPED_CALL, NULL_RTX))
2332 for (unsigned int regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno)
2333 if (targetm.calls.function_value_regno_p (regno)
2334 && ref_iter != ref_end)
2335 *ref_iter++ = rtx_obj_reference (regno, rtx_obj_flags::IS_WRITE,
2336 reg_raw_mode[regno], 0);
2337 if (ref_iter != ref_end && !RTL_CONST_CALL_P (insn))
2338 {
2339 auto mem_flags = rtx_obj_flags::IS_READ;
2340 if (!RTL_PURE_CALL_P (insn))
2341 mem_flags |= rtx_obj_flags::IS_WRITE;
2342 *ref_iter++ = rtx_obj_reference (MEM_REGNO, mem_flags, BLKmode);
2343 }
2344 try_to_add_pattern (pat: PATTERN (insn));
2345 for (rtx link = CALL_INSN_FUNCTION_USAGE (insn); link;
2346 link = XEXP (link, 1))
2347 {
2348 rtx x = XEXP (link, 0);
2349 if (GET_CODE (x) == CLOBBER)
2350 try_to_add_dest (XEXP (x, 0), flags: rtx_obj_flags::IS_CLOBBER);
2351 else if (GET_CODE (x) == USE)
2352 try_to_add_src (XEXP (x, 0));
2353 }
2354 }
2355 else
2356 try_to_add_pattern (pat: PATTERN (insn));
2357
2358 if (include_notes)
2359 for (rtx note = REG_NOTES (insn); note; note = XEXP (note, 1))
2360 if (REG_NOTE_KIND (note) == REG_EQUAL
2361 || REG_NOTE_KIND (note) == REG_EQUIV)
2362 try_to_add_note (XEXP (note, 0));
2363}
2364
2365/* Grow the storage by a bit while keeping the contents of the first
2366 START elements. */
2367
2368void
2369vec_rtx_properties_base::grow (ptrdiff_t start)
2370{
2371 /* The same heuristic that vec uses. */
2372 ptrdiff_t new_elems = (ref_end - ref_begin) * 3 / 2;
2373 if (ref_begin == m_storage)
2374 {
2375 ref_begin = XNEWVEC (rtx_obj_reference, new_elems);
2376 if (start)
2377 memcpy (dest: ref_begin, src: m_storage, n: start * sizeof (rtx_obj_reference));
2378 }
2379 else
2380 ref_begin = reinterpret_cast<rtx_obj_reference *>
2381 (xrealloc (ref_begin, new_elems * sizeof (rtx_obj_reference)));
2382 ref_iter = ref_begin + start;
2383 ref_end = ref_begin + new_elems;
2384}
2385
2386/* Return true if X's old contents don't survive after INSN.
2387 This will be true if X is a register and X dies in INSN or because
2388 INSN entirely sets X.
2389
2390 "Entirely set" means set directly and not through a SUBREG, or
2391 ZERO_EXTRACT, so no trace of the old contents remains.
2392 Likewise, REG_INC does not count.
2393
2394 REG may be a hard or pseudo reg. Renumbering is not taken into account,
2395 but for this use that makes no difference, since regs don't overlap
2396 during their lifetimes. Therefore, this function may be used
2397 at any time after deaths have been computed.
2398
2399 If REG is a hard reg that occupies multiple machine registers, this
2400 function will only return true if each of those registers will be replaced
2401 by INSN. */
2402
2403bool
2404dead_or_set_p (const rtx_insn *insn, const_rtx x)
2405{
2406 unsigned int regno, end_regno;
2407 unsigned int i;
2408
2409 gcc_assert (REG_P (x));
2410
2411 regno = REGNO (x);
2412 end_regno = END_REGNO (x);
2413 for (i = regno; i < end_regno; i++)
2414 if (! dead_or_set_regno_p (insn, i))
2415 return false;
2416
2417 return true;
2418}
2419
2420/* Return TRUE iff DEST is a register or subreg of a register, is a
2421 complete rather than read-modify-write destination, and contains
2422 register TEST_REGNO. */
2423
2424static bool
2425covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
2426{
2427 unsigned int regno, endregno;
2428
2429 if (GET_CODE (dest) == SUBREG && !read_modify_subreg_p (x: dest))
2430 dest = SUBREG_REG (dest);
2431
2432 if (!REG_P (dest))
2433 return false;
2434
2435 regno = REGNO (dest);
2436 endregno = END_REGNO (x: dest);
2437 return (test_regno >= regno && test_regno < endregno);
2438}
2439
2440/* Like covers_regno_no_parallel_p, but also handles PARALLELs where
2441 any member matches the covers_regno_no_parallel_p criteria. */
2442
2443static bool
2444covers_regno_p (const_rtx dest, unsigned int test_regno)
2445{
2446 if (GET_CODE (dest) == PARALLEL)
2447 {
2448 /* Some targets place small structures in registers for return
2449 values of functions, and those registers are wrapped in
2450 PARALLELs that we may see as the destination of a SET. */
2451 int i;
2452
2453 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--)
2454 {
2455 rtx inner = XEXP (XVECEXP (dest, 0, i), 0);
2456 if (inner != NULL_RTX
2457 && covers_regno_no_parallel_p (dest: inner, test_regno))
2458 return true;
2459 }
2460
2461 return false;
2462 }
2463 else
2464 return covers_regno_no_parallel_p (dest, test_regno);
2465}
2466
2467/* Utility function for dead_or_set_p to check an individual register. */
2468
2469bool
2470dead_or_set_regno_p (const rtx_insn *insn, unsigned int test_regno)
2471{
2472 const_rtx pattern;
2473
2474 /* See if there is a death note for something that includes TEST_REGNO. */
2475 if (find_regno_note (insn, REG_DEAD, test_regno))
2476 return true;
2477
2478 if (CALL_P (insn)
2479 && find_regno_fusage (insn, CLOBBER, test_regno))
2480 return true;
2481
2482 pattern = PATTERN (insn);
2483
2484 /* If a COND_EXEC is not executed, the value survives. */
2485 if (GET_CODE (pattern) == COND_EXEC)
2486 return false;
2487
2488 if (GET_CODE (pattern) == SET || GET_CODE (pattern) == CLOBBER)
2489 return covers_regno_p (SET_DEST (pattern), test_regno);
2490 else if (GET_CODE (pattern) == PARALLEL)
2491 {
2492 int i;
2493
2494 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--)
2495 {
2496 rtx body = XVECEXP (pattern, 0, i);
2497
2498 if (GET_CODE (body) == COND_EXEC)
2499 body = COND_EXEC_CODE (body);
2500
2501 if ((GET_CODE (body) == SET || GET_CODE (body) == CLOBBER)
2502 && covers_regno_p (SET_DEST (body), test_regno))
2503 return true;
2504 }
2505 }
2506
2507 return false;
2508}
2509
2510/* Return the reg-note of kind KIND in insn INSN, if there is one.
2511 If DATUM is nonzero, look for one whose datum is DATUM. */
2512
2513rtx
2514find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum)
2515{
2516 rtx link;
2517
2518 gcc_checking_assert (insn);
2519
2520 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2521 if (! INSN_P (insn))
2522 return 0;
2523 if (datum == 0)
2524 {
2525 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2526 if (REG_NOTE_KIND (link) == kind)
2527 return link;
2528 return 0;
2529 }
2530
2531 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2532 if (REG_NOTE_KIND (link) == kind && datum == XEXP (link, 0))
2533 return link;
2534 return 0;
2535}
2536
2537/* Return the reg-note of kind KIND in insn INSN which applies to register
2538 number REGNO, if any. Return 0 if there is no such reg-note. Note that
2539 the REGNO of this NOTE need not be REGNO if REGNO is a hard register;
2540 it might be the case that the note overlaps REGNO. */
2541
2542rtx
2543find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno)
2544{
2545 rtx link;
2546
2547 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */
2548 if (! INSN_P (insn))
2549 return 0;
2550
2551 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2552 if (REG_NOTE_KIND (link) == kind
2553 /* Verify that it is a register, so that scratch and MEM won't cause a
2554 problem here. */
2555 && REG_P (XEXP (link, 0))
2556 && REGNO (XEXP (link, 0)) <= regno
2557 && END_REGNO (XEXP (link, 0)) > regno)
2558 return link;
2559 return 0;
2560}
2561
2562/* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and
2563 has such a note. */
2564
2565rtx
2566find_reg_equal_equiv_note (const_rtx insn)
2567{
2568 rtx link;
2569
2570 if (!INSN_P (insn))
2571 return 0;
2572
2573 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2574 if (REG_NOTE_KIND (link) == REG_EQUAL
2575 || REG_NOTE_KIND (link) == REG_EQUIV)
2576 {
2577 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on
2578 insns that have multiple sets. Checking single_set to
2579 make sure of this is not the proper check, as explained
2580 in the comment in set_unique_reg_note.
2581
2582 This should be changed into an assert. */
2583 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn))
2584 return 0;
2585 return link;
2586 }
2587 return NULL;
2588}
2589
2590/* Check whether INSN is a single_set whose source is known to be
2591 equivalent to a constant. Return that constant if so, otherwise
2592 return null. */
2593
2594rtx
2595find_constant_src (const rtx_insn *insn)
2596{
2597 rtx note, set, x;
2598
2599 set = single_set (insn);
2600 if (set)
2601 {
2602 x = avoid_constant_pool_reference (SET_SRC (set));
2603 if (CONSTANT_P (x))
2604 return x;
2605 }
2606
2607 note = find_reg_equal_equiv_note (insn);
2608 if (note && CONSTANT_P (XEXP (note, 0)))
2609 return XEXP (note, 0);
2610
2611 return NULL_RTX;
2612}
2613
2614/* Return true if DATUM, or any overlap of DATUM, of kind CODE is found
2615 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2616
2617bool
2618find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum)
2619{
2620 /* If it's not a CALL_INSN, it can't possibly have a
2621 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */
2622 if (!CALL_P (insn))
2623 return false;
2624
2625 gcc_assert (datum);
2626
2627 if (!REG_P (datum))
2628 {
2629 rtx link;
2630
2631 for (link = CALL_INSN_FUNCTION_USAGE (insn);
2632 link;
2633 link = XEXP (link, 1))
2634 if (GET_CODE (XEXP (link, 0)) == code
2635 && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0)))
2636 return true;
2637 }
2638 else
2639 {
2640 unsigned int regno = REGNO (datum);
2641
2642 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2643 to pseudo registers, so don't bother checking. */
2644
2645 if (regno < FIRST_PSEUDO_REGISTER)
2646 {
2647 unsigned int end_regno = END_REGNO (x: datum);
2648 unsigned int i;
2649
2650 for (i = regno; i < end_regno; i++)
2651 if (find_regno_fusage (insn, code, i))
2652 return true;
2653 }
2654 }
2655
2656 return false;
2657}
2658
2659/* Return true if REGNO, or any overlap of REGNO, of kind CODE is found
2660 in the CALL_INSN_FUNCTION_USAGE information of INSN. */
2661
2662bool
2663find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno)
2664{
2665 rtx link;
2666
2667 /* CALL_INSN_FUNCTION_USAGE information cannot contain references
2668 to pseudo registers, so don't bother checking. */
2669
2670 if (regno >= FIRST_PSEUDO_REGISTER
2671 || !CALL_P (insn) )
2672 return false;
2673
2674 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
2675 {
2676 rtx op, reg;
2677
2678 if (GET_CODE (op = XEXP (link, 0)) == code
2679 && REG_P (reg = XEXP (op, 0))
2680 && REGNO (reg) <= regno
2681 && END_REGNO (x: reg) > regno)
2682 return true;
2683 }
2684
2685 return false;
2686}
2687
2688
2689/* Return true if KIND is an integer REG_NOTE. */
2690
2691static bool
2692int_reg_note_p (enum reg_note kind)
2693{
2694 return kind == REG_BR_PROB;
2695}
2696
2697/* Allocate a register note with kind KIND and datum DATUM. LIST is
2698 stored as the pointer to the next register note. */
2699
2700rtx
2701alloc_reg_note (enum reg_note kind, rtx datum, rtx list)
2702{
2703 rtx note;
2704
2705 gcc_checking_assert (!int_reg_note_p (kind));
2706 switch (kind)
2707 {
2708 case REG_LABEL_TARGET:
2709 case REG_LABEL_OPERAND:
2710 case REG_TM:
2711 /* These types of register notes use an INSN_LIST rather than an
2712 EXPR_LIST, so that copying is done right and dumps look
2713 better. */
2714 note = alloc_INSN_LIST (datum, list);
2715 PUT_REG_NOTE_KIND (note, kind);
2716 break;
2717
2718 default:
2719 note = alloc_EXPR_LIST (kind, datum, list);
2720 break;
2721 }
2722
2723 return note;
2724}
2725
2726/* Add register note with kind KIND and datum DATUM to INSN. */
2727
2728void
2729add_reg_note (rtx insn, enum reg_note kind, rtx datum)
2730{
2731 REG_NOTES (insn) = alloc_reg_note (kind, datum, REG_NOTES (insn));
2732}
2733
2734/* Add an integer register note with kind KIND and datum DATUM to INSN. */
2735
2736void
2737add_int_reg_note (rtx_insn *insn, enum reg_note kind, int datum)
2738{
2739 gcc_checking_assert (int_reg_note_p (kind));
2740 REG_NOTES (insn) = gen_rtx_INT_LIST ((machine_mode) kind,
2741 datum, REG_NOTES (insn));
2742}
2743
2744/* Add a REG_ARGS_SIZE note to INSN with value VALUE. */
2745
2746void
2747add_args_size_note (rtx_insn *insn, poly_int64 value)
2748{
2749 gcc_checking_assert (!find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX));
2750 add_reg_note (insn, kind: REG_ARGS_SIZE, datum: gen_int_mode (value, Pmode));
2751}
2752
2753/* Add a register note like NOTE to INSN. */
2754
2755void
2756add_shallow_copy_of_reg_note (rtx_insn *insn, rtx note)
2757{
2758 if (GET_CODE (note) == INT_LIST)
2759 add_int_reg_note (insn, REG_NOTE_KIND (note), XINT (note, 0));
2760 else
2761 add_reg_note (insn, REG_NOTE_KIND (note), XEXP (note, 0));
2762}
2763
2764/* Duplicate NOTE and return the copy. */
2765rtx
2766duplicate_reg_note (rtx note)
2767{
2768 reg_note kind = REG_NOTE_KIND (note);
2769
2770 if (GET_CODE (note) == INT_LIST)
2771 return gen_rtx_INT_LIST ((machine_mode) kind, XINT (note, 0), NULL_RTX);
2772 else if (GET_CODE (note) == EXPR_LIST)
2773 return alloc_reg_note (kind, datum: copy_insn_1 (XEXP (note, 0)), NULL_RTX);
2774 else
2775 return alloc_reg_note (kind, XEXP (note, 0), NULL_RTX);
2776}
2777
2778/* Remove register note NOTE from the REG_NOTES of INSN. */
2779
2780void
2781remove_note (rtx_insn *insn, const_rtx note)
2782{
2783 rtx link;
2784
2785 if (note == NULL_RTX)
2786 return;
2787
2788 if (REG_NOTES (insn) == note)
2789 REG_NOTES (insn) = XEXP (note, 1);
2790 else
2791 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
2792 if (XEXP (link, 1) == note)
2793 {
2794 XEXP (link, 1) = XEXP (note, 1);
2795 break;
2796 }
2797
2798 switch (REG_NOTE_KIND (note))
2799 {
2800 case REG_EQUAL:
2801 case REG_EQUIV:
2802 df_notes_rescan (insn);
2803 break;
2804 default:
2805 break;
2806 }
2807}
2808
2809/* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes.
2810 If NO_RESCAN is false and any notes were removed, call
2811 df_notes_rescan. Return true if any note has been removed. */
2812
2813bool
2814remove_reg_equal_equiv_notes (rtx_insn *insn, bool no_rescan)
2815{
2816 rtx *loc;
2817 bool ret = false;
2818
2819 loc = &REG_NOTES (insn);
2820 while (*loc)
2821 {
2822 enum reg_note kind = REG_NOTE_KIND (*loc);
2823 if (kind == REG_EQUAL || kind == REG_EQUIV)
2824 {
2825 *loc = XEXP (*loc, 1);
2826 ret = true;
2827 }
2828 else
2829 loc = &XEXP (*loc, 1);
2830 }
2831 if (ret && !no_rescan)
2832 df_notes_rescan (insn);
2833 return ret;
2834}
2835
2836/* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */
2837
2838void
2839remove_reg_equal_equiv_notes_for_regno (unsigned int regno)
2840{
2841 df_ref eq_use;
2842
2843 if (!df)
2844 return;
2845
2846 /* This loop is a little tricky. We cannot just go down the chain because
2847 it is being modified by some actions in the loop. So we just iterate
2848 over the head. We plan to drain the list anyway. */
2849 while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)) != NULL)
2850 {
2851 rtx_insn *insn = DF_REF_INSN (eq_use);
2852 rtx note = find_reg_equal_equiv_note (insn);
2853
2854 /* This assert is generally triggered when someone deletes a REG_EQUAL
2855 or REG_EQUIV note by hacking the list manually rather than calling
2856 remove_note. */
2857 gcc_assert (note);
2858
2859 remove_note (insn, note);
2860 }
2861}
2862
2863/* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and
2864 return 1 if it is found. A simple equality test is used to determine if
2865 NODE matches. */
2866
2867bool
2868in_insn_list_p (const rtx_insn_list *listp, const rtx_insn *node)
2869{
2870 const_rtx x;
2871
2872 for (x = listp; x; x = XEXP (x, 1))
2873 if (node == XEXP (x, 0))
2874 return true;
2875
2876 return false;
2877}
2878
2879/* Search LISTP (an INSN_LIST) for an entry whose first operand is NODE and
2880 remove that entry from the list if it is found.
2881
2882 A simple equality test is used to determine if NODE matches. */
2883
2884void
2885remove_node_from_insn_list (const rtx_insn *node, rtx_insn_list **listp)
2886{
2887 rtx_insn_list *temp = *listp;
2888 rtx_insn_list *prev = NULL;
2889
2890 while (temp)
2891 {
2892 if (node == temp->insn ())
2893 {
2894 /* Splice the node out of the list. */
2895 if (prev)
2896 XEXP (prev, 1) = temp->next ();
2897 else
2898 *listp = temp->next ();
2899
2900 gcc_checking_assert (!in_insn_list_p (temp->next (), node));
2901 return;
2902 }
2903
2904 prev = temp;
2905 temp = temp->next ();
2906 }
2907}
2908
2909/* Return true if X contains any volatile instructions. These are instructions
2910 which may cause unpredictable machine state instructions, and thus no
2911 instructions or register uses should be moved or combined across them.
2912 This includes only volatile asms and UNSPEC_VOLATILE instructions. */
2913
2914bool
2915volatile_insn_p (const_rtx x)
2916{
2917 const RTX_CODE code = GET_CODE (x);
2918 switch (code)
2919 {
2920 case LABEL_REF:
2921 case SYMBOL_REF:
2922 case CONST:
2923 CASE_CONST_ANY:
2924 case PC:
2925 case REG:
2926 case SCRATCH:
2927 case CLOBBER:
2928 case ADDR_VEC:
2929 case ADDR_DIFF_VEC:
2930 case CALL:
2931 case MEM:
2932 return false;
2933
2934 case UNSPEC_VOLATILE:
2935 return true;
2936
2937 case ASM_INPUT:
2938 case ASM_OPERANDS:
2939 if (MEM_VOLATILE_P (x))
2940 return true;
2941
2942 default:
2943 break;
2944 }
2945
2946 /* Recursively scan the operands of this expression. */
2947
2948 {
2949 const char *const fmt = GET_RTX_FORMAT (code);
2950 int i;
2951
2952 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
2953 {
2954 if (fmt[i] == 'e')
2955 {
2956 if (volatile_insn_p (XEXP (x, i)))
2957 return true;
2958 }
2959 else if (fmt[i] == 'E')
2960 {
2961 int j;
2962 for (j = 0; j < XVECLEN (x, i); j++)
2963 if (volatile_insn_p (XVECEXP (x, i, j)))
2964 return true;
2965 }
2966 }
2967 }
2968 return false;
2969}
2970
2971/* Return true if X contains any volatile memory references
2972 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */
2973
2974bool
2975volatile_refs_p (const_rtx x)
2976{
2977 const RTX_CODE code = GET_CODE (x);
2978 switch (code)
2979 {
2980 case LABEL_REF:
2981 case SYMBOL_REF:
2982 case CONST:
2983 CASE_CONST_ANY:
2984 case PC:
2985 case REG:
2986 case SCRATCH:
2987 case CLOBBER:
2988 case ADDR_VEC:
2989 case ADDR_DIFF_VEC:
2990 return false;
2991
2992 case UNSPEC_VOLATILE:
2993 return true;
2994
2995 case MEM:
2996 case ASM_INPUT:
2997 case ASM_OPERANDS:
2998 if (MEM_VOLATILE_P (x))
2999 return true;
3000
3001 default:
3002 break;
3003 }
3004
3005 /* Recursively scan the operands of this expression. */
3006
3007 {
3008 const char *const fmt = GET_RTX_FORMAT (code);
3009 int i;
3010
3011 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3012 {
3013 if (fmt[i] == 'e')
3014 {
3015 if (volatile_refs_p (XEXP (x, i)))
3016 return true;
3017 }
3018 else if (fmt[i] == 'E')
3019 {
3020 int j;
3021 for (j = 0; j < XVECLEN (x, i); j++)
3022 if (volatile_refs_p (XVECEXP (x, i, j)))
3023 return true;
3024 }
3025 }
3026 }
3027 return false;
3028}
3029
3030/* Similar to above, except that it also rejects register pre- and post-
3031 incrementing. */
3032
3033bool
3034side_effects_p (const_rtx x)
3035{
3036 const RTX_CODE code = GET_CODE (x);
3037 switch (code)
3038 {
3039 case LABEL_REF:
3040 case SYMBOL_REF:
3041 case CONST:
3042 CASE_CONST_ANY:
3043 case PC:
3044 case REG:
3045 case SCRATCH:
3046 case ADDR_VEC:
3047 case ADDR_DIFF_VEC:
3048 case VAR_LOCATION:
3049 return false;
3050
3051 case CLOBBER:
3052 /* Reject CLOBBER with a non-VOID mode. These are made by combine.cc
3053 when some combination can't be done. If we see one, don't think
3054 that we can simplify the expression. */
3055 return (GET_MODE (x) != VOIDmode);
3056
3057 case PRE_INC:
3058 case PRE_DEC:
3059 case POST_INC:
3060 case POST_DEC:
3061 case PRE_MODIFY:
3062 case POST_MODIFY:
3063 case CALL:
3064 case UNSPEC_VOLATILE:
3065 return true;
3066
3067 case MEM:
3068 case ASM_INPUT:
3069 case ASM_OPERANDS:
3070 if (MEM_VOLATILE_P (x))
3071 return true;
3072
3073 default:
3074 break;
3075 }
3076
3077 /* Recursively scan the operands of this expression. */
3078
3079 {
3080 const char *fmt = GET_RTX_FORMAT (code);
3081 int i;
3082
3083 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3084 {
3085 if (fmt[i] == 'e')
3086 {
3087 if (side_effects_p (XEXP (x, i)))
3088 return true;
3089 }
3090 else if (fmt[i] == 'E')
3091 {
3092 int j;
3093 for (j = 0; j < XVECLEN (x, i); j++)
3094 if (side_effects_p (XVECEXP (x, i, j)))
3095 return true;
3096 }
3097 }
3098 }
3099 return false;
3100}
3101
3102/* Return true if evaluating rtx X might cause a trap.
3103 FLAGS controls how to consider MEMs. A true means the context
3104 of the access may have changed from the original, such that the
3105 address may have become invalid. */
3106
3107bool
3108may_trap_p_1 (const_rtx x, unsigned flags)
3109{
3110 int i;
3111 enum rtx_code code;
3112 const char *fmt;
3113
3114 /* We make no distinction currently, but this function is part of
3115 the internal target-hooks ABI so we keep the parameter as
3116 "unsigned flags". */
3117 bool code_changed = flags != 0;
3118
3119 if (x == 0)
3120 return false;
3121 code = GET_CODE (x);
3122 switch (code)
3123 {
3124 /* Handle these cases quickly. */
3125 CASE_CONST_ANY:
3126 case SYMBOL_REF:
3127 case LABEL_REF:
3128 case CONST:
3129 case PC:
3130 case REG:
3131 case SCRATCH:
3132 return false;
3133
3134 case UNSPEC:
3135 return targetm.unspec_may_trap_p (x, flags);
3136
3137 case UNSPEC_VOLATILE:
3138 case ASM_INPUT:
3139 case TRAP_IF:
3140 return true;
3141
3142 case ASM_OPERANDS:
3143 return MEM_VOLATILE_P (x);
3144
3145 /* Memory ref can trap unless it's a static var or a stack slot. */
3146 case MEM:
3147 /* Recognize specific pattern of stack checking probes. */
3148 if (flag_stack_check
3149 && MEM_VOLATILE_P (x)
3150 && XEXP (x, 0) == stack_pointer_rtx)
3151 return true;
3152 if (/* MEM_NOTRAP_P only relates to the actual position of the memory
3153 reference; moving it out of context such as when moving code
3154 when optimizing, might cause its address to become invalid. */
3155 code_changed
3156 || !MEM_NOTRAP_P (x))
3157 {
3158 poly_int64 size = MEM_SIZE_KNOWN_P (x) ? MEM_SIZE (x) : -1;
3159 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset: 0, size,
3160 GET_MODE (x), unaligned_mems: code_changed);
3161 }
3162
3163 return false;
3164
3165 /* Division by a non-constant might trap. */
3166 case DIV:
3167 case MOD:
3168 case UDIV:
3169 case UMOD:
3170 if (HONOR_SNANS (x))
3171 return true;
3172 if (FLOAT_MODE_P (GET_MODE (x)))
3173 return flag_trapping_math;
3174 if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
3175 return true;
3176 if (GET_CODE (XEXP (x, 1)) == CONST_VECTOR)
3177 {
3178 /* For CONST_VECTOR, return 1 if any element is or might be zero. */
3179 unsigned int n_elts;
3180 rtx op = XEXP (x, 1);
3181 if (!GET_MODE_NUNITS (GET_MODE (op)).is_constant (const_value: &n_elts))
3182 {
3183 if (!CONST_VECTOR_DUPLICATE_P (op))
3184 return true;
3185 for (unsigned i = 0; i < (unsigned int) XVECLEN (op, 0); i++)
3186 if (CONST_VECTOR_ENCODED_ELT (op, i) == const0_rtx)
3187 return true;
3188 }
3189 else
3190 for (unsigned i = 0; i < n_elts; i++)
3191 if (CONST_VECTOR_ELT (op, i) == const0_rtx)
3192 return true;
3193 }
3194 break;
3195
3196 case EXPR_LIST:
3197 /* An EXPR_LIST is used to represent a function call. This
3198 certainly may trap. */
3199 return true;
3200
3201 case GE:
3202 case GT:
3203 case LE:
3204 case LT:
3205 case LTGT:
3206 case COMPARE:
3207 /* Treat min/max similar as comparisons. */
3208 case SMIN:
3209 case SMAX:
3210 /* Some floating point comparisons may trap. */
3211 if (!flag_trapping_math)
3212 break;
3213 /* ??? There is no machine independent way to check for tests that trap
3214 when COMPARE is used, though many targets do make this distinction.
3215 For instance, sparc uses CCFPE for compares which generate exceptions
3216 and CCFP for compares which do not generate exceptions. */
3217 if (HONOR_NANS (x))
3218 return true;
3219 /* But often the compare has some CC mode, so check operand
3220 modes as well. */
3221 if (HONOR_NANS (XEXP (x, 0))
3222 || HONOR_NANS (XEXP (x, 1)))
3223 return true;
3224 break;
3225
3226 case EQ:
3227 case NE:
3228 if (HONOR_SNANS (x))
3229 return true;
3230 /* Often comparison is CC mode, so check operand modes. */
3231 if (HONOR_SNANS (XEXP (x, 0))
3232 || HONOR_SNANS (XEXP (x, 1)))
3233 return true;
3234 break;
3235
3236 case FIX:
3237 case UNSIGNED_FIX:
3238 /* Conversion of floating point might trap. */
3239 if (flag_trapping_math && HONOR_NANS (XEXP (x, 0)))
3240 return true;
3241 break;
3242
3243 case NEG:
3244 case ABS:
3245 case SUBREG:
3246 case VEC_MERGE:
3247 case VEC_SELECT:
3248 case VEC_CONCAT:
3249 case VEC_DUPLICATE:
3250 /* These operations don't trap even with floating point. */
3251 break;
3252
3253 default:
3254 /* Any floating arithmetic may trap. */
3255 if (FLOAT_MODE_P (GET_MODE (x)) && flag_trapping_math)
3256 return true;
3257 }
3258
3259 fmt = GET_RTX_FORMAT (code);
3260 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3261 {
3262 if (fmt[i] == 'e')
3263 {
3264 if (may_trap_p_1 (XEXP (x, i), flags))
3265 return true;
3266 }
3267 else if (fmt[i] == 'E')
3268 {
3269 int j;
3270 for (j = 0; j < XVECLEN (x, i); j++)
3271 if (may_trap_p_1 (XVECEXP (x, i, j), flags))
3272 return true;
3273 }
3274 }
3275 return false;
3276}
3277
3278/* Return true if evaluating rtx X might cause a trap. */
3279
3280bool
3281may_trap_p (const_rtx x)
3282{
3283 return may_trap_p_1 (x, flags: 0);
3284}
3285
3286/* Same as above, but additionally return true if evaluating rtx X might
3287 cause a fault. We define a fault for the purpose of this function as a
3288 erroneous execution condition that cannot be encountered during the normal
3289 execution of a valid program; the typical example is an unaligned memory
3290 access on a strict alignment machine. The compiler guarantees that it
3291 doesn't generate code that will fault from a valid program, but this
3292 guarantee doesn't mean anything for individual instructions. Consider
3293 the following example:
3294
3295 struct S { int d; union { char *cp; int *ip; }; };
3296
3297 int foo(struct S *s)
3298 {
3299 if (s->d == 1)
3300 return *s->ip;
3301 else
3302 return *s->cp;
3303 }
3304
3305 on a strict alignment machine. In a valid program, foo will never be
3306 invoked on a structure for which d is equal to 1 and the underlying
3307 unique field of the union not aligned on a 4-byte boundary, but the
3308 expression *s->ip might cause a fault if considered individually.
3309
3310 At the RTL level, potentially problematic expressions will almost always
3311 verify may_trap_p; for example, the above dereference can be emitted as
3312 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register.
3313 However, suppose that foo is inlined in a caller that causes s->cp to
3314 point to a local character variable and guarantees that s->d is not set
3315 to 1; foo may have been effectively translated into pseudo-RTL as:
3316
3317 if ((reg:SI) == 1)
3318 (set (reg:SI) (mem:SI (%fp - 7)))
3319 else
3320 (set (reg:QI) (mem:QI (%fp - 7)))
3321
3322 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a
3323 memory reference to a stack slot, but it will certainly cause a fault
3324 on a strict alignment machine. */
3325
3326bool
3327may_trap_or_fault_p (const_rtx x)
3328{
3329 return may_trap_p_1 (x, flags: 1);
3330}
3331
3332/* Replace any occurrence of FROM in X with TO. The function does
3333 not enter into CONST_DOUBLE for the replace.
3334
3335 Note that copying is not done so X must not be shared unless all copies
3336 are to be modified.
3337
3338 ALL_REGS is true if we want to replace all REGs equal to FROM, not just
3339 those pointer-equal ones. */
3340
3341rtx
3342replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
3343{
3344 int i, j;
3345 const char *fmt;
3346
3347 if (x == from)
3348 return to;
3349
3350 /* Allow this function to make replacements in EXPR_LISTs. */
3351 if (x == 0)
3352 return 0;
3353
3354 if (all_regs
3355 && REG_P (x)
3356 && REG_P (from)
3357 && REGNO (x) == REGNO (from))
3358 {
3359 gcc_assert (GET_MODE (x) == GET_MODE (from));
3360 return to;
3361 }
3362 else if (GET_CODE (x) == SUBREG)
3363 {
3364 rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to, all_regs);
3365
3366 if (CONST_SCALAR_INT_P (new_rtx))
3367 {
3368 x = simplify_subreg (GET_MODE (x), op: new_rtx,
3369 GET_MODE (SUBREG_REG (x)),
3370 SUBREG_BYTE (x));
3371 gcc_assert (x);
3372 }
3373 else
3374 SUBREG_REG (x) = new_rtx;
3375
3376 return x;
3377 }
3378 else if (GET_CODE (x) == ZERO_EXTEND)
3379 {
3380 rtx new_rtx = replace_rtx (XEXP (x, 0), from, to, all_regs);
3381
3382 if (CONST_SCALAR_INT_P (new_rtx))
3383 {
3384 x = simplify_unary_operation (code: ZERO_EXTEND, GET_MODE (x),
3385 op: new_rtx, GET_MODE (XEXP (x, 0)));
3386 gcc_assert (x);
3387 }
3388 else
3389 XEXP (x, 0) = new_rtx;
3390
3391 return x;
3392 }
3393
3394 fmt = GET_RTX_FORMAT (GET_CODE (x));
3395 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3396 {
3397 if (fmt[i] == 'e')
3398 XEXP (x, i) = replace_rtx (XEXP (x, i), from, to, all_regs);
3399 else if (fmt[i] == 'E')
3400 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3401 XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j),
3402 from, to, all_regs);
3403 }
3404
3405 return x;
3406}
3407
3408/* Replace occurrences of the OLD_LABEL in *LOC with NEW_LABEL. Also track
3409 the change in LABEL_NUSES if UPDATE_LABEL_NUSES. */
3410
3411void
3412replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
3413{
3414 /* Handle jump tables specially, since ADDR_{DIFF_,}VECs can be long. */
3415 rtx x = *loc;
3416 if (JUMP_TABLE_DATA_P (x))
3417 {
3418 x = PATTERN (insn: x);
3419 rtvec vec = XVEC (x, GET_CODE (x) == ADDR_DIFF_VEC);
3420 int len = GET_NUM_ELEM (vec);
3421 for (int i = 0; i < len; ++i)
3422 {
3423 rtx ref = RTVEC_ELT (vec, i);
3424 if (XEXP (ref, 0) == old_label)
3425 {
3426 XEXP (ref, 0) = new_label;
3427 if (update_label_nuses)
3428 {
3429 ++LABEL_NUSES (new_label);
3430 --LABEL_NUSES (old_label);
3431 }
3432 }
3433 }
3434 return;
3435 }
3436
3437 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL
3438 field. This is not handled by the iterator because it doesn't
3439 handle unprinted ('0') fields. */
3440 if (JUMP_P (x) && JUMP_LABEL (x) == old_label)
3441 JUMP_LABEL (x) = new_label;
3442
3443 subrtx_ptr_iterator::array_type array;
3444 FOR_EACH_SUBRTX_PTR (iter, array, loc, ALL)
3445 {
3446 rtx *loc = *iter;
3447 if (rtx x = *loc)
3448 {
3449 if (GET_CODE (x) == SYMBOL_REF
3450 && CONSTANT_POOL_ADDRESS_P (x))
3451 {
3452 rtx c = get_pool_constant (x);
3453 if (rtx_referenced_p (old_label, c))
3454 {
3455 /* Create a copy of constant C; replace the label inside
3456 but do not update LABEL_NUSES because uses in constant pool
3457 are not counted. */
3458 rtx new_c = copy_rtx (c);
3459 replace_label (loc: &new_c, old_label, new_label, update_label_nuses: false);
3460
3461 /* Add the new constant NEW_C to constant pool and replace
3462 the old reference to constant by new reference. */
3463 rtx new_mem = force_const_mem (get_pool_mode (x), new_c);
3464 *loc = replace_rtx (x, from: x, XEXP (new_mem, 0));
3465 }
3466 }
3467
3468 if ((GET_CODE (x) == LABEL_REF
3469 || GET_CODE (x) == INSN_LIST)
3470 && XEXP (x, 0) == old_label)
3471 {
3472 XEXP (x, 0) = new_label;
3473 if (update_label_nuses)
3474 {
3475 ++LABEL_NUSES (new_label);
3476 --LABEL_NUSES (old_label);
3477 }
3478 }
3479 }
3480 }
3481}
3482
3483void
3484replace_label_in_insn (rtx_insn *insn, rtx_insn *old_label,
3485 rtx_insn *new_label, bool update_label_nuses)
3486{
3487 rtx insn_as_rtx = insn;
3488 replace_label (loc: &insn_as_rtx, old_label, new_label, update_label_nuses);
3489 gcc_checking_assert (insn_as_rtx == insn);
3490}
3491
3492/* Return true if X is referenced in BODY. */
3493
3494bool
3495rtx_referenced_p (const_rtx x, const_rtx body)
3496{
3497 subrtx_iterator::array_type array;
3498 FOR_EACH_SUBRTX (iter, array, body, ALL)
3499 if (const_rtx y = *iter)
3500 {
3501 /* Check if a label_ref Y refers to label X. */
3502 if (GET_CODE (y) == LABEL_REF
3503 && LABEL_P (x)
3504 && label_ref_label (ref: y) == x)
3505 return true;
3506
3507 if (rtx_equal_p (x, y))
3508 return true;
3509
3510 /* If Y is a reference to pool constant traverse the constant. */
3511 if (GET_CODE (y) == SYMBOL_REF
3512 && CONSTANT_POOL_ADDRESS_P (y))
3513 iter.substitute (x: get_pool_constant (y));
3514 }
3515 return false;
3516}
3517
3518/* If INSN is a tablejump return true and store the label (before jump table) to
3519 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */
3520
3521bool
3522tablejump_p (const rtx_insn *insn, rtx_insn **labelp,
3523 rtx_jump_table_data **tablep)
3524{
3525 if (!JUMP_P (insn))
3526 return false;
3527
3528 rtx target = JUMP_LABEL (insn);
3529 if (target == NULL_RTX || ANY_RETURN_P (target))
3530 return false;
3531
3532 rtx_insn *label = as_a<rtx_insn *> (p: target);
3533 rtx_insn *table = next_insn (label);
3534 if (table == NULL_RTX || !JUMP_TABLE_DATA_P (table))
3535 return false;
3536
3537 if (labelp)
3538 *labelp = label;
3539 if (tablep)
3540 *tablep = as_a <rtx_jump_table_data *> (p: table);
3541 return true;
3542}
3543
3544/* For INSN known to satisfy tablejump_p, determine if it actually is a
3545 CASESI. Return the insn pattern if so, NULL_RTX otherwise. */
3546
3547rtx
3548tablejump_casesi_pattern (const rtx_insn *insn)
3549{
3550 rtx tmp;
3551
3552 if ((tmp = single_set (insn)) != NULL
3553 && SET_DEST (tmp) == pc_rtx
3554 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3555 && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
3556 return tmp;
3557
3558 return NULL_RTX;
3559}
3560
3561/* A subroutine of computed_jump_p, return true if X contains a REG or MEM or
3562 constant that is not in the constant pool and not in the condition
3563 of an IF_THEN_ELSE. */
3564
3565static bool
3566computed_jump_p_1 (const_rtx x)
3567{
3568 const enum rtx_code code = GET_CODE (x);
3569 int i, j;
3570 const char *fmt;
3571
3572 switch (code)
3573 {
3574 case LABEL_REF:
3575 case PC:
3576 return false;
3577
3578 case CONST:
3579 CASE_CONST_ANY:
3580 case SYMBOL_REF:
3581 case REG:
3582 return true;
3583
3584 case MEM:
3585 return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
3586 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
3587
3588 case IF_THEN_ELSE:
3589 return (computed_jump_p_1 (XEXP (x, 1))
3590 || computed_jump_p_1 (XEXP (x, 2)));
3591
3592 default:
3593 break;
3594 }
3595
3596 fmt = GET_RTX_FORMAT (code);
3597 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3598 {
3599 if (fmt[i] == 'e'
3600 && computed_jump_p_1 (XEXP (x, i)))
3601 return true;
3602
3603 else if (fmt[i] == 'E')
3604 for (j = 0; j < XVECLEN (x, i); j++)
3605 if (computed_jump_p_1 (XVECEXP (x, i, j)))
3606 return true;
3607 }
3608
3609 return false;
3610}
3611
3612/* Return true if INSN is an indirect jump (aka computed jump).
3613
3614 Tablejumps and casesi insns are not considered indirect jumps;
3615 we can recognize them by a (use (label_ref)). */
3616
3617bool
3618computed_jump_p (const rtx_insn *insn)
3619{
3620 int i;
3621 if (JUMP_P (insn))
3622 {
3623 rtx pat = PATTERN (insn);
3624
3625 /* If we have a JUMP_LABEL set, we're not a computed jump. */
3626 if (JUMP_LABEL (insn) != NULL)
3627 return false;
3628
3629 if (GET_CODE (pat) == PARALLEL)
3630 {
3631 int len = XVECLEN (pat, 0);
3632 bool has_use_labelref = false;
3633
3634 for (i = len - 1; i >= 0; i--)
3635 if (GET_CODE (XVECEXP (pat, 0, i)) == USE
3636 && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
3637 == LABEL_REF))
3638 {
3639 has_use_labelref = true;
3640 break;
3641 }
3642
3643 if (! has_use_labelref)
3644 for (i = len - 1; i >= 0; i--)
3645 if (GET_CODE (XVECEXP (pat, 0, i)) == SET
3646 && SET_DEST (XVECEXP (pat, 0, i)) == pc_rtx
3647 && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i))))
3648 return true;
3649 }
3650 else if (GET_CODE (pat) == SET
3651 && SET_DEST (pat) == pc_rtx
3652 && computed_jump_p_1 (SET_SRC (pat)))
3653 return true;
3654 }
3655 return false;
3656}
3657
3658
3659
3660/* MEM has a PRE/POST-INC/DEC/MODIFY address X. Extract the operands of
3661 the equivalent add insn and pass the result to FN, using DATA as the
3662 final argument. */
3663
3664static int
3665for_each_inc_dec_find_inc_dec (rtx mem, for_each_inc_dec_fn fn, void *data)
3666{
3667 rtx x = XEXP (mem, 0);
3668 switch (GET_CODE (x))
3669 {
3670 case PRE_INC:
3671 case POST_INC:
3672 {
3673 poly_int64 size = GET_MODE_SIZE (GET_MODE (mem));
3674 rtx r1 = XEXP (x, 0);
3675 rtx c = gen_int_mode (size, GET_MODE (r1));
3676 return fn (mem, x, r1, r1, c, data);
3677 }
3678
3679 case PRE_DEC:
3680 case POST_DEC:
3681 {
3682 poly_int64 size = GET_MODE_SIZE (GET_MODE (mem));
3683 rtx r1 = XEXP (x, 0);
3684 rtx c = gen_int_mode (-size, GET_MODE (r1));
3685 return fn (mem, x, r1, r1, c, data);
3686 }
3687
3688 case PRE_MODIFY:
3689 case POST_MODIFY:
3690 {
3691 rtx r1 = XEXP (x, 0);
3692 rtx add = XEXP (x, 1);
3693 return fn (mem, x, r1, add, NULL, data);
3694 }
3695
3696 default:
3697 gcc_unreachable ();
3698 }
3699}
3700
3701/* Traverse *LOC looking for MEMs that have autoinc addresses.
3702 For each such autoinc operation found, call FN, passing it
3703 the innermost enclosing MEM, the operation itself, the RTX modified
3704 by the operation, two RTXs (the second may be NULL) that, once
3705 added, represent the value to be held by the modified RTX
3706 afterwards, and DATA. FN is to return 0 to continue the
3707 traversal or any other value to have it returned to the caller of
3708 for_each_inc_dec. */
3709
3710int
3711for_each_inc_dec (rtx x,
3712 for_each_inc_dec_fn fn,
3713 void *data)
3714{
3715 subrtx_var_iterator::array_type array;
3716 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
3717 {
3718 rtx mem = *iter;
3719 if (mem
3720 && MEM_P (mem)
3721 && GET_RTX_CLASS (GET_CODE (XEXP (mem, 0))) == RTX_AUTOINC)
3722 {
3723 int res = for_each_inc_dec_find_inc_dec (mem, fn, data);
3724 if (res != 0)
3725 return res;
3726 iter.skip_subrtxes ();
3727 }
3728 }
3729 return 0;
3730}
3731
3732
3733/* Searches X for any reference to REGNO, returning the rtx of the
3734 reference found if any. Otherwise, returns NULL_RTX. */
3735
3736rtx
3737regno_use_in (unsigned int regno, rtx x)
3738{
3739 const char *fmt;
3740 int i, j;
3741 rtx tem;
3742
3743 if (REG_P (x) && REGNO (x) == regno)
3744 return x;
3745
3746 fmt = GET_RTX_FORMAT (GET_CODE (x));
3747 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
3748 {
3749 if (fmt[i] == 'e')
3750 {
3751 if ((tem = regno_use_in (regno, XEXP (x, i))))
3752 return tem;
3753 }
3754 else if (fmt[i] == 'E')
3755 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3756 if ((tem = regno_use_in (regno , XVECEXP (x, i, j))))
3757 return tem;
3758 }
3759
3760 return NULL_RTX;
3761}
3762
3763/* Return a value indicating whether OP, an operand of a commutative
3764 operation, is preferred as the first or second operand. The more
3765 positive the value, the stronger the preference for being the first
3766 operand. */
3767
3768int
3769commutative_operand_precedence (rtx op)
3770{
3771 enum rtx_code code = GET_CODE (op);
3772
3773 /* Constants always become the second operand. Prefer "nice" constants. */
3774 if (code == CONST_INT)
3775 return -10;
3776 if (code == CONST_WIDE_INT)
3777 return -9;
3778 if (code == CONST_POLY_INT)
3779 return -8;
3780 if (code == CONST_DOUBLE)
3781 return -8;
3782 if (code == CONST_FIXED)
3783 return -8;
3784 op = avoid_constant_pool_reference (op);
3785 code = GET_CODE (op);
3786
3787 switch (GET_RTX_CLASS (code))
3788 {
3789 case RTX_CONST_OBJ:
3790 if (code == CONST_INT)
3791 return -7;
3792 if (code == CONST_WIDE_INT)
3793 return -6;
3794 if (code == CONST_POLY_INT)
3795 return -5;
3796 if (code == CONST_DOUBLE)
3797 return -5;
3798 if (code == CONST_FIXED)
3799 return -5;
3800 return -4;
3801
3802 case RTX_EXTRA:
3803 /* SUBREGs of objects should come second. */
3804 if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
3805 return -3;
3806 return 0;
3807
3808 case RTX_OBJ:
3809 /* Complex expressions should be the first, so decrease priority
3810 of objects. Prefer pointer objects over non pointer objects. */
3811 if ((REG_P (op) && REG_POINTER (op))
3812 || (MEM_P (op) && MEM_POINTER (op)))
3813 return -1;
3814 return -2;
3815
3816 case RTX_COMM_ARITH:
3817 /* Prefer operands that are themselves commutative to be first.
3818 This helps to make things linear. In particular,
3819 (and (and (reg) (reg)) (not (reg))) is canonical. */
3820 return 4;
3821
3822 case RTX_BIN_ARITH:
3823 /* If only one operand is a binary expression, it will be the first
3824 operand. In particular, (plus (minus (reg) (reg)) (neg (reg)))
3825 is canonical, although it will usually be further simplified. */
3826 return 2;
3827
3828 case RTX_UNARY:
3829 /* Then prefer NEG and NOT. */
3830 if (code == NEG || code == NOT)
3831 return 1;
3832 /* FALLTHRU */
3833
3834 default:
3835 return 0;
3836 }
3837}
3838
3839/* Return true iff it is necessary to swap operands of commutative operation
3840 in order to canonicalize expression. */
3841
3842bool
3843swap_commutative_operands_p (rtx x, rtx y)
3844{
3845 return (commutative_operand_precedence (op: x)
3846 < commutative_operand_precedence (op: y));
3847}
3848
3849/* Return true if X is an autoincrement side effect and the register is
3850 not the stack pointer. */
3851bool
3852auto_inc_p (const_rtx x)
3853{
3854 switch (GET_CODE (x))
3855 {
3856 case PRE_INC:
3857 case POST_INC:
3858 case PRE_DEC:
3859 case POST_DEC:
3860 case PRE_MODIFY:
3861 case POST_MODIFY:
3862 /* There are no REG_INC notes for SP. */
3863 if (XEXP (x, 0) != stack_pointer_rtx)
3864 return true;
3865 default:
3866 break;
3867 }
3868 return false;
3869}
3870
3871/* Return true if IN contains a piece of rtl that has the address LOC. */
3872bool
3873loc_mentioned_in_p (rtx *loc, const_rtx in)
3874{
3875 enum rtx_code code;
3876 const char *fmt;
3877 int i, j;
3878
3879 if (!in)
3880 return false;
3881
3882 code = GET_CODE (in);
3883 fmt = GET_RTX_FORMAT (code);
3884 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3885 {
3886 if (fmt[i] == 'e')
3887 {
3888 if (loc == &XEXP (in, i) || loc_mentioned_in_p (loc, XEXP (in, i)))
3889 return true;
3890 }
3891 else if (fmt[i] == 'E')
3892 for (j = XVECLEN (in, i) - 1; j >= 0; j--)
3893 if (loc == &XVECEXP (in, i, j)
3894 || loc_mentioned_in_p (loc, XVECEXP (in, i, j)))
3895 return true;
3896 }
3897 return false;
3898}
3899
3900/* Reinterpret a subreg as a bit extraction from an integer and return
3901 the position of the least significant bit of the extracted value.
3902 In other words, if the extraction were performed as a shift right
3903 and mask, return the number of bits to shift right.
3904
3905 The outer value of the subreg has OUTER_BYTES bytes and starts at
3906 byte offset SUBREG_BYTE within an inner value of INNER_BYTES bytes. */
3907
3908poly_uint64
3909subreg_size_lsb (poly_uint64 outer_bytes,
3910 poly_uint64 inner_bytes,
3911 poly_uint64 subreg_byte)
3912{
3913 poly_uint64 subreg_end, trailing_bytes, byte_pos;
3914
3915 /* A paradoxical subreg begins at bit position 0. */
3916 gcc_checking_assert (ordered_p (outer_bytes, inner_bytes));
3917 if (maybe_gt (outer_bytes, inner_bytes))
3918 {
3919 gcc_checking_assert (known_eq (subreg_byte, 0U));
3920 return 0;
3921 }
3922
3923 subreg_end = subreg_byte + outer_bytes;
3924 trailing_bytes = inner_bytes - subreg_end;
3925 if (WORDS_BIG_ENDIAN && BYTES_BIG_ENDIAN)
3926 byte_pos = trailing_bytes;
3927 else if (!WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN)
3928 byte_pos = subreg_byte;
3929 else
3930 {
3931 /* When bytes and words have opposite endianness, we must be able
3932 to split offsets into words and bytes at compile time. */
3933 poly_uint64 leading_word_part
3934 = force_align_down (value: subreg_byte, UNITS_PER_WORD);
3935 poly_uint64 trailing_word_part
3936 = force_align_down (value: trailing_bytes, UNITS_PER_WORD);
3937 /* If the subreg crosses a word boundary ensure that
3938 it also begins and ends on a word boundary. */
3939 gcc_assert (known_le (subreg_end - leading_word_part,
3940 (unsigned int) UNITS_PER_WORD)
3941 || (known_eq (leading_word_part, subreg_byte)
3942 && known_eq (trailing_word_part, trailing_bytes)));
3943 if (WORDS_BIG_ENDIAN)
3944 byte_pos = trailing_word_part + (subreg_byte - leading_word_part);
3945 else
3946 byte_pos = leading_word_part + (trailing_bytes - trailing_word_part);
3947 }
3948
3949 return byte_pos * BITS_PER_UNIT;
3950}
3951
3952/* Given a subreg X, return the bit offset where the subreg begins
3953 (counting from the least significant bit of the reg). */
3954
3955poly_uint64
3956subreg_lsb (const_rtx x)
3957{
3958 return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)),
3959 SUBREG_BYTE (x));
3960}
3961
3962/* Return the subreg byte offset for a subreg whose outer value has
3963 OUTER_BYTES bytes, whose inner value has INNER_BYTES bytes, and where
3964 there are LSB_SHIFT *bits* between the lsb of the outer value and the
3965 lsb of the inner value. This is the inverse of the calculation
3966 performed by subreg_lsb_1 (which converts byte offsets to bit shifts). */
3967
3968poly_uint64
3969subreg_size_offset_from_lsb (poly_uint64 outer_bytes, poly_uint64 inner_bytes,
3970 poly_uint64 lsb_shift)
3971{
3972 /* A paradoxical subreg begins at bit position 0. */
3973 gcc_checking_assert (ordered_p (outer_bytes, inner_bytes));
3974 if (maybe_gt (outer_bytes, inner_bytes))
3975 {
3976 gcc_checking_assert (known_eq (lsb_shift, 0U));
3977 return 0;
3978 }
3979
3980 poly_uint64 lower_bytes = exact_div (a: lsb_shift, BITS_PER_UNIT);
3981 poly_uint64 upper_bytes = inner_bytes - (lower_bytes + outer_bytes);
3982 if (WORDS_BIG_ENDIAN && BYTES_BIG_ENDIAN)
3983 return upper_bytes;
3984 else if (!WORDS_BIG_ENDIAN && !BYTES_BIG_ENDIAN)
3985 return lower_bytes;
3986 else
3987 {
3988 /* When bytes and words have opposite endianness, we must be able
3989 to split offsets into words and bytes at compile time. */
3990 poly_uint64 lower_word_part = force_align_down (value: lower_bytes,
3991 UNITS_PER_WORD);
3992 poly_uint64 upper_word_part = force_align_down (value: upper_bytes,
3993 UNITS_PER_WORD);
3994 if (WORDS_BIG_ENDIAN)
3995 return upper_word_part + (lower_bytes - lower_word_part);
3996 else
3997 return lower_word_part + (upper_bytes - upper_word_part);
3998 }
3999}
4000
4001/* Fill in information about a subreg of a hard register.
4002 xregno - A regno of an inner hard subreg_reg (or what will become one).
4003 xmode - The mode of xregno.
4004 offset - The byte offset.
4005 ymode - The mode of a top level SUBREG (or what may become one).
4006 info - Pointer to structure to fill in.
4007
4008 Rather than considering one particular inner register (and thus one
4009 particular "outer" register) in isolation, this function really uses
4010 XREGNO as a model for a sequence of isomorphic hard registers. Thus the
4011 function does not check whether adding INFO->offset to XREGNO gives
4012 a valid hard register; even if INFO->offset + XREGNO is out of range,
4013 there might be another register of the same type that is in range.
4014 Likewise it doesn't check whether targetm.hard_regno_mode_ok accepts
4015 the new register, since that can depend on things like whether the final
4016 register number is even or odd. Callers that want to check whether
4017 this particular subreg can be replaced by a simple (reg ...) should
4018 use simplify_subreg_regno. */
4019
4020void
4021subreg_get_info (unsigned int xregno, machine_mode xmode,
4022 poly_uint64 offset, machine_mode ymode,
4023 struct subreg_info *info)
4024{
4025 unsigned int nregs_xmode, nregs_ymode;
4026
4027 gcc_assert (xregno < FIRST_PSEUDO_REGISTER);
4028
4029 poly_uint64 xsize = GET_MODE_SIZE (mode: xmode);
4030 poly_uint64 ysize = GET_MODE_SIZE (mode: ymode);
4031
4032 bool rknown = false;
4033
4034 /* If the register representation of a non-scalar mode has holes in it,
4035 we expect the scalar units to be concatenated together, with the holes
4036 distributed evenly among the scalar units. Each scalar unit must occupy
4037 at least one register. */
4038 if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode))
4039 {
4040 /* As a consequence, we must be dealing with a constant number of
4041 scalars, and thus a constant offset and number of units. */
4042 HOST_WIDE_INT coffset = offset.to_constant ();
4043 HOST_WIDE_INT cysize = ysize.to_constant ();
4044 nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode);
4045 unsigned int nunits = GET_MODE_NUNITS (mode: xmode).to_constant ();
4046 scalar_mode xmode_unit = GET_MODE_INNER (xmode);
4047 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit));
4048 gcc_assert (nregs_xmode
4049 == (nunits
4050 * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit)));
4051 gcc_assert (hard_regno_nregs (xregno, xmode)
4052 == hard_regno_nregs (xregno, xmode_unit) * nunits);
4053
4054 /* You can only ask for a SUBREG of a value with holes in the middle
4055 if you don't cross the holes. (Such a SUBREG should be done by
4056 picking a different register class, or doing it in memory if
4057 necessary.) An example of a value with holes is XCmode on 32-bit
4058 x86 with -m128bit-long-double; it's represented in 6 32-bit registers,
4059 3 for each part, but in memory it's two 128-bit parts.
4060 Padding is assumed to be at the end (not necessarily the 'high part')
4061 of each unit. */
4062 if ((coffset / GET_MODE_SIZE (mode: xmode_unit) + 1 < nunits)
4063 && (coffset / GET_MODE_SIZE (mode: xmode_unit)
4064 != ((coffset + cysize - 1) / GET_MODE_SIZE (mode: xmode_unit))))
4065 {
4066 info->representable_p = false;
4067 rknown = true;
4068 }
4069 }
4070 else
4071 nregs_xmode = hard_regno_nregs (regno: xregno, mode: xmode);
4072
4073 nregs_ymode = hard_regno_nregs (regno: xregno, mode: ymode);
4074
4075 /* Subreg sizes must be ordered, so that we can tell whether they are
4076 partial, paradoxical or complete. */
4077 gcc_checking_assert (ordered_p (xsize, ysize));
4078
4079 /* Paradoxical subregs are otherwise valid. */
4080 if (!rknown && known_eq (offset, 0U) && maybe_gt (ysize, xsize))
4081 {
4082 info->representable_p = true;
4083 /* If this is a big endian paradoxical subreg, which uses more
4084 actual hard registers than the original register, we must
4085 return a negative offset so that we find the proper highpart
4086 of the register.
4087
4088 We assume that the ordering of registers within a multi-register
4089 value has a consistent endianness: if bytes and register words
4090 have different endianness, the hard registers that make up a
4091 multi-register value must be at least word-sized. */
4092 if (REG_WORDS_BIG_ENDIAN)
4093 info->offset = (int) nregs_xmode - (int) nregs_ymode;
4094 else
4095 info->offset = 0;
4096 info->nregs = nregs_ymode;
4097 return;
4098 }
4099
4100 /* If registers store different numbers of bits in the different
4101 modes, we cannot generally form this subreg. */
4102 poly_uint64 regsize_xmode, regsize_ymode;
4103 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)
4104 && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode)
4105 && multiple_p (a: xsize, b: nregs_xmode, multiple: &regsize_xmode)
4106 && multiple_p (a: ysize, b: nregs_ymode, multiple: &regsize_ymode))
4107 {
4108 if (!rknown
4109 && ((nregs_ymode > 1 && maybe_gt (regsize_xmode, regsize_ymode))
4110 || (nregs_xmode > 1 && maybe_gt (regsize_ymode, regsize_xmode))))
4111 {
4112 info->representable_p = false;
4113 if (!can_div_away_from_zero_p (a: ysize, b: regsize_xmode, quotient: &info->nregs)
4114 || !can_div_trunc_p (a: offset, b: regsize_xmode, quotient: &info->offset))
4115 /* Checked by validate_subreg. We must know at compile time
4116 which inner registers are being accessed. */
4117 gcc_unreachable ();
4118 return;
4119 }
4120 /* It's not valid to extract a subreg of mode YMODE at OFFSET that
4121 would go outside of XMODE. */
4122 if (!rknown && maybe_gt (ysize + offset, xsize))
4123 {
4124 info->representable_p = false;
4125 info->nregs = nregs_ymode;
4126 if (!can_div_trunc_p (a: offset, b: regsize_xmode, quotient: &info->offset))
4127 /* Checked by validate_subreg. We must know at compile time
4128 which inner registers are being accessed. */
4129 gcc_unreachable ();
4130 return;
4131 }
4132 /* Quick exit for the simple and common case of extracting whole
4133 subregisters from a multiregister value. */
4134 /* ??? It would be better to integrate this into the code below,
4135 if we can generalize the concept enough and figure out how
4136 odd-sized modes can coexist with the other weird cases we support. */
4137 HOST_WIDE_INT count;
4138 if (!rknown
4139 && WORDS_BIG_ENDIAN == REG_WORDS_BIG_ENDIAN
4140 && known_eq (regsize_xmode, regsize_ymode)
4141 && constant_multiple_p (a: offset, b: regsize_ymode, multiple: &count))
4142 {
4143 info->representable_p = true;
4144 info->nregs = nregs_ymode;
4145 info->offset = count;
4146 gcc_assert (info->offset + info->nregs <= (int) nregs_xmode);
4147 return;
4148 }
4149 }
4150
4151 /* Lowpart subregs are otherwise valid. */
4152 if (!rknown && known_eq (offset, subreg_lowpart_offset (ymode, xmode)))
4153 {
4154 info->representable_p = true;
4155 rknown = true;
4156
4157 if (known_eq (offset, 0U) || nregs_xmode == nregs_ymode)
4158 {
4159 info->offset = 0;
4160 info->nregs = nregs_ymode;
4161 return;
4162 }
4163 }
4164
4165 /* Set NUM_BLOCKS to the number of independently-representable YMODE
4166 values there are in (reg:XMODE XREGNO). We can view the register
4167 as consisting of this number of independent "blocks", where each
4168 block occupies NREGS_YMODE registers and contains exactly one
4169 representable YMODE value. */
4170 gcc_assert ((nregs_xmode % nregs_ymode) == 0);
4171 unsigned int num_blocks = nregs_xmode / nregs_ymode;
4172
4173 /* Calculate the number of bytes in each block. This must always
4174 be exact, otherwise we don't know how to verify the constraint.
4175 These conditions may be relaxed but subreg_regno_offset would
4176 need to be redesigned. */
4177 poly_uint64 bytes_per_block = exact_div (a: xsize, b: num_blocks);
4178
4179 /* Get the number of the first block that contains the subreg and the byte
4180 offset of the subreg from the start of that block. */
4181 unsigned int block_number;
4182 poly_uint64 subblock_offset;
4183 if (!can_div_trunc_p (a: offset, b: bytes_per_block, quotient: &block_number,
4184 remainder: &subblock_offset))
4185 /* Checked by validate_subreg. We must know at compile time which
4186 inner registers are being accessed. */
4187 gcc_unreachable ();
4188
4189 if (!rknown)
4190 {
4191 /* Only the lowpart of each block is representable. */
4192 info->representable_p
4193 = known_eq (subblock_offset,
4194 subreg_size_lowpart_offset (ysize, bytes_per_block));
4195 rknown = true;
4196 }
4197
4198 /* We assume that the ordering of registers within a multi-register
4199 value has a consistent endianness: if bytes and register words
4200 have different endianness, the hard registers that make up a
4201 multi-register value must be at least word-sized. */
4202 if (WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN)
4203 /* The block number we calculated above followed memory endianness.
4204 Convert it to register endianness by counting back from the end.
4205 (Note that, because of the assumption above, each block must be
4206 at least word-sized.) */
4207 info->offset = (num_blocks - block_number - 1) * nregs_ymode;
4208 else
4209 info->offset = block_number * nregs_ymode;
4210 info->nregs = nregs_ymode;
4211}
4212
4213/* This function returns the regno offset of a subreg expression.
4214 xregno - A regno of an inner hard subreg_reg (or what will become one).
4215 xmode - The mode of xregno.
4216 offset - The byte offset.
4217 ymode - The mode of a top level SUBREG (or what may become one).
4218 RETURN - The regno offset which would be used. */
4219unsigned int
4220subreg_regno_offset (unsigned int xregno, machine_mode xmode,
4221 poly_uint64 offset, machine_mode ymode)
4222{
4223 struct subreg_info info;
4224 subreg_get_info (xregno, xmode, offset, ymode, info: &info);
4225 return info.offset;
4226}
4227
4228/* This function returns true when the offset is representable via
4229 subreg_offset in the given regno.
4230 xregno - A regno of an inner hard subreg_reg (or what will become one).
4231 xmode - The mode of xregno.
4232 offset - The byte offset.
4233 ymode - The mode of a top level SUBREG (or what may become one).
4234 RETURN - Whether the offset is representable. */
4235bool
4236subreg_offset_representable_p (unsigned int xregno, machine_mode xmode,
4237 poly_uint64 offset, machine_mode ymode)
4238{
4239 struct subreg_info info;
4240 subreg_get_info (xregno, xmode, offset, ymode, info: &info);
4241 return info.representable_p;
4242}
4243
4244/* Return the number of a YMODE register to which
4245
4246 (subreg:YMODE (reg:XMODE XREGNO) OFFSET)
4247
4248 can be simplified. Return -1 if the subreg can't be simplified.
4249
4250 XREGNO is a hard register number. */
4251
4252int
4253simplify_subreg_regno (unsigned int xregno, machine_mode xmode,
4254 poly_uint64 offset, machine_mode ymode)
4255{
4256 struct subreg_info info;
4257 unsigned int yregno;
4258
4259 /* Give the backend a chance to disallow the mode change. */
4260 if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT
4261 && GET_MODE_CLASS (xmode) != MODE_COMPLEX_FLOAT
4262 && !REG_CAN_CHANGE_MODE_P (xregno, xmode, ymode))
4263 return -1;
4264
4265 /* We shouldn't simplify stack-related registers. */
4266 if ((!reload_completed || frame_pointer_needed)
4267 && xregno == FRAME_POINTER_REGNUM)
4268 return -1;
4269
4270 if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
4271 && xregno == ARG_POINTER_REGNUM)
4272 return -1;
4273
4274 if (xregno == STACK_POINTER_REGNUM
4275 /* We should convert hard stack register in LRA if it is
4276 possible. */
4277 && ! lra_in_progress)
4278 return -1;
4279
4280 /* Try to get the register offset. */
4281 subreg_get_info (xregno, xmode, offset, ymode, info: &info);
4282 if (!info.representable_p)
4283 return -1;
4284
4285 /* Make sure that the offsetted register value is in range. */
4286 yregno = xregno + info.offset;
4287 if (!HARD_REGISTER_NUM_P (yregno))
4288 return -1;
4289
4290 /* See whether (reg:YMODE YREGNO) is valid.
4291
4292 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid.
4293 This is a kludge to work around how complex FP arguments are passed
4294 on IA-64 and should be fixed. See PR target/49226. */
4295 if (!targetm.hard_regno_mode_ok (yregno, ymode)
4296 && targetm.hard_regno_mode_ok (xregno, xmode))
4297 return -1;
4298
4299 return (int) yregno;
4300}
4301
4302/* A wrapper around simplify_subreg_regno that uses subreg_lowpart_offset
4303 (xmode, ymode) as the offset. */
4304
4305int
4306lowpart_subreg_regno (unsigned int regno, machine_mode xmode,
4307 machine_mode ymode)
4308{
4309 poly_uint64 offset = subreg_lowpart_offset (outermode: xmode, innermode: ymode);
4310 return simplify_subreg_regno (xregno: regno, xmode, offset, ymode);
4311}
4312
4313/* Return the final regno that a subreg expression refers to. */
4314unsigned int
4315subreg_regno (const_rtx x)
4316{
4317 unsigned int ret;
4318 rtx subreg = SUBREG_REG (x);
4319 int regno = REGNO (subreg);
4320
4321 ret = regno + subreg_regno_offset (xregno: regno,
4322 GET_MODE (subreg),
4323 SUBREG_BYTE (x),
4324 GET_MODE (x));
4325 return ret;
4326
4327}
4328
4329/* Return the number of registers that a subreg expression refers
4330 to. */
4331unsigned int
4332subreg_nregs (const_rtx x)
4333{
4334 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x)), x);
4335}
4336
4337/* Return the number of registers that a subreg REG with REGNO
4338 expression refers to. This is a copy of the rtlanal.cc:subreg_nregs
4339 changed so that the regno can be passed in. */
4340
4341unsigned int
4342subreg_nregs_with_regno (unsigned int regno, const_rtx x)
4343{
4344 struct subreg_info info;
4345 rtx subreg = SUBREG_REG (x);
4346
4347 subreg_get_info (xregno: regno, GET_MODE (subreg), SUBREG_BYTE (x), GET_MODE (x),
4348 info: &info);
4349 return info.nregs;
4350}
4351
4352struct parms_set_data
4353{
4354 int nregs;
4355 HARD_REG_SET regs;
4356};
4357
4358/* Helper function for noticing stores to parameter registers. */
4359static void
4360parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
4361{
4362 struct parms_set_data *const d = (struct parms_set_data *) data;
4363 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER
4364 && TEST_HARD_REG_BIT (set: d->regs, REGNO (x)))
4365 {
4366 CLEAR_HARD_REG_BIT (set&: d->regs, REGNO (x));
4367 d->nregs--;
4368 }
4369}
4370
4371/* Look backward for first parameter to be loaded.
4372 Note that loads of all parameters will not necessarily be
4373 found if CSE has eliminated some of them (e.g., an argument
4374 to the outer function is passed down as a parameter).
4375 Do not skip BOUNDARY. */
4376rtx_insn *
4377find_first_parameter_load (rtx_insn *call_insn, rtx_insn *boundary)
4378{
4379 struct parms_set_data parm;
4380 rtx p;
4381 rtx_insn *before, *first_set;
4382
4383 /* Since different machines initialize their parameter registers
4384 in different orders, assume nothing. Collect the set of all
4385 parameter registers. */
4386 CLEAR_HARD_REG_SET (set&: parm.regs);
4387 parm.nregs = 0;
4388 for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1))
4389 if (GET_CODE (XEXP (p, 0)) == USE
4390 && REG_P (XEXP (XEXP (p, 0), 0))
4391 && !STATIC_CHAIN_REG_P (XEXP (XEXP (p, 0), 0)))
4392 {
4393 gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER);
4394
4395 /* We only care about registers which can hold function
4396 arguments. */
4397 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0))))
4398 continue;
4399
4400 SET_HARD_REG_BIT (set&: parm.regs, REGNO (XEXP (XEXP (p, 0), 0)));
4401 parm.nregs++;
4402 }
4403 before = call_insn;
4404 first_set = call_insn;
4405
4406 /* Search backward for the first set of a register in this set. */
4407 while (parm.nregs && before != boundary)
4408 {
4409 before = PREV_INSN (insn: before);
4410
4411 /* It is possible that some loads got CSEed from one call to
4412 another. Stop in that case. */
4413 if (CALL_P (before))
4414 break;
4415
4416 /* Our caller needs either ensure that we will find all sets
4417 (in case code has not been optimized yet), or take care
4418 for possible labels in a way by setting boundary to preceding
4419 CODE_LABEL. */
4420 if (LABEL_P (before))
4421 {
4422 gcc_assert (before == boundary);
4423 break;
4424 }
4425
4426 if (INSN_P (before))
4427 {
4428 int nregs_old = parm.nregs;
4429 note_stores (insn: before, fun: parms_set, data: &parm);
4430 /* If we found something that did not set a parameter reg,
4431 we're done. Do not keep going, as that might result
4432 in hoisting an insn before the setting of a pseudo
4433 that is used by the hoisted insn. */
4434 if (nregs_old != parm.nregs)
4435 first_set = before;
4436 else
4437 break;
4438 }
4439 }
4440 return first_set;
4441}
4442
4443/* Return true if we should avoid inserting code between INSN and preceding
4444 call instruction. */
4445
4446bool
4447keep_with_call_p (const rtx_insn *insn)
4448{
4449 rtx set;
4450
4451 if (INSN_P (insn) && (set = single_set (insn)) != NULL)
4452 {
4453 if (REG_P (SET_DEST (set))
4454 && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER
4455 && fixed_regs[REGNO (SET_DEST (set))]
4456 && general_operand (SET_SRC (set), VOIDmode))
4457 return true;
4458 if (REG_P (SET_SRC (set))
4459 && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set)))
4460 && REG_P (SET_DEST (set))
4461 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER)
4462 return true;
4463 /* There may be a stack pop just after the call and before the store
4464 of the return register. Search for the actual store when deciding
4465 if we can break or not. */
4466 if (SET_DEST (set) == stack_pointer_rtx)
4467 {
4468 /* This CONST_CAST is okay because next_nonnote_insn just
4469 returns its argument and we assign it to a const_rtx
4470 variable. */
4471 const rtx_insn *i2
4472 = next_nonnote_insn (const_cast<rtx_insn *> (insn));
4473 if (i2 && keep_with_call_p (insn: i2))
4474 return true;
4475 }
4476 }
4477 return false;
4478}
4479
4480/* Return true if LABEL is a target of JUMP_INSN. This applies only
4481 to non-complex jumps. That is, direct unconditional, conditional,
4482 and tablejumps, but not computed jumps or returns. It also does
4483 not apply to the fallthru case of a conditional jump. */
4484
4485bool
4486label_is_jump_target_p (const_rtx label, const rtx_insn *jump_insn)
4487{
4488 rtx tmp = JUMP_LABEL (jump_insn);
4489 rtx_jump_table_data *table;
4490
4491 if (label == tmp)
4492 return true;
4493
4494 if (tablejump_p (insn: jump_insn, NULL, tablep: &table))
4495 {
4496 rtvec vec = table->get_labels ();
4497 int i, veclen = GET_NUM_ELEM (vec);
4498
4499 for (i = 0; i < veclen; ++i)
4500 if (XEXP (RTVEC_ELT (vec, i), 0) == label)
4501 return true;
4502 }
4503
4504 if (find_reg_note (insn: jump_insn, kind: REG_LABEL_TARGET, datum: label))
4505 return true;
4506
4507 return false;
4508}
4509
4510
4511/* Return an estimate of the cost of computing rtx X.
4512 One use is in cse, to decide which expression to keep in the hash table.
4513 Another is in rtl generation, to pick the cheapest way to multiply.
4514 Other uses like the latter are expected in the future.
4515
4516 X appears as operand OPNO in an expression with code OUTER_CODE.
4517 SPEED specifies whether costs optimized for speed or size should
4518 be returned. */
4519
4520int
4521rtx_cost (rtx x, machine_mode mode, enum rtx_code outer_code,
4522 int opno, bool speed)
4523{
4524 int i, j;
4525 enum rtx_code code;
4526 const char *fmt;
4527 int total;
4528 int factor;
4529 unsigned mode_size;
4530
4531 if (x == 0)
4532 return 0;
4533
4534 if (GET_CODE (x) == SET)
4535 /* A SET doesn't have a mode, so let's look at the SET_DEST to get
4536 the mode for the factor. */
4537 mode = GET_MODE (SET_DEST (x));
4538 else if (GET_MODE (x) != VOIDmode)
4539 mode = GET_MODE (x);
4540
4541 mode_size = estimated_poly_value (x: GET_MODE_SIZE (mode));
4542
4543 /* A size N times larger than UNITS_PER_WORD likely needs N times as
4544 many insns, taking N times as long. */
4545 factor = mode_size > UNITS_PER_WORD ? mode_size / UNITS_PER_WORD : 1;
4546
4547 /* Compute the default costs of certain things.
4548 Note that targetm.rtx_costs can override the defaults. */
4549
4550 code = GET_CODE (x);
4551 switch (code)
4552 {
4553 case MULT:
4554 case FMA:
4555 case SS_MULT:
4556 case US_MULT:
4557 case SMUL_HIGHPART:
4558 case UMUL_HIGHPART:
4559 /* Multiplication has time-complexity O(N*N), where N is the
4560 number of units (translated from digits) when using
4561 schoolbook long multiplication. */
4562 total = factor * factor * COSTS_N_INSNS (5);
4563 break;
4564 case DIV:
4565 case UDIV:
4566 case MOD:
4567 case UMOD:
4568 case SS_DIV:
4569 case US_DIV:
4570 /* Similarly, complexity for schoolbook long division. */
4571 total = factor * factor * COSTS_N_INSNS (7);
4572 break;
4573 case USE:
4574 /* Used in combine.cc as a marker. */
4575 total = 0;
4576 break;
4577 default:
4578 total = factor * COSTS_N_INSNS (1);
4579 }
4580
4581 switch (code)
4582 {
4583 case REG:
4584 return 0;
4585
4586 case SUBREG:
4587 total = 0;
4588 /* If we can't tie these modes, make this expensive. The larger
4589 the mode, the more expensive it is. */
4590 if (!targetm.modes_tieable_p (mode, GET_MODE (SUBREG_REG (x))))
4591 return COSTS_N_INSNS (2 + factor);
4592 break;
4593
4594 case TRUNCATE:
4595 if (targetm.modes_tieable_p (mode, GET_MODE (XEXP (x, 0))))
4596 {
4597 total = 0;
4598 break;
4599 }
4600 /* FALLTHRU */
4601 default:
4602 if (targetm.rtx_costs (x, mode, outer_code, opno, &total, speed))
4603 return total;
4604 break;
4605 }
4606
4607 /* Sum the costs of the sub-rtx's, plus cost of this operation,
4608 which is already in total. */
4609
4610 fmt = GET_RTX_FORMAT (code);
4611 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4612 if (fmt[i] == 'e')
4613 total += rtx_cost (XEXP (x, i), mode, outer_code: code, opno: i, speed);
4614 else if (fmt[i] == 'E')
4615 for (j = 0; j < XVECLEN (x, i); j++)
4616 total += rtx_cost (XVECEXP (x, i, j), mode, outer_code: code, opno: i, speed);
4617
4618 return total;
4619}
4620
4621/* Fill in the structure C with information about both speed and size rtx
4622 costs for X, which is operand OPNO in an expression with code OUTER. */
4623
4624void
4625get_full_rtx_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno,
4626 struct full_rtx_costs *c)
4627{
4628 c->speed = rtx_cost (x, mode, outer_code: outer, opno, speed: true);
4629 c->size = rtx_cost (x, mode, outer_code: outer, opno, speed: false);
4630}
4631
4632
4633/* Return cost of address expression X.
4634 Expect that X is properly formed address reference.
4635
4636 SPEED parameter specify whether costs optimized for speed or size should
4637 be returned. */
4638
4639int
4640address_cost (rtx x, machine_mode mode, addr_space_t as, bool speed)
4641{
4642 /* We may be asked for cost of various unusual addresses, such as operands
4643 of push instruction. It is not worthwhile to complicate writing
4644 of the target hook by such cases. */
4645
4646 if (!memory_address_addr_space_p (mode, x, as))
4647 return 1000;
4648
4649 return targetm.address_cost (x, mode, as, speed);
4650}
4651
4652/* If the target doesn't override, compute the cost as with arithmetic. */
4653
4654int
4655default_address_cost (rtx x, machine_mode, addr_space_t, bool speed)
4656{
4657 return rtx_cost (x, Pmode, outer_code: MEM, opno: 0, speed);
4658}
4659
4660
4661unsigned HOST_WIDE_INT
4662nonzero_bits (const_rtx x, machine_mode mode)
4663{
4664 if (mode == VOIDmode)
4665 mode = GET_MODE (x);
4666 scalar_int_mode int_mode;
4667 if (!is_a <scalar_int_mode> (m: mode, result: &int_mode))
4668 return GET_MODE_MASK (mode);
4669 return cached_nonzero_bits (x, int_mode, NULL_RTX, VOIDmode, 0);
4670}
4671
4672unsigned int
4673num_sign_bit_copies (const_rtx x, machine_mode mode)
4674{
4675 if (mode == VOIDmode)
4676 mode = GET_MODE (x);
4677 scalar_int_mode int_mode;
4678 if (!is_a <scalar_int_mode> (m: mode, result: &int_mode))
4679 return 1;
4680 return cached_num_sign_bit_copies (x, int_mode, NULL_RTX, VOIDmode, 0);
4681}
4682
4683/* Return true if nonzero_bits1 might recurse into both operands
4684 of X. */
4685
4686static inline bool
4687nonzero_bits_binary_arith_p (const_rtx x)
4688{
4689 if (!ARITHMETIC_P (x))
4690 return false;
4691 switch (GET_CODE (x))
4692 {
4693 case AND:
4694 case XOR:
4695 case IOR:
4696 case UMIN:
4697 case UMAX:
4698 case SMIN:
4699 case SMAX:
4700 case PLUS:
4701 case MINUS:
4702 case MULT:
4703 case DIV:
4704 case UDIV:
4705 case MOD:
4706 case UMOD:
4707 return true;
4708 default:
4709 return false;
4710 }
4711}
4712
4713/* The function cached_nonzero_bits is a wrapper around nonzero_bits1.
4714 It avoids exponential behavior in nonzero_bits1 when X has
4715 identical subexpressions on the first or the second level. */
4716
4717static unsigned HOST_WIDE_INT
4718cached_nonzero_bits (const_rtx x, scalar_int_mode mode, const_rtx known_x,
4719 machine_mode known_mode,
4720 unsigned HOST_WIDE_INT known_ret)
4721{
4722 if (x == known_x && mode == known_mode)
4723 return known_ret;
4724
4725 /* Try to find identical subexpressions. If found call
4726 nonzero_bits1 on X with the subexpressions as KNOWN_X and the
4727 precomputed value for the subexpression as KNOWN_RET. */
4728
4729 if (nonzero_bits_binary_arith_p (x))
4730 {
4731 rtx x0 = XEXP (x, 0);
4732 rtx x1 = XEXP (x, 1);
4733
4734 /* Check the first level. */
4735 if (x0 == x1)
4736 return nonzero_bits1 (x, mode, x0, mode,
4737 cached_nonzero_bits (x: x0, mode, known_x,
4738 known_mode, known_ret));
4739
4740 /* Check the second level. */
4741 if (nonzero_bits_binary_arith_p (x: x0)
4742 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
4743 return nonzero_bits1 (x, mode, x1, mode,
4744 cached_nonzero_bits (x: x1, mode, known_x,
4745 known_mode, known_ret));
4746
4747 if (nonzero_bits_binary_arith_p (x: x1)
4748 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
4749 return nonzero_bits1 (x, mode, x0, mode,
4750 cached_nonzero_bits (x: x0, mode, known_x,
4751 known_mode, known_ret));
4752 }
4753
4754 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret);
4755}
4756
4757/* We let num_sign_bit_copies recur into nonzero_bits as that is useful.
4758 We don't let nonzero_bits recur into num_sign_bit_copies, because that
4759 is less useful. We can't allow both, because that results in exponential
4760 run time recursion. There is a nullstone testcase that triggered
4761 this. This macro avoids accidental uses of num_sign_bit_copies. */
4762#define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior
4763
4764/* Given an expression, X, compute which bits in X can be nonzero.
4765 We don't care about bits outside of those defined in MODE.
4766
4767 For most X this is simply GET_MODE_MASK (GET_MODE (X)), but if X is
4768 an arithmetic operation, we can do better. */
4769
4770static unsigned HOST_WIDE_INT
4771nonzero_bits1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
4772 machine_mode known_mode,
4773 unsigned HOST_WIDE_INT known_ret)
4774{
4775 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode);
4776 unsigned HOST_WIDE_INT inner_nz;
4777 enum rtx_code code = GET_CODE (x);
4778 machine_mode inner_mode;
4779 unsigned int inner_width;
4780 scalar_int_mode xmode;
4781
4782 unsigned int mode_width = GET_MODE_PRECISION (mode);
4783
4784 if (CONST_INT_P (x))
4785 {
4786 if (SHORT_IMMEDIATES_SIGN_EXTEND
4787 && INTVAL (x) > 0
4788 && mode_width < BITS_PER_WORD
4789 && (UINTVAL (x) & (HOST_WIDE_INT_1U << (mode_width - 1))) != 0)
4790 return UINTVAL (x) | (HOST_WIDE_INT_M1U << mode_width);
4791
4792 return UINTVAL (x);
4793 }
4794
4795 if (!is_a <scalar_int_mode> (GET_MODE (x), result: &xmode))
4796 return nonzero;
4797 unsigned int xmode_width = GET_MODE_PRECISION (mode: xmode);
4798
4799 /* If X is wider than MODE, use its mode instead. */
4800 if (xmode_width > mode_width)
4801 {
4802 mode = xmode;
4803 nonzero = GET_MODE_MASK (mode);
4804 mode_width = xmode_width;
4805 }
4806
4807 if (mode_width > HOST_BITS_PER_WIDE_INT)
4808 /* Our only callers in this case look for single bit values. So
4809 just return the mode mask. Those tests will then be false. */
4810 return nonzero;
4811
4812 /* If MODE is wider than X, but both are a single word for both the host
4813 and target machines, we can compute this from which bits of the object
4814 might be nonzero in its own mode, taking into account the fact that, on
4815 CISC machines, accessing an object in a wider mode generally causes the
4816 high-order bits to become undefined, so they are not known to be zero.
4817 We extend this reasoning to RISC machines for operations that might not
4818 operate on the full registers. */
4819 if (mode_width > xmode_width
4820 && xmode_width <= BITS_PER_WORD
4821 && xmode_width <= HOST_BITS_PER_WIDE_INT
4822 && !(WORD_REGISTER_OPERATIONS && word_register_operation_p (x)))
4823 {
4824 nonzero &= cached_nonzero_bits (x, mode: xmode,
4825 known_x, known_mode, known_ret);
4826 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (xmode);
4827 return nonzero;
4828 }
4829
4830 /* Please keep nonzero_bits_binary_arith_p above in sync with
4831 the code in the switch below. */
4832 switch (code)
4833 {
4834 case REG:
4835#if defined(POINTERS_EXTEND_UNSIGNED)
4836 /* If pointers extend unsigned and this is a pointer in Pmode, say that
4837 all the bits above ptr_mode are known to be zero. */
4838 /* As we do not know which address space the pointer is referring to,
4839 we can do this only if the target does not support different pointer
4840 or address modes depending on the address space. */
4841 if (target_default_pointer_address_modes_p ()
4842 && POINTERS_EXTEND_UNSIGNED
4843 && xmode == Pmode
4844 && REG_POINTER (x)
4845 && !targetm.have_ptr_extend ())
4846 nonzero &= GET_MODE_MASK (ptr_mode);
4847#endif
4848
4849 /* Include declared information about alignment of pointers. */
4850 /* ??? We don't properly preserve REG_POINTER changes across
4851 pointer-to-integer casts, so we can't trust it except for
4852 things that we know must be pointers. See execute/960116-1.c. */
4853 if ((x == stack_pointer_rtx
4854 || x == frame_pointer_rtx
4855 || x == arg_pointer_rtx)
4856 && REGNO_POINTER_ALIGN (REGNO (x)))
4857 {
4858 unsigned HOST_WIDE_INT alignment
4859 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT;
4860
4861#ifdef PUSH_ROUNDING
4862 /* If PUSH_ROUNDING is defined, it is possible for the
4863 stack to be momentarily aligned only to that amount,
4864 so we pick the least alignment. */
4865 if (x == stack_pointer_rtx && targetm.calls.push_argument (0))
4866 {
4867 poly_uint64 rounded_1 = PUSH_ROUNDING (poly_int64 (1));
4868 alignment = MIN (known_alignment (rounded_1), alignment);
4869 }
4870#endif
4871
4872 nonzero &= ~(alignment - 1);
4873 }
4874
4875 {
4876 unsigned HOST_WIDE_INT nonzero_for_hook = nonzero;
4877 rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, xmode, mode,
4878 &nonzero_for_hook);
4879
4880 if (new_rtx)
4881 nonzero_for_hook &= cached_nonzero_bits (x: new_rtx, mode, known_x,
4882 known_mode, known_ret);
4883
4884 return nonzero_for_hook;
4885 }
4886
4887 case MEM:
4888 /* In many, if not most, RISC machines, reading a byte from memory
4889 zeros the rest of the register. Noticing that fact saves a lot
4890 of extra zero-extends. */
4891 if (load_extend_op (mode: xmode) == ZERO_EXTEND)
4892 nonzero &= GET_MODE_MASK (xmode);
4893 break;
4894
4895 case EQ: case NE:
4896 case UNEQ: case LTGT:
4897 case GT: case GTU: case UNGT:
4898 case LT: case LTU: case UNLT:
4899 case GE: case GEU: case UNGE:
4900 case LE: case LEU: case UNLE:
4901 case UNORDERED: case ORDERED:
4902 /* If this produces an integer result, we know which bits are set.
4903 Code here used to clear bits outside the mode of X, but that is
4904 now done above. */
4905 /* Mind that MODE is the mode the caller wants to look at this
4906 operation in, and not the actual operation mode. We can wind
4907 up with (subreg:DI (gt:V4HI x y)), and we don't have anything
4908 that describes the results of a vector compare. */
4909 if (GET_MODE_CLASS (xmode) == MODE_INT
4910 && mode_width <= HOST_BITS_PER_WIDE_INT)
4911 nonzero = STORE_FLAG_VALUE;
4912 break;
4913
4914 case NEG:
4915#if 0
4916 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4917 and num_sign_bit_copies. */
4918 if (num_sign_bit_copies (XEXP (x, 0), xmode) == xmode_width)
4919 nonzero = 1;
4920#endif
4921
4922 if (xmode_width < mode_width)
4923 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (xmode));
4924 break;
4925
4926 case ABS:
4927#if 0
4928 /* Disabled to avoid exponential mutual recursion between nonzero_bits
4929 and num_sign_bit_copies. */
4930 if (num_sign_bit_copies (XEXP (x, 0), xmode) == xmode_width)
4931 nonzero = 1;
4932#endif
4933 break;
4934
4935 case TRUNCATE:
4936 nonzero &= (cached_nonzero_bits (XEXP (x, 0), mode,
4937 known_x, known_mode, known_ret)
4938 & GET_MODE_MASK (mode));
4939 break;
4940
4941 case ZERO_EXTEND:
4942 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
4943 known_x, known_mode, known_ret);
4944 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
4945 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
4946 break;
4947
4948 case SIGN_EXTEND:
4949 /* If the sign bit is known clear, this is the same as ZERO_EXTEND.
4950 Otherwise, show all the bits in the outer mode but not the inner
4951 may be nonzero. */
4952 inner_nz = cached_nonzero_bits (XEXP (x, 0), mode,
4953 known_x, known_mode, known_ret);
4954 if (GET_MODE (XEXP (x, 0)) != VOIDmode)
4955 {
4956 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0)));
4957 if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0)), inner_nz))
4958 inner_nz |= (GET_MODE_MASK (mode)
4959 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0))));
4960 }
4961
4962 nonzero &= inner_nz;
4963 break;
4964
4965 case AND:
4966 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode,
4967 known_x, known_mode, known_ret)
4968 & cached_nonzero_bits (XEXP (x, 1), mode,
4969 known_x, known_mode, known_ret);
4970 break;
4971
4972 case XOR: case IOR:
4973 case UMIN: case UMAX: case SMIN: case SMAX:
4974 {
4975 unsigned HOST_WIDE_INT nonzero0
4976 = cached_nonzero_bits (XEXP (x, 0), mode,
4977 known_x, known_mode, known_ret);
4978
4979 /* Don't call nonzero_bits for the second time if it cannot change
4980 anything. */
4981 if ((nonzero & nonzero0) != nonzero)
4982 nonzero &= nonzero0
4983 | cached_nonzero_bits (XEXP (x, 1), mode,
4984 known_x, known_mode, known_ret);
4985 }
4986 break;
4987
4988 case PLUS: case MINUS:
4989 case MULT:
4990 case DIV: case UDIV:
4991 case MOD: case UMOD:
4992 /* We can apply the rules of arithmetic to compute the number of
4993 high- and low-order zero bits of these operations. We start by
4994 computing the width (position of the highest-order nonzero bit)
4995 and the number of low-order zero bits for each value. */
4996 {
4997 unsigned HOST_WIDE_INT nz0
4998 = cached_nonzero_bits (XEXP (x, 0), mode,
4999 known_x, known_mode, known_ret);
5000 unsigned HOST_WIDE_INT nz1
5001 = cached_nonzero_bits (XEXP (x, 1), mode,
5002 known_x, known_mode, known_ret);
5003 int sign_index = xmode_width - 1;
5004 int width0 = floor_log2 (x: nz0) + 1;
5005 int width1 = floor_log2 (x: nz1) + 1;
5006 int low0 = ctz_or_zero (x: nz0);
5007 int low1 = ctz_or_zero (x: nz1);
5008 unsigned HOST_WIDE_INT op0_maybe_minusp
5009 = nz0 & (HOST_WIDE_INT_1U << sign_index);
5010 unsigned HOST_WIDE_INT op1_maybe_minusp
5011 = nz1 & (HOST_WIDE_INT_1U << sign_index);
5012 unsigned int result_width = mode_width;
5013 int result_low = 0;
5014
5015 switch (code)
5016 {
5017 case PLUS:
5018 result_width = MAX (width0, width1) + 1;
5019 result_low = MIN (low0, low1);
5020 break;
5021 case MINUS:
5022 result_low = MIN (low0, low1);
5023 break;
5024 case MULT:
5025 result_width = width0 + width1;
5026 result_low = low0 + low1;
5027 break;
5028 case DIV:
5029 if (width1 == 0)
5030 break;
5031 if (!op0_maybe_minusp && !op1_maybe_minusp)
5032 result_width = width0;
5033 break;
5034 case UDIV:
5035 if (width1 == 0)
5036 break;
5037 result_width = width0;
5038 break;
5039 case MOD:
5040 if (width1 == 0)
5041 break;
5042 if (!op0_maybe_minusp && !op1_maybe_minusp)
5043 result_width = MIN (width0, width1);
5044 result_low = MIN (low0, low1);
5045 break;
5046 case UMOD:
5047 if (width1 == 0)
5048 break;
5049 result_width = MIN (width0, width1);
5050 result_low = MIN (low0, low1);
5051 break;
5052 default:
5053 gcc_unreachable ();
5054 }
5055
5056 /* Note that mode_width <= HOST_BITS_PER_WIDE_INT, see above. */
5057 if (result_width < mode_width)
5058 nonzero &= (HOST_WIDE_INT_1U << result_width) - 1;
5059
5060 if (result_low > 0)
5061 {
5062 if (result_low < HOST_BITS_PER_WIDE_INT)
5063 nonzero &= ~((HOST_WIDE_INT_1U << result_low) - 1);
5064 else
5065 nonzero = 0;
5066 }
5067 }
5068 break;
5069
5070 case ZERO_EXTRACT:
5071 if (CONST_INT_P (XEXP (x, 1))
5072 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
5073 nonzero &= (HOST_WIDE_INT_1U << INTVAL (XEXP (x, 1))) - 1;
5074 break;
5075
5076 case SUBREG:
5077 /* If this is a SUBREG formed for a promoted variable that has
5078 been zero-extended, we know that at least the high-order bits
5079 are zero, though others might be too. */
5080 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x))
5081 nonzero = GET_MODE_MASK (xmode)
5082 & cached_nonzero_bits (SUBREG_REG (x), mode: xmode,
5083 known_x, known_mode, known_ret);
5084
5085 /* If the inner mode is a single word for both the host and target
5086 machines, we can compute this from which bits of the inner
5087 object might be nonzero. */
5088 inner_mode = GET_MODE (SUBREG_REG (x));
5089 if (GET_MODE_PRECISION (mode: inner_mode).is_constant (const_value: &inner_width)
5090 && inner_width <= BITS_PER_WORD
5091 && inner_width <= HOST_BITS_PER_WIDE_INT)
5092 {
5093 nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode,
5094 known_x, known_mode, known_ret);
5095
5096 /* On a typical CISC machine, accessing an object in a wider mode
5097 causes the high-order bits to become undefined. So they are
5098 not known to be zero.
5099
5100 On a typical RISC machine, we only have to worry about the way
5101 loads are extended. Otherwise, if we get a reload for the inner
5102 part, it may be loaded from the stack, and then we may lose all
5103 the zero bits that existed before the store to the stack. */
5104 rtx_code extend_op;
5105 if ((!WORD_REGISTER_OPERATIONS
5106 || ((extend_op = load_extend_op (mode: inner_mode)) == SIGN_EXTEND
5107 ? val_signbit_known_set_p (inner_mode, nonzero)
5108 : extend_op != ZERO_EXTEND)
5109 || !MEM_P (SUBREG_REG (x)))
5110 && xmode_width > inner_width)
5111 nonzero
5112 |= (GET_MODE_MASK (GET_MODE (x)) & ~GET_MODE_MASK (inner_mode));
5113 }
5114 break;
5115
5116 case ASHIFT:
5117 case ASHIFTRT:
5118 case LSHIFTRT:
5119 case ROTATE:
5120 case ROTATERT:
5121 /* The nonzero bits are in two classes: any bits within MODE
5122 that aren't in xmode are always significant. The rest of the
5123 nonzero bits are those that are significant in the operand of
5124 the shift when shifted the appropriate number of bits. This
5125 shows that high-order bits are cleared by the right shift and
5126 low-order bits by left shifts. */
5127 if (CONST_INT_P (XEXP (x, 1))
5128 && INTVAL (XEXP (x, 1)) >= 0
5129 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
5130 && INTVAL (XEXP (x, 1)) < xmode_width)
5131 {
5132 int count = INTVAL (XEXP (x, 1));
5133 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (xmode);
5134 unsigned HOST_WIDE_INT op_nonzero
5135 = cached_nonzero_bits (XEXP (x, 0), mode,
5136 known_x, known_mode, known_ret);
5137 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask;
5138 unsigned HOST_WIDE_INT outer = 0;
5139
5140 if (mode_width > xmode_width)
5141 outer = (op_nonzero & nonzero & ~mode_mask);
5142
5143 switch (code)
5144 {
5145 case ASHIFT:
5146 inner <<= count;
5147 break;
5148
5149 case LSHIFTRT:
5150 inner >>= count;
5151 break;
5152
5153 case ASHIFTRT:
5154 inner >>= count;
5155
5156 /* If the sign bit may have been nonzero before the shift, we
5157 need to mark all the places it could have been copied to
5158 by the shift as possibly nonzero. */
5159 if (inner & (HOST_WIDE_INT_1U << (xmode_width - 1 - count)))
5160 inner |= (((HOST_WIDE_INT_1U << count) - 1)
5161 << (xmode_width - count));
5162 break;
5163
5164 case ROTATE:
5165 inner = (inner << (count % xmode_width)
5166 | (inner >> (xmode_width - (count % xmode_width))))
5167 & mode_mask;
5168 break;
5169
5170 case ROTATERT:
5171 inner = (inner >> (count % xmode_width)
5172 | (inner << (xmode_width - (count % xmode_width))))
5173 & mode_mask;
5174 break;
5175
5176 default:
5177 gcc_unreachable ();
5178 }
5179
5180 nonzero &= (outer | inner);
5181 }
5182 break;
5183
5184 case FFS:
5185 case POPCOUNT:
5186 /* This is at most the number of bits in the mode. */
5187 nonzero = ((unsigned HOST_WIDE_INT) 2 << (floor_log2 (x: mode_width))) - 1;
5188 break;
5189
5190 case CLZ:
5191 /* If CLZ has a known value at zero, then the nonzero bits are
5192 that value, plus the number of bits in the mode minus one. */
5193 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
5194 nonzero
5195 |= (HOST_WIDE_INT_1U << (floor_log2 (x: mode_width))) - 1;
5196 else
5197 nonzero = -1;
5198 break;
5199
5200 case CTZ:
5201 /* If CTZ has a known value at zero, then the nonzero bits are
5202 that value, plus the number of bits in the mode minus one. */
5203 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero))
5204 nonzero
5205 |= (HOST_WIDE_INT_1U << (floor_log2 (x: mode_width))) - 1;
5206 else
5207 nonzero = -1;
5208 break;
5209
5210 case CLRSB:
5211 /* This is at most the number of bits in the mode minus 1. */
5212 nonzero = (HOST_WIDE_INT_1U << (floor_log2 (x: mode_width))) - 1;
5213 break;
5214
5215 case PARITY:
5216 nonzero = 1;
5217 break;
5218
5219 case IF_THEN_ELSE:
5220 {
5221 unsigned HOST_WIDE_INT nonzero_true
5222 = cached_nonzero_bits (XEXP (x, 1), mode,
5223 known_x, known_mode, known_ret);
5224
5225 /* Don't call nonzero_bits for the second time if it cannot change
5226 anything. */
5227 if ((nonzero & nonzero_true) != nonzero)
5228 nonzero &= nonzero_true
5229 | cached_nonzero_bits (XEXP (x, 2), mode,
5230 known_x, known_mode, known_ret);
5231 }
5232 break;
5233
5234 default:
5235 break;
5236 }
5237
5238 return nonzero;
5239}
5240
5241/* See the macro definition above. */
5242#undef cached_num_sign_bit_copies
5243
5244
5245/* Return true if num_sign_bit_copies1 might recurse into both operands
5246 of X. */
5247
5248static inline bool
5249num_sign_bit_copies_binary_arith_p (const_rtx x)
5250{
5251 if (!ARITHMETIC_P (x))
5252 return false;
5253 switch (GET_CODE (x))
5254 {
5255 case IOR:
5256 case AND:
5257 case XOR:
5258 case SMIN:
5259 case SMAX:
5260 case UMIN:
5261 case UMAX:
5262 case PLUS:
5263 case MINUS:
5264 case MULT:
5265 return true;
5266 default:
5267 return false;
5268 }
5269}
5270
5271/* The function cached_num_sign_bit_copies is a wrapper around
5272 num_sign_bit_copies1. It avoids exponential behavior in
5273 num_sign_bit_copies1 when X has identical subexpressions on the
5274 first or the second level. */
5275
5276static unsigned int
5277cached_num_sign_bit_copies (const_rtx x, scalar_int_mode mode,
5278 const_rtx known_x, machine_mode known_mode,
5279 unsigned int known_ret)
5280{
5281 if (x == known_x && mode == known_mode)
5282 return known_ret;
5283
5284 /* Try to find identical subexpressions. If found call
5285 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and
5286 the precomputed value for the subexpression as KNOWN_RET. */
5287
5288 if (num_sign_bit_copies_binary_arith_p (x))
5289 {
5290 rtx x0 = XEXP (x, 0);
5291 rtx x1 = XEXP (x, 1);
5292
5293 /* Check the first level. */
5294 if (x0 == x1)
5295 return
5296 num_sign_bit_copies1 (x, mode, x0, mode,
5297 cached_num_sign_bit_copies (x: x0, mode, known_x,
5298 known_mode,
5299 known_ret));
5300
5301 /* Check the second level. */
5302 if (num_sign_bit_copies_binary_arith_p (x: x0)
5303 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
5304 return
5305 num_sign_bit_copies1 (x, mode, x1, mode,
5306 cached_num_sign_bit_copies (x: x1, mode, known_x,
5307 known_mode,
5308 known_ret));
5309
5310 if (num_sign_bit_copies_binary_arith_p (x: x1)
5311 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
5312 return
5313 num_sign_bit_copies1 (x, mode, x0, mode,
5314 cached_num_sign_bit_copies (x: x0, mode, known_x,
5315 known_mode,
5316 known_ret));
5317 }
5318
5319 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret);
5320}
5321
5322/* Return the number of bits at the high-order end of X that are known to
5323 be equal to the sign bit. X will be used in mode MODE. The returned
5324 value will always be between 1 and the number of bits in MODE. */
5325
5326static unsigned int
5327num_sign_bit_copies1 (const_rtx x, scalar_int_mode mode, const_rtx known_x,
5328 machine_mode known_mode,
5329 unsigned int known_ret)
5330{
5331 enum rtx_code code = GET_CODE (x);
5332 unsigned int bitwidth = GET_MODE_PRECISION (mode);
5333 int num0, num1, result;
5334 unsigned HOST_WIDE_INT nonzero;
5335
5336 if (CONST_INT_P (x))
5337 {
5338 /* If the constant is negative, take its 1's complement and remask.
5339 Then see how many zero bits we have. */
5340 nonzero = UINTVAL (x) & GET_MODE_MASK (mode);
5341 if (bitwidth <= HOST_BITS_PER_WIDE_INT
5342 && (nonzero & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5343 nonzero = (~nonzero) & GET_MODE_MASK (mode);
5344
5345 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (x: nonzero) - 1);
5346 }
5347
5348 scalar_int_mode xmode, inner_mode;
5349 if (!is_a <scalar_int_mode> (GET_MODE (x), result: &xmode))
5350 return 1;
5351
5352 unsigned int xmode_width = GET_MODE_PRECISION (mode: xmode);
5353
5354 /* For a smaller mode, just ignore the high bits. */
5355 if (bitwidth < xmode_width)
5356 {
5357 num0 = cached_num_sign_bit_copies (x, mode: xmode,
5358 known_x, known_mode, known_ret);
5359 return MAX (1, num0 - (int) (xmode_width - bitwidth));
5360 }
5361
5362 if (bitwidth > xmode_width)
5363 {
5364 /* If this machine does not do all register operations on the entire
5365 register and MODE is wider than the mode of X, we can say nothing
5366 at all about the high-order bits. We extend this reasoning to RISC
5367 machines for operations that might not operate on full registers. */
5368 if (!(WORD_REGISTER_OPERATIONS && word_register_operation_p (x)))
5369 return 1;
5370
5371 /* Likewise on machines that do, if the mode of the object is smaller
5372 than a word and loads of that size don't sign extend, we can say
5373 nothing about the high order bits. */
5374 if (xmode_width < BITS_PER_WORD
5375 && load_extend_op (mode: xmode) != SIGN_EXTEND)
5376 return 1;
5377 }
5378
5379 /* Please keep num_sign_bit_copies_binary_arith_p above in sync with
5380 the code in the switch below. */
5381 switch (code)
5382 {
5383 case REG:
5384
5385#if defined(POINTERS_EXTEND_UNSIGNED)
5386 /* If pointers extend signed and this is a pointer in Pmode, say that
5387 all the bits above ptr_mode are known to be sign bit copies. */
5388 /* As we do not know which address space the pointer is referring to,
5389 we can do this only if the target does not support different pointer
5390 or address modes depending on the address space. */
5391 if (target_default_pointer_address_modes_p ()
5392 && ! POINTERS_EXTEND_UNSIGNED && xmode == Pmode
5393 && mode == Pmode && REG_POINTER (x)
5394 && !targetm.have_ptr_extend ())
5395 return GET_MODE_PRECISION (Pmode) - GET_MODE_PRECISION (mode: ptr_mode) + 1;
5396#endif
5397
5398 {
5399 unsigned int copies_for_hook = 1, copies = 1;
5400 rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, xmode, mode,
5401 &copies_for_hook);
5402
5403 if (new_rtx)
5404 copies = cached_num_sign_bit_copies (x: new_rtx, mode, known_x,
5405 known_mode, known_ret);
5406
5407 if (copies > 1 || copies_for_hook > 1)
5408 return MAX (copies, copies_for_hook);
5409
5410 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */
5411 }
5412 break;
5413
5414 case MEM:
5415 /* Some RISC machines sign-extend all loads of smaller than a word. */
5416 if (load_extend_op (mode: xmode) == SIGN_EXTEND)
5417 return MAX (1, ((int) bitwidth - (int) xmode_width + 1));
5418 break;
5419
5420 case SUBREG:
5421 /* If this is a SUBREG for a promoted object that is sign-extended
5422 and we are looking at it in a wider mode, we know that at least the
5423 high-order bits are known to be sign bit copies. */
5424
5425 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_SIGNED_P (x))
5426 {
5427 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode,
5428 known_x, known_mode, known_ret);
5429 return MAX ((int) bitwidth - (int) xmode_width + 1, num0);
5430 }
5431
5432 if (is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (x)), result: &inner_mode))
5433 {
5434 /* For a smaller object, just ignore the high bits. */
5435 if (bitwidth <= GET_MODE_PRECISION (mode: inner_mode))
5436 {
5437 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode: inner_mode,
5438 known_x, known_mode,
5439 known_ret);
5440 return MAX (1, num0 - (int) (GET_MODE_PRECISION (inner_mode)
5441 - bitwidth));
5442 }
5443
5444 /* For paradoxical SUBREGs on machines where all register operations
5445 affect the entire register, just look inside. Note that we are
5446 passing MODE to the recursive call, so the number of sign bit
5447 copies will remain relative to that mode, not the inner mode.
5448
5449 This works only if loads sign extend. Otherwise, if we get a
5450 reload for the inner part, it may be loaded from the stack, and
5451 then we lose all sign bit copies that existed before the store
5452 to the stack. */
5453 if (WORD_REGISTER_OPERATIONS
5454 && load_extend_op (mode: inner_mode) == SIGN_EXTEND
5455 && paradoxical_subreg_p (x)
5456 && MEM_P (SUBREG_REG (x)))
5457 return cached_num_sign_bit_copies (SUBREG_REG (x), mode,
5458 known_x, known_mode, known_ret);
5459 }
5460 break;
5461
5462 case SIGN_EXTRACT:
5463 if (CONST_INT_P (XEXP (x, 1)))
5464 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1)));
5465 break;
5466
5467 case SIGN_EXTEND:
5468 if (is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), result: &inner_mode))
5469 return (bitwidth - GET_MODE_PRECISION (mode: inner_mode)
5470 + cached_num_sign_bit_copies (XEXP (x, 0), mode: inner_mode,
5471 known_x, known_mode, known_ret));
5472 break;
5473
5474 case TRUNCATE:
5475 /* For a smaller object, just ignore the high bits. */
5476 inner_mode = as_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)));
5477 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode: inner_mode,
5478 known_x, known_mode, known_ret);
5479 return MAX (1, (num0 - (int) (GET_MODE_PRECISION (inner_mode)
5480 - bitwidth)));
5481
5482 case NOT:
5483 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
5484 known_x, known_mode, known_ret);
5485
5486 case ROTATE: case ROTATERT:
5487 /* If we are rotating left by a number of bits less than the number
5488 of sign bit copies, we can just subtract that amount from the
5489 number. */
5490 if (CONST_INT_P (XEXP (x, 1))
5491 && INTVAL (XEXP (x, 1)) >= 0
5492 && INTVAL (XEXP (x, 1)) < (int) bitwidth)
5493 {
5494 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5495 known_x, known_mode, known_ret);
5496 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1))
5497 : (int) bitwidth - INTVAL (XEXP (x, 1))));
5498 }
5499 break;
5500
5501 case NEG:
5502 /* In general, this subtracts one sign bit copy. But if the value
5503 is known to be positive, the number of sign bit copies is the
5504 same as that of the input. Finally, if the input has just one bit
5505 that might be nonzero, all the bits are copies of the sign bit. */
5506 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5507 known_x, known_mode, known_ret);
5508 if (bitwidth > HOST_BITS_PER_WIDE_INT)
5509 return num0 > 1 ? num0 - 1 : 1;
5510
5511 nonzero = nonzero_bits (XEXP (x, 0), mode);
5512 if (nonzero == 1)
5513 return bitwidth;
5514
5515 if (num0 > 1
5516 && ((HOST_WIDE_INT_1U << (bitwidth - 1)) & nonzero))
5517 num0--;
5518
5519 return num0;
5520
5521 case IOR: case AND: case XOR:
5522 case SMIN: case SMAX: case UMIN: case UMAX:
5523 /* Logical operations will preserve the number of sign-bit copies.
5524 MIN and MAX operations always return one of the operands. */
5525 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5526 known_x, known_mode, known_ret);
5527 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
5528 known_x, known_mode, known_ret);
5529
5530 /* If num1 is clearing some of the top bits then regardless of
5531 the other term, we are guaranteed to have at least that many
5532 high-order zero bits. */
5533 if (code == AND
5534 && num1 > 1
5535 && bitwidth <= HOST_BITS_PER_WIDE_INT
5536 && CONST_INT_P (XEXP (x, 1))
5537 && (UINTVAL (XEXP (x, 1))
5538 & (HOST_WIDE_INT_1U << (bitwidth - 1))) == 0)
5539 return num1;
5540
5541 /* Similarly for IOR when setting high-order bits. */
5542 if (code == IOR
5543 && num1 > 1
5544 && bitwidth <= HOST_BITS_PER_WIDE_INT
5545 && CONST_INT_P (XEXP (x, 1))
5546 && (UINTVAL (XEXP (x, 1))
5547 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5548 return num1;
5549
5550 return MIN (num0, num1);
5551
5552 case PLUS: case MINUS:
5553 /* For addition and subtraction, we can have a 1-bit carry. However,
5554 if we are subtracting 1 from a positive number, there will not
5555 be such a carry. Furthermore, if the positive number is known to
5556 be 0 or 1, we know the result is either -1 or 0. */
5557
5558 if (code == PLUS && XEXP (x, 1) == constm1_rtx
5559 && bitwidth <= HOST_BITS_PER_WIDE_INT)
5560 {
5561 nonzero = nonzero_bits (XEXP (x, 0), mode);
5562 if (((HOST_WIDE_INT_1U << (bitwidth - 1)) & nonzero) == 0)
5563 return (nonzero == 1 || nonzero == 0 ? bitwidth
5564 : bitwidth - floor_log2 (x: nonzero) - 1);
5565 }
5566
5567 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5568 known_x, known_mode, known_ret);
5569 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
5570 known_x, known_mode, known_ret);
5571 result = MAX (1, MIN (num0, num1) - 1);
5572
5573 return result;
5574
5575 case MULT:
5576 /* The number of bits of the product is the sum of the number of
5577 bits of both terms. However, unless one of the terms if known
5578 to be positive, we must allow for an additional bit since negating
5579 a negative number can remove one sign bit copy. */
5580
5581 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5582 known_x, known_mode, known_ret);
5583 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
5584 known_x, known_mode, known_ret);
5585
5586 result = bitwidth - (bitwidth - num0) - (bitwidth - num1);
5587 if (result > 0
5588 && (bitwidth > HOST_BITS_PER_WIDE_INT
5589 || (((nonzero_bits (XEXP (x, 0), mode)
5590 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5591 && ((nonzero_bits (XEXP (x, 1), mode)
5592 & (HOST_WIDE_INT_1U << (bitwidth - 1)))
5593 != 0))))
5594 result--;
5595
5596 return MAX (1, result);
5597
5598 case UDIV:
5599 /* The result must be <= the first operand. If the first operand
5600 has the high bit set, we know nothing about the number of sign
5601 bit copies. */
5602 if (bitwidth > HOST_BITS_PER_WIDE_INT)
5603 return 1;
5604 else if ((nonzero_bits (XEXP (x, 0), mode)
5605 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5606 return 1;
5607 else
5608 return cached_num_sign_bit_copies (XEXP (x, 0), mode,
5609 known_x, known_mode, known_ret);
5610
5611 case UMOD:
5612 /* The result must be <= the second operand. If the second operand
5613 has (or just might have) the high bit set, we know nothing about
5614 the number of sign bit copies. */
5615 if (bitwidth > HOST_BITS_PER_WIDE_INT)
5616 return 1;
5617 else if ((nonzero_bits (XEXP (x, 1), mode)
5618 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5619 return 1;
5620 else
5621 return cached_num_sign_bit_copies (XEXP (x, 1), mode,
5622 known_x, known_mode, known_ret);
5623
5624 case DIV:
5625 /* Similar to unsigned division, except that we have to worry about
5626 the case where the divisor is negative, in which case we have
5627 to add 1. */
5628 result = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5629 known_x, known_mode, known_ret);
5630 if (result > 1
5631 && (bitwidth > HOST_BITS_PER_WIDE_INT
5632 || (nonzero_bits (XEXP (x, 1), mode)
5633 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0))
5634 result--;
5635
5636 return result;
5637
5638 case MOD:
5639 result = cached_num_sign_bit_copies (XEXP (x, 1), mode,
5640 known_x, known_mode, known_ret);
5641 if (result > 1
5642 && (bitwidth > HOST_BITS_PER_WIDE_INT
5643 || (nonzero_bits (XEXP (x, 1), mode)
5644 & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0))
5645 result--;
5646
5647 return result;
5648
5649 case ASHIFTRT:
5650 /* Shifts by a constant add to the number of bits equal to the
5651 sign bit. */
5652 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5653 known_x, known_mode, known_ret);
5654 if (CONST_INT_P (XEXP (x, 1))
5655 && INTVAL (XEXP (x, 1)) > 0
5656 && INTVAL (XEXP (x, 1)) < xmode_width)
5657 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1)));
5658
5659 return num0;
5660
5661 case ASHIFT:
5662 /* Left shifts destroy copies. */
5663 if (!CONST_INT_P (XEXP (x, 1))
5664 || INTVAL (XEXP (x, 1)) < 0
5665 || INTVAL (XEXP (x, 1)) >= (int) bitwidth
5666 || INTVAL (XEXP (x, 1)) >= xmode_width)
5667 return 1;
5668
5669 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode,
5670 known_x, known_mode, known_ret);
5671 return MAX (1, num0 - INTVAL (XEXP (x, 1)));
5672
5673 case IF_THEN_ELSE:
5674 num0 = cached_num_sign_bit_copies (XEXP (x, 1), mode,
5675 known_x, known_mode, known_ret);
5676 num1 = cached_num_sign_bit_copies (XEXP (x, 2), mode,
5677 known_x, known_mode, known_ret);
5678 return MIN (num0, num1);
5679
5680 case EQ: case NE: case GE: case GT: case LE: case LT:
5681 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT:
5682 case GEU: case GTU: case LEU: case LTU:
5683 case UNORDERED: case ORDERED:
5684 /* If the constant is negative, take its 1's complement and remask.
5685 Then see how many zero bits we have. */
5686 nonzero = STORE_FLAG_VALUE;
5687 if (bitwidth <= HOST_BITS_PER_WIDE_INT
5688 && (nonzero & (HOST_WIDE_INT_1U << (bitwidth - 1))) != 0)
5689 nonzero = (~nonzero) & GET_MODE_MASK (mode);
5690
5691 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (x: nonzero) - 1);
5692
5693 default:
5694 break;
5695 }
5696
5697 /* If we haven't been able to figure it out by one of the above rules,
5698 see if some of the high-order bits are known to be zero. If so,
5699 count those bits and return one less than that amount. If we can't
5700 safely compute the mask for this mode, always return BITWIDTH. */
5701
5702 bitwidth = GET_MODE_PRECISION (mode);
5703 if (bitwidth > HOST_BITS_PER_WIDE_INT)
5704 return 1;
5705
5706 nonzero = nonzero_bits (x, mode);
5707 return nonzero & (HOST_WIDE_INT_1U << (bitwidth - 1))
5708 ? 1 : bitwidth - floor_log2 (x: nonzero) - 1;
5709}
5710
5711/* Calculate the rtx_cost of a single instruction pattern. A return value of
5712 zero indicates an instruction pattern without a known cost. */
5713
5714int
5715pattern_cost (rtx pat, bool speed)
5716{
5717 int i, cost;
5718 rtx set;
5719
5720 /* Extract the single set rtx from the instruction pattern. We
5721 can't use single_set since we only have the pattern. We also
5722 consider PARALLELs of a normal set and a single comparison. In
5723 that case we use the cost of the non-comparison SET operation,
5724 which is most-likely to be the real cost of this operation. */
5725 if (GET_CODE (pat) == SET)
5726 set = pat;
5727 else if (GET_CODE (pat) == PARALLEL)
5728 {
5729 set = NULL_RTX;
5730 rtx comparison = NULL_RTX;
5731
5732 for (i = 0; i < XVECLEN (pat, 0); i++)
5733 {
5734 rtx x = XVECEXP (pat, 0, i);
5735 if (GET_CODE (x) == SET)
5736 {
5737 if (GET_CODE (SET_SRC (x)) == COMPARE)
5738 {
5739 if (comparison)
5740 return 0;
5741 comparison = x;
5742 }
5743 else
5744 {
5745 if (set)
5746 return 0;
5747 set = x;
5748 }
5749 }
5750 }
5751
5752 if (!set && comparison)
5753 set = comparison;
5754
5755 if (!set)
5756 return 0;
5757 }
5758 else
5759 return 0;
5760
5761 cost = set_src_cost (SET_SRC (set), GET_MODE (SET_DEST (set)), speed_p: speed);
5762 return cost > 0 ? cost : COSTS_N_INSNS (1);
5763}
5764
5765/* Calculate the cost of a single instruction. A return value of zero
5766 indicates an instruction pattern without a known cost. */
5767
5768int
5769insn_cost (rtx_insn *insn, bool speed)
5770{
5771 if (targetm.insn_cost)
5772 return targetm.insn_cost (insn, speed);
5773
5774 return pattern_cost (pat: PATTERN (insn), speed);
5775}
5776
5777/* Returns estimate on cost of computing SEQ. */
5778
5779unsigned
5780seq_cost (const rtx_insn *seq, bool speed)
5781{
5782 unsigned cost = 0;
5783 rtx set;
5784
5785 for (; seq; seq = NEXT_INSN (insn: seq))
5786 {
5787 set = single_set (insn: seq);
5788 if (set)
5789 cost += set_rtx_cost (x: set, speed_p: speed);
5790 else if (NONDEBUG_INSN_P (seq))
5791 {
5792 int this_cost = insn_cost (CONST_CAST_RTX_INSN (seq), speed);
5793 if (this_cost > 0)
5794 cost += this_cost;
5795 else
5796 cost++;
5797 }
5798 }
5799
5800 return cost;
5801}
5802
5803/* Given an insn INSN and condition COND, return the condition in a
5804 canonical form to simplify testing by callers. Specifically:
5805
5806 (1) The code will always be a comparison operation (EQ, NE, GT, etc.).
5807 (2) Both operands will be machine operands.
5808 (3) If an operand is a constant, it will be the second operand.
5809 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly
5810 for GE, GEU, and LEU.
5811
5812 If the condition cannot be understood, or is an inequality floating-point
5813 comparison which needs to be reversed, 0 will be returned.
5814
5815 If REVERSE is nonzero, then reverse the condition prior to canonizing it.
5816
5817 If EARLIEST is nonzero, it is a pointer to a place where the earliest
5818 insn used in locating the condition was found. If a replacement test
5819 of the condition is desired, it should be placed in front of that
5820 insn and we will be sure that the inputs are still valid.
5821
5822 If WANT_REG is nonzero, we wish the condition to be relative to that
5823 register, if possible. Therefore, do not canonicalize the condition
5824 further. If ALLOW_CC_MODE is nonzero, allow the condition returned
5825 to be a compare to a CC mode register.
5826
5827 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST
5828 and at INSN. */
5829
5830rtx
5831canonicalize_condition (rtx_insn *insn, rtx cond, int reverse,
5832 rtx_insn **earliest,
5833 rtx want_reg, int allow_cc_mode, int valid_at_insn_p)
5834{
5835 enum rtx_code code;
5836 rtx_insn *prev = insn;
5837 const_rtx set;
5838 rtx tem;
5839 rtx op0, op1;
5840 int reverse_code = 0;
5841 machine_mode mode;
5842 basic_block bb = BLOCK_FOR_INSN (insn);
5843
5844 code = GET_CODE (cond);
5845 mode = GET_MODE (cond);
5846 op0 = XEXP (cond, 0);
5847 op1 = XEXP (cond, 1);
5848
5849 if (reverse)
5850 code = reversed_comparison_code (cond, insn);
5851 if (code == UNKNOWN)
5852 return 0;
5853
5854 if (earliest)
5855 *earliest = insn;
5856
5857 /* If we are comparing a register with zero, see if the register is set
5858 in the previous insn to a COMPARE or a comparison operation. Perform
5859 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args
5860 in cse.cc */
5861
5862 while ((GET_RTX_CLASS (code) == RTX_COMPARE
5863 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
5864 && op1 == CONST0_RTX (GET_MODE (op0))
5865 && op0 != want_reg)
5866 {
5867 /* Set nonzero when we find something of interest. */
5868 rtx x = 0;
5869
5870 /* If this is a COMPARE, pick up the two things being compared. */
5871 if (GET_CODE (op0) == COMPARE)
5872 {
5873 op1 = XEXP (op0, 1);
5874 op0 = XEXP (op0, 0);
5875 continue;
5876 }
5877 else if (!REG_P (op0))
5878 break;
5879
5880 /* Go back to the previous insn. Stop if it is not an INSN. We also
5881 stop if it isn't a single set or if it has a REG_INC note because
5882 we don't want to bother dealing with it. */
5883
5884 prev = prev_nonnote_nondebug_insn (prev);
5885
5886 if (prev == 0
5887 || !NONJUMP_INSN_P (prev)
5888 || FIND_REG_INC_NOTE (prev, NULL_RTX)
5889 /* In cfglayout mode, there do not have to be labels at the
5890 beginning of a block, or jumps at the end, so the previous
5891 conditions would not stop us when we reach bb boundary. */
5892 || BLOCK_FOR_INSN (insn: prev) != bb)
5893 break;
5894
5895 set = set_of (pat: op0, insn: prev);
5896
5897 if (set
5898 && (GET_CODE (set) != SET
5899 || !rtx_equal_p (SET_DEST (set), op0)))
5900 break;
5901
5902 /* If this is setting OP0, get what it sets it to if it looks
5903 relevant. */
5904 if (set)
5905 {
5906 machine_mode inner_mode = GET_MODE (SET_DEST (set));
5907#ifdef FLOAT_STORE_FLAG_VALUE
5908 REAL_VALUE_TYPE fsfv;
5909#endif
5910
5911 /* ??? We may not combine comparisons done in a CCmode with
5912 comparisons not done in a CCmode. This is to aid targets
5913 like Alpha that have an IEEE compliant EQ instruction, and
5914 a non-IEEE compliant BEQ instruction. The use of CCmode is
5915 actually artificial, simply to prevent the combination, but
5916 should not affect other platforms.
5917
5918 However, we must allow VOIDmode comparisons to match either
5919 CCmode or non-CCmode comparison, because some ports have
5920 modeless comparisons inside branch patterns.
5921
5922 ??? This mode check should perhaps look more like the mode check
5923 in simplify_comparison in combine. */
5924 if (((GET_MODE_CLASS (mode) == MODE_CC)
5925 != (GET_MODE_CLASS (inner_mode) == MODE_CC))
5926 && mode != VOIDmode
5927 && inner_mode != VOIDmode)
5928 break;
5929 if (GET_CODE (SET_SRC (set)) == COMPARE
5930 || (((code == NE
5931 || (code == LT
5932 && val_signbit_known_set_p (inner_mode,
5933 STORE_FLAG_VALUE))
5934#ifdef FLOAT_STORE_FLAG_VALUE
5935 || (code == LT
5936 && SCALAR_FLOAT_MODE_P (inner_mode)
5937 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
5938 REAL_VALUE_NEGATIVE (fsfv)))
5939#endif
5940 ))
5941 && COMPARISON_P (SET_SRC (set))))
5942 x = SET_SRC (set);
5943 else if (((code == EQ
5944 || (code == GE
5945 && val_signbit_known_set_p (inner_mode,
5946 STORE_FLAG_VALUE))
5947#ifdef FLOAT_STORE_FLAG_VALUE
5948 || (code == GE
5949 && SCALAR_FLOAT_MODE_P (inner_mode)
5950 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode),
5951 REAL_VALUE_NEGATIVE (fsfv)))
5952#endif
5953 ))
5954 && COMPARISON_P (SET_SRC (set)))
5955 {
5956 reverse_code = 1;
5957 x = SET_SRC (set);
5958 }
5959 else if ((code == EQ || code == NE)
5960 && GET_CODE (SET_SRC (set)) == XOR)
5961 /* Handle sequences like:
5962
5963 (set op0 (xor X Y))
5964 ...(eq|ne op0 (const_int 0))...
5965
5966 in which case:
5967
5968 (eq op0 (const_int 0)) reduces to (eq X Y)
5969 (ne op0 (const_int 0)) reduces to (ne X Y)
5970
5971 This is the form used by MIPS16, for example. */
5972 x = SET_SRC (set);
5973 else
5974 break;
5975 }
5976
5977 else if (reg_set_p (reg: op0, insn: prev))
5978 /* If this sets OP0, but not directly, we have to give up. */
5979 break;
5980
5981 if (x)
5982 {
5983 /* If the caller is expecting the condition to be valid at INSN,
5984 make sure X doesn't change before INSN. */
5985 if (valid_at_insn_p)
5986 if (modified_in_p (x, insn: prev) || modified_between_p (x, start: prev, end: insn))
5987 break;
5988 if (COMPARISON_P (x))
5989 code = GET_CODE (x);
5990 if (reverse_code)
5991 {
5992 code = reversed_comparison_code (x, prev);
5993 if (code == UNKNOWN)
5994 return 0;
5995 reverse_code = 0;
5996 }
5997
5998 op0 = XEXP (x, 0), op1 = XEXP (x, 1);
5999 if (earliest)
6000 *earliest = prev;
6001 }
6002 }
6003
6004 /* If constant is first, put it last. */
6005 if (CONSTANT_P (op0))
6006 code = swap_condition (code), tem = op0, op0 = op1, op1 = tem;
6007
6008 /* If OP0 is the result of a comparison, we weren't able to find what
6009 was really being compared, so fail. */
6010 if (!allow_cc_mode
6011 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
6012 return 0;
6013
6014 /* Canonicalize any ordered comparison with integers involving equality
6015 if we can do computations in the relevant mode and we do not
6016 overflow. */
6017
6018 scalar_int_mode op0_mode;
6019 if (CONST_INT_P (op1)
6020 && is_a <scalar_int_mode> (GET_MODE (op0), result: &op0_mode)
6021 && GET_MODE_PRECISION (mode: op0_mode) <= HOST_BITS_PER_WIDE_INT)
6022 {
6023 HOST_WIDE_INT const_val = INTVAL (op1);
6024 unsigned HOST_WIDE_INT uconst_val = const_val;
6025 unsigned HOST_WIDE_INT max_val
6026 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (op0_mode);
6027
6028 switch (code)
6029 {
6030 case LE:
6031 if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1)
6032 code = LT, op1 = gen_int_mode (const_val + 1, op0_mode);
6033 break;
6034
6035 /* When cross-compiling, const_val might be sign-extended from
6036 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */
6037 case GE:
6038 if ((const_val & max_val)
6039 != (HOST_WIDE_INT_1U << (GET_MODE_PRECISION (mode: op0_mode) - 1)))
6040 code = GT, op1 = gen_int_mode (const_val - 1, op0_mode);
6041 break;
6042
6043 case LEU:
6044 if (uconst_val < max_val)
6045 code = LTU, op1 = gen_int_mode (uconst_val + 1, op0_mode);
6046 break;
6047
6048 case GEU:
6049 if (uconst_val != 0)
6050 code = GTU, op1 = gen_int_mode (uconst_val - 1, op0_mode);
6051 break;
6052
6053 default:
6054 break;
6055 }
6056 }
6057
6058 /* We promised to return a comparison. */
6059 rtx ret = gen_rtx_fmt_ee (code, VOIDmode, op0, op1);
6060 if (COMPARISON_P (ret))
6061 return ret;
6062 return 0;
6063}
6064
6065/* Given a jump insn JUMP, return the condition that will cause it to branch
6066 to its JUMP_LABEL. If the condition cannot be understood, or is an
6067 inequality floating-point comparison which needs to be reversed, 0 will
6068 be returned.
6069
6070 If EARLIEST is nonzero, it is a pointer to a place where the earliest
6071 insn used in locating the condition was found. If a replacement test
6072 of the condition is desired, it should be placed in front of that
6073 insn and we will be sure that the inputs are still valid. If EARLIEST
6074 is null, the returned condition will be valid at INSN.
6075
6076 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a
6077 compare CC mode register.
6078
6079 VALID_AT_INSN_P is the same as for canonicalize_condition. */
6080
6081rtx
6082get_condition (rtx_insn *jump, rtx_insn **earliest, int allow_cc_mode,
6083 int valid_at_insn_p)
6084{
6085 rtx cond;
6086 int reverse;
6087 rtx set;
6088
6089 /* If this is not a standard conditional jump, we can't parse it. */
6090 if (!JUMP_P (jump)
6091 || ! any_condjump_p (jump))
6092 return 0;
6093 set = pc_set (jump);
6094
6095 cond = XEXP (SET_SRC (set), 0);
6096
6097 /* If this branches to JUMP_LABEL when the condition is false, reverse
6098 the condition. */
6099 reverse
6100 = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
6101 && label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump);
6102
6103 return canonicalize_condition (insn: jump, cond, reverse, earliest, NULL_RTX,
6104 allow_cc_mode, valid_at_insn_p);
6105}
6106
6107/* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on
6108 TARGET_MODE_REP_EXTENDED.
6109
6110 Note that we assume that the property of
6111 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes
6112 narrower than mode B. I.e., if A is a mode narrower than B then in
6113 order to be able to operate on it in mode B, mode A needs to
6114 satisfy the requirements set by the representation of mode B. */
6115
6116static void
6117init_num_sign_bit_copies_in_rep (void)
6118{
6119 opt_scalar_int_mode in_mode_iter;
6120 scalar_int_mode mode;
6121
6122 FOR_EACH_MODE_IN_CLASS (in_mode_iter, MODE_INT)
6123 FOR_EACH_MODE_UNTIL (mode, in_mode_iter.require ())
6124 {
6125 scalar_int_mode in_mode = in_mode_iter.require ();
6126 scalar_int_mode i;
6127
6128 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED
6129 extends to the next widest mode. */
6130 gcc_assert (targetm.mode_rep_extended (mode, in_mode) == UNKNOWN
6131 || GET_MODE_WIDER_MODE (mode).require () == in_mode);
6132
6133 /* We are in in_mode. Count how many bits outside of mode
6134 have to be copies of the sign-bit. */
6135 FOR_EACH_MODE (i, mode, in_mode)
6136 {
6137 /* This must always exist (for the last iteration it will be
6138 IN_MODE). */
6139 scalar_int_mode wider = GET_MODE_WIDER_MODE (m: i).require ();
6140
6141 if (targetm.mode_rep_extended (i, wider) == SIGN_EXTEND
6142 /* We can only check sign-bit copies starting from the
6143 top-bit. In order to be able to check the bits we
6144 have already seen we pretend that subsequent bits
6145 have to be sign-bit copies too. */
6146 || num_sign_bit_copies_in_rep [in_mode][mode])
6147 num_sign_bit_copies_in_rep [in_mode][mode]
6148 += GET_MODE_PRECISION (mode: wider) - GET_MODE_PRECISION (mode: i);
6149 }
6150 }
6151}
6152
6153/* Suppose that truncation from the machine mode of X to MODE is not a
6154 no-op. See if there is anything special about X so that we can
6155 assume it already contains a truncated value of MODE. */
6156
6157bool
6158truncated_to_mode (machine_mode mode, const_rtx x)
6159{
6160 /* This register has already been used in MODE without explicit
6161 truncation. */
6162 if (REG_P (x) && rtl_hooks.reg_truncated_to_mode (mode, x))
6163 return true;
6164
6165 /* See if we already satisfy the requirements of MODE. If yes we
6166 can just switch to MODE. */
6167 if (num_sign_bit_copies_in_rep[GET_MODE (x)][mode]
6168 && (num_sign_bit_copies (x, GET_MODE (x))
6169 >= num_sign_bit_copies_in_rep[GET_MODE (x)][mode] + 1))
6170 return true;
6171
6172 return false;
6173}
6174
6175/* Return true if RTX code CODE has a single sequence of zero or more
6176 "e" operands and no rtvec operands. Initialize its rtx_all_subrtx_bounds
6177 entry in that case. */
6178
6179static bool
6180setup_reg_subrtx_bounds (unsigned int code)
6181{
6182 const char *format = GET_RTX_FORMAT ((enum rtx_code) code);
6183 unsigned int i = 0;
6184 for (; format[i] != 'e'; ++i)
6185 {
6186 if (!format[i])
6187 /* No subrtxes. Leave start and count as 0. */
6188 return true;
6189 if (format[i] == 'E' || format[i] == 'V')
6190 return false;
6191 }
6192
6193 /* Record the sequence of 'e's. */
6194 rtx_all_subrtx_bounds[code].start = i;
6195 do
6196 ++i;
6197 while (format[i] == 'e');
6198 rtx_all_subrtx_bounds[code].count = i - rtx_all_subrtx_bounds[code].start;
6199 /* rtl-iter.h relies on this. */
6200 gcc_checking_assert (rtx_all_subrtx_bounds[code].count <= 3);
6201
6202 for (; format[i]; ++i)
6203 if (format[i] == 'E' || format[i] == 'V' || format[i] == 'e')
6204 return false;
6205
6206 return true;
6207}
6208
6209/* Initialize rtx_all_subrtx_bounds. */
6210void
6211init_rtlanal (void)
6212{
6213 int i;
6214 for (i = 0; i < NUM_RTX_CODE; i++)
6215 {
6216 if (!setup_reg_subrtx_bounds (i))
6217 rtx_all_subrtx_bounds[i].count = UCHAR_MAX;
6218 if (GET_RTX_CLASS (i) != RTX_CONST_OBJ)
6219 rtx_nonconst_subrtx_bounds[i] = rtx_all_subrtx_bounds[i];
6220 }
6221
6222 init_num_sign_bit_copies_in_rep ();
6223}
6224
6225/* Check whether this is a constant pool constant. */
6226bool
6227constant_pool_constant_p (rtx x)
6228{
6229 x = avoid_constant_pool_reference (x);
6230 return CONST_DOUBLE_P (x);
6231}
6232
6233/* If M is a bitmask that selects a field of low-order bits within an item but
6234 not the entire word, return the length of the field. Return -1 otherwise.
6235 M is used in machine mode MODE. */
6236
6237int
6238low_bitmask_len (machine_mode mode, unsigned HOST_WIDE_INT m)
6239{
6240 if (mode != VOIDmode)
6241 {
6242 if (!HWI_COMPUTABLE_MODE_P (mode))
6243 return -1;
6244 m &= GET_MODE_MASK (mode);
6245 }
6246
6247 return exact_log2 (x: m + 1);
6248}
6249
6250/* Return the mode of MEM's address. */
6251
6252scalar_int_mode
6253get_address_mode (rtx mem)
6254{
6255 machine_mode mode;
6256
6257 gcc_assert (MEM_P (mem));
6258 mode = GET_MODE (XEXP (mem, 0));
6259 if (mode != VOIDmode)
6260 return as_a <scalar_int_mode> (m: mode);
6261 return targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem));
6262}
6263
6264/* Split up a CONST_DOUBLE or integer constant rtx
6265 into two rtx's for single words,
6266 storing in *FIRST the word that comes first in memory in the target
6267 and in *SECOND the other.
6268
6269 TODO: This function needs to be rewritten to work on any size
6270 integer. */
6271
6272void
6273split_double (rtx value, rtx *first, rtx *second)
6274{
6275 if (CONST_INT_P (value))
6276 {
6277 if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD))
6278 {
6279 /* In this case the CONST_INT holds both target words.
6280 Extract the bits from it into two word-sized pieces.
6281 Sign extend each half to HOST_WIDE_INT. */
6282 unsigned HOST_WIDE_INT low, high;
6283 unsigned HOST_WIDE_INT mask, sign_bit, sign_extend;
6284 unsigned bits_per_word = BITS_PER_WORD;
6285
6286 /* Set sign_bit to the most significant bit of a word. */
6287 sign_bit = 1;
6288 sign_bit <<= bits_per_word - 1;
6289
6290 /* Set mask so that all bits of the word are set. We could
6291 have used 1 << BITS_PER_WORD instead of basing the
6292 calculation on sign_bit. However, on machines where
6293 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a
6294 compiler warning, even though the code would never be
6295 executed. */
6296 mask = sign_bit << 1;
6297 mask--;
6298
6299 /* Set sign_extend as any remaining bits. */
6300 sign_extend = ~mask;
6301
6302 /* Pick the lower word and sign-extend it. */
6303 low = INTVAL (value);
6304 low &= mask;
6305 if (low & sign_bit)
6306 low |= sign_extend;
6307
6308 /* Pick the higher word, shifted to the least significant
6309 bits, and sign-extend it. */
6310 high = INTVAL (value);
6311 high >>= bits_per_word - 1;
6312 high >>= 1;
6313 high &= mask;
6314 if (high & sign_bit)
6315 high |= sign_extend;
6316
6317 /* Store the words in the target machine order. */
6318 if (WORDS_BIG_ENDIAN)
6319 {
6320 *first = GEN_INT (high);
6321 *second = GEN_INT (low);
6322 }
6323 else
6324 {
6325 *first = GEN_INT (low);
6326 *second = GEN_INT (high);
6327 }
6328 }
6329 else
6330 {
6331 /* The rule for using CONST_INT for a wider mode
6332 is that we regard the value as signed.
6333 So sign-extend it. */
6334 rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx);
6335 if (WORDS_BIG_ENDIAN)
6336 {
6337 *first = high;
6338 *second = value;
6339 }
6340 else
6341 {
6342 *first = value;
6343 *second = high;
6344 }
6345 }
6346 }
6347 else if (GET_CODE (value) == CONST_WIDE_INT)
6348 {
6349 /* All of this is scary code and needs to be converted to
6350 properly work with any size integer. */
6351 gcc_assert (CONST_WIDE_INT_NUNITS (value) == 2);
6352 if (WORDS_BIG_ENDIAN)
6353 {
6354 *first = GEN_INT (CONST_WIDE_INT_ELT (value, 1));
6355 *second = GEN_INT (CONST_WIDE_INT_ELT (value, 0));
6356 }
6357 else
6358 {
6359 *first = GEN_INT (CONST_WIDE_INT_ELT (value, 0));
6360 *second = GEN_INT (CONST_WIDE_INT_ELT (value, 1));
6361 }
6362 }
6363 else if (!CONST_DOUBLE_P (value))
6364 {
6365 if (WORDS_BIG_ENDIAN)
6366 {
6367 *first = const0_rtx;
6368 *second = value;
6369 }
6370 else
6371 {
6372 *first = value;
6373 *second = const0_rtx;
6374 }
6375 }
6376 else if (GET_MODE (value) == VOIDmode
6377 /* This is the old way we did CONST_DOUBLE integers. */
6378 || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT)
6379 {
6380 /* In an integer, the words are defined as most and least significant.
6381 So order them by the target's convention. */
6382 if (WORDS_BIG_ENDIAN)
6383 {
6384 *first = GEN_INT (CONST_DOUBLE_HIGH (value));
6385 *second = GEN_INT (CONST_DOUBLE_LOW (value));
6386 }
6387 else
6388 {
6389 *first = GEN_INT (CONST_DOUBLE_LOW (value));
6390 *second = GEN_INT (CONST_DOUBLE_HIGH (value));
6391 }
6392 }
6393 else
6394 {
6395 long l[2];
6396
6397 /* Note, this converts the REAL_VALUE_TYPE to the target's
6398 format, splits up the floating point double and outputs
6399 exactly 32 bits of it into each of l[0] and l[1] --
6400 not necessarily BITS_PER_WORD bits. */
6401 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (value), l);
6402
6403 /* If 32 bits is an entire word for the target, but not for the host,
6404 then sign-extend on the host so that the number will look the same
6405 way on the host that it would on the target. See for instance
6406 simplify_unary_operation. The #if is needed to avoid compiler
6407 warnings. */
6408
6409#if HOST_BITS_PER_LONG > 32
6410 if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32)
6411 {
6412 if (l[0] & ((long) 1 << 31))
6413 l[0] |= ((unsigned long) (-1) << 32);
6414 if (l[1] & ((long) 1 << 31))
6415 l[1] |= ((unsigned long) (-1) << 32);
6416 }
6417#endif
6418
6419 *first = GEN_INT (l[0]);
6420 *second = GEN_INT (l[1]);
6421 }
6422}
6423
6424/* Return true if X is a sign_extract or zero_extract from the least
6425 significant bit. */
6426
6427static bool
6428lsb_bitfield_op_p (rtx x)
6429{
6430 if (GET_RTX_CLASS (GET_CODE (x)) == RTX_BITFIELD_OPS)
6431 {
6432 machine_mode mode = GET_MODE (XEXP (x, 0));
6433 HOST_WIDE_INT len = INTVAL (XEXP (x, 1));
6434 HOST_WIDE_INT pos = INTVAL (XEXP (x, 2));
6435 poly_int64 remaining_bits = GET_MODE_PRECISION (mode) - len;
6436
6437 return known_eq (pos, BITS_BIG_ENDIAN ? remaining_bits : 0);
6438 }
6439 return false;
6440}
6441
6442/* Strip outer address "mutations" from LOC and return a pointer to the
6443 inner value. If OUTER_CODE is nonnull, store the code of the innermost
6444 stripped expression there.
6445
6446 "Mutations" either convert between modes or apply some kind of
6447 extension, truncation or alignment. */
6448
6449rtx *
6450strip_address_mutations (rtx *loc, enum rtx_code *outer_code)
6451{
6452 for (;;)
6453 {
6454 enum rtx_code code = GET_CODE (*loc);
6455 if (GET_RTX_CLASS (code) == RTX_UNARY)
6456 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be
6457 used to convert between pointer sizes. */
6458 loc = &XEXP (*loc, 0);
6459 else if (lsb_bitfield_op_p (x: *loc))
6460 /* A [SIGN|ZERO]_EXTRACT from the least significant bit effectively
6461 acts as a combined truncation and extension. */
6462 loc = &XEXP (*loc, 0);
6463 else if (code == AND && CONST_INT_P (XEXP (*loc, 1)))
6464 /* (and ... (const_int -X)) is used to align to X bytes. */
6465 loc = &XEXP (*loc, 0);
6466 else if (code == SUBREG
6467 && !OBJECT_P (SUBREG_REG (*loc))
6468 && subreg_lowpart_p (*loc))
6469 /* (subreg (operator ...) ...) inside and is used for mode
6470 conversion too. */
6471 loc = &SUBREG_REG (*loc);
6472 else
6473 return loc;
6474 if (outer_code)
6475 *outer_code = code;
6476 }
6477}
6478
6479/* Return true if CODE applies some kind of scale. The scaled value is
6480 is the first operand and the scale is the second. */
6481
6482static bool
6483binary_scale_code_p (enum rtx_code code)
6484{
6485 return (code == MULT
6486 || code == ASHIFT
6487 /* Needed by ARM targets. */
6488 || code == ASHIFTRT
6489 || code == LSHIFTRT
6490 || code == ROTATE
6491 || code == ROTATERT);
6492}
6493
6494/* If *INNER can be interpreted as a base, return a pointer to the inner term
6495 (see address_info). Return null otherwise. */
6496
6497static rtx *
6498get_base_term (rtx *inner)
6499{
6500 if (GET_CODE (*inner) == LO_SUM)
6501 inner = strip_address_mutations (loc: &XEXP (*inner, 0));
6502 if (REG_P (*inner)
6503 || MEM_P (*inner)
6504 || GET_CODE (*inner) == SUBREG
6505 || GET_CODE (*inner) == SCRATCH)
6506 return inner;
6507 return 0;
6508}
6509
6510/* If *INNER can be interpreted as an index, return a pointer to the inner term
6511 (see address_info). Return null otherwise. */
6512
6513static rtx *
6514get_index_term (rtx *inner)
6515{
6516 /* At present, only constant scales are allowed. */
6517 if (binary_scale_code_p (GET_CODE (*inner)) && CONSTANT_P (XEXP (*inner, 1)))
6518 inner = strip_address_mutations (loc: &XEXP (*inner, 0));
6519 if (REG_P (*inner)
6520 || MEM_P (*inner)
6521 || GET_CODE (*inner) == SUBREG
6522 || GET_CODE (*inner) == SCRATCH)
6523 return inner;
6524 return 0;
6525}
6526
6527/* Set the segment part of address INFO to LOC, given that INNER is the
6528 unmutated value. */
6529
6530static void
6531set_address_segment (struct address_info *info, rtx *loc, rtx *inner)
6532{
6533 gcc_assert (!info->segment);
6534 info->segment = loc;
6535 info->segment_term = inner;
6536}
6537
6538/* Set the base part of address INFO to LOC, given that INNER is the
6539 unmutated value. */
6540
6541static void
6542set_address_base (struct address_info *info, rtx *loc, rtx *inner)
6543{
6544 gcc_assert (!info->base);
6545 info->base = loc;
6546 info->base_term = inner;
6547}
6548
6549/* Set the index part of address INFO to LOC, given that INNER is the
6550 unmutated value. */
6551
6552static void
6553set_address_index (struct address_info *info, rtx *loc, rtx *inner)
6554{
6555 gcc_assert (!info->index);
6556 info->index = loc;
6557 info->index_term = inner;
6558}
6559
6560/* Set the displacement part of address INFO to LOC, given that INNER
6561 is the constant term. */
6562
6563static void
6564set_address_disp (struct address_info *info, rtx *loc, rtx *inner)
6565{
6566 gcc_assert (!info->disp);
6567 info->disp = loc;
6568 info->disp_term = inner;
6569}
6570
6571/* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the
6572 rest of INFO accordingly. */
6573
6574static void
6575decompose_incdec_address (struct address_info *info)
6576{
6577 info->autoinc_p = true;
6578
6579 rtx *base = &XEXP (*info->inner, 0);
6580 set_address_base (info, loc: base, inner: base);
6581 gcc_checking_assert (info->base == info->base_term);
6582
6583 /* These addresses are only valid when the size of the addressed
6584 value is known. */
6585 gcc_checking_assert (info->mode != VOIDmode);
6586}
6587
6588/* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest
6589 of INFO accordingly. */
6590
6591static void
6592decompose_automod_address (struct address_info *info)
6593{
6594 info->autoinc_p = true;
6595
6596 rtx *base = &XEXP (*info->inner, 0);
6597 set_address_base (info, loc: base, inner: base);
6598 gcc_checking_assert (info->base == info->base_term);
6599
6600 rtx plus = XEXP (*info->inner, 1);
6601 gcc_assert (GET_CODE (plus) == PLUS);
6602
6603 info->base_term2 = &XEXP (plus, 0);
6604 gcc_checking_assert (rtx_equal_p (*info->base_term, *info->base_term2));
6605
6606 rtx *step = &XEXP (plus, 1);
6607 rtx *inner_step = strip_address_mutations (loc: step);
6608 if (CONSTANT_P (*inner_step))
6609 set_address_disp (info, loc: step, inner: inner_step);
6610 else
6611 set_address_index (info, loc: step, inner: inner_step);
6612}
6613
6614/* Treat *LOC as a tree of PLUS operands and store pointers to the summed
6615 values in [PTR, END). Return a pointer to the end of the used array. */
6616
6617static rtx **
6618extract_plus_operands (rtx *loc, rtx **ptr, rtx **end)
6619{
6620 rtx x = *loc;
6621 if (GET_CODE (x) == PLUS)
6622 {
6623 ptr = extract_plus_operands (loc: &XEXP (x, 0), ptr, end);
6624 ptr = extract_plus_operands (loc: &XEXP (x, 1), ptr, end);
6625 }
6626 else
6627 {
6628 gcc_assert (ptr != end);
6629 *ptr++ = loc;
6630 }
6631 return ptr;
6632}
6633
6634/* Evaluate the likelihood of X being a base or index value, returning
6635 positive if it is likely to be a base, negative if it is likely to be
6636 an index, and 0 if we can't tell. Make the magnitude of the return
6637 value reflect the amount of confidence we have in the answer.
6638
6639 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */
6640
6641static int
6642baseness (rtx x, machine_mode mode, addr_space_t as,
6643 enum rtx_code outer_code, enum rtx_code index_code)
6644{
6645 /* Believe *_POINTER unless the address shape requires otherwise. */
6646 if (REG_P (x) && REG_POINTER (x))
6647 return 2;
6648 if (MEM_P (x) && MEM_POINTER (x))
6649 return 2;
6650
6651 if (REG_P (x) && HARD_REGISTER_P (x))
6652 {
6653 /* X is a hard register. If it only fits one of the base
6654 or index classes, choose that interpretation. */
6655 int regno = REGNO (x);
6656 bool base_p = ok_for_base_p_1 (regno, mode, as, outer_code, index_code);
6657 bool index_p = REGNO_OK_FOR_INDEX_P (regno);
6658 if (base_p != index_p)
6659 return base_p ? 1 : -1;
6660 }
6661 return 0;
6662}
6663
6664/* INFO->INNER describes a normal, non-automodified address.
6665 Fill in the rest of INFO accordingly. */
6666
6667static void
6668decompose_normal_address (struct address_info *info)
6669{
6670 /* Treat the address as the sum of up to four values. */
6671 rtx *ops[4];
6672 size_t n_ops = extract_plus_operands (loc: info->inner, ptr: ops,
6673 end: ops + ARRAY_SIZE (ops)) - ops;
6674
6675 /* If there is more than one component, any base component is in a PLUS. */
6676 if (n_ops > 1)
6677 info->base_outer_code = PLUS;
6678
6679 /* Try to classify each sum operand now. Leave those that could be
6680 either a base or an index in OPS. */
6681 rtx *inner_ops[4];
6682 size_t out = 0;
6683 for (size_t in = 0; in < n_ops; ++in)
6684 {
6685 rtx *loc = ops[in];
6686 rtx *inner = strip_address_mutations (loc);
6687 if (CONSTANT_P (*inner))
6688 set_address_disp (info, loc, inner);
6689 else if (GET_CODE (*inner) == UNSPEC)
6690 set_address_segment (info, loc, inner);
6691 else
6692 {
6693 /* The only other possibilities are a base or an index. */
6694 rtx *base_term = get_base_term (inner);
6695 rtx *index_term = get_index_term (inner);
6696 gcc_assert (base_term || index_term);
6697 if (!base_term)
6698 set_address_index (info, loc, inner: index_term);
6699 else if (!index_term)
6700 set_address_base (info, loc, inner: base_term);
6701 else
6702 {
6703 gcc_assert (base_term == index_term);
6704 ops[out] = loc;
6705 inner_ops[out] = base_term;
6706 ++out;
6707 }
6708 }
6709 }
6710
6711 /* Classify the remaining OPS members as bases and indexes. */
6712 if (out == 1)
6713 {
6714 /* If we haven't seen a base or an index yet, assume that this is
6715 the base. If we were confident that another term was the base
6716 or index, treat the remaining operand as the other kind. */
6717 if (!info->base)
6718 set_address_base (info, loc: ops[0], inner: inner_ops[0]);
6719 else
6720 set_address_index (info, loc: ops[0], inner: inner_ops[0]);
6721 }
6722 else if (out == 2)
6723 {
6724 /* In the event of a tie, assume the base comes first. */
6725 if (baseness (x: *inner_ops[0], mode: info->mode, as: info->as, outer_code: PLUS,
6726 GET_CODE (*ops[1]))
6727 >= baseness (x: *inner_ops[1], mode: info->mode, as: info->as, outer_code: PLUS,
6728 GET_CODE (*ops[0])))
6729 {
6730 set_address_base (info, loc: ops[0], inner: inner_ops[0]);
6731 set_address_index (info, loc: ops[1], inner: inner_ops[1]);
6732 }
6733 else
6734 {
6735 set_address_base (info, loc: ops[1], inner: inner_ops[1]);
6736 set_address_index (info, loc: ops[0], inner: inner_ops[0]);
6737 }
6738 }
6739 else
6740 gcc_assert (out == 0);
6741}
6742
6743/* Describe address *LOC in *INFO. MODE is the mode of the addressed value,
6744 or VOIDmode if not known. AS is the address space associated with LOC.
6745 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */
6746
6747void
6748decompose_address (struct address_info *info, rtx *loc, machine_mode mode,
6749 addr_space_t as, enum rtx_code outer_code)
6750{
6751 memset (s: info, c: 0, n: sizeof (*info));
6752 info->mode = mode;
6753 info->as = as;
6754 info->addr_outer_code = outer_code;
6755 info->outer = loc;
6756 info->inner = strip_address_mutations (loc, outer_code: &outer_code);
6757 info->base_outer_code = outer_code;
6758 switch (GET_CODE (*info->inner))
6759 {
6760 case PRE_DEC:
6761 case PRE_INC:
6762 case POST_DEC:
6763 case POST_INC:
6764 decompose_incdec_address (info);
6765 break;
6766
6767 case PRE_MODIFY:
6768 case POST_MODIFY:
6769 decompose_automod_address (info);
6770 break;
6771
6772 default:
6773 decompose_normal_address (info);
6774 break;
6775 }
6776}
6777
6778/* Describe address operand LOC in INFO. */
6779
6780void
6781decompose_lea_address (struct address_info *info, rtx *loc)
6782{
6783 decompose_address (info, loc, VOIDmode, ADDR_SPACE_GENERIC, outer_code: ADDRESS);
6784}
6785
6786/* Describe the address of MEM X in INFO. */
6787
6788void
6789decompose_mem_address (struct address_info *info, rtx x)
6790{
6791 gcc_assert (MEM_P (x));
6792 decompose_address (info, loc: &XEXP (x, 0), GET_MODE (x),
6793 MEM_ADDR_SPACE (x), outer_code: MEM);
6794}
6795
6796/* Update INFO after a change to the address it describes. */
6797
6798void
6799update_address (struct address_info *info)
6800{
6801 decompose_address (info, loc: info->outer, mode: info->mode, as: info->as,
6802 outer_code: info->addr_outer_code);
6803}
6804
6805/* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is
6806 more complicated than that. */
6807
6808HOST_WIDE_INT
6809get_index_scale (const struct address_info *info)
6810{
6811 rtx index = *info->index;
6812 if (GET_CODE (index) == MULT
6813 && CONST_INT_P (XEXP (index, 1))
6814 && info->index_term == &XEXP (index, 0))
6815 return INTVAL (XEXP (index, 1));
6816
6817 if (GET_CODE (index) == ASHIFT
6818 && CONST_INT_P (XEXP (index, 1))
6819 && info->index_term == &XEXP (index, 0))
6820 return HOST_WIDE_INT_1 << INTVAL (XEXP (index, 1));
6821
6822 if (info->index == info->index_term)
6823 return 1;
6824
6825 return 0;
6826}
6827
6828/* Return the "index code" of INFO, in the form required by
6829 ok_for_base_p_1. */
6830
6831enum rtx_code
6832get_index_code (const struct address_info *info)
6833{
6834 if (info->index)
6835 return GET_CODE (*info->index);
6836
6837 if (info->disp)
6838 return GET_CODE (*info->disp);
6839
6840 return SCRATCH;
6841}
6842
6843/* Return true if RTL X contains a SYMBOL_REF. */
6844
6845bool
6846contains_symbol_ref_p (const_rtx x)
6847{
6848 subrtx_iterator::array_type array;
6849 FOR_EACH_SUBRTX (iter, array, x, ALL)
6850 if (SYMBOL_REF_P (*iter))
6851 return true;
6852
6853 return false;
6854}
6855
6856/* Return true if RTL X contains a SYMBOL_REF or LABEL_REF. */
6857
6858bool
6859contains_symbolic_reference_p (const_rtx x)
6860{
6861 subrtx_iterator::array_type array;
6862 FOR_EACH_SUBRTX (iter, array, x, ALL)
6863 if (SYMBOL_REF_P (*iter) || GET_CODE (*iter) == LABEL_REF)
6864 return true;
6865
6866 return false;
6867}
6868
6869/* Return true if RTL X contains a constant pool address. */
6870
6871bool
6872contains_constant_pool_address_p (const_rtx x)
6873{
6874 subrtx_iterator::array_type array;
6875 FOR_EACH_SUBRTX (iter, array, x, ALL)
6876 if (SYMBOL_REF_P (*iter) && CONSTANT_POOL_ADDRESS_P (*iter))
6877 return true;
6878
6879 return false;
6880}
6881
6882
6883/* Return true if X contains a thread-local symbol. */
6884
6885bool
6886tls_referenced_p (const_rtx x)
6887{
6888 if (!targetm.have_tls)
6889 return false;
6890
6891 subrtx_iterator::array_type array;
6892 FOR_EACH_SUBRTX (iter, array, x, ALL)
6893 if (GET_CODE (*iter) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (*iter) != 0)
6894 return true;
6895 return false;
6896}
6897
6898/* Process recursively X of INSN and add REG_INC notes if necessary. */
6899void
6900add_auto_inc_notes (rtx_insn *insn, rtx x)
6901{
6902 enum rtx_code code = GET_CODE (x);
6903 const char *fmt;
6904 int i, j;
6905
6906 if (code == MEM && auto_inc_p (XEXP (x, 0)))
6907 {
6908 add_reg_note (insn, kind: REG_INC, XEXP (XEXP (x, 0), 0));
6909 return;
6910 }
6911
6912 /* Scan all X sub-expressions. */
6913 fmt = GET_RTX_FORMAT (code);
6914 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6915 {
6916 if (fmt[i] == 'e')
6917 add_auto_inc_notes (insn, XEXP (x, i));
6918 else if (fmt[i] == 'E')
6919 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
6920 add_auto_inc_notes (insn, XVECEXP (x, i, j));
6921 }
6922}
6923
6924/* Return true if X is register asm. */
6925
6926bool
6927register_asm_p (const_rtx x)
6928{
6929 return (REG_P (x)
6930 && REG_EXPR (x) != NULL_TREE
6931 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (x))
6932 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (x))
6933 && DECL_REGISTER (REG_EXPR (x)));
6934}
6935
6936/* Return true if, for all OP of mode OP_MODE:
6937
6938 (vec_select:RESULT_MODE OP SEL)
6939
6940 is equivalent to the highpart RESULT_MODE of OP. */
6941
6942bool
6943vec_series_highpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel)
6944{
6945 int nunits;
6946 if (GET_MODE_NUNITS (mode: op_mode).is_constant (const_value: &nunits)
6947 && targetm.can_change_mode_class (op_mode, result_mode, ALL_REGS))
6948 {
6949 int offset = BYTES_BIG_ENDIAN ? 0 : nunits - XVECLEN (sel, 0);
6950 return rtvec_series_p (XVEC (sel, 0), offset);
6951 }
6952 return false;
6953}
6954
6955/* Return true if, for all OP of mode OP_MODE:
6956
6957 (vec_select:RESULT_MODE OP SEL)
6958
6959 is equivalent to the lowpart RESULT_MODE of OP. */
6960
6961bool
6962vec_series_lowpart_p (machine_mode result_mode, machine_mode op_mode, rtx sel)
6963{
6964 int nunits;
6965 if (GET_MODE_NUNITS (mode: op_mode).is_constant (const_value: &nunits)
6966 && targetm.can_change_mode_class (op_mode, result_mode, ALL_REGS))
6967 {
6968 int offset = BYTES_BIG_ENDIAN ? nunits - XVECLEN (sel, 0) : 0;
6969 return rtvec_series_p (XVEC (sel, 0), offset);
6970 }
6971 return false;
6972}
6973
6974/* Return true if X contains a paradoxical subreg. */
6975
6976bool
6977contains_paradoxical_subreg_p (rtx x)
6978{
6979 subrtx_var_iterator::array_type array;
6980 FOR_EACH_SUBRTX_VAR (iter, array, x, NONCONST)
6981 {
6982 x = *iter;
6983 if (SUBREG_P (x) && paradoxical_subreg_p (x))
6984 return true;
6985 }
6986 return false;
6987}
6988

source code of gcc/rtlanal.cc