| 1 | /* Atomic operations. X86 version. |
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| 2 | Copyright (C) 2018-2024 Free Software Foundation, Inc. |
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| 3 | This file is part of the GNU C Library. |
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| 4 | |
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| 5 | The GNU C Library is free software; you can redistribute it and/or |
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| 6 | modify it under the terms of the GNU Lesser General Public |
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| 7 | License as published by the Free Software Foundation; either |
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| 8 | version 2.1 of the License, or (at your option) any later version. |
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| 9 | |
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| 10 | The GNU C Library is distributed in the hope that it will be useful, |
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| 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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| 13 | Lesser General Public License for more details. |
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| 14 | |
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| 15 | You should have received a copy of the GNU Lesser General Public |
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| 16 | License along with the GNU C Library; if not, see |
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| 17 | <https://www.gnu.org/licenses/>. */ |
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| 18 | |
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| 19 | #ifndef _X86_ATOMIC_MACHINE_H |
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| 20 | #define _X86_ATOMIC_MACHINE_H 1 |
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| 21 | |
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| 22 | #include <stdint.h> |
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| 23 | #include <tls.h> /* For tcbhead_t. */ |
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| 24 | #include <libc-pointer-arith.h> /* For cast_to_integer. */ |
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| 25 | |
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| 26 | #define LOCK_PREFIX "lock;" |
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| 27 | |
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| 28 | #define USE_ATOMIC_COMPILER_BUILTINS 1 |
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| 29 | |
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| 30 | #ifdef __x86_64__ |
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| 31 | # define __HAVE_64B_ATOMICS 1 |
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| 32 | # define SP_REG "rsp" |
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| 33 | # define SEG_REG "fs" |
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| 34 | # define BR_CONSTRAINT "q" |
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| 35 | # define IBR_CONSTRAINT "iq" |
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| 36 | #else |
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| 37 | /* Since the Pentium, i386 CPUs have supported 64-bit atomics, but the |
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| 38 | i386 psABI supplement provides only 4-byte alignment for uint64_t |
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| 39 | inside structs, so it is currently not possible to use 64-bit |
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| 40 | atomics on this platform. */ |
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| 41 | # define __HAVE_64B_ATOMICS 0 |
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| 42 | # define SP_REG "esp" |
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| 43 | # define SEG_REG "gs" |
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| 44 | # define BR_CONSTRAINT "r" |
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| 45 | # define IBR_CONSTRAINT "ir" |
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| 46 | #endif |
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| 47 | #define ATOMIC_EXCHANGE_USES_CAS 0 |
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| 48 | |
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| 49 | #define atomic_compare_and_exchange_val_acq(mem, newval, oldval) \ |
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| 50 | __sync_val_compare_and_swap (mem, oldval, newval) |
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| 51 | #define atomic_compare_and_exchange_bool_acq(mem, newval, oldval) \ |
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| 52 | (! __sync_bool_compare_and_swap (mem, oldval, newval)) |
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| 53 | |
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| 54 | |
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| 55 | #define __arch_c_compare_and_exchange_val_8_acq(mem, newval, oldval) \ |
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| 56 | ({ __typeof (*mem) ret; \ |
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| 57 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
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| 58 | "je 0f\n\t" \ |
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| 59 | "lock\n" \ |
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| 60 | "0:\tcmpxchgb %b2, %1" \ |
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| 61 | : "=a" (ret), "=m" (*mem) \ |
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| 62 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
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| 63 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 64 | ret; }) |
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| 65 | |
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| 66 | #define __arch_c_compare_and_exchange_val_16_acq(mem, newval, oldval) \ |
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| 67 | ({ __typeof (*mem) ret; \ |
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| 68 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
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| 69 | "je 0f\n\t" \ |
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| 70 | "lock\n" \ |
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| 71 | "0:\tcmpxchgw %w2, %1" \ |
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| 72 | : "=a" (ret), "=m" (*mem) \ |
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| 73 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
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| 74 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 75 | ret; }) |
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| 76 | |
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| 77 | #define __arch_c_compare_and_exchange_val_32_acq(mem, newval, oldval) \ |
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| 78 | ({ __typeof (*mem) ret; \ |
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| 79 | __asm __volatile ("cmpl $0, %%" SEG_REG ":%P5\n\t" \ |
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| 80 | "je 0f\n\t" \ |
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| 81 | "lock\n" \ |
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| 82 | "0:\tcmpxchgl %2, %1" \ |
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| 83 | : "=a" (ret), "=m" (*mem) \ |
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| 84 | : BR_CONSTRAINT (newval), "m" (*mem), "0" (oldval), \ |
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| 85 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 86 | ret; }) |
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| 87 | |
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| 88 | #ifdef __x86_64__ |
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| 89 | # define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \ |
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| 90 | ({ __typeof (*mem) ret; \ |
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| 91 | __asm __volatile ("cmpl $0, %%fs:%P5\n\t" \ |
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| 92 | "je 0f\n\t" \ |
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| 93 | "lock\n" \ |
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| 94 | "0:\tcmpxchgq %q2, %1" \ |
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| 95 | : "=a" (ret), "=m" (*mem) \ |
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| 96 | : "q" ((int64_t) cast_to_integer (newval)), \ |
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| 97 | "m" (*mem), \ |
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| 98 | "0" ((int64_t) cast_to_integer (oldval)), \ |
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| 99 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 100 | ret; }) |
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| 101 | # define do_exchange_and_add_val_64_acq(pfx, mem, value) 0 |
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| 102 | # define do_add_val_64_acq(pfx, mem, value) do { } while (0) |
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| 103 | #else |
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| 104 | /* XXX We do not really need 64-bit compare-and-exchange. At least |
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| 105 | not in the moment. Using it would mean causing portability |
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| 106 | problems since not many other 32-bit architectures have support for |
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| 107 | such an operation. So don't define any code for now. If it is |
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| 108 | really going to be used the code below can be used on Intel Pentium |
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| 109 | and later, but NOT on i486. */ |
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| 110 | # define __arch_c_compare_and_exchange_val_64_acq(mem, newval, oldval) \ |
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| 111 | ({ __typeof (*mem) ret = *(mem); \ |
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| 112 | __atomic_link_error (); \ |
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| 113 | ret = (newval); \ |
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| 114 | ret = (oldval); \ |
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| 115 | ret; }) |
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| 116 | |
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| 117 | # define __arch_compare_and_exchange_val_64_acq(mem, newval, oldval) \ |
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| 118 | ({ __typeof (*mem) ret = *(mem); \ |
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| 119 | __atomic_link_error (); \ |
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| 120 | ret = (newval); \ |
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| 121 | ret = (oldval); \ |
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| 122 | ret; }) |
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| 123 | |
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| 124 | # define do_exchange_and_add_val_64_acq(pfx, mem, value) \ |
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| 125 | ({ __typeof (value) __addval = (value); \ |
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| 126 | __typeof (*mem) __result; \ |
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| 127 | __typeof (mem) __memp = (mem); \ |
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| 128 | __typeof (*mem) __tmpval; \ |
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| 129 | __result = *__memp; \ |
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| 130 | do \ |
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| 131 | __tmpval = __result; \ |
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| 132 | while ((__result = pfx##_compare_and_exchange_val_64_acq \ |
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| 133 | (__memp, __result + __addval, __result)) == __tmpval); \ |
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| 134 | __result; }) |
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| 135 | |
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| 136 | # define do_add_val_64_acq(pfx, mem, value) \ |
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| 137 | { \ |
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| 138 | __typeof (value) __addval = (value); \ |
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| 139 | __typeof (mem) __memp = (mem); \ |
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| 140 | __typeof (*mem) __oldval = *__memp; \ |
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| 141 | __typeof (*mem) __tmpval; \ |
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| 142 | do \ |
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| 143 | __tmpval = __oldval; \ |
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| 144 | while ((__oldval = pfx##_compare_and_exchange_val_64_acq \ |
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| 145 | (__memp, __oldval + __addval, __oldval)) == __tmpval); \ |
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| 146 | } |
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| 147 | #endif |
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| 148 | |
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| 149 | |
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| 150 | /* Note that we need no lock prefix. */ |
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| 151 | #define atomic_exchange_acq(mem, newvalue) \ |
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| 152 | ({ __typeof (*mem) result; \ |
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| 153 | if (sizeof (*mem) == 1) \ |
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| 154 | __asm __volatile ("xchgb %b0, %1" \ |
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| 155 | : "=q" (result), "=m" (*mem) \ |
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| 156 | : "0" (newvalue), "m" (*mem)); \ |
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| 157 | else if (sizeof (*mem) == 2) \ |
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| 158 | __asm __volatile ("xchgw %w0, %1" \ |
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| 159 | : "=r" (result), "=m" (*mem) \ |
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| 160 | : "0" (newvalue), "m" (*mem)); \ |
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| 161 | else if (sizeof (*mem) == 4) \ |
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| 162 | __asm __volatile ("xchgl %0, %1" \ |
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| 163 | : "=r" (result), "=m" (*mem) \ |
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| 164 | : "0" (newvalue), "m" (*mem)); \ |
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| 165 | else if (__HAVE_64B_ATOMICS) \ |
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| 166 | __asm __volatile ("xchgq %q0, %1" \ |
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| 167 | : "=r" (result), "=m" (*mem) \ |
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| 168 | : "0" ((int64_t) cast_to_integer (newvalue)), \ |
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| 169 | "m" (*mem)); \ |
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| 170 | else \ |
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| 171 | { \ |
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| 172 | result = 0; \ |
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| 173 | __atomic_link_error (); \ |
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| 174 | } \ |
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| 175 | result; }) |
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| 176 | |
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| 177 | |
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| 178 | #define __arch_exchange_and_add_body(lock, pfx, mem, value) \ |
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| 179 | ({ __typeof (*mem) __result; \ |
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| 180 | __typeof (value) __addval = (value); \ |
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| 181 | if (sizeof (*mem) == 1) \ |
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| 182 | __asm __volatile (lock "xaddb %b0, %1" \ |
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| 183 | : "=q" (__result), "=m" (*mem) \ |
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| 184 | : "0" (__addval), "m" (*mem), \ |
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| 185 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 186 | else if (sizeof (*mem) == 2) \ |
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| 187 | __asm __volatile (lock "xaddw %w0, %1" \ |
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| 188 | : "=r" (__result), "=m" (*mem) \ |
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| 189 | : "0" (__addval), "m" (*mem), \ |
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| 190 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 191 | else if (sizeof (*mem) == 4) \ |
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| 192 | __asm __volatile (lock "xaddl %0, %1" \ |
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| 193 | : "=r" (__result), "=m" (*mem) \ |
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| 194 | : "0" (__addval), "m" (*mem), \ |
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| 195 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 196 | else if (__HAVE_64B_ATOMICS) \ |
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| 197 | __asm __volatile (lock "xaddq %q0, %1" \ |
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| 198 | : "=r" (__result), "=m" (*mem) \ |
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| 199 | : "0" ((int64_t) cast_to_integer (__addval)), \ |
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| 200 | "m" (*mem), \ |
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| 201 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 202 | else \ |
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| 203 | __result = do_exchange_and_add_val_64_acq (pfx, (mem), __addval); \ |
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| 204 | __result; }) |
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| 205 | |
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| 206 | #define atomic_exchange_and_add(mem, value) \ |
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| 207 | __sync_fetch_and_add (mem, value) |
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| 208 | |
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| 209 | #define __arch_exchange_and_add_cprefix \ |
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| 210 | "cmpl $0, %%" SEG_REG ":%P4\n\tje 0f\n\tlock\n0:\t" |
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| 211 | |
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| 212 | #define catomic_exchange_and_add(mem, value) \ |
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| 213 | __arch_exchange_and_add_body (__arch_exchange_and_add_cprefix, __arch_c, \ |
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| 214 | mem, value) |
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| 215 | |
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| 216 | |
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| 217 | #define __arch_add_body(lock, pfx, apfx, mem, value) \ |
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| 218 | do { \ |
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| 219 | if (__builtin_constant_p (value) && (value) == 1) \ |
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| 220 | pfx##_increment (mem); \ |
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| 221 | else if (__builtin_constant_p (value) && (value) == -1) \ |
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| 222 | pfx##_decrement (mem); \ |
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| 223 | else if (sizeof (*mem) == 1) \ |
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| 224 | __asm __volatile (lock "addb %b1, %0" \ |
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| 225 | : "=m" (*mem) \ |
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| 226 | : IBR_CONSTRAINT (value), "m" (*mem), \ |
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| 227 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 228 | else if (sizeof (*mem) == 2) \ |
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| 229 | __asm __volatile (lock "addw %w1, %0" \ |
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| 230 | : "=m" (*mem) \ |
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| 231 | : "ir" (value), "m" (*mem), \ |
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| 232 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 233 | else if (sizeof (*mem) == 4) \ |
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| 234 | __asm __volatile (lock "addl %1, %0" \ |
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| 235 | : "=m" (*mem) \ |
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| 236 | : "ir" (value), "m" (*mem), \ |
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| 237 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 238 | else if (__HAVE_64B_ATOMICS) \ |
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| 239 | __asm __volatile (lock "addq %q1, %0" \ |
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| 240 | : "=m" (*mem) \ |
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| 241 | : "ir" ((int64_t) cast_to_integer (value)), \ |
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| 242 | "m" (*mem), \ |
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| 243 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 244 | else \ |
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| 245 | do_add_val_64_acq (apfx, (mem), (value)); \ |
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| 246 | } while (0) |
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| 247 | |
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| 248 | # define atomic_add(mem, value) \ |
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| 249 | __arch_add_body (LOCK_PREFIX, atomic, __arch, mem, value) |
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| 250 | |
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| 251 | #define __arch_add_cprefix \ |
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| 252 | "cmpl $0, %%" SEG_REG ":%P3\n\tje 0f\n\tlock\n0:\t" |
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| 253 | |
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| 254 | #define catomic_add(mem, value) \ |
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| 255 | __arch_add_body (__arch_add_cprefix, atomic, __arch_c, mem, value) |
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| 256 | |
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| 257 | |
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| 258 | #define atomic_add_negative(mem, value) \ |
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| 259 | ({ unsigned char __result; \ |
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| 260 | if (sizeof (*mem) == 1) \ |
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| 261 | __asm __volatile (LOCK_PREFIX "addb %b2, %0; sets %1" \ |
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| 262 | : "=m" (*mem), "=qm" (__result) \ |
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| 263 | : IBR_CONSTRAINT (value), "m" (*mem)); \ |
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| 264 | else if (sizeof (*mem) == 2) \ |
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| 265 | __asm __volatile (LOCK_PREFIX "addw %w2, %0; sets %1" \ |
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| 266 | : "=m" (*mem), "=qm" (__result) \ |
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| 267 | : "ir" (value), "m" (*mem)); \ |
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| 268 | else if (sizeof (*mem) == 4) \ |
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| 269 | __asm __volatile (LOCK_PREFIX "addl %2, %0; sets %1" \ |
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| 270 | : "=m" (*mem), "=qm" (__result) \ |
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| 271 | : "ir" (value), "m" (*mem)); \ |
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| 272 | else if (__HAVE_64B_ATOMICS) \ |
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| 273 | __asm __volatile (LOCK_PREFIX "addq %q2, %0; sets %1" \ |
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| 274 | : "=m" (*mem), "=qm" (__result) \ |
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| 275 | : "ir" ((int64_t) cast_to_integer (value)), \ |
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| 276 | "m" (*mem)); \ |
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| 277 | else \ |
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| 278 | __atomic_link_error (); \ |
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| 279 | __result; }) |
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| 280 | |
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| 281 | |
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| 282 | #define atomic_add_zero(mem, value) \ |
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| 283 | ({ unsigned char __result; \ |
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| 284 | if (sizeof (*mem) == 1) \ |
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| 285 | __asm __volatile (LOCK_PREFIX "addb %b2, %0; setz %1" \ |
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| 286 | : "=m" (*mem), "=qm" (__result) \ |
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| 287 | : IBR_CONSTRAINT (value), "m" (*mem)); \ |
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| 288 | else if (sizeof (*mem) == 2) \ |
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| 289 | __asm __volatile (LOCK_PREFIX "addw %w2, %0; setz %1" \ |
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| 290 | : "=m" (*mem), "=qm" (__result) \ |
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| 291 | : "ir" (value), "m" (*mem)); \ |
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| 292 | else if (sizeof (*mem) == 4) \ |
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| 293 | __asm __volatile (LOCK_PREFIX "addl %2, %0; setz %1" \ |
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| 294 | : "=m" (*mem), "=qm" (__result) \ |
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| 295 | : "ir" (value), "m" (*mem)); \ |
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| 296 | else if (__HAVE_64B_ATOMICS) \ |
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| 297 | __asm __volatile (LOCK_PREFIX "addq %q2, %0; setz %1" \ |
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| 298 | : "=m" (*mem), "=qm" (__result) \ |
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| 299 | : "ir" ((int64_t) cast_to_integer (value)), \ |
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| 300 | "m" (*mem)); \ |
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| 301 | else \ |
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| 302 | __atomic_link_error (); \ |
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| 303 | __result; }) |
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| 304 | |
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| 305 | |
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| 306 | #define __arch_increment_body(lock, pfx, mem) \ |
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| 307 | do { \ |
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| 308 | if (sizeof (*mem) == 1) \ |
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| 309 | __asm __volatile (lock "incb %b0" \ |
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| 310 | : "=m" (*mem) \ |
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| 311 | : "m" (*mem), \ |
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| 312 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 313 | else if (sizeof (*mem) == 2) \ |
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| 314 | __asm __volatile (lock "incw %w0" \ |
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| 315 | : "=m" (*mem) \ |
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| 316 | : "m" (*mem), \ |
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| 317 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 318 | else if (sizeof (*mem) == 4) \ |
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| 319 | __asm __volatile (lock "incl %0" \ |
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| 320 | : "=m" (*mem) \ |
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| 321 | : "m" (*mem), \ |
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| 322 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 323 | else if (__HAVE_64B_ATOMICS) \ |
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| 324 | __asm __volatile (lock "incq %q0" \ |
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| 325 | : "=m" (*mem) \ |
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| 326 | : "m" (*mem), \ |
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| 327 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 328 | else \ |
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| 329 | do_add_val_64_acq (pfx, mem, 1); \ |
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| 330 | } while (0) |
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| 331 | |
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| 332 | #define atomic_increment(mem) __arch_increment_body (LOCK_PREFIX, __arch, mem) |
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| 333 | |
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| 334 | #define __arch_increment_cprefix \ |
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| 335 | "cmpl $0, %%" SEG_REG ":%P2\n\tje 0f\n\tlock\n0:\t" |
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| 336 | |
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| 337 | #define catomic_increment(mem) \ |
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| 338 | __arch_increment_body (__arch_increment_cprefix, __arch_c, mem) |
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| 339 | |
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| 340 | |
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| 341 | #define atomic_increment_and_test(mem) \ |
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| 342 | ({ unsigned char __result; \ |
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| 343 | if (sizeof (*mem) == 1) \ |
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| 344 | __asm __volatile (LOCK_PREFIX "incb %b0; sete %b1" \ |
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| 345 | : "=m" (*mem), "=qm" (__result) \ |
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| 346 | : "m" (*mem)); \ |
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| 347 | else if (sizeof (*mem) == 2) \ |
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| 348 | __asm __volatile (LOCK_PREFIX "incw %w0; sete %w1" \ |
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| 349 | : "=m" (*mem), "=qm" (__result) \ |
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| 350 | : "m" (*mem)); \ |
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| 351 | else if (sizeof (*mem) == 4) \ |
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| 352 | __asm __volatile (LOCK_PREFIX "incl %0; sete %1" \ |
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| 353 | : "=m" (*mem), "=qm" (__result) \ |
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| 354 | : "m" (*mem)); \ |
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| 355 | else if (__HAVE_64B_ATOMICS) \ |
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| 356 | __asm __volatile (LOCK_PREFIX "incq %q0; sete %1" \ |
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| 357 | : "=m" (*mem), "=qm" (__result) \ |
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| 358 | : "m" (*mem)); \ |
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| 359 | else \ |
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| 360 | __atomic_link_error (); \ |
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| 361 | __result; }) |
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| 362 | |
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| 363 | |
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| 364 | #define __arch_decrement_body(lock, pfx, mem) \ |
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| 365 | do { \ |
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| 366 | if (sizeof (*mem) == 1) \ |
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| 367 | __asm __volatile (lock "decb %b0" \ |
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| 368 | : "=m" (*mem) \ |
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| 369 | : "m" (*mem), \ |
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| 370 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 371 | else if (sizeof (*mem) == 2) \ |
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| 372 | __asm __volatile (lock "decw %w0" \ |
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| 373 | : "=m" (*mem) \ |
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| 374 | : "m" (*mem), \ |
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| 375 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 376 | else if (sizeof (*mem) == 4) \ |
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| 377 | __asm __volatile (lock "decl %0" \ |
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| 378 | : "=m" (*mem) \ |
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| 379 | : "m" (*mem), \ |
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| 380 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 381 | else if (__HAVE_64B_ATOMICS) \ |
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| 382 | __asm __volatile (lock "decq %q0" \ |
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| 383 | : "=m" (*mem) \ |
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| 384 | : "m" (*mem), \ |
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| 385 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 386 | else \ |
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| 387 | do_add_val_64_acq (pfx, mem, -1); \ |
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| 388 | } while (0) |
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| 389 | |
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| 390 | #define atomic_decrement(mem) __arch_decrement_body (LOCK_PREFIX, __arch, mem) |
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| 391 | |
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| 392 | #define __arch_decrement_cprefix \ |
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| 393 | "cmpl $0, %%" SEG_REG ":%P2\n\tje 0f\n\tlock\n0:\t" |
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| 394 | |
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| 395 | #define catomic_decrement(mem) \ |
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| 396 | __arch_decrement_body (__arch_decrement_cprefix, __arch_c, mem) |
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| 397 | |
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| 398 | |
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| 399 | #define atomic_decrement_and_test(mem) \ |
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| 400 | ({ unsigned char __result; \ |
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| 401 | if (sizeof (*mem) == 1) \ |
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| 402 | __asm __volatile (LOCK_PREFIX "decb %b0; sete %1" \ |
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| 403 | : "=m" (*mem), "=qm" (__result) \ |
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| 404 | : "m" (*mem)); \ |
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| 405 | else if (sizeof (*mem) == 2) \ |
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| 406 | __asm __volatile (LOCK_PREFIX "decw %w0; sete %1" \ |
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| 407 | : "=m" (*mem), "=qm" (__result) \ |
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| 408 | : "m" (*mem)); \ |
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| 409 | else if (sizeof (*mem) == 4) \ |
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| 410 | __asm __volatile (LOCK_PREFIX "decl %0; sete %1" \ |
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| 411 | : "=m" (*mem), "=qm" (__result) \ |
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| 412 | : "m" (*mem)); \ |
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| 413 | else \ |
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| 414 | __asm __volatile (LOCK_PREFIX "decq %q0; sete %1" \ |
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| 415 | : "=m" (*mem), "=qm" (__result) \ |
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| 416 | : "m" (*mem)); \ |
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| 417 | __result; }) |
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| 418 | |
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| 419 | |
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| 420 | #define atomic_bit_set(mem, bit) \ |
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| 421 | do { \ |
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| 422 | if (sizeof (*mem) == 1) \ |
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| 423 | __asm __volatile (LOCK_PREFIX "orb %b2, %0" \ |
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| 424 | : "=m" (*mem) \ |
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| 425 | : "m" (*mem), IBR_CONSTRAINT (1L << (bit))); \ |
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| 426 | else if (sizeof (*mem) == 2) \ |
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| 427 | __asm __volatile (LOCK_PREFIX "orw %w2, %0" \ |
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| 428 | : "=m" (*mem) \ |
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| 429 | : "m" (*mem), "ir" (1L << (bit))); \ |
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| 430 | else if (sizeof (*mem) == 4) \ |
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| 431 | __asm __volatile (LOCK_PREFIX "orl %2, %0" \ |
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| 432 | : "=m" (*mem) \ |
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| 433 | : "m" (*mem), "ir" (1L << (bit))); \ |
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| 434 | else if (__builtin_constant_p (bit) && (bit) < 32) \ |
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| 435 | __asm __volatile (LOCK_PREFIX "orq %2, %0" \ |
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| 436 | : "=m" (*mem) \ |
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| 437 | : "m" (*mem), "i" (1L << (bit))); \ |
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| 438 | else if (__HAVE_64B_ATOMICS) \ |
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| 439 | __asm __volatile (LOCK_PREFIX "orq %q2, %0" \ |
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| 440 | : "=m" (*mem) \ |
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| 441 | : "m" (*mem), "r" (1UL << (bit))); \ |
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| 442 | else \ |
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| 443 | __atomic_link_error (); \ |
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| 444 | } while (0) |
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| 445 | |
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| 446 | |
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| 447 | #define atomic_bit_test_set(mem, bit) \ |
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| 448 | ({ unsigned char __result; \ |
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| 449 | if (sizeof (*mem) == 1) \ |
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| 450 | __asm __volatile (LOCK_PREFIX "btsb %3, %1; setc %0" \ |
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| 451 | : "=q" (__result), "=m" (*mem) \ |
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| 452 | : "m" (*mem), IBR_CONSTRAINT (bit)); \ |
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| 453 | else if (sizeof (*mem) == 2) \ |
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| 454 | __asm __volatile (LOCK_PREFIX "btsw %3, %1; setc %0" \ |
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| 455 | : "=q" (__result), "=m" (*mem) \ |
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| 456 | : "m" (*mem), "ir" (bit)); \ |
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| 457 | else if (sizeof (*mem) == 4) \ |
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| 458 | __asm __volatile (LOCK_PREFIX "btsl %3, %1; setc %0" \ |
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| 459 | : "=q" (__result), "=m" (*mem) \ |
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| 460 | : "m" (*mem), "ir" (bit)); \ |
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| 461 | else if (__HAVE_64B_ATOMICS) \ |
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| 462 | __asm __volatile (LOCK_PREFIX "btsq %3, %1; setc %0" \ |
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| 463 | : "=q" (__result), "=m" (*mem) \ |
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| 464 | : "m" (*mem), "ir" (bit)); \ |
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| 465 | else \ |
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| 466 | __atomic_link_error (); \ |
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| 467 | __result; }) |
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| 468 | |
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| 469 | |
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| 470 | #define __arch_and_body(lock, mem, mask) \ |
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| 471 | do { \ |
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| 472 | if (sizeof (*mem) == 1) \ |
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| 473 | __asm __volatile (lock "andb %b1, %0" \ |
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| 474 | : "=m" (*mem) \ |
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| 475 | : IBR_CONSTRAINT (mask), "m" (*mem), \ |
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| 476 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 477 | else if (sizeof (*mem) == 2) \ |
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| 478 | __asm __volatile (lock "andw %w1, %0" \ |
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| 479 | : "=m" (*mem) \ |
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| 480 | : "ir" (mask), "m" (*mem), \ |
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| 481 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 482 | else if (sizeof (*mem) == 4) \ |
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| 483 | __asm __volatile (lock "andl %1, %0" \ |
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| 484 | : "=m" (*mem) \ |
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| 485 | : "ir" (mask), "m" (*mem), \ |
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| 486 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 487 | else if (__HAVE_64B_ATOMICS) \ |
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| 488 | __asm __volatile (lock "andq %q1, %0" \ |
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| 489 | : "=m" (*mem) \ |
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| 490 | : "ir" (mask), "m" (*mem), \ |
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| 491 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 492 | else \ |
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| 493 | __atomic_link_error (); \ |
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| 494 | } while (0) |
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| 495 | |
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| 496 | #define __arch_cprefix \ |
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| 497 | "cmpl $0, %%" SEG_REG ":%P3\n\tje 0f\n\tlock\n0:\t" |
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| 498 | |
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| 499 | #define atomic_and(mem, mask) __arch_and_body (LOCK_PREFIX, mem, mask) |
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| 500 | |
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| 501 | #define catomic_and(mem, mask) __arch_and_body (__arch_cprefix, mem, mask) |
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| 502 | |
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| 503 | |
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| 504 | #define __arch_or_body(lock, mem, mask) \ |
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| 505 | do { \ |
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| 506 | if (sizeof (*mem) == 1) \ |
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| 507 | __asm __volatile (lock "orb %b1, %0" \ |
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| 508 | : "=m" (*mem) \ |
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| 509 | : IBR_CONSTRAINT (mask), "m" (*mem), \ |
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| 510 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 511 | else if (sizeof (*mem) == 2) \ |
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| 512 | __asm __volatile (lock "orw %w1, %0" \ |
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| 513 | : "=m" (*mem) \ |
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| 514 | : "ir" (mask), "m" (*mem), \ |
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| 515 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 516 | else if (sizeof (*mem) == 4) \ |
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| 517 | __asm __volatile (lock "orl %1, %0" \ |
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| 518 | : "=m" (*mem) \ |
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| 519 | : "ir" (mask), "m" (*mem), \ |
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| 520 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 521 | else if (__HAVE_64B_ATOMICS) \ |
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| 522 | __asm __volatile (lock "orq %q1, %0" \ |
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| 523 | : "=m" (*mem) \ |
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| 524 | : "ir" (mask), "m" (*mem), \ |
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| 525 | "i" (offsetof (tcbhead_t, multiple_threads))); \ |
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| 526 | else \ |
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| 527 | __atomic_link_error (); \ |
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| 528 | } while (0) |
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| 529 | |
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| 530 | #define atomic_or(mem, mask) __arch_or_body (LOCK_PREFIX, mem, mask) |
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| 531 | |
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| 532 | #define catomic_or(mem, mask) __arch_or_body (__arch_cprefix, mem, mask) |
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| 533 | |
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| 534 | /* We don't use mfence because it is supposedly slower due to having to |
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| 535 | provide stronger guarantees (e.g., regarding self-modifying code). */ |
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| 536 | #define atomic_full_barrier() \ |
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| 537 | __asm __volatile (LOCK_PREFIX "orl $0, (%%" SP_REG ")" ::: "memory") |
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| 538 | #define atomic_read_barrier() __asm ("" ::: "memory") |
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| 539 | #define atomic_write_barrier() __asm ("" ::: "memory") |
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| 540 | |
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| 541 | #define atomic_spin_nop() __asm ("pause") |
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| 542 | |
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| 543 | #endif /* atomic-machine.h */ |
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| 544 | |
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