1 | // SPDX-License-Identifier: GPL-2.0-only |
2 | /* |
3 | * AXS101/AXS103 Software Development Platform |
4 | * |
5 | * Copyright (C) 2013-15 Synopsys, Inc. (www.synopsys.com) |
6 | */ |
7 | |
8 | #include <linux/of_fdt.h> |
9 | #include <linux/libfdt.h> |
10 | |
11 | #include <asm/asm-offsets.h> |
12 | #include <asm/io.h> |
13 | #include <asm/mach_desc.h> |
14 | #include <soc/arc/mcip.h> |
15 | |
16 | #define AXS_MB_CGU 0xE0010000 |
17 | #define AXS_MB_CREG 0xE0011000 |
18 | |
19 | #define CREG_MB_IRQ_MUX (AXS_MB_CREG + 0x214) |
20 | #define CREG_MB_SW_RESET (AXS_MB_CREG + 0x220) |
21 | #define CREG_MB_VER (AXS_MB_CREG + 0x230) |
22 | #define CREG_MB_CONFIG (AXS_MB_CREG + 0x234) |
23 | |
24 | #define AXC001_CREG 0xF0001000 |
25 | #define AXC001_GPIO_INTC 0xF0003000 |
26 | |
27 | static void __init axs10x_enable_gpio_intc_wire(void) |
28 | { |
29 | /* |
30 | * Peripherals on CPU Card and Mother Board are wired to cpu intc via |
31 | * intermediate DW APB GPIO blocks (mainly for debouncing) |
32 | * |
33 | * --------------------- |
34 | * | snps,arc700-intc | |
35 | * --------------------- |
36 | * | #7 | #15 |
37 | * ------------------- ------------------- |
38 | * | snps,dw-apb-gpio | | snps,dw-apb-gpio | |
39 | * ------------------- ------------------- |
40 | * | #12 | |
41 | * | [ Debug UART on cpu card ] |
42 | * | |
43 | * ------------------------ |
44 | * | snps,dw-apb-intc (MB)| |
45 | * ------------------------ |
46 | * | | | | |
47 | * [eth] [uart] [... other perip on Main Board] |
48 | * |
49 | * Current implementation of "irq-dw-apb-ictl" driver doesn't work well |
50 | * with stacked INTCs. In particular problem happens if its master INTC |
51 | * not yet instantiated. See discussion here - |
52 | * https://lore.kernel.org/lkml/54F6FE2C.7020309@synopsys.com |
53 | * |
54 | * So setup the first gpio block as a passive pass thru and hide it from |
55 | * DT hardware topology - connect MB intc directly to cpu intc |
56 | * The GPIO "wire" needs to be init nevertheless (here) |
57 | * |
58 | * One side adv is that peripheral interrupt handling avoids one nested |
59 | * intc ISR hop |
60 | */ |
61 | #define GPIO_INTEN (AXC001_GPIO_INTC + 0x30) |
62 | #define GPIO_INTMASK (AXC001_GPIO_INTC + 0x34) |
63 | #define GPIO_INTTYPE_LEVEL (AXC001_GPIO_INTC + 0x38) |
64 | #define GPIO_INT_POLARITY (AXC001_GPIO_INTC + 0x3c) |
65 | #define MB_TO_GPIO_IRQ 12 |
66 | |
67 | iowrite32(~(1 << MB_TO_GPIO_IRQ), (void __iomem *) GPIO_INTMASK); |
68 | iowrite32(0, (void __iomem *) GPIO_INTTYPE_LEVEL); |
69 | iowrite32(~0, (void __iomem *) GPIO_INT_POLARITY); |
70 | iowrite32(1 << MB_TO_GPIO_IRQ, (void __iomem *) GPIO_INTEN); |
71 | } |
72 | |
73 | static void __init axs10x_print_board_ver(unsigned int creg, const char *str) |
74 | { |
75 | union ver { |
76 | struct { |
77 | #ifdef CONFIG_CPU_BIG_ENDIAN |
78 | unsigned int pad:11, y:12, m:4, d:5; |
79 | #else |
80 | unsigned int d:5, m:4, y:12, pad:11; |
81 | #endif |
82 | }; |
83 | unsigned int val; |
84 | } board; |
85 | |
86 | board.val = ioread32((void __iomem *)creg); |
87 | pr_info("AXS: %s FPGA Date: %u-%u-%u\n" , str, board.d, board.m, |
88 | board.y); |
89 | } |
90 | |
91 | static void __init axs10x_early_init(void) |
92 | { |
93 | int mb_rev; |
94 | char mb[32]; |
95 | |
96 | /* Determine motherboard version */ |
97 | if (ioread32((void __iomem *) CREG_MB_CONFIG) & (1 << 28)) |
98 | mb_rev = 3; /* HT-3 (rev3.0) */ |
99 | else |
100 | mb_rev = 2; /* HT-2 (rev2.0) */ |
101 | |
102 | axs10x_enable_gpio_intc_wire(); |
103 | |
104 | scnprintf(buf: mb, size: 32, fmt: "MainBoard v%d" , mb_rev); |
105 | axs10x_print_board_ver(CREG_MB_VER, str: mb); |
106 | } |
107 | |
108 | #ifdef CONFIG_AXS101 |
109 | |
110 | #define CREG_CPU_ADDR_770 (AXC001_CREG + 0x20) |
111 | #define CREG_CPU_ADDR_TUNN (AXC001_CREG + 0x60) |
112 | #define CREG_CPU_ADDR_770_UPD (AXC001_CREG + 0x34) |
113 | #define CREG_CPU_ADDR_TUNN_UPD (AXC001_CREG + 0x74) |
114 | |
115 | #define CREG_CPU_ARC770_IRQ_MUX (AXC001_CREG + 0x114) |
116 | #define CREG_CPU_GPIO_UART_MUX (AXC001_CREG + 0x120) |
117 | |
118 | /* |
119 | * Set up System Memory Map for ARC cpu / peripherals controllers |
120 | * |
121 | * Each AXI master has a 4GB memory map specified as 16 apertures of 256MB, each |
122 | * of which maps to a corresponding 256MB aperture in Target slave memory map. |
123 | * |
124 | * e.g. ARC cpu AXI Master's aperture 8 (0x8000_0000) is mapped to aperture 0 |
125 | * (0x0000_0000) of DDR Port 0 (slave #1) |
126 | * |
127 | * Access from cpu to MB controllers such as GMAC is setup using AXI Tunnel: |
128 | * which has master/slaves on both ends. |
129 | * e.g. aperture 14 (0xE000_0000) of ARC cpu is mapped to aperture 14 |
130 | * (0xE000_0000) of CPU Card AXI Tunnel slave (slave #3) which is mapped to |
131 | * MB AXI Tunnel Master, which also has a mem map setup |
132 | * |
133 | * In the reverse direction, MB AXI Masters (e.g. GMAC) mem map is setup |
134 | * to map to MB AXI Tunnel slave which connects to CPU Card AXI Tunnel Master |
135 | */ |
136 | struct aperture { |
137 | unsigned int slave_sel:4, slave_off:4, pad:24; |
138 | }; |
139 | |
140 | /* CPU Card target slaves */ |
141 | #define AXC001_SLV_NONE 0 |
142 | #define AXC001_SLV_DDR_PORT0 1 |
143 | #define AXC001_SLV_SRAM 2 |
144 | #define AXC001_SLV_AXI_TUNNEL 3 |
145 | #define AXC001_SLV_AXI2APB 6 |
146 | #define AXC001_SLV_DDR_PORT1 7 |
147 | |
148 | /* MB AXI Target slaves */ |
149 | #define AXS_MB_SLV_NONE 0 |
150 | #define AXS_MB_SLV_AXI_TUNNEL_CPU 1 |
151 | #define AXS_MB_SLV_AXI_TUNNEL_HAPS 2 |
152 | #define AXS_MB_SLV_SRAM 3 |
153 | #define AXS_MB_SLV_CONTROL 4 |
154 | |
155 | /* MB AXI masters */ |
156 | #define AXS_MB_MST_TUNNEL_CPU 0 |
157 | #define AXS_MB_MST_USB_OHCI 10 |
158 | |
159 | /* |
160 | * memmap for ARC core on CPU Card |
161 | */ |
162 | static const struct aperture axc001_memmap[16] = { |
163 | {AXC001_SLV_AXI_TUNNEL, 0x0}, |
164 | {AXC001_SLV_AXI_TUNNEL, 0x1}, |
165 | {AXC001_SLV_SRAM, 0x0}, /* 0x2000_0000: Local SRAM */ |
166 | {AXC001_SLV_NONE, 0x0}, |
167 | {AXC001_SLV_NONE, 0x0}, |
168 | {AXC001_SLV_NONE, 0x0}, |
169 | {AXC001_SLV_NONE, 0x0}, |
170 | {AXC001_SLV_NONE, 0x0}, |
171 | {AXC001_SLV_DDR_PORT0, 0x0}, /* 0x8000_0000: DDR 0..256M */ |
172 | {AXC001_SLV_DDR_PORT0, 0x1}, /* 0x9000_0000: DDR 256..512M */ |
173 | {AXC001_SLV_DDR_PORT0, 0x2}, |
174 | {AXC001_SLV_DDR_PORT0, 0x3}, |
175 | {AXC001_SLV_NONE, 0x0}, |
176 | {AXC001_SLV_AXI_TUNNEL, 0xD}, |
177 | {AXC001_SLV_AXI_TUNNEL, 0xE}, /* MB: CREG, CGU... */ |
178 | {AXC001_SLV_AXI2APB, 0x0}, /* CPU Card local CREG, CGU... */ |
179 | }; |
180 | |
181 | /* |
182 | * memmap for CPU Card AXI Tunnel Master (for access by MB controllers) |
183 | * GMAC (MB) -> MB AXI Tunnel slave -> CPU Card AXI Tunnel Master -> DDR |
184 | */ |
185 | static const struct aperture axc001_axi_tunnel_memmap[16] = { |
186 | {AXC001_SLV_AXI_TUNNEL, 0x0}, |
187 | {AXC001_SLV_AXI_TUNNEL, 0x1}, |
188 | {AXC001_SLV_SRAM, 0x0}, |
189 | {AXC001_SLV_NONE, 0x0}, |
190 | {AXC001_SLV_NONE, 0x0}, |
191 | {AXC001_SLV_NONE, 0x0}, |
192 | {AXC001_SLV_NONE, 0x0}, |
193 | {AXC001_SLV_NONE, 0x0}, |
194 | {AXC001_SLV_DDR_PORT1, 0x0}, |
195 | {AXC001_SLV_DDR_PORT1, 0x1}, |
196 | {AXC001_SLV_DDR_PORT1, 0x2}, |
197 | {AXC001_SLV_DDR_PORT1, 0x3}, |
198 | {AXC001_SLV_NONE, 0x0}, |
199 | {AXC001_SLV_AXI_TUNNEL, 0xD}, |
200 | {AXC001_SLV_AXI_TUNNEL, 0xE}, |
201 | {AXC001_SLV_AXI2APB, 0x0}, |
202 | }; |
203 | |
204 | /* |
205 | * memmap for MB AXI Masters |
206 | * Same mem map for all perip controllers as well as MB AXI Tunnel Master |
207 | */ |
208 | static const struct aperture axs_mb_memmap[16] = { |
209 | {AXS_MB_SLV_SRAM, 0x0}, |
210 | {AXS_MB_SLV_SRAM, 0x0}, |
211 | {AXS_MB_SLV_NONE, 0x0}, |
212 | {AXS_MB_SLV_NONE, 0x0}, |
213 | {AXS_MB_SLV_NONE, 0x0}, |
214 | {AXS_MB_SLV_NONE, 0x0}, |
215 | {AXS_MB_SLV_NONE, 0x0}, |
216 | {AXS_MB_SLV_NONE, 0x0}, |
217 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x8}, /* DDR on CPU Card */ |
218 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0x9}, /* DDR on CPU Card */ |
219 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xA}, |
220 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xB}, |
221 | {AXS_MB_SLV_NONE, 0x0}, |
222 | {AXS_MB_SLV_AXI_TUNNEL_HAPS, 0xD}, |
223 | {AXS_MB_SLV_CONTROL, 0x0}, /* MB Local CREG, CGU... */ |
224 | {AXS_MB_SLV_AXI_TUNNEL_CPU, 0xF}, |
225 | }; |
226 | |
227 | static noinline void __init |
228 | axs101_set_memmap(void __iomem *base, const struct aperture map[16]) |
229 | { |
230 | unsigned int slave_select, slave_offset; |
231 | int i; |
232 | |
233 | slave_select = slave_offset = 0; |
234 | for (i = 0; i < 8; i++) { |
235 | slave_select |= map[i].slave_sel << (i << 2); |
236 | slave_offset |= map[i].slave_off << (i << 2); |
237 | } |
238 | |
239 | iowrite32(slave_select, base + 0x0); /* SLV0 */ |
240 | iowrite32(slave_offset, base + 0x8); /* OFFSET0 */ |
241 | |
242 | slave_select = slave_offset = 0; |
243 | for (i = 0; i < 8; i++) { |
244 | slave_select |= map[i+8].slave_sel << (i << 2); |
245 | slave_offset |= map[i+8].slave_off << (i << 2); |
246 | } |
247 | |
248 | iowrite32(slave_select, base + 0x4); /* SLV1 */ |
249 | iowrite32(slave_offset, base + 0xC); /* OFFSET1 */ |
250 | } |
251 | |
252 | static void __init axs101_early_init(void) |
253 | { |
254 | int i; |
255 | |
256 | /* ARC 770D memory view */ |
257 | axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_770, axc001_memmap); |
258 | iowrite32(1, (void __iomem *) CREG_CPU_ADDR_770_UPD); |
259 | |
260 | /* AXI tunnel memory map (incoming traffic from MB into CPU Card */ |
261 | axs101_set_memmap((void __iomem *) CREG_CPU_ADDR_TUNN, |
262 | axc001_axi_tunnel_memmap); |
263 | iowrite32(1, (void __iomem *) CREG_CPU_ADDR_TUNN_UPD); |
264 | |
265 | /* MB peripherals memory map */ |
266 | for (i = AXS_MB_MST_TUNNEL_CPU; i <= AXS_MB_MST_USB_OHCI; i++) |
267 | axs101_set_memmap((void __iomem *) AXS_MB_CREG + (i << 4), |
268 | axs_mb_memmap); |
269 | |
270 | iowrite32(0x3ff, (void __iomem *) AXS_MB_CREG + 0x100); /* Update */ |
271 | |
272 | /* GPIO pins 18 and 19 are used as UART rx and tx, respectively. */ |
273 | iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); |
274 | |
275 | /* Set up the MB interrupt system: mux interrupts to GPIO7) */ |
276 | iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); |
277 | |
278 | /* reset ethernet and ULPI interfaces */ |
279 | iowrite32(0x18, (void __iomem *) CREG_MB_SW_RESET); |
280 | |
281 | /* map GPIO 14:10 to ARC 9:5 (IRQ mux change for MB v2 onwards) */ |
282 | iowrite32(0x52, (void __iomem *) CREG_CPU_ARC770_IRQ_MUX); |
283 | |
284 | axs10x_early_init(); |
285 | } |
286 | |
287 | #endif /* CONFIG_AXS101 */ |
288 | |
289 | #ifdef CONFIG_AXS103 |
290 | |
291 | #define AXC003_CREG 0xF0001000 |
292 | #define AXC003_MST_AXI_TUNNEL 0 |
293 | #define AXC003_MST_HS38 1 |
294 | |
295 | #define CREG_CPU_AXI_M0_IRQ_MUX (AXC003_CREG + 0x440) |
296 | #define CREG_CPU_GPIO_UART_MUX (AXC003_CREG + 0x480) |
297 | #define CREG_CPU_TUN_IO_CTRL (AXC003_CREG + 0x494) |
298 | |
299 | |
300 | static void __init axs103_early_init(void) |
301 | { |
302 | #ifdef CONFIG_ARC_MCIP |
303 | /* |
304 | * AXS103 configurations for SMP/QUAD configurations share device tree |
305 | * which defaults to 100 MHz. However recent failures of Quad config |
306 | * revealed P&R timing violations so clamp it down to safe 50 MHz |
307 | * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack |
308 | * of fudging the freq in DT |
309 | */ |
310 | #define AXS103_QUAD_CORE_CPU_FREQ_HZ 50000000 |
311 | |
312 | unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; |
313 | if (num_cores > 2) { |
314 | u32 freq; |
315 | int off = fdt_path_offset(initial_boot_params, "/cpu_card/core_clk" ); |
316 | const struct fdt_property *prop; |
317 | |
318 | prop = fdt_get_property(initial_boot_params, off, |
319 | "assigned-clock-rates" , NULL); |
320 | freq = be32_to_cpu(*(u32 *)(prop->data)); |
321 | |
322 | /* Patching .dtb in-place with new core clock value */ |
323 | if (freq != AXS103_QUAD_CORE_CPU_FREQ_HZ) { |
324 | freq = cpu_to_be32(AXS103_QUAD_CORE_CPU_FREQ_HZ); |
325 | fdt_setprop_inplace(initial_boot_params, off, |
326 | "assigned-clock-rates" , &freq, sizeof(freq)); |
327 | } |
328 | } |
329 | #endif |
330 | |
331 | /* Memory maps already config in pre-bootloader */ |
332 | |
333 | /* set GPIO mux to UART */ |
334 | iowrite32(0x01, (void __iomem *) CREG_CPU_GPIO_UART_MUX); |
335 | |
336 | iowrite32((0x00100000U | 0x000C0000U | 0x00003322U), |
337 | (void __iomem *) CREG_CPU_TUN_IO_CTRL); |
338 | |
339 | /* Set up the AXS_MB interrupt system.*/ |
340 | iowrite32(12, (void __iomem *) (CREG_CPU_AXI_M0_IRQ_MUX |
341 | + (AXC003_MST_HS38 << 2))); |
342 | |
343 | /* connect ICTL - Main Board with GPIO line */ |
344 | iowrite32(0x01, (void __iomem *) CREG_MB_IRQ_MUX); |
345 | |
346 | axs10x_print_board_ver(AXC003_CREG + 4088, "AXC003 CPU Card" ); |
347 | |
348 | axs10x_early_init(); |
349 | } |
350 | #endif |
351 | |
352 | #ifdef CONFIG_AXS101 |
353 | |
354 | static const char *axs101_compat[] __initconst = { |
355 | "snps,axs101" , |
356 | NULL, |
357 | }; |
358 | |
359 | MACHINE_START(AXS101, "axs101" ) |
360 | .dt_compat = axs101_compat, |
361 | .init_early = axs101_early_init, |
362 | MACHINE_END |
363 | |
364 | #endif /* CONFIG_AXS101 */ |
365 | |
366 | #ifdef CONFIG_AXS103 |
367 | |
368 | static const char *axs103_compat[] __initconst = { |
369 | "snps,axs103" , |
370 | NULL, |
371 | }; |
372 | |
373 | MACHINE_START(AXS103, "axs103" ) |
374 | .dt_compat = axs103_compat, |
375 | .init_early = axs103_early_init, |
376 | MACHINE_END |
377 | |
378 | /* |
379 | * For the VDK OS-kit, to get the offset to pid and command fields |
380 | */ |
381 | char coware_swa_pid_offset[TASK_PID]; |
382 | char coware_swa_comm_offset[TASK_COMM]; |
383 | |
384 | #endif /* CONFIG_AXS103 */ |
385 | |