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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7#ifndef __ARM64_KVM_HYP_SWITCH_H__
8#define __ARM64_KVM_HYP_SWITCH_H__
9
10#include <hyp/adjust_pc.h>
11#include <hyp/fault.h>
12
13#include <linux/arm-smccc.h>
14#include <linux/kvm_host.h>
15#include <linux/types.h>
16#include <linux/jump_label.h>
17#include <uapi/linux/psci.h>
18
19#include <kvm/arm_psci.h>
20
21#include <asm/barrier.h>
22#include <asm/cpufeature.h>
23#include <asm/extable.h>
24#include <asm/kprobes.h>
25#include <asm/kvm_asm.h>
26#include <asm/kvm_emulate.h>
27#include <asm/kvm_hyp.h>
28#include <asm/kvm_mmu.h>
29#include <asm/kvm_nested.h>
30#include <asm/fpsimd.h>
31#include <asm/debug-monitors.h>
32#include <asm/processor.h>
33#include <asm/traps.h>
34
35struct kvm_exception_table_entry {
36 int insn, fixup;
37};
38
39extern struct kvm_exception_table_entry __start___kvm_ex_table;
40extern struct kvm_exception_table_entry __stop___kvm_ex_table;
41
42/* Save the 32-bit only FPSIMD system register state */
43static inline void __fpsimd_save_fpexc32(struct kvm_vcpu *vcpu)
44{
45 if (!vcpu_el1_is_32bit(vcpu))
46 return;
47
48 __vcpu_assign_sys_reg(vcpu, FPEXC32_EL2, read_sysreg(fpexc32_el2));
49}
50
51static inline void __activate_traps_fpsimd32(struct kvm_vcpu *vcpu)
52{
53 /*
54 * We are about to set CPTR_EL2.TFP to trap all floating point
55 * register accesses to EL2, however, the ARM ARM clearly states that
56 * traps are only taken to EL2 if the operation would not otherwise
57 * trap to EL1. Therefore, always make sure that for 32-bit guests,
58 * we set FPEXC.EN to prevent traps to EL1, when setting the TFP bit.
59 * If FP/ASIMD is not implemented, FPEXC is UNDEFINED and any access to
60 * it will cause an exception.
61 */
62 if (vcpu_el1_is_32bit(vcpu) && system_supports_fpsimd()) {
63 write_sysreg(1 << 30, fpexc32_el2);
64 isb();
65 }
66}
67
68static inline void __activate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
69{
70 u64 val = CPTR_NVHE_EL2_RES1 | CPTR_EL2_TAM | CPTR_EL2_TTA;
71
72 /*
73 * Always trap SME since it's not supported in KVM.
74 * TSM is RES1 if SME isn't implemented.
75 */
76 val |= CPTR_EL2_TSM;
77
78 if (!vcpu_has_sve(vcpu) || !guest_owns_fp_regs())
79 val |= CPTR_EL2_TZ;
80
81 if (!guest_owns_fp_regs())
82 val |= CPTR_EL2_TFP;
83
84 write_sysreg(val, cptr_el2);
85}
86
87static inline void __activate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
88{
89 /*
90 * With VHE (HCR.E2H == 1), accesses to CPACR_EL1 are routed to
91 * CPTR_EL2. In general, CPACR_EL1 has the same layout as CPTR_EL2,
92 * except for some missing controls, such as TAM.
93 * In this case, CPTR_EL2.TAM has the same position with or without
94 * VHE (HCR.E2H == 1) which allows us to use here the CPTR_EL2.TAM
95 * shift value for trapping the AMU accesses.
96 */
97 u64 val = CPTR_EL2_TAM | CPACR_EL1_TTA;
98 u64 cptr;
99
100 if (guest_owns_fp_regs()) {
101 val |= CPACR_EL1_FPEN;
102 if (vcpu_has_sve(vcpu))
103 val |= CPACR_EL1_ZEN;
104 }
105
106 if (!vcpu_has_nv(vcpu))
107 goto write;
108
109 /*
110 * The architecture is a bit crap (what a surprise): an EL2 guest
111 * writing to CPTR_EL2 via CPACR_EL1 can't set any of TCPAC or TTA,
112 * as they are RES0 in the guest's view. To work around it, trap the
113 * sucker using the very same bit it can't set...
114 */
115 if (vcpu_el2_e2h_is_set(vcpu) && is_hyp_ctxt(vcpu))
116 val |= CPTR_EL2_TCPAC;
117
118 /*
119 * Layer the guest hypervisor's trap configuration on top of our own if
120 * we're in a nested context.
121 */
122 if (is_hyp_ctxt(vcpu))
123 goto write;
124
125 cptr = vcpu_sanitised_cptr_el2(vcpu);
126
127 /*
128 * Pay attention, there's some interesting detail here.
129 *
130 * The CPTR_EL2.xEN fields are 2 bits wide, although there are only two
131 * meaningful trap states when HCR_EL2.TGE = 0 (running a nested guest):
132 *
133 * - CPTR_EL2.xEN = x0, traps are enabled
134 * - CPTR_EL2.xEN = x1, traps are disabled
135 *
136 * In other words, bit[0] determines if guest accesses trap or not. In
137 * the interest of simplicity, clear the entire field if the guest
138 * hypervisor has traps enabled to dispel any illusion of something more
139 * complicated taking place.
140 */
141 if (!(SYS_FIELD_GET(CPACR_EL1, FPEN, cptr) & BIT(0)))
142 val &= ~CPACR_EL1_FPEN;
143 if (!(SYS_FIELD_GET(CPACR_EL1, ZEN, cptr) & BIT(0)))
144 val &= ~CPACR_EL1_ZEN;
145
146 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S2POE, IMP))
147 val |= cptr & CPACR_EL1_E0POE;
148
149 val |= cptr & CPTR_EL2_TCPAC;
150
151write:
152 write_sysreg(val, cpacr_el1);
153}
154
155static inline void __activate_cptr_traps(struct kvm_vcpu *vcpu)
156{
157 if (!guest_owns_fp_regs())
158 __activate_traps_fpsimd32(vcpu);
159
160 if (has_vhe() || has_hvhe())
161 __activate_cptr_traps_vhe(vcpu);
162 else
163 __activate_cptr_traps_nvhe(vcpu);
164}
165
166static inline void __deactivate_cptr_traps_nvhe(struct kvm_vcpu *vcpu)
167{
168 u64 val = CPTR_NVHE_EL2_RES1;
169
170 if (!cpus_have_final_cap(ARM64_SVE))
171 val |= CPTR_EL2_TZ;
172 if (!cpus_have_final_cap(ARM64_SME))
173 val |= CPTR_EL2_TSM;
174
175 write_sysreg(val, cptr_el2);
176}
177
178static inline void __deactivate_cptr_traps_vhe(struct kvm_vcpu *vcpu)
179{
180 u64 val = CPACR_EL1_FPEN;
181
182 if (cpus_have_final_cap(ARM64_SVE))
183 val |= CPACR_EL1_ZEN;
184 if (cpus_have_final_cap(ARM64_SME))
185 val |= CPACR_EL1_SMEN;
186
187 write_sysreg(val, cpacr_el1);
188}
189
190static inline void __deactivate_cptr_traps(struct kvm_vcpu *vcpu)
191{
192 if (has_vhe() || has_hvhe())
193 __deactivate_cptr_traps_vhe(vcpu);
194 else
195 __deactivate_cptr_traps_nvhe(vcpu);
196}
197
198static inline bool cpu_has_amu(void)
199{
200 u64 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
201
202 return cpuid_feature_extract_unsigned_field(pfr0,
203 ID_AA64PFR0_EL1_AMU_SHIFT);
204}
205
206#define __activate_fgt(hctxt, vcpu, reg) \
207 do { \
208 ctxt_sys_reg(hctxt, reg) = read_sysreg_s(SYS_ ## reg); \
209 write_sysreg_s(*vcpu_fgt(vcpu, reg), SYS_ ## reg); \
210 } while (0)
211
212static inline void __activate_traps_hfgxtr(struct kvm_vcpu *vcpu)
213{
214 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
215
216 if (!cpus_have_final_cap(ARM64_HAS_FGT))
217 return;
218
219 __activate_fgt(hctxt, vcpu, HFGRTR_EL2);
220 __activate_fgt(hctxt, vcpu, HFGWTR_EL2);
221 __activate_fgt(hctxt, vcpu, HFGITR_EL2);
222 __activate_fgt(hctxt, vcpu, HDFGRTR_EL2);
223 __activate_fgt(hctxt, vcpu, HDFGWTR_EL2);
224
225 if (cpu_has_amu())
226 __activate_fgt(hctxt, vcpu, HAFGRTR_EL2);
227
228 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
229 return;
230
231 __activate_fgt(hctxt, vcpu, HFGRTR2_EL2);
232 __activate_fgt(hctxt, vcpu, HFGWTR2_EL2);
233 __activate_fgt(hctxt, vcpu, HFGITR2_EL2);
234 __activate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
235 __activate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
236}
237
238#define __deactivate_fgt(htcxt, vcpu, reg) \
239 do { \
240 write_sysreg_s(ctxt_sys_reg(hctxt, reg), \
241 SYS_ ## reg); \
242 } while(0)
243
244static inline void __deactivate_traps_hfgxtr(struct kvm_vcpu *vcpu)
245{
246 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
247
248 if (!cpus_have_final_cap(ARM64_HAS_FGT))
249 return;
250
251 __deactivate_fgt(hctxt, vcpu, HFGRTR_EL2);
252 __deactivate_fgt(hctxt, vcpu, HFGWTR_EL2);
253 __deactivate_fgt(hctxt, vcpu, HFGITR_EL2);
254 __deactivate_fgt(hctxt, vcpu, HDFGRTR_EL2);
255 __deactivate_fgt(hctxt, vcpu, HDFGWTR_EL2);
256
257 if (cpu_has_amu())
258 __deactivate_fgt(hctxt, vcpu, HAFGRTR_EL2);
259
260 if (!cpus_have_final_cap(ARM64_HAS_FGT2))
261 return;
262
263 __deactivate_fgt(hctxt, vcpu, HFGRTR2_EL2);
264 __deactivate_fgt(hctxt, vcpu, HFGWTR2_EL2);
265 __deactivate_fgt(hctxt, vcpu, HFGITR2_EL2);
266 __deactivate_fgt(hctxt, vcpu, HDFGRTR2_EL2);
267 __deactivate_fgt(hctxt, vcpu, HDFGWTR2_EL2);
268}
269
270static inline void __activate_traps_mpam(struct kvm_vcpu *vcpu)
271{
272 u64 r = MPAM2_EL2_TRAPMPAM0EL1 | MPAM2_EL2_TRAPMPAM1EL1;
273
274 if (!system_supports_mpam())
275 return;
276
277 /* trap guest access to MPAMIDR_EL1 */
278 if (system_supports_mpam_hcr()) {
279 write_sysreg_s(MPAMHCR_EL2_TRAP_MPAMIDR_EL1, SYS_MPAMHCR_EL2);
280 } else {
281 /* From v1.1 TIDR can trap MPAMIDR, set it unconditionally */
282 r |= MPAM2_EL2_TIDR;
283 }
284
285 write_sysreg_s(r, SYS_MPAM2_EL2);
286}
287
288static inline void __deactivate_traps_mpam(void)
289{
290 if (!system_supports_mpam())
291 return;
292
293 write_sysreg_s(0, SYS_MPAM2_EL2);
294
295 if (system_supports_mpam_hcr())
296 write_sysreg_s(MPAMHCR_HOST_FLAGS, SYS_MPAMHCR_EL2);
297}
298
299static inline void __activate_traps_common(struct kvm_vcpu *vcpu)
300{
301 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
302
303 /* Trap on AArch32 cp15 c15 (impdef sysregs) accesses (EL1 or EL0) */
304 write_sysreg(1 << 15, hstr_el2);
305
306 /*
307 * Make sure we trap PMU access from EL0 to EL2. Also sanitize
308 * PMSELR_EL0 to make sure it never contains the cycle
309 * counter, which could make a PMXEVCNTR_EL0 access UNDEF at
310 * EL1 instead of being trapped to EL2.
311 */
312 if (system_supports_pmuv3()) {
313 write_sysreg(0, pmselr_el0);
314
315 ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0);
316 write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0);
317 vcpu_set_flag(vcpu, PMUSERENR_ON_CPU);
318 }
319
320 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
321 u64 hcrx = vcpu->arch.hcrx_el2;
322 if (is_nested_ctxt(vcpu)) {
323 u64 val = __vcpu_sys_reg(vcpu, HCRX_EL2);
324 hcrx |= val & __HCRX_EL2_MASK;
325 hcrx &= ~(~val & __HCRX_EL2_nMASK);
326 }
327
328 ctxt_sys_reg(hctxt, HCRX_EL2) = read_sysreg_s(SYS_HCRX_EL2);
329 write_sysreg_s(hcrx, SYS_HCRX_EL2);
330 }
331
332 __activate_traps_hfgxtr(vcpu);
333 __activate_traps_mpam(vcpu);
334}
335
336static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu)
337{
338 struct kvm_cpu_context *hctxt = host_data_ptr(host_ctxt);
339
340 write_sysreg(0, hstr_el2);
341 if (system_supports_pmuv3()) {
342 write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0);
343 vcpu_clear_flag(vcpu, PMUSERENR_ON_CPU);
344 }
345
346 if (cpus_have_final_cap(ARM64_HAS_HCX))
347 write_sysreg_s(ctxt_sys_reg(hctxt, HCRX_EL2), SYS_HCRX_EL2);
348
349 __deactivate_traps_hfgxtr(vcpu);
350 __deactivate_traps_mpam();
351}
352
353static inline void ___activate_traps(struct kvm_vcpu *vcpu, u64 hcr)
354{
355 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM))
356 hcr |= HCR_TVM;
357
358 write_sysreg_hcr(hcr);
359
360 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN) && (hcr & HCR_VSE)) {
361 u64 vsesr;
362
363 /*
364 * When HCR_EL2.AMO is set, physical SErrors are taken to EL2
365 * and vSError injection is enabled for EL1. Conveniently, for
366 * NV this means that it is never the case where a 'physical'
367 * SError (injected by KVM or userspace) and vSError are
368 * deliverable to the same context.
369 *
370 * As such, we can trivially select between the host or guest's
371 * VSESR_EL2. Except for the case that FEAT_RAS hasn't been
372 * exposed to the guest, where ESR propagation in hardware
373 * occurs unconditionally.
374 *
375 * Paper over the architectural wart and use an IMPLEMENTATION
376 * DEFINED ESR value in case FEAT_RAS is hidden from the guest.
377 */
378 if (!vserror_state_is_nested(vcpu))
379 vsesr = vcpu->arch.vsesr_el2;
380 else if (kvm_has_ras(kern_hyp_va(vcpu->kvm)))
381 vsesr = __vcpu_sys_reg(vcpu, VSESR_EL2);
382 else
383 vsesr = ESR_ELx_ISV;
384
385 write_sysreg_s(vsesr, SYS_VSESR_EL2);
386 }
387}
388
389static inline void ___deactivate_traps(struct kvm_vcpu *vcpu)
390{
391 u64 *hcr;
392
393 if (vserror_state_is_nested(vcpu))
394 hcr = __ctxt_sys_reg(&vcpu->arch.ctxt, HCR_EL2);
395 else
396 hcr = &vcpu->arch.hcr_el2;
397
398 /*
399 * If we pended a virtual abort, preserve it until it gets
400 * cleared. See D1.14.3 (Virtual Interrupts) for details, but
401 * the crucial bit is "On taking a vSError interrupt,
402 * HCR_EL2.VSE is cleared to 0."
403 *
404 * Additionally, when in a nested context we need to propagate the
405 * updated state to the guest hypervisor's HCR_EL2.
406 */
407 if (*hcr & HCR_VSE) {
408 *hcr &= ~HCR_VSE;
409 *hcr |= read_sysreg(hcr_el2) & HCR_VSE;
410 }
411}
412
413static inline bool __populate_fault_info(struct kvm_vcpu *vcpu)
414{
415 return __get_fault_info(vcpu->arch.fault.esr_el2, &vcpu->arch.fault);
416}
417
418static inline bool kvm_hyp_handle_mops(struct kvm_vcpu *vcpu, u64 *exit_code)
419{
420 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
421 arm64_mops_reset_regs(vcpu_gp_regs(vcpu), vcpu->arch.fault.esr_el2);
422 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
423
424 /*
425 * Finish potential single step before executing the prologue
426 * instruction.
427 */
428 *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
429 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
430
431 return true;
432}
433
434static inline void __hyp_sve_restore_guest(struct kvm_vcpu *vcpu)
435{
436 /*
437 * The vCPU's saved SVE state layout always matches the max VL of the
438 * vCPU. Start off with the max VL so we can load the SVE state.
439 */
440 sve_cond_update_zcr_vq(vcpu_sve_max_vq(vcpu) - 1, SYS_ZCR_EL2);
441 __sve_restore_state(vcpu_sve_pffr(vcpu),
442 &vcpu->arch.ctxt.fp_regs.fpsr,
443 true);
444
445 /*
446 * The effective VL for a VM could differ from the max VL when running a
447 * nested guest, as the guest hypervisor could select a smaller VL. Slap
448 * that into hardware before wrapping up.
449 */
450 if (is_nested_ctxt(vcpu))
451 sve_cond_update_zcr_vq(__vcpu_sys_reg(vcpu, ZCR_EL2), SYS_ZCR_EL2);
452
453 write_sysreg_el1(__vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu)), SYS_ZCR);
454}
455
456static inline void __hyp_sve_save_host(void)
457{
458 struct cpu_sve_state *sve_state = *host_data_ptr(sve_state);
459
460 sve_state->zcr_el1 = read_sysreg_el1(SYS_ZCR);
461 write_sysreg_s(sve_vq_from_vl(kvm_host_sve_max_vl) - 1, SYS_ZCR_EL2);
462 __sve_save_state(sve_state->sve_regs + sve_ffr_offset(kvm_host_sve_max_vl),
463 &sve_state->fpsr,
464 true);
465}
466
467static inline void fpsimd_lazy_switch_to_guest(struct kvm_vcpu *vcpu)
468{
469 u64 zcr_el1, zcr_el2;
470
471 if (!guest_owns_fp_regs())
472 return;
473
474 if (vcpu_has_sve(vcpu)) {
475 /* A guest hypervisor may restrict the effective max VL. */
476 if (is_nested_ctxt(vcpu))
477 zcr_el2 = __vcpu_sys_reg(vcpu, ZCR_EL2);
478 else
479 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
480
481 write_sysreg_el2(zcr_el2, SYS_ZCR);
482
483 zcr_el1 = __vcpu_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu));
484 write_sysreg_el1(zcr_el1, SYS_ZCR);
485 }
486}
487
488static inline void fpsimd_lazy_switch_to_host(struct kvm_vcpu *vcpu)
489{
490 u64 zcr_el1, zcr_el2;
491
492 if (!guest_owns_fp_regs())
493 return;
494
495 /*
496 * When the guest owns the FP regs, we know that guest+hyp traps for
497 * any FPSIMD/SVE/SME features exposed to the guest have been disabled
498 * by either fpsimd_lazy_switch_to_guest() or kvm_hyp_handle_fpsimd()
499 * prior to __guest_entry(). As __guest_entry() guarantees a context
500 * synchronization event, we don't need an ISB here to avoid taking
501 * traps for anything that was exposed to the guest.
502 */
503 if (vcpu_has_sve(vcpu)) {
504 zcr_el1 = read_sysreg_el1(SYS_ZCR);
505 __vcpu_assign_sys_reg(vcpu, vcpu_sve_zcr_elx(vcpu), zcr_el1);
506
507 /*
508 * The guest's state is always saved using the guest's max VL.
509 * Ensure that the host has the guest's max VL active such that
510 * the host can save the guest's state lazily, but don't
511 * artificially restrict the host to the guest's max VL.
512 */
513 if (has_vhe()) {
514 zcr_el2 = vcpu_sve_max_vq(vcpu) - 1;
515 write_sysreg_el2(zcr_el2, SYS_ZCR);
516 } else {
517 zcr_el2 = sve_vq_from_vl(kvm_host_sve_max_vl) - 1;
518 write_sysreg_el2(zcr_el2, SYS_ZCR);
519
520 zcr_el1 = vcpu_sve_max_vq(vcpu) - 1;
521 write_sysreg_el1(zcr_el1, SYS_ZCR);
522 }
523 }
524}
525
526static void kvm_hyp_save_fpsimd_host(struct kvm_vcpu *vcpu)
527{
528 /*
529 * Non-protected kvm relies on the host restoring its sve state.
530 * Protected kvm restores the host's sve state as not to reveal that
531 * fpsimd was used by a guest nor leak upper sve bits.
532 */
533 if (system_supports_sve()) {
534 __hyp_sve_save_host();
535 } else {
536 __fpsimd_save_state(host_data_ptr(host_ctxt.fp_regs));
537 }
538
539 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
540 *host_data_ptr(fpmr) = read_sysreg_s(SYS_FPMR);
541}
542
543
544/*
545 * We trap the first access to the FP/SIMD to save the host context and
546 * restore the guest context lazily.
547 * If FP/SIMD is not implemented, handle the trap and inject an undefined
548 * instruction exception to the guest. Similarly for trapped SVE accesses.
549 */
550static inline bool kvm_hyp_handle_fpsimd(struct kvm_vcpu *vcpu, u64 *exit_code)
551{
552 bool sve_guest;
553 u8 esr_ec;
554
555 if (!system_supports_fpsimd())
556 return false;
557
558 sve_guest = vcpu_has_sve(vcpu);
559 esr_ec = kvm_vcpu_trap_get_class(vcpu);
560
561 /* Only handle traps the vCPU can support here: */
562 switch (esr_ec) {
563 case ESR_ELx_EC_FP_ASIMD:
564 /* Forward traps to the guest hypervisor as required */
565 if (guest_hyp_fpsimd_traps_enabled(vcpu))
566 return false;
567 break;
568 case ESR_ELx_EC_SYS64:
569 if (WARN_ON_ONCE(!is_hyp_ctxt(vcpu)))
570 return false;
571 fallthrough;
572 case ESR_ELx_EC_SVE:
573 if (!sve_guest)
574 return false;
575 if (guest_hyp_sve_traps_enabled(vcpu))
576 return false;
577 break;
578 default:
579 return false;
580 }
581
582 /* Valid trap. Switch the context: */
583
584 /* First disable enough traps to allow us to update the registers */
585 __deactivate_cptr_traps(vcpu);
586 isb();
587
588 /* Write out the host state if it's in the registers */
589 if (is_protected_kvm_enabled() && host_owns_fp_regs())
590 kvm_hyp_save_fpsimd_host(vcpu);
591
592 /* Restore the guest state */
593 if (sve_guest)
594 __hyp_sve_restore_guest(vcpu);
595 else
596 __fpsimd_restore_state(&vcpu->arch.ctxt.fp_regs);
597
598 if (kvm_has_fpmr(kern_hyp_va(vcpu->kvm)))
599 write_sysreg_s(__vcpu_sys_reg(vcpu, FPMR), SYS_FPMR);
600
601 /* Skip restoring fpexc32 for AArch64 guests */
602 if (!(read_sysreg(hcr_el2) & HCR_RW))
603 write_sysreg(__vcpu_sys_reg(vcpu, FPEXC32_EL2), fpexc32_el2);
604
605 *host_data_ptr(fp_owner) = FP_STATE_GUEST_OWNED;
606
607 /*
608 * Re-enable traps necessary for the current state of the guest, e.g.
609 * those enabled by a guest hypervisor. The ERET to the guest will
610 * provide the necessary context synchronization.
611 */
612 __activate_cptr_traps(vcpu);
613
614 return true;
615}
616
617static inline bool handle_tx2_tvm(struct kvm_vcpu *vcpu)
618{
619 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
620 int rt = kvm_vcpu_sys_get_rt(vcpu);
621 u64 val = vcpu_get_reg(vcpu, rt);
622
623 /*
624 * The normal sysreg handling code expects to see the traps,
625 * let's not do anything here.
626 */
627 if (vcpu->arch.hcr_el2 & HCR_TVM)
628 return false;
629
630 switch (sysreg) {
631 case SYS_SCTLR_EL1:
632 write_sysreg_el1(val, SYS_SCTLR);
633 break;
634 case SYS_TTBR0_EL1:
635 write_sysreg_el1(val, SYS_TTBR0);
636 break;
637 case SYS_TTBR1_EL1:
638 write_sysreg_el1(val, SYS_TTBR1);
639 break;
640 case SYS_TCR_EL1:
641 write_sysreg_el1(val, SYS_TCR);
642 break;
643 case SYS_ESR_EL1:
644 write_sysreg_el1(val, SYS_ESR);
645 break;
646 case SYS_FAR_EL1:
647 write_sysreg_el1(val, SYS_FAR);
648 break;
649 case SYS_AFSR0_EL1:
650 write_sysreg_el1(val, SYS_AFSR0);
651 break;
652 case SYS_AFSR1_EL1:
653 write_sysreg_el1(val, SYS_AFSR1);
654 break;
655 case SYS_MAIR_EL1:
656 write_sysreg_el1(val, SYS_MAIR);
657 break;
658 case SYS_AMAIR_EL1:
659 write_sysreg_el1(val, SYS_AMAIR);
660 break;
661 case SYS_CONTEXTIDR_EL1:
662 write_sysreg_el1(val, SYS_CONTEXTIDR);
663 break;
664 default:
665 return false;
666 }
667
668 __kvm_skip_instr(vcpu);
669 return true;
670}
671
672/* Open-coded version of timer_get_offset() to allow for kern_hyp_va() */
673static inline u64 hyp_timer_get_offset(struct arch_timer_context *ctxt)
674{
675 u64 offset = 0;
676
677 if (ctxt->offset.vm_offset)
678 offset += *kern_hyp_va(ctxt->offset.vm_offset);
679 if (ctxt->offset.vcpu_offset)
680 offset += *kern_hyp_va(ctxt->offset.vcpu_offset);
681
682 return offset;
683}
684
685static inline u64 compute_counter_value(struct arch_timer_context *ctxt)
686{
687 return arch_timer_read_cntpct_el0() - hyp_timer_get_offset(ctxt);
688}
689
690static bool kvm_handle_cntxct(struct kvm_vcpu *vcpu)
691{
692 struct arch_timer_context *ctxt;
693 u32 sysreg;
694 u64 val;
695
696 /*
697 * We only get here for 64bit guests, 32bit guests will hit
698 * the long and winding road all the way to the standard
699 * handling. Yes, it sucks to be irrelevant.
700 *
701 * Also, we only deal with non-hypervisor context here (either
702 * an EL1 guest, or a non-HYP context of an EL2 guest).
703 */
704 if (is_hyp_ctxt(vcpu))
705 return false;
706
707 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
708
709 switch (sysreg) {
710 case SYS_CNTPCT_EL0:
711 case SYS_CNTPCTSS_EL0:
712 if (vcpu_has_nv(vcpu)) {
713 /* Check for guest hypervisor trapping */
714 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
715 if (!vcpu_el2_e2h_is_set(vcpu))
716 val = (val & CNTHCTL_EL1PCTEN) << 10;
717
718 if (!(val & (CNTHCTL_EL1PCTEN << 10)))
719 return false;
720 }
721
722 ctxt = vcpu_ptimer(vcpu);
723 break;
724 case SYS_CNTVCT_EL0:
725 case SYS_CNTVCTSS_EL0:
726 if (vcpu_has_nv(vcpu)) {
727 /* Check for guest hypervisor trapping */
728 val = __vcpu_sys_reg(vcpu, CNTHCTL_EL2);
729
730 if (val & CNTHCTL_EL1TVCT)
731 return false;
732 }
733
734 ctxt = vcpu_vtimer(vcpu);
735 break;
736 default:
737 return false;
738 }
739
740 val = compute_counter_value(ctxt);
741
742 vcpu_set_reg(vcpu, kvm_vcpu_sys_get_rt(vcpu), val);
743 __kvm_skip_instr(vcpu);
744 return true;
745}
746
747static bool handle_ampere1_tcr(struct kvm_vcpu *vcpu)
748{
749 u32 sysreg = esr_sys64_to_sysreg(kvm_vcpu_get_esr(vcpu));
750 int rt = kvm_vcpu_sys_get_rt(vcpu);
751 u64 val = vcpu_get_reg(vcpu, rt);
752
753 if (sysreg != SYS_TCR_EL1)
754 return false;
755
756 /*
757 * Affected parts do not advertise support for hardware Access Flag /
758 * Dirty state management in ID_AA64MMFR1_EL1.HAFDBS, but the underlying
759 * control bits are still functional. The architecture requires these be
760 * RES0 on systems that do not implement FEAT_HAFDBS.
761 *
762 * Uphold the requirements of the architecture by masking guest writes
763 * to TCR_EL1.{HA,HD} here.
764 */
765 val &= ~(TCR_HD | TCR_HA);
766 write_sysreg_el1(val, SYS_TCR);
767 __kvm_skip_instr(vcpu);
768 return true;
769}
770
771static inline bool kvm_hyp_handle_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
772{
773 if (cpus_have_final_cap(ARM64_WORKAROUND_CAVIUM_TX2_219_TVM) &&
774 handle_tx2_tvm(vcpu))
775 return true;
776
777 if (cpus_have_final_cap(ARM64_WORKAROUND_AMPERE_AC03_CPU_38) &&
778 handle_ampere1_tcr(vcpu))
779 return true;
780
781 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
782 __vgic_v3_perform_cpuif_access(vcpu) == 1)
783 return true;
784
785 if (kvm_handle_cntxct(vcpu))
786 return true;
787
788 return false;
789}
790
791static inline bool kvm_hyp_handle_cp15_32(struct kvm_vcpu *vcpu, u64 *exit_code)
792{
793 if (static_branch_unlikely(&vgic_v3_cpuif_trap) &&
794 __vgic_v3_perform_cpuif_access(vcpu) == 1)
795 return true;
796
797 return false;
798}
799
800static inline bool kvm_hyp_handle_memory_fault(struct kvm_vcpu *vcpu,
801 u64 *exit_code)
802{
803 if (!__populate_fault_info(vcpu))
804 return true;
805
806 return false;
807}
808#define kvm_hyp_handle_iabt_low kvm_hyp_handle_memory_fault
809#define kvm_hyp_handle_watchpt_low kvm_hyp_handle_memory_fault
810
811static inline bool kvm_hyp_handle_dabt_low(struct kvm_vcpu *vcpu, u64 *exit_code)
812{
813 if (kvm_hyp_handle_memory_fault(vcpu, exit_code))
814 return true;
815
816 if (static_branch_unlikely(&vgic_v2_cpuif_trap)) {
817 bool valid;
818
819 valid = kvm_vcpu_trap_is_translation_fault(vcpu) &&
820 kvm_vcpu_dabt_isvalid(vcpu) &&
821 !kvm_vcpu_abt_issea(vcpu) &&
822 !kvm_vcpu_abt_iss1tw(vcpu);
823
824 if (valid) {
825 int ret = __vgic_v2_perform_cpuif_access(vcpu);
826
827 if (ret == 1)
828 return true;
829
830 /* Promote an illegal access to an SError.*/
831 if (ret == -1)
832 *exit_code = ARM_EXCEPTION_EL1_SERROR;
833 }
834 }
835
836 return false;
837}
838
839typedef bool (*exit_handler_fn)(struct kvm_vcpu *, u64 *);
840
841/*
842 * Allow the hypervisor to handle the exit with an exit handler if it has one.
843 *
844 * Returns true if the hypervisor handled the exit, and control should go back
845 * to the guest, or false if it hasn't.
846 */
847static inline bool kvm_hyp_handle_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
848 const exit_handler_fn *handlers)
849{
850 exit_handler_fn fn = handlers[kvm_vcpu_trap_get_class(vcpu)];
851 if (fn)
852 return fn(vcpu, exit_code);
853
854 return false;
855}
856
857static inline void synchronize_vcpu_pstate(struct kvm_vcpu *vcpu)
858{
859 /*
860 * Check for the conditions of Cortex-A510's #2077057. When these occur
861 * SPSR_EL2 can't be trusted, but isn't needed either as it is
862 * unchanged from the value in vcpu_gp_regs(vcpu)->pstate.
863 * Are we single-stepping the guest, and took a PAC exception from the
864 * active-not-pending state?
865 */
866 if (cpus_have_final_cap(ARM64_WORKAROUND_2077057) &&
867 vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
868 *vcpu_cpsr(vcpu) & DBG_SPSR_SS &&
869 ESR_ELx_EC(read_sysreg_el2(SYS_ESR)) == ESR_ELx_EC_PAC)
870 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
871
872 vcpu->arch.ctxt.regs.pstate = read_sysreg_el2(SYS_SPSR);
873}
874
875/*
876 * Return true when we were able to fixup the guest exit and should return to
877 * the guest, false when we should restore the host state and return to the
878 * main run loop.
879 */
880static inline bool __fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code,
881 const exit_handler_fn *handlers)
882{
883 if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ)
884 vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR);
885
886 if (ARM_SERROR_PENDING(*exit_code) &&
887 ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) {
888 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
889
890 /*
891 * HVC already have an adjusted PC, which we need to
892 * correct in order to return to after having injected
893 * the SError.
894 *
895 * SMC, on the other hand, is *trapped*, meaning its
896 * preferred return address is the SMC itself.
897 */
898 if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64)
899 write_sysreg_el2(read_sysreg_el2(SYS_ELR) - 4, SYS_ELR);
900 }
901
902 /*
903 * We're using the raw exception code in order to only process
904 * the trap if no SError is pending. We will come back to the
905 * same PC once the SError has been injected, and replay the
906 * trapping instruction.
907 */
908 if (*exit_code != ARM_EXCEPTION_TRAP)
909 goto exit;
910
911 /* Check if there's an exit handler and allow it to handle the exit. */
912 if (kvm_hyp_handle_exit(vcpu, exit_code, handlers))
913 goto guest;
914exit:
915 /* Return to the host kernel and handle the exit */
916 return false;
917
918guest:
919 /* Re-enter the guest */
920 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412));
921 return true;
922}
923
924static inline void __kvm_unexpected_el2_exception(void)
925{
926 extern char __guest_exit_restore_elr_and_panic[];
927 unsigned long addr, fixup;
928 struct kvm_exception_table_entry *entry, *end;
929 unsigned long elr_el2 = read_sysreg(elr_el2);
930
931 entry = &__start___kvm_ex_table;
932 end = &__stop___kvm_ex_table;
933
934 while (entry < end) {
935 addr = (unsigned long)&entry->insn + entry->insn;
936 fixup = (unsigned long)&entry->fixup + entry->fixup;
937
938 if (addr != elr_el2) {
939 entry++;
940 continue;
941 }
942
943 write_sysreg(fixup, elr_el2);
944 return;
945 }
946
947 /* Trigger a panic after restoring the hyp context. */
948 this_cpu_ptr(&kvm_hyp_ctxt)->sys_regs[ELR_EL2] = elr_el2;
949 write_sysreg(__guest_exit_restore_elr_and_panic, elr_el2);
950}
951
952#endif /* __ARM64_KVM_HYP_SWITCH_H__ */
953

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/arch/arm64/kvm/hyp/include/hyp/switch.h