1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2021 Google LLC
4 * Author: Fuad Tabba <tabba@google.com>
5 */
6
7#include <linux/irqchip/arm-gic-v3.h>
8
9#include <asm/kvm_asm.h>
10#include <asm/kvm_mmu.h>
11
12#include <hyp/adjust_pc.h>
13
14#include <nvhe/pkvm.h>
15
16#include "../../sys_regs.h"
17
18/*
19 * Copies of the host's CPU features registers holding sanitized values at hyp.
20 */
21u64 id_aa64pfr0_el1_sys_val;
22u64 id_aa64pfr1_el1_sys_val;
23u64 id_aa64isar0_el1_sys_val;
24u64 id_aa64isar1_el1_sys_val;
25u64 id_aa64isar2_el1_sys_val;
26u64 id_aa64mmfr0_el1_sys_val;
27u64 id_aa64mmfr1_el1_sys_val;
28u64 id_aa64mmfr2_el1_sys_val;
29u64 id_aa64smfr0_el1_sys_val;
30
31struct pvm_ftr_bits {
32 bool sign;
33 u8 shift;
34 u8 width;
35 u8 max_val;
36 bool (*vm_supported)(const struct kvm *kvm);
37};
38
39#define __MAX_FEAT_FUNC(id, fld, max, func, sgn) \
40 { \
41 .sign = sgn, \
42 .shift = id##_##fld##_SHIFT, \
43 .width = id##_##fld##_WIDTH, \
44 .max_val = id##_##fld##_##max, \
45 .vm_supported = func, \
46 }
47
48#define MAX_FEAT_FUNC(id, fld, max, func) \
49 __MAX_FEAT_FUNC(id, fld, max, func, id##_##fld##_SIGNED)
50
51#define MAX_FEAT(id, fld, max) \
52 MAX_FEAT_FUNC(id, fld, max, NULL)
53
54#define MAX_FEAT_ENUM(id, fld, max) \
55 __MAX_FEAT_FUNC(id, fld, max, NULL, false)
56
57#define FEAT_END { .width = 0, }
58
59static bool vm_has_ptrauth(const struct kvm *kvm)
60{
61 if (!IS_ENABLED(CONFIG_ARM64_PTR_AUTH))
62 return false;
63
64 return (cpus_have_final_cap(ARM64_HAS_ADDRESS_AUTH) ||
65 cpus_have_final_cap(ARM64_HAS_GENERIC_AUTH)) &&
66 kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_PTRAUTH_GENERIC);
67}
68
69static bool vm_has_sve(const struct kvm *kvm)
70{
71 return system_supports_sve() && kvm_vcpu_has_feature(kvm, KVM_ARM_VCPU_SVE);
72}
73
74/*
75 * Definitions for features to be allowed or restricted for protected guests.
76 *
77 * Each field in the masks represents the highest supported value for the
78 * feature. If a feature field is not present, it is not supported. Moreover,
79 * these are used to generate the guest's view of the feature registers.
80 *
81 * The approach for protected VMs is to at least support features that are:
82 * - Needed by common Linux distributions (e.g., floating point)
83 * - Trivial to support, e.g., supporting the feature does not introduce or
84 * require tracking of additional state in KVM
85 * - Cannot be trapped or prevent the guest from using anyway
86 */
87
88static const struct pvm_ftr_bits pvmid_aa64pfr0[] = {
89 MAX_FEAT(ID_AA64PFR0_EL1, EL0, IMP),
90 MAX_FEAT(ID_AA64PFR0_EL1, EL1, IMP),
91 MAX_FEAT(ID_AA64PFR0_EL1, EL2, IMP),
92 MAX_FEAT(ID_AA64PFR0_EL1, EL3, IMP),
93 MAX_FEAT(ID_AA64PFR0_EL1, FP, FP16),
94 MAX_FEAT(ID_AA64PFR0_EL1, AdvSIMD, FP16),
95 MAX_FEAT(ID_AA64PFR0_EL1, GIC, IMP),
96 MAX_FEAT_FUNC(ID_AA64PFR0_EL1, SVE, IMP, vm_has_sve),
97 MAX_FEAT(ID_AA64PFR0_EL1, RAS, IMP),
98 MAX_FEAT(ID_AA64PFR0_EL1, DIT, IMP),
99 MAX_FEAT(ID_AA64PFR0_EL1, CSV2, IMP),
100 MAX_FEAT(ID_AA64PFR0_EL1, CSV3, IMP),
101 FEAT_END
102};
103
104static const struct pvm_ftr_bits pvmid_aa64pfr1[] = {
105 MAX_FEAT(ID_AA64PFR1_EL1, BT, IMP),
106 MAX_FEAT(ID_AA64PFR1_EL1, SSBS, SSBS2),
107 MAX_FEAT_ENUM(ID_AA64PFR1_EL1, MTE_frac, NI),
108 FEAT_END
109};
110
111static const struct pvm_ftr_bits pvmid_aa64mmfr0[] = {
112 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, PARANGE, 40),
113 MAX_FEAT_ENUM(ID_AA64MMFR0_EL1, ASIDBITS, 16),
114 MAX_FEAT(ID_AA64MMFR0_EL1, BIGEND, IMP),
115 MAX_FEAT(ID_AA64MMFR0_EL1, SNSMEM, IMP),
116 MAX_FEAT(ID_AA64MMFR0_EL1, BIGENDEL0, IMP),
117 MAX_FEAT(ID_AA64MMFR0_EL1, EXS, IMP),
118 FEAT_END
119};
120
121static const struct pvm_ftr_bits pvmid_aa64mmfr1[] = {
122 MAX_FEAT(ID_AA64MMFR1_EL1, HAFDBS, DBM),
123 MAX_FEAT_ENUM(ID_AA64MMFR1_EL1, VMIDBits, 16),
124 MAX_FEAT(ID_AA64MMFR1_EL1, HPDS, HPDS2),
125 MAX_FEAT(ID_AA64MMFR1_EL1, PAN, PAN3),
126 MAX_FEAT(ID_AA64MMFR1_EL1, SpecSEI, IMP),
127 MAX_FEAT(ID_AA64MMFR1_EL1, ETS, IMP),
128 MAX_FEAT(ID_AA64MMFR1_EL1, CMOW, IMP),
129 FEAT_END
130};
131
132static const struct pvm_ftr_bits pvmid_aa64mmfr2[] = {
133 MAX_FEAT(ID_AA64MMFR2_EL1, CnP, IMP),
134 MAX_FEAT(ID_AA64MMFR2_EL1, UAO, IMP),
135 MAX_FEAT(ID_AA64MMFR2_EL1, IESB, IMP),
136 MAX_FEAT(ID_AA64MMFR2_EL1, AT, IMP),
137 MAX_FEAT_ENUM(ID_AA64MMFR2_EL1, IDS, 0x18),
138 MAX_FEAT(ID_AA64MMFR2_EL1, TTL, IMP),
139 MAX_FEAT(ID_AA64MMFR2_EL1, BBM, 2),
140 MAX_FEAT(ID_AA64MMFR2_EL1, E0PD, IMP),
141 FEAT_END
142};
143
144static const struct pvm_ftr_bits pvmid_aa64isar1[] = {
145 MAX_FEAT(ID_AA64ISAR1_EL1, DPB, DPB2),
146 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, APA, PAuth, vm_has_ptrauth),
147 MAX_FEAT_FUNC(ID_AA64ISAR1_EL1, API, PAuth, vm_has_ptrauth),
148 MAX_FEAT(ID_AA64ISAR1_EL1, JSCVT, IMP),
149 MAX_FEAT(ID_AA64ISAR1_EL1, FCMA, IMP),
150 MAX_FEAT(ID_AA64ISAR1_EL1, LRCPC, LRCPC3),
151 MAX_FEAT(ID_AA64ISAR1_EL1, GPA, IMP),
152 MAX_FEAT(ID_AA64ISAR1_EL1, GPI, IMP),
153 MAX_FEAT(ID_AA64ISAR1_EL1, FRINTTS, IMP),
154 MAX_FEAT(ID_AA64ISAR1_EL1, SB, IMP),
155 MAX_FEAT(ID_AA64ISAR1_EL1, SPECRES, COSP_RCTX),
156 MAX_FEAT(ID_AA64ISAR1_EL1, BF16, EBF16),
157 MAX_FEAT(ID_AA64ISAR1_EL1, DGH, IMP),
158 MAX_FEAT(ID_AA64ISAR1_EL1, I8MM, IMP),
159 FEAT_END
160};
161
162static const struct pvm_ftr_bits pvmid_aa64isar2[] = {
163 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, GPA3, IMP, vm_has_ptrauth),
164 MAX_FEAT_FUNC(ID_AA64ISAR2_EL1, APA3, PAuth, vm_has_ptrauth),
165 MAX_FEAT(ID_AA64ISAR2_EL1, ATS1A, IMP),
166 FEAT_END
167};
168
169/*
170 * None of the features in ID_AA64DFR0_EL1 nor ID_AA64MMFR4_EL1 are supported.
171 * However, both have Not-Implemented values that are non-zero. Define them
172 * so they can be used when getting the value of these registers.
173 */
174#define ID_AA64DFR0_EL1_NONZERO_NI \
175( \
176 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DoubleLock, NI) | \
177 SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, MTPMU, NI) \
178)
179
180#define ID_AA64MMFR4_EL1_NONZERO_NI \
181 SYS_FIELD_PREP_ENUM(ID_AA64MMFR4_EL1, E2H0, NI)
182
183/*
184 * Returns the value of the feature registers based on the system register
185 * value, the vcpu support for the revelant features, and the additional
186 * restrictions for protected VMs.
187 */
188static u64 get_restricted_features(const struct kvm_vcpu *vcpu,
189 u64 sys_reg_val,
190 const struct pvm_ftr_bits restrictions[])
191{
192 u64 val = 0UL;
193 int i;
194
195 for (i = 0; restrictions[i].width != 0; i++) {
196 bool (*vm_supported)(const struct kvm *) = restrictions[i].vm_supported;
197 bool sign = restrictions[i].sign;
198 int shift = restrictions[i].shift;
199 int width = restrictions[i].width;
200 u64 min_signed = (1UL << width) - 1UL;
201 u64 sign_bit = 1UL << (width - 1);
202 u64 mask = GENMASK_ULL(width + shift - 1, shift);
203 u64 sys_val = (sys_reg_val & mask) >> shift;
204 u64 pvm_max = restrictions[i].max_val;
205
206 if (vm_supported && !vm_supported(vcpu->kvm))
207 val |= (sign ? min_signed : 0) << shift;
208 else if (sign && (sys_val >= sign_bit || pvm_max >= sign_bit))
209 val |= max(sys_val, pvm_max) << shift;
210 else
211 val |= min(sys_val, pvm_max) << shift;
212 }
213
214 return val;
215}
216
217static u64 pvm_calc_id_reg(const struct kvm_vcpu *vcpu, u32 id)
218{
219 switch (id) {
220 case SYS_ID_AA64PFR0_EL1:
221 return get_restricted_features(vcpu, sys_reg_val: id_aa64pfr0_el1_sys_val, restrictions: pvmid_aa64pfr0);
222 case SYS_ID_AA64PFR1_EL1:
223 return get_restricted_features(vcpu, sys_reg_val: id_aa64pfr1_el1_sys_val, restrictions: pvmid_aa64pfr1);
224 case SYS_ID_AA64ISAR0_EL1:
225 return id_aa64isar0_el1_sys_val;
226 case SYS_ID_AA64ISAR1_EL1:
227 return get_restricted_features(vcpu, sys_reg_val: id_aa64isar1_el1_sys_val, restrictions: pvmid_aa64isar1);
228 case SYS_ID_AA64ISAR2_EL1:
229 return get_restricted_features(vcpu, sys_reg_val: id_aa64isar2_el1_sys_val, restrictions: pvmid_aa64isar2);
230 case SYS_ID_AA64MMFR0_EL1:
231 return get_restricted_features(vcpu, sys_reg_val: id_aa64mmfr0_el1_sys_val, restrictions: pvmid_aa64mmfr0);
232 case SYS_ID_AA64MMFR1_EL1:
233 return get_restricted_features(vcpu, sys_reg_val: id_aa64mmfr1_el1_sys_val, restrictions: pvmid_aa64mmfr1);
234 case SYS_ID_AA64MMFR2_EL1:
235 return get_restricted_features(vcpu, sys_reg_val: id_aa64mmfr2_el1_sys_val, restrictions: pvmid_aa64mmfr2);
236 case SYS_ID_AA64DFR0_EL1:
237 return ID_AA64DFR0_EL1_NONZERO_NI;
238 case SYS_ID_AA64MMFR4_EL1:
239 return ID_AA64MMFR4_EL1_NONZERO_NI;
240 default:
241 /* Unhandled ID register, RAZ */
242 return 0;
243 }
244}
245
246/*
247 * Inject an unknown/undefined exception to an AArch64 guest while most of its
248 * sysregs are live.
249 */
250static void inject_undef64(struct kvm_vcpu *vcpu)
251{
252 u64 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
253
254 *vcpu_pc(vcpu) = read_sysreg_el2(SYS_ELR);
255 *vcpu_cpsr(vcpu) = read_sysreg_el2(SYS_SPSR);
256 __vcpu_assign_sys_reg(vcpu, VBAR_EL1, read_sysreg_el1(SYS_VBAR));
257
258 kvm_pend_exception(vcpu, EXCEPT_AA64_EL1_SYNC);
259
260 __kvm_adjust_pc(vcpu);
261
262 write_sysreg_el1(esr, SYS_ESR);
263 write_sysreg_el1(read_sysreg_el2(SYS_ELR), SYS_ELR);
264 write_sysreg_el2(*vcpu_pc(vcpu), SYS_ELR);
265 write_sysreg_el2(*vcpu_cpsr(vcpu), SYS_SPSR);
266}
267
268static u64 read_id_reg(const struct kvm_vcpu *vcpu,
269 struct sys_reg_desc const *r)
270{
271 struct kvm *kvm = vcpu->kvm;
272 u32 reg = reg_to_encoding(r);
273
274 if (WARN_ON_ONCE(!test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags)))
275 return 0;
276
277 if (reg >= sys_reg(3, 0, 0, 1, 0) && reg <= sys_reg(3, 0, 0, 7, 7))
278 return kvm->arch.id_regs[IDREG_IDX(reg)];
279
280 return 0;
281}
282
283/* Handler to RAZ/WI sysregs */
284static bool pvm_access_raz_wi(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
285 const struct sys_reg_desc *r)
286{
287 if (!p->is_write)
288 p->regval = 0;
289
290 return true;
291}
292
293/*
294 * Accessor for AArch32 feature id registers.
295 *
296 * The value of these registers is "unknown" according to the spec if AArch32
297 * isn't supported.
298 */
299static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *r)
302{
303 if (p->is_write) {
304 inject_undef64(vcpu);
305 return false;
306 }
307
308 return pvm_access_raz_wi(vcpu, p, r);
309}
310
311/*
312 * Accessor for AArch64 feature id registers.
313 *
314 * If access is allowed, set the regval to the protected VM's view of the
315 * register and return true.
316 * Otherwise, inject an undefined exception and return false.
317 */
318static bool pvm_access_id_aarch64(struct kvm_vcpu *vcpu,
319 struct sys_reg_params *p,
320 const struct sys_reg_desc *r)
321{
322 if (p->is_write) {
323 inject_undef64(vcpu);
324 return false;
325 }
326
327 p->regval = read_id_reg(vcpu, r);
328 return true;
329}
330
331static bool pvm_gic_read_sre(struct kvm_vcpu *vcpu,
332 struct sys_reg_params *p,
333 const struct sys_reg_desc *r)
334{
335 /* pVMs only support GICv3. 'nuf said. */
336 if (!p->is_write)
337 p->regval = ICC_SRE_EL1_DIB | ICC_SRE_EL1_DFB | ICC_SRE_EL1_SRE;
338
339 return true;
340}
341
342/* Mark the specified system register as an AArch32 feature id register. */
343#define AARCH32(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch32 }
344
345/* Mark the specified system register as an AArch64 feature id register. */
346#define AARCH64(REG) { SYS_DESC(REG), .access = pvm_access_id_aarch64 }
347
348/*
349 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
350 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
351 * (1 <= crm < 8, 0 <= Op2 < 8).
352 */
353#define ID_UNALLOCATED(crm, op2) { \
354 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
355 .access = pvm_access_id_aarch64, \
356}
357
358/* Mark the specified system register as Read-As-Zero/Write-Ignored */
359#define RAZ_WI(REG) { SYS_DESC(REG), .access = pvm_access_raz_wi }
360
361/* Mark the specified system register as not being handled in hyp. */
362#define HOST_HANDLED(REG) { SYS_DESC(REG), .access = NULL }
363
364/*
365 * Architected system registers.
366 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
367 *
368 * NOTE: Anything not explicitly listed here is *restricted by default*, i.e.,
369 * it will lead to injecting an exception into the guest.
370 */
371static const struct sys_reg_desc pvm_sys_reg_descs[] = {
372 /* Cache maintenance by set/way operations are restricted. */
373
374 /* Debug and Trace Registers are restricted. */
375
376 /* Group 1 ID registers */
377 HOST_HANDLED(SYS_REVIDR_EL1),
378
379 /* AArch64 mappings of the AArch32 ID registers */
380 /* CRm=1 */
381 AARCH32(SYS_ID_PFR0_EL1),
382 AARCH32(SYS_ID_PFR1_EL1),
383 AARCH32(SYS_ID_DFR0_EL1),
384 AARCH32(SYS_ID_AFR0_EL1),
385 AARCH32(SYS_ID_MMFR0_EL1),
386 AARCH32(SYS_ID_MMFR1_EL1),
387 AARCH32(SYS_ID_MMFR2_EL1),
388 AARCH32(SYS_ID_MMFR3_EL1),
389
390 /* CRm=2 */
391 AARCH32(SYS_ID_ISAR0_EL1),
392 AARCH32(SYS_ID_ISAR1_EL1),
393 AARCH32(SYS_ID_ISAR2_EL1),
394 AARCH32(SYS_ID_ISAR3_EL1),
395 AARCH32(SYS_ID_ISAR4_EL1),
396 AARCH32(SYS_ID_ISAR5_EL1),
397 AARCH32(SYS_ID_MMFR4_EL1),
398 AARCH32(SYS_ID_ISAR6_EL1),
399
400 /* CRm=3 */
401 AARCH32(SYS_MVFR0_EL1),
402 AARCH32(SYS_MVFR1_EL1),
403 AARCH32(SYS_MVFR2_EL1),
404 ID_UNALLOCATED(3,3),
405 AARCH32(SYS_ID_PFR2_EL1),
406 AARCH32(SYS_ID_DFR1_EL1),
407 AARCH32(SYS_ID_MMFR5_EL1),
408 ID_UNALLOCATED(3,7),
409
410 /* AArch64 ID registers */
411 /* CRm=4 */
412 AARCH64(SYS_ID_AA64PFR0_EL1),
413 AARCH64(SYS_ID_AA64PFR1_EL1),
414 ID_UNALLOCATED(4,2),
415 ID_UNALLOCATED(4,3),
416 AARCH64(SYS_ID_AA64ZFR0_EL1),
417 ID_UNALLOCATED(4,5),
418 ID_UNALLOCATED(4,6),
419 ID_UNALLOCATED(4,7),
420 AARCH64(SYS_ID_AA64DFR0_EL1),
421 AARCH64(SYS_ID_AA64DFR1_EL1),
422 ID_UNALLOCATED(5,2),
423 ID_UNALLOCATED(5,3),
424 AARCH64(SYS_ID_AA64AFR0_EL1),
425 AARCH64(SYS_ID_AA64AFR1_EL1),
426 ID_UNALLOCATED(5,6),
427 ID_UNALLOCATED(5,7),
428 AARCH64(SYS_ID_AA64ISAR0_EL1),
429 AARCH64(SYS_ID_AA64ISAR1_EL1),
430 AARCH64(SYS_ID_AA64ISAR2_EL1),
431 ID_UNALLOCATED(6,3),
432 ID_UNALLOCATED(6,4),
433 ID_UNALLOCATED(6,5),
434 ID_UNALLOCATED(6,6),
435 ID_UNALLOCATED(6,7),
436 AARCH64(SYS_ID_AA64MMFR0_EL1),
437 AARCH64(SYS_ID_AA64MMFR1_EL1),
438 AARCH64(SYS_ID_AA64MMFR2_EL1),
439 ID_UNALLOCATED(7,3),
440 ID_UNALLOCATED(7,4),
441 ID_UNALLOCATED(7,5),
442 ID_UNALLOCATED(7,6),
443 ID_UNALLOCATED(7,7),
444
445 /* Scalable Vector Registers are restricted. */
446
447 HOST_HANDLED(SYS_ICC_PMR_EL1),
448
449 RAZ_WI(SYS_ERRIDR_EL1),
450 RAZ_WI(SYS_ERRSELR_EL1),
451 RAZ_WI(SYS_ERXFR_EL1),
452 RAZ_WI(SYS_ERXCTLR_EL1),
453 RAZ_WI(SYS_ERXSTATUS_EL1),
454 RAZ_WI(SYS_ERXADDR_EL1),
455 RAZ_WI(SYS_ERXMISC0_EL1),
456 RAZ_WI(SYS_ERXMISC1_EL1),
457
458 /* Performance Monitoring Registers are restricted. */
459
460 /* Limited Ordering Regions Registers are restricted. */
461
462 HOST_HANDLED(SYS_ICC_DIR_EL1),
463 HOST_HANDLED(SYS_ICC_RPR_EL1),
464 HOST_HANDLED(SYS_ICC_SGI1R_EL1),
465 HOST_HANDLED(SYS_ICC_ASGI1R_EL1),
466 HOST_HANDLED(SYS_ICC_SGI0R_EL1),
467 HOST_HANDLED(SYS_ICC_CTLR_EL1),
468 { SYS_DESC(SYS_ICC_SRE_EL1), .access = pvm_gic_read_sre, },
469
470 HOST_HANDLED(SYS_CCSIDR_EL1),
471 HOST_HANDLED(SYS_CLIDR_EL1),
472 HOST_HANDLED(SYS_AIDR_EL1),
473 HOST_HANDLED(SYS_CSSELR_EL1),
474 HOST_HANDLED(SYS_CTR_EL0),
475
476 /* Performance Monitoring Registers are restricted. */
477
478 /* Activity Monitoring Registers are restricted. */
479
480 HOST_HANDLED(SYS_CNTP_TVAL_EL0),
481 HOST_HANDLED(SYS_CNTP_CTL_EL0),
482 HOST_HANDLED(SYS_CNTP_CVAL_EL0),
483
484 /* Performance Monitoring Registers are restricted. */
485};
486
487/*
488 * Initializes feature registers for protected vms.
489 */
490void kvm_init_pvm_id_regs(struct kvm_vcpu *vcpu)
491{
492 struct kvm *kvm = vcpu->kvm;
493 struct kvm_arch *ka = &kvm->arch;
494 u32 r;
495
496 hyp_assert_lock_held(&vm_table_lock);
497
498 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
499 return;
500
501 /*
502 * Initialize only AArch64 id registers since AArch32 isn't supported
503 * for protected VMs.
504 */
505 for (r = sys_reg(3, 0, 0, 4, 0); r <= sys_reg(3, 0, 0, 7, 7); r += sys_reg(0, 0, 0, 0, 1))
506 ka->id_regs[IDREG_IDX(r)] = pvm_calc_id_reg(vcpu, id: r);
507
508 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
509}
510
511/*
512 * Checks that the sysreg table is unique and in-order.
513 *
514 * Returns 0 if the table is consistent, or 1 otherwise.
515 */
516int kvm_check_pvm_sysreg_table(void)
517{
518 unsigned int i;
519
520 for (i = 1; i < ARRAY_SIZE(pvm_sys_reg_descs); i++) {
521 if (cmp_sys_reg(i1: &pvm_sys_reg_descs[i-1], i2: &pvm_sys_reg_descs[i]) >= 0)
522 return 1;
523 }
524
525 return 0;
526}
527
528/*
529 * Handler for protected VM MSR, MRS or System instruction execution.
530 *
531 * Returns true if the hypervisor has handled the exit, and control should go
532 * back to the guest, or false if it hasn't, to be handled by the host.
533 */
534bool kvm_handle_pvm_sysreg(struct kvm_vcpu *vcpu, u64 *exit_code)
535{
536 const struct sys_reg_desc *r;
537 struct sys_reg_params params;
538 unsigned long esr = kvm_vcpu_get_esr(vcpu);
539 int Rt = kvm_vcpu_sys_get_rt(vcpu);
540
541 params = esr_sys64_to_params(esr);
542 params.regval = vcpu_get_reg(vcpu, Rt);
543
544 r = find_reg(params: &params, table: pvm_sys_reg_descs, num: ARRAY_SIZE(pvm_sys_reg_descs));
545
546 /* Undefined (RESTRICTED). */
547 if (r == NULL) {
548 inject_undef64(vcpu);
549 return true;
550 }
551
552 /* Handled by the host (HOST_HANDLED) */
553 if (r->access == NULL)
554 return false;
555
556 /* Handled by hyp: skip instruction if instructed to do so. */
557 if (r->access(vcpu, &params, r))
558 __kvm_skip_instr(vcpu);
559
560 if (!params.is_write)
561 vcpu_set_reg(vcpu, Rt, params.regval);
562
563 return true;
564}
565
566/*
567 * Handler for protected VM restricted exceptions.
568 *
569 * Inject an undefined exception into the guest and return true to indicate that
570 * the hypervisor has handled the exit, and control should go back to the guest.
571 */
572bool kvm_handle_pvm_restricted(struct kvm_vcpu *vcpu, u64 *exit_code)
573{
574 inject_undef64(vcpu);
575 return true;
576}
577

source code of linux/arch/arm64/kvm/hyp/nvhe/sys_regs.c