1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 *
4 * Copyright (C) 2003, 04, 11 Ralf Baechle (ralf@linux-mips.org)
5 * Copyright (C) 2011 Wind River Systems,
6 * written by Ralf Baechle (ralf@linux-mips.org)
7 */
8#include <linux/bug.h>
9#include <linux/kernel.h>
10#include <linux/mm.h>
11#include <linux/memblock.h>
12#include <linux/export.h>
13#include <linux/init.h>
14#include <linux/types.h>
15#include <linux/pci.h>
16#include <linux/of_address.h>
17
18#include <asm/cpu-info.h>
19
20/*
21 * If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
22 * assignments.
23 */
24
25/*
26 * The PCI controller list.
27 */
28static LIST_HEAD(controllers);
29
30static int pci_initialized;
31
32unsigned long pci_address_to_pio(phys_addr_t address)
33{
34 if (address > IO_SPACE_LIMIT)
35 return (unsigned long)-1;
36
37 return (unsigned long) address;
38}
39
40/*
41 * We need to avoid collisions with `mirrored' VGA ports
42 * and other strange ISA hardware, so we always want the
43 * addresses to be allocated in the 0x000-0x0ff region
44 * modulo 0x400.
45 *
46 * Why? Because some silly external IO cards only decode
47 * the low 10 bits of the IO address. The 0x00-0xff region
48 * is reserved for motherboard devices that decode all 16
49 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
50 * but we want to try to avoid allocating at 0x2900-0x2bff
51 * which might have be mirrored at 0x0100-0x03ff..
52 */
53resource_size_t
54pcibios_align_resource(void *data, const struct resource *res,
55 resource_size_t size, resource_size_t align)
56{
57 struct pci_dev *dev = data;
58 struct pci_controller *hose = dev->sysdata;
59 resource_size_t start = res->start;
60
61 if (res->flags & IORESOURCE_IO) {
62 /* Make sure we start at our min on all hoses */
63 if (start < PCIBIOS_MIN_IO + hose->io_resource->start)
64 start = PCIBIOS_MIN_IO + hose->io_resource->start;
65
66 /*
67 * Put everything into 0x00-0xff region modulo 0x400
68 */
69 if (start & 0x300)
70 start = (start + 0x3ff) & ~0x3ff;
71 } else if (res->flags & IORESOURCE_MEM) {
72 /* Make sure we start at our min on all hoses */
73 if (start < PCIBIOS_MIN_MEM + hose->mem_resource->start)
74 start = PCIBIOS_MIN_MEM + hose->mem_resource->start;
75 }
76
77 return start;
78}
79
80static void pcibios_scanbus(struct pci_controller *hose)
81{
82 static int next_busno;
83 static int need_domain_info;
84 LIST_HEAD(resources);
85 struct pci_bus *bus;
86 struct pci_host_bridge *bridge;
87 int ret;
88
89 bridge = pci_alloc_host_bridge(priv: 0);
90 if (!bridge)
91 return;
92
93 if (hose->get_busno && pci_has_flag(flag: PCI_PROBE_ONLY))
94 next_busno = (*hose->get_busno)();
95
96 pci_add_resource_offset(resources: &resources,
97 res: hose->mem_resource, offset: hose->mem_offset);
98 pci_add_resource_offset(resources: &resources,
99 res: hose->io_resource, offset: hose->io_offset);
100 list_splice_init(list: &resources, head: &bridge->windows);
101 bridge->dev.parent = NULL;
102 bridge->sysdata = hose;
103 bridge->busnr = next_busno;
104 bridge->ops = hose->pci_ops;
105 bridge->swizzle_irq = pci_common_swizzle;
106 bridge->map_irq = pcibios_map_irq;
107 ret = pci_scan_root_bus_bridge(bridge);
108 if (ret) {
109 pci_free_host_bridge(bridge);
110 return;
111 }
112
113 hose->bus = bus = bridge->bus;
114
115 need_domain_info = need_domain_info || pci_domain_nr(bus);
116 set_pci_need_domain_info(hose, need_domain_info);
117
118 next_busno = bus->busn_res.end + 1;
119 /* Don't allow 8-bit bus number overflow inside the hose -
120 reserve some space for bridges. */
121 if (next_busno > 224) {
122 next_busno = 0;
123 need_domain_info = 1;
124 }
125
126 /*
127 * We insert PCI resources into the iomem_resource and
128 * ioport_resource trees in either pci_bus_claim_resources()
129 * or pci_bus_assign_resources().
130 */
131 if (pci_has_flag(flag: PCI_PROBE_ONLY)) {
132 pci_bus_claim_resources(bus);
133 } else {
134 struct pci_bus *child;
135
136 pci_bus_size_bridges(bus);
137 pci_bus_assign_resources(bus);
138 list_for_each_entry(child, &bus->children, node)
139 pcie_bus_configure_settings(bus: child);
140 }
141 pci_bus_add_devices(bus);
142}
143
144#ifdef CONFIG_OF
145void pci_load_of_ranges(struct pci_controller *hose, struct device_node *node)
146{
147 struct of_pci_range range;
148 struct of_pci_range_parser parser;
149
150 hose->of_node = node;
151
152 if (of_pci_range_parser_init(parser: &parser, node))
153 return;
154
155 for_each_of_pci_range(&parser, &range) {
156 struct resource *res = NULL;
157
158 switch (range.flags & IORESOURCE_TYPE_BITS) {
159 case IORESOURCE_IO:
160 hose->io_map_base =
161 (unsigned long)ioremap(offset: range.cpu_addr,
162 size: range.size);
163 res = hose->io_resource;
164 break;
165 case IORESOURCE_MEM:
166 res = hose->mem_resource;
167 break;
168 }
169 if (res != NULL) {
170 res->name = node->full_name;
171 res->flags = range.flags;
172 res->start = range.cpu_addr;
173 res->end = range.cpu_addr + range.size - 1;
174 res->parent = res->child = res->sibling = NULL;
175 }
176 }
177}
178
179struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
180{
181 struct pci_controller *hose = bus->sysdata;
182
183 return of_node_get(node: hose->of_node);
184}
185#endif
186
187static DEFINE_MUTEX(pci_scan_mutex);
188
189void register_pci_controller(struct pci_controller *hose)
190{
191 struct resource *parent;
192
193 parent = hose->mem_resource->parent;
194 if (!parent)
195 parent = &iomem_resource;
196
197 if (request_resource(root: parent, new: hose->mem_resource) < 0)
198 goto out;
199
200 parent = hose->io_resource->parent;
201 if (!parent)
202 parent = &ioport_resource;
203
204 if (request_resource(root: parent, new: hose->io_resource) < 0) {
205 release_resource(new: hose->mem_resource);
206 goto out;
207 }
208
209 INIT_LIST_HEAD(list: &hose->list);
210 list_add_tail(new: &hose->list, head: &controllers);
211
212 /*
213 * Do not panic here but later - this might happen before console init.
214 */
215 if (!hose->io_map_base) {
216 printk(KERN_WARNING
217 "registering PCI controller with io_map_base unset\n");
218 }
219
220 /*
221 * Scan the bus if it is register after the PCI subsystem
222 * initialization.
223 */
224 if (pci_initialized) {
225 mutex_lock(&pci_scan_mutex);
226 pcibios_scanbus(hose);
227 mutex_unlock(lock: &pci_scan_mutex);
228 }
229
230 return;
231
232out:
233 printk(KERN_WARNING
234 "Skipping PCI bus scan due to resource conflict\n");
235}
236
237static int __init pcibios_init(void)
238{
239 struct pci_controller *hose;
240
241 /* Scan all of the recorded PCI controllers. */
242 list_for_each_entry(hose, &controllers, list)
243 pcibios_scanbus(hose);
244
245 pci_initialized = 1;
246
247 return 0;
248}
249
250subsys_initcall(pcibios_init);
251
252int pcibios_enable_device(struct pci_dev *dev, int mask)
253{
254 int err;
255
256 err = pci_enable_resources(dev, mask);
257 if (err < 0)
258 return err;
259
260 return pcibios_plat_dev_init(dev);
261}
262
263void pcibios_fixup_bus(struct pci_bus *bus)
264{
265 struct pci_dev *dev = bus->self;
266
267 if (pci_has_flag(flag: PCI_PROBE_ONLY) && dev &&
268 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
269 pci_read_bridge_bases(child: bus);
270 }
271}
272
273char * (*pcibios_plat_setup)(char *str) __initdata;
274
275char *__init pcibios_setup(char *str)
276{
277 if (pcibios_plat_setup)
278 return pcibios_plat_setup(str);
279 return str;
280}
281

source code of linux/arch/mips/pci/pci-legacy.c