1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Joshua Henderson <joshua.henderson@microchip.com>
4 * Copyright (C) 2015 Microchip Technology Inc. All rights reserved.
5 */
6#include <asm/io.h>
7
8#include "early_pin.h"
9
10#define PPS_BASE 0x1f800000
11
12/* Input PPS Registers */
13#define INT1R 0x1404
14#define INT2R 0x1408
15#define INT3R 0x140C
16#define INT4R 0x1410
17#define T2CKR 0x1418
18#define T3CKR 0x141C
19#define T4CKR 0x1420
20#define T5CKR 0x1424
21#define T6CKR 0x1428
22#define T7CKR 0x142C
23#define T8CKR 0x1430
24#define T9CKR 0x1434
25#define IC1R 0x1438
26#define IC2R 0x143C
27#define IC3R 0x1440
28#define IC4R 0x1444
29#define IC5R 0x1448
30#define IC6R 0x144C
31#define IC7R 0x1450
32#define IC8R 0x1454
33#define IC9R 0x1458
34#define OCFAR 0x1460
35#define U1RXR 0x1468
36#define U1CTSR 0x146C
37#define U2RXR 0x1470
38#define U2CTSR 0x1474
39#define U3RXR 0x1478
40#define U3CTSR 0x147C
41#define U4RXR 0x1480
42#define U4CTSR 0x1484
43#define U5RXR 0x1488
44#define U5CTSR 0x148C
45#define U6RXR 0x1490
46#define U6CTSR 0x1494
47#define SDI1R 0x149C
48#define SS1R 0x14A0
49#define SDI2R 0x14A8
50#define SS2R 0x14AC
51#define SDI3R 0x14B4
52#define SS3R 0x14B8
53#define SDI4R 0x14C0
54#define SS4R 0x14C4
55#define SDI5R 0x14CC
56#define SS5R 0x14D0
57#define SDI6R 0x14D8
58#define SS6R 0x14DC
59#define C1RXR 0x14E0
60#define C2RXR 0x14E4
61#define REFCLKI1R 0x14E8
62#define REFCLKI3R 0x14F0
63#define REFCLKI4R 0x14F4
64
65static const struct
66{
67 int function;
68 int reg;
69} input_pin_reg[] = {
70 { IN_FUNC_INT3, INT3R },
71 { IN_FUNC_T2CK, T2CKR },
72 { IN_FUNC_T6CK, T6CKR },
73 { IN_FUNC_IC3, IC3R },
74 { IN_FUNC_IC7, IC7R },
75 { IN_FUNC_U1RX, U1RXR },
76 { IN_FUNC_U2CTS, U2CTSR },
77 { IN_FUNC_U5RX, U5RXR },
78 { IN_FUNC_U6CTS, U6CTSR },
79 { IN_FUNC_SDI1, SDI1R },
80 { IN_FUNC_SDI3, SDI3R },
81 { IN_FUNC_SDI5, SDI5R },
82 { IN_FUNC_SS6, SS6R },
83 { IN_FUNC_REFCLKI1, REFCLKI1R },
84 { IN_FUNC_INT4, INT4R },
85 { IN_FUNC_T5CK, T5CKR },
86 { IN_FUNC_T7CK, T7CKR },
87 { IN_FUNC_IC4, IC4R },
88 { IN_FUNC_IC8, IC8R },
89 { IN_FUNC_U3RX, U3RXR },
90 { IN_FUNC_U4CTS, U4CTSR },
91 { IN_FUNC_SDI2, SDI2R },
92 { IN_FUNC_SDI4, SDI4R },
93 { IN_FUNC_C1RX, C1RXR },
94 { IN_FUNC_REFCLKI4, REFCLKI4R },
95 { IN_FUNC_INT2, INT2R },
96 { IN_FUNC_T3CK, T3CKR },
97 { IN_FUNC_T8CK, T8CKR },
98 { IN_FUNC_IC2, IC2R },
99 { IN_FUNC_IC5, IC5R },
100 { IN_FUNC_IC9, IC9R },
101 { IN_FUNC_U1CTS, U1CTSR },
102 { IN_FUNC_U2RX, U2RXR },
103 { IN_FUNC_U5CTS, U5CTSR },
104 { IN_FUNC_SS1, SS1R },
105 { IN_FUNC_SS3, SS3R },
106 { IN_FUNC_SS4, SS4R },
107 { IN_FUNC_SS5, SS5R },
108 { IN_FUNC_C2RX, C2RXR },
109 { IN_FUNC_INT1, INT1R },
110 { IN_FUNC_T4CK, T4CKR },
111 { IN_FUNC_T9CK, T9CKR },
112 { IN_FUNC_IC1, IC1R },
113 { IN_FUNC_IC6, IC6R },
114 { IN_FUNC_U3CTS, U3CTSR },
115 { IN_FUNC_U4RX, U4RXR },
116 { IN_FUNC_U6RX, U6RXR },
117 { IN_FUNC_SS2, SS2R },
118 { IN_FUNC_SDI6, SDI6R },
119 { IN_FUNC_OCFA, OCFAR },
120 { IN_FUNC_REFCLKI3, REFCLKI3R },
121};
122
123void pic32_pps_input(int function, int pin)
124{
125 void __iomem *pps_base = ioremap(PPS_BASE, size: 0xF4);
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(input_pin_reg); i++) {
129 if (input_pin_reg[i].function == function) {
130 __raw_writel(val: pin, addr: pps_base + input_pin_reg[i].reg);
131 return;
132 }
133 }
134
135 iounmap(addr: pps_base);
136}
137
138/* Output PPS Registers */
139#define RPA14R 0x1538
140#define RPA15R 0x153C
141#define RPB0R 0x1540
142#define RPB1R 0x1544
143#define RPB2R 0x1548
144#define RPB3R 0x154C
145#define RPB5R 0x1554
146#define RPB6R 0x1558
147#define RPB7R 0x155C
148#define RPB8R 0x1560
149#define RPB9R 0x1564
150#define RPB10R 0x1568
151#define RPB14R 0x1578
152#define RPB15R 0x157C
153#define RPC1R 0x1584
154#define RPC2R 0x1588
155#define RPC3R 0x158C
156#define RPC4R 0x1590
157#define RPC13R 0x15B4
158#define RPC14R 0x15B8
159#define RPD0R 0x15C0
160#define RPD1R 0x15C4
161#define RPD2R 0x15C8
162#define RPD3R 0x15CC
163#define RPD4R 0x15D0
164#define RPD5R 0x15D4
165#define RPD6R 0x15D8
166#define RPD7R 0x15DC
167#define RPD9R 0x15E4
168#define RPD10R 0x15E8
169#define RPD11R 0x15EC
170#define RPD12R 0x15F0
171#define RPD14R 0x15F8
172#define RPD15R 0x15FC
173#define RPE3R 0x160C
174#define RPE5R 0x1614
175#define RPE8R 0x1620
176#define RPE9R 0x1624
177#define RPF0R 0x1640
178#define RPF1R 0x1644
179#define RPF2R 0x1648
180#define RPF3R 0x164C
181#define RPF4R 0x1650
182#define RPF5R 0x1654
183#define RPF8R 0x1660
184#define RPF12R 0x1670
185#define RPF13R 0x1674
186#define RPG0R 0x1680
187#define RPG1R 0x1684
188#define RPG6R 0x1698
189#define RPG7R 0x169C
190#define RPG8R 0x16A0
191#define RPG9R 0x16A4
192
193static const struct
194{
195 int pin;
196 int reg;
197} output_pin_reg[] = {
198 { OUT_RPD2, RPD2R },
199 { OUT_RPG8, RPG8R },
200 { OUT_RPF4, RPF4R },
201 { OUT_RPD10, RPD10R },
202 { OUT_RPF1, RPF1R },
203 { OUT_RPB9, RPB9R },
204 { OUT_RPB10, RPB10R },
205 { OUT_RPC14, RPC14R },
206 { OUT_RPB5, RPB5R },
207 { OUT_RPC1, RPC1R },
208 { OUT_RPD14, RPD14R },
209 { OUT_RPG1, RPG1R },
210 { OUT_RPA14, RPA14R },
211 { OUT_RPD6, RPD6R },
212 { OUT_RPD3, RPD3R },
213 { OUT_RPG7, RPG7R },
214 { OUT_RPF5, RPF5R },
215 { OUT_RPD11, RPD11R },
216 { OUT_RPF0, RPF0R },
217 { OUT_RPB1, RPB1R },
218 { OUT_RPE5, RPE5R },
219 { OUT_RPC13, RPC13R },
220 { OUT_RPB3, RPB3R },
221 { OUT_RPC4, RPC4R },
222 { OUT_RPD15, RPD15R },
223 { OUT_RPG0, RPG0R },
224 { OUT_RPA15, RPA15R },
225 { OUT_RPD7, RPD7R },
226 { OUT_RPD9, RPD9R },
227 { OUT_RPG6, RPG6R },
228 { OUT_RPB8, RPB8R },
229 { OUT_RPB15, RPB15R },
230 { OUT_RPD4, RPD4R },
231 { OUT_RPB0, RPB0R },
232 { OUT_RPE3, RPE3R },
233 { OUT_RPB7, RPB7R },
234 { OUT_RPF12, RPF12R },
235 { OUT_RPD12, RPD12R },
236 { OUT_RPF8, RPF8R },
237 { OUT_RPC3, RPC3R },
238 { OUT_RPE9, RPE9R },
239 { OUT_RPD1, RPD1R },
240 { OUT_RPG9, RPG9R },
241 { OUT_RPB14, RPB14R },
242 { OUT_RPD0, RPD0R },
243 { OUT_RPB6, RPB6R },
244 { OUT_RPD5, RPD5R },
245 { OUT_RPB2, RPB2R },
246 { OUT_RPF3, RPF3R },
247 { OUT_RPF13, RPF13R },
248 { OUT_RPC2, RPC2R },
249 { OUT_RPE8, RPE8R },
250 { OUT_RPF2, RPF2R },
251};
252
253void pic32_pps_output(int function, int pin)
254{
255 void __iomem *pps_base = ioremap(PPS_BASE, size: 0x170);
256 int i;
257
258 for (i = 0; i < ARRAY_SIZE(output_pin_reg); i++) {
259 if (output_pin_reg[i].pin == pin) {
260 __raw_writel(val: function,
261 addr: pps_base + output_pin_reg[i].reg);
262 return;
263 }
264 }
265
266 iounmap(addr: pps_base);
267}
268

source code of linux/arch/mips/pic32/pic32mzda/early_pin.c