1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 *
4 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2013 John Crispin <john@phrozen.org>
6 */
7
8#include <linux/io.h>
9#include <linux/bitops.h>
10#include <linux/of.h>
11#include <linux/of_address.h>
12#include <linux/of_irq.h>
13#include <linux/irqdomain.h>
14#include <linux/interrupt.h>
15
16#include <asm/irq_cpu.h>
17#include <asm/mipsregs.h>
18#include <asm/time.h>
19
20#include "common.h"
21
22#define INTC_INT_GLOBAL BIT(31)
23
24#define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
25#define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
26#define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
27#define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
28#define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
29
30/* we have a cascade of 8 irqs */
31#define RALINK_INTC_IRQ_BASE 8
32
33/* we have 32 SoC irqs */
34#define RALINK_INTC_IRQ_COUNT 32
35
36#define RALINK_INTC_IRQ_PERFC (RALINK_INTC_IRQ_BASE + 9)
37
38enum rt_intc_regs_enum {
39 INTC_REG_STATUS0 = 0,
40 INTC_REG_STATUS1,
41 INTC_REG_TYPE,
42 INTC_REG_RAW_STATUS,
43 INTC_REG_ENABLE,
44 INTC_REG_DISABLE,
45};
46
47static u32 rt_intc_regs[] = {
48 [INTC_REG_STATUS0] = 0x00,
49 [INTC_REG_STATUS1] = 0x04,
50 [INTC_REG_TYPE] = 0x20,
51 [INTC_REG_RAW_STATUS] = 0x30,
52 [INTC_REG_ENABLE] = 0x34,
53 [INTC_REG_DISABLE] = 0x38,
54};
55
56static void __iomem *rt_intc_membase;
57
58static int rt_perfcount_irq;
59
60static inline void rt_intc_w32(u32 val, unsigned reg)
61{
62 __raw_writel(val, addr: rt_intc_membase + rt_intc_regs[reg]);
63}
64
65static inline u32 rt_intc_r32(unsigned reg)
66{
67 return __raw_readl(addr: rt_intc_membase + rt_intc_regs[reg]);
68}
69
70static void ralink_intc_irq_unmask(struct irq_data *d)
71{
72 rt_intc_w32(BIT(d->hwirq), reg: INTC_REG_ENABLE);
73}
74
75static void ralink_intc_irq_mask(struct irq_data *d)
76{
77 rt_intc_w32(BIT(d->hwirq), reg: INTC_REG_DISABLE);
78}
79
80static struct irq_chip ralink_intc_irq_chip = {
81 .name = "INTC",
82 .irq_unmask = ralink_intc_irq_unmask,
83 .irq_mask = ralink_intc_irq_mask,
84 .irq_mask_ack = ralink_intc_irq_mask,
85};
86
87int get_c0_perfcount_int(void)
88{
89 return rt_perfcount_irq;
90}
91EXPORT_SYMBOL_GPL(get_c0_perfcount_int);
92
93unsigned int get_c0_compare_int(void)
94{
95 return CP0_LEGACY_COMPARE_IRQ;
96}
97
98static void ralink_intc_irq_handler(struct irq_desc *desc)
99{
100 u32 pending = rt_intc_r32(reg: INTC_REG_STATUS0);
101
102 if (pending) {
103 struct irq_domain *domain = irq_desc_get_handler_data(desc);
104 generic_handle_domain_irq(domain, __ffs(pending));
105 } else {
106 spurious_interrupt();
107 }
108}
109
110asmlinkage void plat_irq_dispatch(void)
111{
112 unsigned long pending;
113
114 pending = read_c0_status() & read_c0_cause() & ST0_IM;
115
116 if (pending & STATUSF_IP7)
117 do_IRQ(RALINK_CPU_IRQ_COUNTER);
118
119 else if (pending & STATUSF_IP5)
120 do_IRQ(RALINK_CPU_IRQ_FE);
121
122 else if (pending & STATUSF_IP6)
123 do_IRQ(RALINK_CPU_IRQ_WIFI);
124
125 else if (pending & STATUSF_IP4)
126 do_IRQ(RALINK_CPU_IRQ_PCI);
127
128 else if (pending & STATUSF_IP2)
129 do_IRQ(RALINK_CPU_IRQ_INTC);
130
131 else
132 spurious_interrupt();
133}
134
135static int intc_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
136{
137 irq_set_chip_and_handler(irq, chip: &ralink_intc_irq_chip, handle: handle_level_irq);
138
139 return 0;
140}
141
142static const struct irq_domain_ops irq_domain_ops = {
143 .xlate = irq_domain_xlate_onecell,
144 .map = intc_map,
145};
146
147static int __init intc_of_init(struct device_node *node,
148 struct device_node *parent)
149{
150 struct resource res;
151 struct irq_domain *domain;
152 int irq;
153
154 if (!of_property_read_u32_array(np: node, propname: "ralink,intc-registers",
155 out_values: rt_intc_regs, sz: 6))
156 pr_info("intc: using register map from devicetree\n");
157
158 irq = irq_of_parse_and_map(node, index: 0);
159 if (!irq)
160 panic(fmt: "Failed to get INTC IRQ");
161
162 if (of_address_to_resource(dev: node, index: 0, r: &res))
163 panic(fmt: "Failed to get intc memory range");
164
165 if (!request_mem_region(res.start, resource_size(&res),
166 res.name))
167 pr_err("Failed to request intc memory");
168
169 rt_intc_membase = ioremap(offset: res.start,
170 size: resource_size(res: &res));
171 if (!rt_intc_membase)
172 panic(fmt: "Failed to remap intc memory");
173
174 /* disable all interrupts */
175 rt_intc_w32(val: ~0, reg: INTC_REG_DISABLE);
176
177 /* route all INTC interrupts to MIPS HW0 interrupt */
178 rt_intc_w32(val: 0, reg: INTC_REG_TYPE);
179
180 domain = irq_domain_create_legacy(of_fwnode_handle(node), RALINK_INTC_IRQ_COUNT,
181 RALINK_INTC_IRQ_BASE, first_hwirq: 0, ops: &irq_domain_ops, NULL);
182 if (!domain)
183 panic(fmt: "Failed to add irqdomain");
184
185 rt_intc_w32(INTC_INT_GLOBAL, reg: INTC_REG_ENABLE);
186
187 irq_set_chained_handler_and_data(irq, handle: ralink_intc_irq_handler, data: domain);
188
189 /* tell the kernel which irq is used for performance monitoring */
190 rt_perfcount_irq = irq_create_mapping(domain, hwirq: 9);
191
192 return 0;
193}
194
195static struct of_device_id __initdata of_irq_ids[] = {
196 { .compatible = "mti,cpu-interrupt-controller", .data = mips_cpu_irq_of_init },
197 { .compatible = "ralink,rt2880-intc", .data = intc_of_init },
198 {},
199};
200
201void __init arch_init_irq(void)
202{
203 of_irq_init(matches: of_irq_ids);
204}
205
206

source code of linux/arch/mips/ralink/irq.c