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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2#ifndef _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
3#define _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_
4/*
5 * PowerPC64 memory management structures
6 *
7 * Dave Engebretsen & Mike Corrigan <{engebret|mikejc}@us.ibm.com>
8 * PPC64 rework.
9 */
10
11#include <asm/page.h>
12#include <asm/bug.h>
13#include <asm/asm-const.h>
14
15/*
16 * This is necessary to get the definition of PGTABLE_RANGE which we
17 * need for various slices related matters. Note that this isn't the
18 * complete pgtable.h but only a portion of it.
19 */
20#include <asm/book3s/64/pgtable.h>
21#include <asm/book3s/64/slice.h>
22#include <asm/task_size_64.h>
23#include <asm/cpu_has_feature.h>
24
25/*
26 * SLB
27 */
28
29#define SLB_NUM_BOLTED 2
30#define SLB_CACHE_ENTRIES 8
31#define SLB_MIN_SIZE 32
32
33/* Bits in the SLB ESID word */
34#define SLB_ESID_V ASM_CONST(0x0000000008000000) /* valid */
35
36/* Bits in the SLB VSID word */
37#define SLB_VSID_SHIFT 12
38#define SLB_VSID_SHIFT_256M SLB_VSID_SHIFT
39#define SLB_VSID_SHIFT_1T 24
40#define SLB_VSID_SSIZE_SHIFT 62
41#define SLB_VSID_B ASM_CONST(0xc000000000000000)
42#define SLB_VSID_B_256M ASM_CONST(0x0000000000000000)
43#define SLB_VSID_B_1T ASM_CONST(0x4000000000000000)
44#define SLB_VSID_KS ASM_CONST(0x0000000000000800)
45#define SLB_VSID_KP ASM_CONST(0x0000000000000400)
46#define SLB_VSID_N ASM_CONST(0x0000000000000200) /* no-execute */
47#define SLB_VSID_L ASM_CONST(0x0000000000000100)
48#define SLB_VSID_C ASM_CONST(0x0000000000000080) /* class */
49#define SLB_VSID_LP ASM_CONST(0x0000000000000030)
50#define SLB_VSID_LP_00 ASM_CONST(0x0000000000000000)
51#define SLB_VSID_LP_01 ASM_CONST(0x0000000000000010)
52#define SLB_VSID_LP_10 ASM_CONST(0x0000000000000020)
53#define SLB_VSID_LP_11 ASM_CONST(0x0000000000000030)
54#define SLB_VSID_LLP (SLB_VSID_L|SLB_VSID_LP)
55
56#define SLB_VSID_KERNEL (SLB_VSID_KP)
57#define SLB_VSID_USER (SLB_VSID_KP|SLB_VSID_KS|SLB_VSID_C)
58
59#define SLBIE_C (0x08000000)
60#define SLBIE_SSIZE_SHIFT 25
61
62/*
63 * Hash table
64 */
65
66#define HPTES_PER_GROUP 8
67
68#define HPTE_V_SSIZE_SHIFT 62
69#define HPTE_V_AVPN_SHIFT 7
70#define HPTE_V_COMMON_BITS ASM_CONST(0x000fffffffffffff)
71#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80)
72#define HPTE_V_AVPN_3_0 ASM_CONST(0x000fffffffffff80)
73#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
74#define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & 0xffffffffffffff80UL))
75#define HPTE_V_BOLTED ASM_CONST(0x0000000000000010)
76#define HPTE_V_LOCK ASM_CONST(0x0000000000000008)
77#define HPTE_V_LARGE ASM_CONST(0x0000000000000004)
78#define HPTE_V_SECONDARY ASM_CONST(0x0000000000000002)
79#define HPTE_V_VALID ASM_CONST(0x0000000000000001)
80
81/*
82 * ISA 3.0 has a different HPTE format.
83 */
84#define HPTE_R_3_0_SSIZE_SHIFT 58
85#define HPTE_R_3_0_SSIZE_MASK (3ull << HPTE_R_3_0_SSIZE_SHIFT)
86#define HPTE_R_PP0 ASM_CONST(0x8000000000000000)
87#define HPTE_R_TS ASM_CONST(0x4000000000000000)
88#define HPTE_R_KEY_HI ASM_CONST(0x3000000000000000)
89#define HPTE_R_KEY_BIT4 ASM_CONST(0x2000000000000000)
90#define HPTE_R_KEY_BIT3 ASM_CONST(0x1000000000000000)
91#define HPTE_R_RPN_SHIFT 12
92#define HPTE_R_RPN ASM_CONST(0x0ffffffffffff000)
93#define HPTE_R_RPN_3_0 ASM_CONST(0x01fffffffffff000)
94#define HPTE_R_PP ASM_CONST(0x0000000000000003)
95#define HPTE_R_PPP ASM_CONST(0x8000000000000003)
96#define HPTE_R_N ASM_CONST(0x0000000000000004)
97#define HPTE_R_G ASM_CONST(0x0000000000000008)
98#define HPTE_R_M ASM_CONST(0x0000000000000010)
99#define HPTE_R_I ASM_CONST(0x0000000000000020)
100#define HPTE_R_W ASM_CONST(0x0000000000000040)
101#define HPTE_R_WIMG ASM_CONST(0x0000000000000078)
102#define HPTE_R_C ASM_CONST(0x0000000000000080)
103#define HPTE_R_R ASM_CONST(0x0000000000000100)
104#define HPTE_R_KEY_LO ASM_CONST(0x0000000000000e00)
105#define HPTE_R_KEY_BIT2 ASM_CONST(0x0000000000000800)
106#define HPTE_R_KEY_BIT1 ASM_CONST(0x0000000000000400)
107#define HPTE_R_KEY_BIT0 ASM_CONST(0x0000000000000200)
108#define HPTE_R_KEY (HPTE_R_KEY_LO | HPTE_R_KEY_HI)
109
110#define HPTE_V_1TB_SEG ASM_CONST(0x4000000000000000)
111#define HPTE_V_VRMA_MASK ASM_CONST(0x4001ffffff000000)
112
113/* Values for PP (assumes Ks=0, Kp=1) */
114#define PP_RWXX 0 /* Supervisor read/write, User none */
115#define PP_RWRX 1 /* Supervisor read/write, User read */
116#define PP_RWRW 2 /* Supervisor read/write, User read/write */
117#define PP_RXRX 3 /* Supervisor read, User read */
118#define PP_RXXX (HPTE_R_PP0 | 2) /* Supervisor read, user none */
119
120/* Fields for tlbiel instruction in architecture 2.06 */
121#define TLBIEL_INVAL_SEL_MASK 0xc00 /* invalidation selector */
122#define TLBIEL_INVAL_PAGE 0x000 /* invalidate a single page */
123#define TLBIEL_INVAL_SET_LPID 0x800 /* invalidate a set for current LPID */
124#define TLBIEL_INVAL_SET 0xc00 /* invalidate a set for all LPIDs */
125#define TLBIEL_INVAL_SET_MASK 0xfff000 /* set number to inval. */
126#define TLBIEL_INVAL_SET_SHIFT 12
127
128#define POWER7_TLB_SETS 128 /* # sets in POWER7 TLB */
129#define POWER8_TLB_SETS 512 /* # sets in POWER8 TLB */
130#define POWER9_TLB_SETS_HASH 256 /* # sets in POWER9 TLB Hash mode */
131#define POWER9_TLB_SETS_RADIX 128 /* # sets in POWER9 TLB Radix mode */
132
133#ifndef __ASSEMBLER__
134
135struct mmu_hash_ops {
136 void (*hpte_invalidate)(unsigned long slot,
137 unsigned long vpn,
138 int bpsize, int apsize,
139 int ssize, int local);
140 long (*hpte_updatepp)(unsigned long slot,
141 unsigned long newpp,
142 unsigned long vpn,
143 int bpsize, int apsize,
144 int ssize, unsigned long flags);
145 void (*hpte_updateboltedpp)(unsigned long newpp,
146 unsigned long ea,
147 int psize, int ssize);
148 long (*hpte_insert)(unsigned long hpte_group,
149 unsigned long vpn,
150 unsigned long prpn,
151 unsigned long rflags,
152 unsigned long vflags,
153 int psize, int apsize,
154 int ssize);
155 long (*hpte_remove)(unsigned long hpte_group);
156 int (*hpte_removebolted)(unsigned long ea,
157 int psize, int ssize);
158 void (*flush_hash_range)(unsigned long number, int local);
159 void (*hugepage_invalidate)(unsigned long vsid,
160 unsigned long addr,
161 unsigned char *hpte_slot_array,
162 int psize, int ssize, int local);
163 int (*resize_hpt)(unsigned long shift);
164 /*
165 * Special for kexec.
166 * To be called in real mode with interrupts disabled. No locks are
167 * taken as such, concurrent access on pre POWER5 hardware could result
168 * in a deadlock.
169 * The linear mapping is destroyed as well.
170 */
171 void (*hpte_clear_all)(void);
172};
173extern struct mmu_hash_ops mmu_hash_ops;
174
175struct hash_pte {
176 __be64 v;
177 __be64 r;
178};
179
180extern struct hash_pte *htab_address;
181extern unsigned long htab_size_bytes;
182extern unsigned long htab_hash_mask;
183
184
185static inline int shift_to_mmu_psize(unsigned int shift)
186{
187 int psize;
188
189 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize)
190 if (mmu_psize_defs[psize].shift == shift)
191 return psize;
192 return -1;
193}
194
195static inline unsigned int mmu_psize_to_shift(unsigned int mmu_psize)
196{
197 if (mmu_psize_defs[mmu_psize].shift)
198 return mmu_psize_defs[mmu_psize].shift;
199 BUG();
200}
201
202static inline unsigned int ap_to_shift(unsigned long ap)
203{
204 int psize;
205
206 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
207 if (mmu_psize_defs[psize].ap == ap)
208 return mmu_psize_defs[psize].shift;
209 }
210
211 return -1;
212}
213
214static inline unsigned long get_sllp_encoding(int psize)
215{
216 unsigned long sllp;
217
218 sllp = ((mmu_psize_defs[psize].sllp & SLB_VSID_L) >> 6) |
219 ((mmu_psize_defs[psize].sllp & SLB_VSID_LP) >> 4);
220 return sllp;
221}
222
223#endif /* __ASSEMBLER__ */
224
225/*
226 * Segment sizes.
227 * These are the values used by hardware in the B field of
228 * SLB entries and the first dword of MMU hashtable entries.
229 * The B field is 2 bits; the values 2 and 3 are unused and reserved.
230 */
231#define MMU_SEGSIZE_256M 0
232#define MMU_SEGSIZE_1T 1
233
234/*
235 * encode page number shift.
236 * in order to fit the 78 bit va in a 64 bit variable we shift the va by
237 * 12 bits. This enable us to address upto 76 bit va.
238 * For hpt hash from a va we can ignore the page size bits of va and for
239 * hpte encoding we ignore up to 23 bits of va. So ignoring lower 12 bits ensure
240 * we work in all cases including 4k page size.
241 */
242#define VPN_SHIFT 12
243
244/*
245 * HPTE Large Page (LP) details
246 */
247#define LP_SHIFT 12
248#define LP_BITS 8
249#define LP_MASK(i) ((0xFF >> (i)) << LP_SHIFT)
250
251#ifndef __ASSEMBLER__
252
253static inline int slb_vsid_shift(int ssize)
254{
255 if (ssize == MMU_SEGSIZE_256M)
256 return SLB_VSID_SHIFT;
257 return SLB_VSID_SHIFT_1T;
258}
259
260static inline int segment_shift(int ssize)
261{
262 if (ssize == MMU_SEGSIZE_256M)
263 return SID_SHIFT;
264 return SID_SHIFT_1T;
265}
266
267/*
268 * This array is indexed by the LP field of the HPTE second dword.
269 * Since this field may contain some RPN bits, some entries are
270 * replicated so that we get the same value irrespective of RPN.
271 * The top 4 bits are the page size index (MMU_PAGE_*) for the
272 * actual page size, the bottom 4 bits are the base page size.
273 */
274extern u8 hpte_page_sizes[1 << LP_BITS];
275
276static inline unsigned long __hpte_page_size(unsigned long h, unsigned long l,
277 bool is_base_size)
278{
279 unsigned int i, lp;
280
281 if (!(h & HPTE_V_LARGE))
282 return 1ul << 12;
283
284 /* Look at the 8 bit LP value */
285 lp = (l >> LP_SHIFT) & ((1 << LP_BITS) - 1);
286 i = hpte_page_sizes[lp];
287 if (!i)
288 return 0;
289 if (!is_base_size)
290 i >>= 4;
291 return 1ul << mmu_psize_defs[i & 0xf].shift;
292}
293
294static inline unsigned long hpte_page_size(unsigned long h, unsigned long l)
295{
296 return __hpte_page_size(h, l, 0);
297}
298
299static inline unsigned long hpte_base_page_size(unsigned long h, unsigned long l)
300{
301 return __hpte_page_size(h, l, 1);
302}
303
304/*
305 * The current system page and segment sizes
306 */
307extern int mmu_kernel_ssize;
308extern int mmu_highuser_ssize;
309extern u16 mmu_slb_size;
310extern unsigned long tce_alloc_start, tce_alloc_end;
311
312/*
313 * If the processor supports 64k normal pages but not 64k cache
314 * inhibited pages, we have to be prepared to switch processes
315 * to use 4k pages when they create cache-inhibited mappings.
316 * If this is the case, mmu_ci_restrictions will be set to 1.
317 */
318extern int mmu_ci_restrictions;
319
320/*
321 * This computes the AVPN and B fields of the first dword of a HPTE,
322 * for use when we want to match an existing PTE. The bottom 7 bits
323 * of the returned value are zero.
324 */
325static inline unsigned long hpte_encode_avpn(unsigned long vpn, int psize,
326 int ssize)
327{
328 unsigned long v;
329 /*
330 * The AVA field omits the low-order 23 bits of the 78 bits VA.
331 * These bits are not needed in the PTE, because the
332 * low-order b of these bits are part of the byte offset
333 * into the virtual page and, if b < 23, the high-order
334 * 23-b of these bits are always used in selecting the
335 * PTEGs to be searched
336 */
337 v = (vpn >> (23 - VPN_SHIFT)) & ~(mmu_psize_defs[psize].avpnm);
338 v <<= HPTE_V_AVPN_SHIFT;
339 v |= ((unsigned long) ssize) << HPTE_V_SSIZE_SHIFT;
340 return v;
341}
342
343/*
344 * ISA v3.0 defines a new HPTE format, which differs from the old
345 * format in having smaller AVPN and ARPN fields, and the B field
346 * in the second dword instead of the first.
347 */
348static inline unsigned long hpte_old_to_new_v(unsigned long v)
349{
350 /* trim AVPN, drop B */
351 return v & HPTE_V_COMMON_BITS;
352}
353
354static inline unsigned long hpte_old_to_new_r(unsigned long v, unsigned long r)
355{
356 /* move B field from 1st to 2nd dword, trim ARPN */
357 return (r & ~HPTE_R_3_0_SSIZE_MASK) |
358 (((v) >> HPTE_V_SSIZE_SHIFT) << HPTE_R_3_0_SSIZE_SHIFT);
359}
360
361static inline unsigned long hpte_new_to_old_v(unsigned long v, unsigned long r)
362{
363 /* insert B field */
364 return (v & HPTE_V_COMMON_BITS) |
365 ((r & HPTE_R_3_0_SSIZE_MASK) <<
366 (HPTE_V_SSIZE_SHIFT - HPTE_R_3_0_SSIZE_SHIFT));
367}
368
369static inline unsigned long hpte_new_to_old_r(unsigned long r)
370{
371 /* clear out B field */
372 return r & ~HPTE_R_3_0_SSIZE_MASK;
373}
374
375static inline unsigned long hpte_get_old_v(struct hash_pte *hptep)
376{
377 unsigned long hpte_v;
378
379 hpte_v = be64_to_cpu(hptep->v);
380 if (cpu_has_feature(CPU_FTR_ARCH_300))
381 hpte_v = hpte_new_to_old_v(hpte_v, be64_to_cpu(hptep->r));
382 return hpte_v;
383}
384
385/*
386 * This function sets the AVPN and L fields of the HPTE appropriately
387 * using the base page size and actual page size.
388 */
389static inline unsigned long hpte_encode_v(unsigned long vpn, int base_psize,
390 int actual_psize, int ssize)
391{
392 unsigned long v;
393 v = hpte_encode_avpn(vpn, base_psize, ssize);
394 if (actual_psize != MMU_PAGE_4K)
395 v |= HPTE_V_LARGE;
396 return v;
397}
398
399/*
400 * This function sets the ARPN, and LP fields of the HPTE appropriately
401 * for the page size. We assume the pa is already "clean" that is properly
402 * aligned for the requested page size
403 */
404static inline unsigned long hpte_encode_r(unsigned long pa, int base_psize,
405 int actual_psize)
406{
407 /* A 4K page needs no special encoding */
408 if (actual_psize == MMU_PAGE_4K)
409 return pa & HPTE_R_RPN;
410 else {
411 unsigned int penc = mmu_psize_defs[base_psize].penc[actual_psize];
412 unsigned int shift = mmu_psize_defs[actual_psize].shift;
413 return (pa & ~((1ul << shift) - 1)) | (penc << LP_SHIFT);
414 }
415}
416
417/*
418 * Build a VPN_SHIFT bit shifted va given VSID, EA and segment size.
419 */
420static inline unsigned long hpt_vpn(unsigned long ea,
421 unsigned long vsid, int ssize)
422{
423 unsigned long mask;
424 int s_shift = segment_shift(ssize);
425
426 mask = (1ul << (s_shift - VPN_SHIFT)) - 1;
427 return (vsid << (s_shift - VPN_SHIFT)) | ((ea >> VPN_SHIFT) & mask);
428}
429
430/*
431 * This hashes a virtual address
432 */
433static inline unsigned long hpt_hash(unsigned long vpn,
434 unsigned int shift, int ssize)
435{
436 unsigned long mask;
437 unsigned long hash, vsid;
438
439 /* VPN_SHIFT can be atmost 12 */
440 if (ssize == MMU_SEGSIZE_256M) {
441 mask = (1ul << (SID_SHIFT - VPN_SHIFT)) - 1;
442 hash = (vpn >> (SID_SHIFT - VPN_SHIFT)) ^
443 ((vpn & mask) >> (shift - VPN_SHIFT));
444 } else {
445 mask = (1ul << (SID_SHIFT_1T - VPN_SHIFT)) - 1;
446 vsid = vpn >> (SID_SHIFT_1T - VPN_SHIFT);
447 hash = vsid ^ (vsid << 25) ^
448 ((vpn & mask) >> (shift - VPN_SHIFT)) ;
449 }
450 return hash & 0x7fffffffffUL;
451}
452
453#define HPTE_LOCAL_UPDATE 0x1
454#define HPTE_NOHPTE_UPDATE 0x2
455#define HPTE_USE_KERNEL_KEY 0x4
456
457long hpte_insert_repeating(unsigned long hash, unsigned long vpn, unsigned long pa,
458 unsigned long rlags, unsigned long vflags, int psize, int ssize);
459extern int __hash_page_4K(unsigned long ea, unsigned long access,
460 unsigned long vsid, pte_t *ptep, unsigned long trap,
461 unsigned long flags, int ssize, int subpage_prot);
462extern int __hash_page_64K(unsigned long ea, unsigned long access,
463 unsigned long vsid, pte_t *ptep, unsigned long trap,
464 unsigned long flags, int ssize);
465struct mm_struct;
466unsigned int hash_page_do_lazy_icache(unsigned int pp, pte_t pte, int trap);
467extern int hash_page_mm(struct mm_struct *mm, unsigned long ea,
468 unsigned long access, unsigned long trap,
469 unsigned long flags);
470extern int hash_page(unsigned long ea, unsigned long access, unsigned long trap,
471 unsigned long dsisr);
472void low_hash_fault(struct pt_regs *regs, unsigned long address, int rc);
473int __hash_page(unsigned long trap, unsigned long ea, unsigned long dsisr, unsigned long msr);
474int __hash_page_huge(unsigned long ea, unsigned long access, unsigned long vsid,
475 pte_t *ptep, unsigned long trap, unsigned long flags,
476 int ssize, unsigned int shift, unsigned int mmu_psize);
477#ifdef CONFIG_TRANSPARENT_HUGEPAGE
478extern int __hash_page_thp(unsigned long ea, unsigned long access,
479 unsigned long vsid, pmd_t *pmdp, unsigned long trap,
480 unsigned long flags, int ssize, unsigned int psize);
481#else
482static inline int __hash_page_thp(unsigned long ea, unsigned long access,
483 unsigned long vsid, pmd_t *pmdp,
484 unsigned long trap, unsigned long flags,
485 int ssize, unsigned int psize)
486{
487 BUG();
488 return -1;
489}
490#endif
491extern void hash_failure_debug(unsigned long ea, unsigned long access,
492 unsigned long vsid, unsigned long trap,
493 int ssize, int psize, int lpsize,
494 unsigned long pte);
495extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
496 unsigned long pstart, unsigned long prot,
497 int psize, int ssize);
498int htab_remove_mapping(unsigned long vstart, unsigned long vend,
499 int psize, int ssize);
500extern void pseries_add_gpage(u64 addr, u64 page_size, unsigned long number_of_pages);
501extern void demote_segment_4k(struct mm_struct *mm, unsigned long addr);
502
503extern void hash__setup_new_exec(void);
504
505#ifdef CONFIG_PPC_PSERIES
506void hpte_init_pseries(void);
507#else
508static inline void hpte_init_pseries(void) { }
509#endif
510
511extern void hpte_init_native(void);
512
513struct slb_entry {
514 u64 esid;
515 u64 vsid;
516};
517
518extern void slb_initialize(void);
519void slb_flush_and_restore_bolted(void);
520void slb_flush_all_realmode(void);
521void __slb_restore_bolted_realmode(void);
522void slb_restore_bolted_realmode(void);
523void slb_save_contents(struct slb_entry *slb_ptr);
524void slb_dump_contents(struct slb_entry *slb_ptr);
525
526extern void slb_vmalloc_update(void);
527
528#ifdef CONFIG_PPC_64S_HASH_MMU
529void slb_set_size(u16 size);
530#else
531static inline void slb_set_size(u16 size) { }
532#endif
533
534#endif /* __ASSEMBLER__ */
535
536/*
537 * VSID allocation (256MB segment)
538 *
539 * We first generate a 37-bit "proto-VSID". Proto-VSIDs are generated
540 * from mmu context id and effective segment id of the address.
541 *
542 * For user processes max context id is limited to MAX_USER_CONTEXT.
543 * more details in get_user_context
544 *
545 * For kernel space get_kernel_context
546 *
547 * The proto-VSIDs are then scrambled into real VSIDs with the
548 * multiplicative hash:
549 *
550 * VSID = (proto-VSID * VSID_MULTIPLIER) % VSID_MODULUS
551 *
552 * VSID_MULTIPLIER is prime, so in particular it is
553 * co-prime to VSID_MODULUS, making this a 1:1 scrambling function.
554 * Because the modulus is 2^n-1 we can compute it efficiently without
555 * a divide or extra multiply (see below). The scramble function gives
556 * robust scattering in the hash table (at least based on some initial
557 * results).
558 *
559 * We use VSID 0 to indicate an invalid VSID. The means we can't use context id
560 * 0, because a context id of 0 and an EA of 0 gives a proto-VSID of 0, which
561 * will produce a VSID of 0.
562 *
563 * We also need to avoid the last segment of the last context, because that
564 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
565 * because of the modulo operation in vsid scramble.
566 */
567
568/*
569 * Max Va bits we support as of now is 68 bits. We want 19 bit
570 * context ID.
571 * Restrictions:
572 * GPU has restrictions of not able to access beyond 128TB
573 * (47 bit effective address). We also cannot do more than 20bit PID.
574 * For p4 and p5 which can only do 65 bit VA, we restrict our CONTEXT_BITS
575 * to 16 bits (ie, we can only have 2^16 pids at the same time).
576 */
577#define VA_BITS 68
578#define CONTEXT_BITS 19
579#define ESID_BITS (VA_BITS - (SID_SHIFT + CONTEXT_BITS))
580#define ESID_BITS_1T (VA_BITS - (SID_SHIFT_1T + CONTEXT_BITS))
581
582#define ESID_BITS_MASK ((1 << ESID_BITS) - 1)
583#define ESID_BITS_1T_MASK ((1 << ESID_BITS_1T) - 1)
584
585/*
586 * Now certain config support MAX_PHYSMEM more than 512TB. Hence we will need
587 * to use more than one context for linear mapping the kernel.
588 * For vmalloc and memmap, we use just one context with 512TB. With 64 byte
589 * struct page size, we need ony 32 TB in memmap for 2PB (51 bits (MAX_PHYSMEM_BITS)).
590 */
591#if (H_MAX_PHYSMEM_BITS > MAX_EA_BITS_PER_CONTEXT)
592#define MAX_KERNEL_CTX_CNT (1UL << (H_MAX_PHYSMEM_BITS - MAX_EA_BITS_PER_CONTEXT))
593#else
594#define MAX_KERNEL_CTX_CNT 1
595#endif
596
597#define MAX_VMALLOC_CTX_CNT 1
598#define MAX_IO_CTX_CNT 1
599#define MAX_VMEMMAP_CTX_CNT 1
600
601/*
602 * 256MB segment
603 * The proto-VSID space has 2^(CONTEX_BITS + ESID_BITS) - 1 segments
604 * available for user + kernel mapping. VSID 0 is reserved as invalid, contexts
605 * 1-4 are used for kernel mapping. Each segment contains 2^28 bytes. Each
606 * context maps 2^49 bytes (512TB).
607 *
608 * We also need to avoid the last segment of the last context, because that
609 * would give a protovsid of 0x1fffffffff. That will result in a VSID 0
610 * because of the modulo operation in vsid scramble.
611 *
612 */
613#define MAX_USER_CONTEXT ((ASM_CONST(1) << CONTEXT_BITS) - 2)
614
615// The + 2 accounts for INVALID_REGION and 1 more to avoid overlap with kernel
616#define MIN_USER_CONTEXT (MAX_KERNEL_CTX_CNT + MAX_VMALLOC_CTX_CNT + \
617 MAX_IO_CTX_CNT + MAX_VMEMMAP_CTX_CNT + 2)
618
619/*
620 * For platforms that support on 65bit VA we limit the context bits
621 */
622#define MAX_USER_CONTEXT_65BIT_VA ((ASM_CONST(1) << (65 - (SID_SHIFT + ESID_BITS))) - 2)
623
624/*
625 * This should be computed such that protovosid * vsid_mulitplier
626 * doesn't overflow 64 bits. The vsid_mutliplier should also be
627 * co-prime to vsid_modulus. We also need to make sure that number
628 * of bits in multiplied result (dividend) is less than twice the number of
629 * protovsid bits for our modulus optmization to work.
630 *
631 * The below table shows the current values used.
632 * |-------+------------+----------------------+------------+-------------------|
633 * | | Prime Bits | proto VSID_BITS_65VA | Total Bits | 2* prot VSID_BITS |
634 * |-------+------------+----------------------+------------+-------------------|
635 * | 1T | 24 | 25 | 49 | 50 |
636 * |-------+------------+----------------------+------------+-------------------|
637 * | 256MB | 24 | 37 | 61 | 74 |
638 * |-------+------------+----------------------+------------+-------------------|
639 *
640 * |-------+------------+----------------------+------------+--------------------|
641 * | | Prime Bits | proto VSID_BITS_68VA | Total Bits | 2* proto VSID_BITS |
642 * |-------+------------+----------------------+------------+--------------------|
643 * | 1T | 24 | 28 | 52 | 56 |
644 * |-------+------------+----------------------+------------+--------------------|
645 * | 256MB | 24 | 40 | 64 | 80 |
646 * |-------+------------+----------------------+------------+--------------------|
647 *
648 */
649#define VSID_MULTIPLIER_256M ASM_CONST(12538073) /* 24-bit prime */
650#define VSID_BITS_256M (VA_BITS - SID_SHIFT)
651#define VSID_BITS_65_256M (65 - SID_SHIFT)
652/*
653 * Modular multiplicative inverse of VSID_MULTIPLIER under modulo VSID_MODULUS
654 */
655#define VSID_MULINV_256M ASM_CONST(665548017062)
656
657#define VSID_MULTIPLIER_1T ASM_CONST(12538073) /* 24-bit prime */
658#define VSID_BITS_1T (VA_BITS - SID_SHIFT_1T)
659#define VSID_BITS_65_1T (65 - SID_SHIFT_1T)
660#define VSID_MULINV_1T ASM_CONST(209034062)
661
662/* 1TB VSID reserved for VRMA */
663#define VRMA_VSID 0x1ffffffUL
664#define USER_VSID_RANGE (1UL << (ESID_BITS + SID_SHIFT))
665
666/* 4 bits per slice and we have one slice per 1TB */
667#define SLICE_ARRAY_SIZE (H_PGTABLE_RANGE >> 41)
668#define LOW_SLICE_ARRAY_SZ (BITS_PER_LONG / BITS_PER_BYTE)
669#define TASK_SLICE_ARRAY_SZ(x) ((x)->hash_context->slb_addr_limit >> 41)
670#ifndef __ASSEMBLER__
671
672#ifdef CONFIG_PPC_SUBPAGE_PROT
673/*
674 * For the sub-page protection option, we extend the PGD with one of
675 * these. Basically we have a 3-level tree, with the top level being
676 * the protptrs array. To optimize speed and memory consumption when
677 * only addresses < 4GB are being protected, pointers to the first
678 * four pages of sub-page protection words are stored in the low_prot
679 * array.
680 * Each page of sub-page protection words protects 1GB (4 bytes
681 * protects 64k). For the 3-level tree, each page of pointers then
682 * protects 8TB.
683 */
684struct subpage_prot_table {
685 unsigned long maxaddr; /* only addresses < this are protected */
686 unsigned int **protptrs[(TASK_SIZE_USER64 >> 43)];
687 unsigned int *low_prot[4];
688};
689
690#define SBP_L1_BITS (PAGE_SHIFT - 2)
691#define SBP_L2_BITS (PAGE_SHIFT - 3)
692#define SBP_L1_COUNT (1 << SBP_L1_BITS)
693#define SBP_L2_COUNT (1 << SBP_L2_BITS)
694#define SBP_L2_SHIFT (PAGE_SHIFT + SBP_L1_BITS)
695#define SBP_L3_SHIFT (SBP_L2_SHIFT + SBP_L2_BITS)
696
697extern void subpage_prot_free(struct mm_struct *mm);
698#else
699static inline void subpage_prot_free(struct mm_struct *mm) {}
700#endif /* CONFIG_PPC_SUBPAGE_PROT */
701
702/*
703 * One bit per slice. We have lower slices which cover 256MB segments
704 * upto 4G range. That gets us 16 low slices. For the rest we track slices
705 * in 1TB size.
706 */
707struct slice_mask {
708 u64 low_slices;
709 DECLARE_BITMAP(high_slices, SLICE_NUM_HIGH);
710};
711
712struct hash_mm_context {
713 u16 user_psize; /* page size index */
714
715 /* SLB page size encodings*/
716 unsigned char low_slices_psize[LOW_SLICE_ARRAY_SZ];
717 unsigned char high_slices_psize[SLICE_ARRAY_SIZE];
718 unsigned long slb_addr_limit;
719#ifdef CONFIG_PPC_64K_PAGES
720 struct slice_mask mask_64k;
721#endif
722 struct slice_mask mask_4k;
723#ifdef CONFIG_HUGETLB_PAGE
724 struct slice_mask mask_16m;
725 struct slice_mask mask_16g;
726#endif
727
728#ifdef CONFIG_PPC_SUBPAGE_PROT
729 struct subpage_prot_table *spt;
730#endif /* CONFIG_PPC_SUBPAGE_PROT */
731};
732
733#if 0
734/*
735 * The code below is equivalent to this function for arguments
736 * < 2^VSID_BITS, which is all this should ever be called
737 * with. However gcc is not clever enough to compute the
738 * modulus (2^n-1) without a second multiply.
739 */
740#define vsid_scramble(protovsid, size) \
741 ((((protovsid) * VSID_MULTIPLIER_##size) % VSID_MODULUS_##size))
742
743/* simplified form avoiding mod operation */
744#define vsid_scramble(protovsid, size) \
745 ({ \
746 unsigned long x; \
747 x = (protovsid) * VSID_MULTIPLIER_##size; \
748 x = (x >> VSID_BITS_##size) + (x & VSID_MODULUS_##size); \
749 (x + ((x+1) >> VSID_BITS_##size)) & VSID_MODULUS_##size; \
750 })
751
752#else /* 1 */
753static inline unsigned long vsid_scramble(unsigned long protovsid,
754 unsigned long vsid_multiplier, int vsid_bits)
755{
756 unsigned long vsid;
757 unsigned long vsid_modulus = ((1UL << vsid_bits) - 1);
758 /*
759 * We have same multipler for both 256 and 1T segements now
760 */
761 vsid = protovsid * vsid_multiplier;
762 vsid = (vsid >> vsid_bits) + (vsid & vsid_modulus);
763 return (vsid + ((vsid + 1) >> vsid_bits)) & vsid_modulus;
764}
765
766#endif /* 1 */
767
768/* Returns the segment size indicator for a user address */
769static inline int user_segment_size(unsigned long addr)
770{
771 /* Use 1T segments if possible for addresses >= 1T */
772 if (addr >= (1UL << SID_SHIFT_1T))
773 return mmu_highuser_ssize;
774 return MMU_SEGSIZE_256M;
775}
776
777static inline unsigned long get_vsid(unsigned long context, unsigned long ea,
778 int ssize)
779{
780 unsigned long va_bits = VA_BITS;
781 unsigned long vsid_bits;
782 unsigned long protovsid;
783
784 /*
785 * Bad address. We return VSID 0 for that
786 */
787 if ((ea & EA_MASK) >= H_PGTABLE_RANGE)
788 return 0;
789
790 if (!mmu_has_feature(MMU_FTR_68_BIT_VA))
791 va_bits = 65;
792
793 if (ssize == MMU_SEGSIZE_256M) {
794 vsid_bits = va_bits - SID_SHIFT;
795 protovsid = (context << ESID_BITS) |
796 ((ea >> SID_SHIFT) & ESID_BITS_MASK);
797 return vsid_scramble(protovsid, VSID_MULTIPLIER_256M, vsid_bits);
798 }
799 /* 1T segment */
800 vsid_bits = va_bits - SID_SHIFT_1T;
801 protovsid = (context << ESID_BITS_1T) |
802 ((ea >> SID_SHIFT_1T) & ESID_BITS_1T_MASK);
803 return vsid_scramble(protovsid, VSID_MULTIPLIER_1T, vsid_bits);
804}
805
806/*
807 * For kernel space, we use context ids as
808 * below. Range is 512TB per context.
809 *
810 * 0x00001 - [ 0xc000000000000000 - 0xc001ffffffffffff]
811 * 0x00002 - [ 0xc002000000000000 - 0xc003ffffffffffff]
812 * 0x00003 - [ 0xc004000000000000 - 0xc005ffffffffffff]
813 * 0x00004 - [ 0xc006000000000000 - 0xc007ffffffffffff]
814 *
815 * vmap, IO, vmemap
816 *
817 * 0x00005 - [ 0xc008000000000000 - 0xc009ffffffffffff]
818 * 0x00006 - [ 0xc00a000000000000 - 0xc00bffffffffffff]
819 * 0x00007 - [ 0xc00c000000000000 - 0xc00dffffffffffff]
820 *
821 */
822static inline unsigned long get_kernel_context(unsigned long ea)
823{
824 unsigned long region_id = get_region_id(ea);
825 unsigned long ctx;
826 /*
827 * Depending on Kernel config, kernel region can have one context
828 * or more.
829 */
830 if (region_id == LINEAR_MAP_REGION_ID) {
831 /*
832 * We already verified ea to be not beyond the addr limit.
833 */
834 ctx = 1 + ((ea & EA_MASK) >> MAX_EA_BITS_PER_CONTEXT);
835 } else
836 ctx = region_id + MAX_KERNEL_CTX_CNT - 1;
837 return ctx;
838}
839
840/*
841 * This is only valid for addresses >= PAGE_OFFSET
842 */
843static inline unsigned long get_kernel_vsid(unsigned long ea, int ssize)
844{
845 unsigned long context;
846
847 if (!is_kernel_addr(ea))
848 return 0;
849
850 context = get_kernel_context(ea);
851 return get_vsid(context, ea, ssize);
852}
853
854unsigned htab_shift_for_mem_size(unsigned long mem_size);
855
856enum slb_index {
857 LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */
858 KSTACK_INDEX = 1, /* Kernel stack map */
859};
860
861#define slb_esid_mask(ssize) \
862 (((ssize) == MMU_SEGSIZE_256M) ? ESID_MASK : ESID_MASK_1T)
863
864static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
865 enum slb_index index)
866{
867 return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
868}
869
870static inline unsigned long __mk_vsid_data(unsigned long vsid, int ssize,
871 unsigned long flags)
872{
873 return (vsid << slb_vsid_shift(ssize)) | flags |
874 ((unsigned long)ssize << SLB_VSID_SSIZE_SHIFT);
875}
876
877static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
878 unsigned long flags)
879{
880 return __mk_vsid_data(get_kernel_vsid(ea, ssize), ssize, flags);
881}
882
883#endif /* __ASSEMBLER__ */
884#endif /* _ASM_POWERPC_BOOK3S_64_MMU_HASH_H_ */
885

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/arch/powerpc/include/asm/book3s/64/mmu-hash.h