| 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
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| 2 | /* |
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| 3 | * This file contains sleep low-level functions for PowerBook G3. |
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| 4 | * Copyright (C) 1999 Benjamin Herrenschmidt (benh@kernel.crashing.org) |
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| 5 | * and Paul Mackerras (paulus@samba.org). |
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| 6 | */ |
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| 7 | |
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| 8 | #include <asm/processor.h> |
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| 9 | #include <asm/page.h> |
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| 10 | #include <asm/ppc_asm.h> |
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| 11 | #include <asm/cputable.h> |
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| 12 | #include <asm/cache.h> |
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| 13 | #include <asm/thread_info.h> |
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| 14 | #include <asm/asm-offsets.h> |
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| 15 | #include <asm/mmu.h> |
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| 16 | #include <asm/feature-fixups.h> |
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| 17 | |
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| 18 | #define MAGIC 0x4c617273 /* 'Lars' */ |
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| 19 | |
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| 20 | /* |
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| 21 | * Structure for storing CPU registers on the stack. |
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| 22 | */ |
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| 23 | #define SL_SP 0 |
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| 24 | #define SL_PC 4 |
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| 25 | #define SL_MSR 8 |
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| 26 | #define SL_SDR1 0xc |
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| 27 | #define SL_SPRG0 0x10 /* 4 sprg's */ |
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| 28 | #define SL_DBAT0 0x20 |
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| 29 | #define SL_IBAT0 0x28 |
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| 30 | #define SL_DBAT1 0x30 |
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| 31 | #define SL_IBAT1 0x38 |
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| 32 | #define SL_DBAT2 0x40 |
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| 33 | #define SL_IBAT2 0x48 |
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| 34 | #define SL_DBAT3 0x50 |
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| 35 | #define SL_IBAT3 0x58 |
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| 36 | #define SL_DBAT4 0x60 |
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| 37 | #define SL_IBAT4 0x68 |
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| 38 | #define SL_DBAT5 0x70 |
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| 39 | #define SL_IBAT5 0x78 |
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| 40 | #define SL_DBAT6 0x80 |
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| 41 | #define SL_IBAT6 0x88 |
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| 42 | #define SL_DBAT7 0x90 |
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| 43 | #define SL_IBAT7 0x98 |
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| 44 | #define SL_TB 0xa0 |
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| 45 | #define SL_R2 0xa8 |
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| 46 | #define SL_CR 0xac |
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| 47 | #define SL_LR 0xb0 |
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| 48 | #define SL_R12 0xb4 /* r12 to r31 */ |
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| 49 | #define SL_SIZE (SL_R12 + 80) |
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| 50 | |
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| 51 | .section .text |
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| 52 | .align 5 |
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| 53 | |
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| 54 | #if defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ_PMAC) || \ |
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| 55 | (defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_PPC32)) |
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| 56 | |
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| 57 | /* This gets called by via-pmu.c late during the sleep process. |
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| 58 | * The PMU was already send the sleep command and will shut us down |
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| 59 | * soon. We need to save all that is needed and setup the wakeup |
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| 60 | * vector that will be called by the ROM on wakeup |
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| 61 | */ |
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| 62 | _GLOBAL(low_sleep_handler) |
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| 63 | #ifndef CONFIG_PPC_BOOK3S_32 |
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| 64 | blr |
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| 65 | #else |
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| 66 | mflr r0 |
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| 67 | lis r11,sleep_storage@ha |
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| 68 | addi r11,r11,sleep_storage@l |
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| 69 | stw r0,SL_LR(r11) |
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| 70 | mfcr r0 |
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| 71 | stw r0,SL_CR(r11) |
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| 72 | stw r1,SL_SP(r11) |
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| 73 | stw r2,SL_R2(r11) |
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| 74 | stmw r12,SL_R12(r11) |
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| 75 | |
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| 76 | /* Save MSR & SDR1 */ |
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| 77 | mfmsr r4 |
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| 78 | stw r4,SL_MSR(r11) |
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| 79 | mfsdr1 r4 |
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| 80 | stw r4,SL_SDR1(r11) |
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| 81 | |
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| 82 | /* Get a stable timebase and save it */ |
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| 83 | 1: mftbu r4 |
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| 84 | stw r4,SL_TB(r11) |
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| 85 | mftb r5 |
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| 86 | stw r5,SL_TB+4(r11) |
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| 87 | mftbu r3 |
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| 88 | cmpw r3,r4 |
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| 89 | bne 1b |
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| 90 | |
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| 91 | /* Save SPRGs */ |
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| 92 | mfsprg r4,0 |
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| 93 | stw r4,SL_SPRG0(r11) |
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| 94 | mfsprg r4,1 |
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| 95 | stw r4,SL_SPRG0+4(r11) |
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| 96 | mfsprg r4,2 |
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| 97 | stw r4,SL_SPRG0+8(r11) |
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| 98 | mfsprg r4,3 |
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| 99 | stw r4,SL_SPRG0+12(r11) |
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| 100 | |
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| 101 | /* Save BATs */ |
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| 102 | mfdbatu r4,0 |
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| 103 | stw r4,SL_DBAT0(r11) |
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| 104 | mfdbatl r4,0 |
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| 105 | stw r4,SL_DBAT0+4(r11) |
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| 106 | mfdbatu r4,1 |
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| 107 | stw r4,SL_DBAT1(r11) |
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| 108 | mfdbatl r4,1 |
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| 109 | stw r4,SL_DBAT1+4(r11) |
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| 110 | mfdbatu r4,2 |
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| 111 | stw r4,SL_DBAT2(r11) |
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| 112 | mfdbatl r4,2 |
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| 113 | stw r4,SL_DBAT2+4(r11) |
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| 114 | mfdbatu r4,3 |
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| 115 | stw r4,SL_DBAT3(r11) |
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| 116 | mfdbatl r4,3 |
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| 117 | stw r4,SL_DBAT3+4(r11) |
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| 118 | mfibatu r4,0 |
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| 119 | stw r4,SL_IBAT0(r11) |
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| 120 | mfibatl r4,0 |
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| 121 | stw r4,SL_IBAT0+4(r11) |
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| 122 | mfibatu r4,1 |
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| 123 | stw r4,SL_IBAT1(r11) |
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| 124 | mfibatl r4,1 |
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| 125 | stw r4,SL_IBAT1+4(r11) |
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| 126 | mfibatu r4,2 |
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| 127 | stw r4,SL_IBAT2(r11) |
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| 128 | mfibatl r4,2 |
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| 129 | stw r4,SL_IBAT2+4(r11) |
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| 130 | mfibatu r4,3 |
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| 131 | stw r4,SL_IBAT3(r11) |
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| 132 | mfibatl r4,3 |
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| 133 | stw r4,SL_IBAT3+4(r11) |
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| 134 | |
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| 135 | BEGIN_MMU_FTR_SECTION |
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| 136 | mfspr r4,SPRN_DBAT4U |
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| 137 | stw r4,SL_DBAT4(r11) |
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| 138 | mfspr r4,SPRN_DBAT4L |
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| 139 | stw r4,SL_DBAT4+4(r11) |
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| 140 | mfspr r4,SPRN_DBAT5U |
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| 141 | stw r4,SL_DBAT5(r11) |
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| 142 | mfspr r4,SPRN_DBAT5L |
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| 143 | stw r4,SL_DBAT5+4(r11) |
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| 144 | mfspr r4,SPRN_DBAT6U |
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| 145 | stw r4,SL_DBAT6(r11) |
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| 146 | mfspr r4,SPRN_DBAT6L |
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| 147 | stw r4,SL_DBAT6+4(r11) |
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| 148 | mfspr r4,SPRN_DBAT7U |
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| 149 | stw r4,SL_DBAT7(r11) |
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| 150 | mfspr r4,SPRN_DBAT7L |
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| 151 | stw r4,SL_DBAT7+4(r11) |
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| 152 | mfspr r4,SPRN_IBAT4U |
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| 153 | stw r4,SL_IBAT4(r11) |
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| 154 | mfspr r4,SPRN_IBAT4L |
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| 155 | stw r4,SL_IBAT4+4(r11) |
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| 156 | mfspr r4,SPRN_IBAT5U |
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| 157 | stw r4,SL_IBAT5(r11) |
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| 158 | mfspr r4,SPRN_IBAT5L |
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| 159 | stw r4,SL_IBAT5+4(r11) |
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| 160 | mfspr r4,SPRN_IBAT6U |
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| 161 | stw r4,SL_IBAT6(r11) |
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| 162 | mfspr r4,SPRN_IBAT6L |
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| 163 | stw r4,SL_IBAT6+4(r11) |
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| 164 | mfspr r4,SPRN_IBAT7U |
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| 165 | stw r4,SL_IBAT7(r11) |
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| 166 | mfspr r4,SPRN_IBAT7L |
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| 167 | stw r4,SL_IBAT7+4(r11) |
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| 168 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
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| 169 | |
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| 170 | /* Backup various CPU config stuffs */ |
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| 171 | bl __save_cpu_setup |
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| 172 | |
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| 173 | /* The ROM can wake us up via 2 different vectors: |
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| 174 | * - On wallstreet & lombard, we must write a magic |
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| 175 | * value 'Lars' at address 4 and a pointer to a |
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| 176 | * memory location containing the PC to resume from |
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| 177 | * at address 0. |
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| 178 | * - On Core99, we must store the wakeup vector at |
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| 179 | * address 0x80 and eventually its parameters |
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| 180 | * at address 0x84. I've have some trouble with those |
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| 181 | * parameters however and I no longer use them. |
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| 182 | */ |
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| 183 | lis r5,grackle_wake_up@ha |
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| 184 | addi r5,r5,grackle_wake_up@l |
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| 185 | tophys(r5,r5) |
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| 186 | stw r5,SL_PC(r11) |
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| 187 | lis r4,KERNELBASE@h |
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| 188 | tophys(r5,r11) |
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| 189 | addi r5,r5,SL_PC |
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| 190 | lis r6,MAGIC@ha |
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| 191 | addi r6,r6,MAGIC@l |
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| 192 | stw r5,0(r4) |
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| 193 | stw r6,4(r4) |
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| 194 | /* Setup stuffs at 0x80-0x84 for Core99 */ |
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| 195 | lis r3,core99_wake_up@ha |
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| 196 | addi r3,r3,core99_wake_up@l |
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| 197 | tophys(r3,r3) |
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| 198 | stw r3,0x80(r4) |
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| 199 | stw r5,0x84(r4) |
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| 200 | |
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| 201 | .globl low_cpu_offline_self |
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| 202 | low_cpu_offline_self: |
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| 203 | /* Flush & disable all caches */ |
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| 204 | bl flush_disable_caches |
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| 205 | |
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| 206 | /* Turn off data relocation. */ |
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| 207 | mfmsr r3 /* Save MSR in r7 */ |
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| 208 | rlwinm r3,r3,0,28,26 /* Turn off DR bit */ |
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| 209 | sync |
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| 210 | mtmsr r3 |
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| 211 | isync |
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| 212 | |
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| 213 | BEGIN_FTR_SECTION |
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| 214 | /* Flush any pending L2 data prefetches to work around HW bug */ |
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| 215 | sync |
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| 216 | lis r3,0xfff0 |
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| 217 | lwz r0,0(r3) /* perform cache-inhibited load to ROM */ |
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| 218 | sync /* (caches are disabled at this point) */ |
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| 219 | END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) |
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| 220 | |
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| 221 | /* |
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| 222 | * Set the HID0 and MSR for sleep. |
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| 223 | */ |
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| 224 | mfspr r2,SPRN_HID0 |
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| 225 | rlwinm r2,r2,0,10,7 /* clear doze, nap */ |
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| 226 | oris r2,r2,HID0_SLEEP@h |
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| 227 | sync |
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| 228 | isync |
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| 229 | mtspr SPRN_HID0,r2 |
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| 230 | sync |
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| 231 | |
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| 232 | /* This loop puts us back to sleep in case we have a spurrious |
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| 233 | * wakeup so that the host bridge properly stays asleep. The |
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| 234 | * CPU will be turned off, either after a known time (about 1 |
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| 235 | * second) on wallstreet & lombard, or as soon as the CPU enters |
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| 236 | * SLEEP mode on core99 |
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| 237 | */ |
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| 238 | mfmsr r2 |
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| 239 | oris r2,r2,MSR_POW@h |
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| 240 | 1: sync |
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| 241 | mtmsr r2 |
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| 242 | isync |
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| 243 | b 1b |
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| 244 | _ASM_NOKPROBE_SYMBOL(low_cpu_offline_self) |
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| 245 | /* |
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| 246 | * Here is the resume code. |
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| 247 | */ |
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| 248 | |
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| 249 | |
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| 250 | /* |
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| 251 | * Core99 machines resume here |
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| 252 | * r4 has the physical address of SL_PC(sp) (unused) |
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| 253 | */ |
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| 254 | _GLOBAL(core99_wake_up) |
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| 255 | /* Make sure HID0 no longer contains any sleep bit and that data cache |
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| 256 | * is disabled |
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| 257 | */ |
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| 258 | mfspr r3,SPRN_HID0 |
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| 259 | rlwinm r3,r3,0,11,7 /* clear SLEEP, NAP, DOZE bits */ |
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| 260 | rlwinm 3,r3,0,18,15 /* clear DCE, ICE */ |
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| 261 | mtspr SPRN_HID0,r3 |
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| 262 | sync |
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| 263 | isync |
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| 264 | |
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| 265 | /* sanitize MSR */ |
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| 266 | mfmsr r3 |
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| 267 | ori r3,r3,MSR_EE|MSR_IP |
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| 268 | xori r3,r3,MSR_EE|MSR_IP |
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| 269 | sync |
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| 270 | isync |
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| 271 | mtmsr r3 |
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| 272 | sync |
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| 273 | isync |
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| 274 | |
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| 275 | /* Recover sleep storage */ |
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| 276 | lis r3,sleep_storage@ha |
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| 277 | addi r3,r3,sleep_storage@l |
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| 278 | tophys(r3,r3) |
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| 279 | addi r1,r3,SL_PC |
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| 280 | |
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| 281 | /* Pass thru to older resume code ... */ |
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| 282 | _ASM_NOKPROBE_SYMBOL(core99_wake_up) |
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| 283 | /* |
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| 284 | * Here is the resume code for older machines. |
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| 285 | * r1 has the physical address of SL_PC(sp). |
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| 286 | */ |
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| 287 | |
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| 288 | grackle_wake_up: |
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| 289 | |
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| 290 | /* Restore the kernel's segment registers before |
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| 291 | * we do any r1 memory access as we are not sure they |
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| 292 | * are in a sane state above the first 256Mb region |
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| 293 | */ |
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| 294 | bl load_segment_registers |
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| 295 | sync |
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| 296 | isync |
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| 297 | |
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| 298 | subi r1,r1,SL_PC |
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| 299 | |
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| 300 | /* Restore various CPU config stuffs */ |
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| 301 | bl __restore_cpu_setup |
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| 302 | |
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| 303 | /* Make sure all FPRs have been initialized */ |
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| 304 | bl reloc_offset |
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| 305 | bl __init_fpu_registers |
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| 306 | |
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| 307 | /* Invalidate & enable L1 cache, we don't care about |
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| 308 | * whatever the ROM may have tried to write to memory |
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| 309 | */ |
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| 310 | bl __inval_enable_L1 |
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| 311 | |
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| 312 | /* Restore the BATs, and SDR1. Then we can turn on the MMU. */ |
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| 313 | lwz r4,SL_SDR1(r1) |
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| 314 | mtsdr1 r4 |
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| 315 | lwz r4,SL_SPRG0(r1) |
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| 316 | mtsprg 0,r4 |
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| 317 | lwz r4,SL_SPRG0+4(r1) |
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| 318 | mtsprg 1,r4 |
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| 319 | lwz r4,SL_SPRG0+8(r1) |
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| 320 | mtsprg 2,r4 |
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| 321 | lwz r4,SL_SPRG0+12(r1) |
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| 322 | mtsprg 3,r4 |
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| 323 | |
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| 324 | lwz r4,SL_DBAT0(r1) |
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| 325 | mtdbatu 0,r4 |
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| 326 | lwz r4,SL_DBAT0+4(r1) |
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| 327 | mtdbatl 0,r4 |
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| 328 | lwz r4,SL_DBAT1(r1) |
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| 329 | mtdbatu 1,r4 |
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| 330 | lwz r4,SL_DBAT1+4(r1) |
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| 331 | mtdbatl 1,r4 |
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| 332 | lwz r4,SL_DBAT2(r1) |
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| 333 | mtdbatu 2,r4 |
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| 334 | lwz r4,SL_DBAT2+4(r1) |
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| 335 | mtdbatl 2,r4 |
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| 336 | lwz r4,SL_DBAT3(r1) |
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| 337 | mtdbatu 3,r4 |
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| 338 | lwz r4,SL_DBAT3+4(r1) |
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| 339 | mtdbatl 3,r4 |
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| 340 | lwz r4,SL_IBAT0(r1) |
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| 341 | mtibatu 0,r4 |
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| 342 | lwz r4,SL_IBAT0+4(r1) |
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| 343 | mtibatl 0,r4 |
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| 344 | lwz r4,SL_IBAT1(r1) |
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| 345 | mtibatu 1,r4 |
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| 346 | lwz r4,SL_IBAT1+4(r1) |
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| 347 | mtibatl 1,r4 |
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| 348 | lwz r4,SL_IBAT2(r1) |
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| 349 | mtibatu 2,r4 |
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| 350 | lwz r4,SL_IBAT2+4(r1) |
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| 351 | mtibatl 2,r4 |
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| 352 | lwz r4,SL_IBAT3(r1) |
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| 353 | mtibatu 3,r4 |
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| 354 | lwz r4,SL_IBAT3+4(r1) |
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| 355 | mtibatl 3,r4 |
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| 356 | |
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| 357 | BEGIN_MMU_FTR_SECTION |
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| 358 | lwz r4,SL_DBAT4(r1) |
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| 359 | mtspr SPRN_DBAT4U,r4 |
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| 360 | lwz r4,SL_DBAT4+4(r1) |
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| 361 | mtspr SPRN_DBAT4L,r4 |
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| 362 | lwz r4,SL_DBAT5(r1) |
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| 363 | mtspr SPRN_DBAT5U,r4 |
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| 364 | lwz r4,SL_DBAT5+4(r1) |
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| 365 | mtspr SPRN_DBAT5L,r4 |
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| 366 | lwz r4,SL_DBAT6(r1) |
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| 367 | mtspr SPRN_DBAT6U,r4 |
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| 368 | lwz r4,SL_DBAT6+4(r1) |
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| 369 | mtspr SPRN_DBAT6L,r4 |
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| 370 | lwz r4,SL_DBAT7(r1) |
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| 371 | mtspr SPRN_DBAT7U,r4 |
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| 372 | lwz r4,SL_DBAT7+4(r1) |
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| 373 | mtspr SPRN_DBAT7L,r4 |
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| 374 | lwz r4,SL_IBAT4(r1) |
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| 375 | mtspr SPRN_IBAT4U,r4 |
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| 376 | lwz r4,SL_IBAT4+4(r1) |
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| 377 | mtspr SPRN_IBAT4L,r4 |
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| 378 | lwz r4,SL_IBAT5(r1) |
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| 379 | mtspr SPRN_IBAT5U,r4 |
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| 380 | lwz r4,SL_IBAT5+4(r1) |
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| 381 | mtspr SPRN_IBAT5L,r4 |
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| 382 | lwz r4,SL_IBAT6(r1) |
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| 383 | mtspr SPRN_IBAT6U,r4 |
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| 384 | lwz r4,SL_IBAT6+4(r1) |
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| 385 | mtspr SPRN_IBAT6L,r4 |
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| 386 | lwz r4,SL_IBAT7(r1) |
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| 387 | mtspr SPRN_IBAT7U,r4 |
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| 388 | lwz r4,SL_IBAT7+4(r1) |
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| 389 | mtspr SPRN_IBAT7L,r4 |
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| 390 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
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| 391 | |
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| 392 | /* Flush all TLBs */ |
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| 393 | lis r4,0x1000 |
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| 394 | 1: addic. r4,r4,-0x1000 |
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| 395 | tlbie r4 |
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| 396 | blt 1b |
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| 397 | sync |
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| 398 | |
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| 399 | /* Restore TB */ |
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| 400 | li r3,0 |
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| 401 | mttbl r3 |
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| 402 | lwz r3,SL_TB(r1) |
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| 403 | lwz r4,SL_TB+4(r1) |
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| 404 | mttbu r3 |
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| 405 | mttbl r4 |
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| 406 | |
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| 407 | /* Restore the callee-saved registers and return */ |
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| 408 | lwz r0,SL_CR(r1) |
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| 409 | mtcr r0 |
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| 410 | lwz r2,SL_R2(r1) |
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| 411 | lmw r12,SL_R12(r1) |
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| 412 | |
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| 413 | /* restore the MSR and SP and turn on the MMU and return */ |
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| 414 | lwz r3,SL_MSR(r1) |
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| 415 | lwz r4,SL_LR(r1) |
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| 416 | lwz r1,SL_SP(r1) |
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| 417 | mtsrr0 r4 |
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| 418 | mtsrr1 r3 |
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| 419 | sync |
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| 420 | isync |
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| 421 | rfi |
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| 422 | _ASM_NOKPROBE_SYMBOL(grackle_wake_up) |
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| 423 | |
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| 424 | #endif /* defined(CONFIG_PM) || defined(CONFIG_CPU_FREQ) */ |
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| 425 | |
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| 426 | .section .bss |
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| 427 | .balign L1_CACHE_BYTES |
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| 428 | sleep_storage: |
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| 429 | .space SL_SIZE |
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| 430 | .balign L1_CACHE_BYTES, 0 |
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| 431 | |
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| 432 | #endif /* CONFIG_PPC_BOOK3S_32 */ |
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| 433 | .section .text |
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| 434 | |
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