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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * S390 version
4 * Copyright IBM Corp. 1999, 2000
5 * Author(s): Hartmut Penner (hp@de.ibm.com)
6 * Ulrich Weigand (weigand@de.ibm.com)
7 * Martin Schwidefsky (schwidefsky@de.ibm.com)
8 *
9 * Derived from "include/asm-i386/pgtable.h"
10 */
11
12#ifndef _ASM_S390_PGTABLE_H
13#define _ASM_S390_PGTABLE_H
14
15#include <linux/sched.h>
16#include <linux/mm_types.h>
17#include <linux/cpufeature.h>
18#include <linux/page-flags.h>
19#include <linux/radix-tree.h>
20#include <linux/atomic.h>
21#include <asm/ctlreg.h>
22#include <asm/bug.h>
23#include <asm/page.h>
24#include <asm/uv.h>
25
26extern pgd_t swapper_pg_dir[];
27extern pgd_t invalid_pg_dir[];
28extern void paging_init(void);
29extern struct ctlreg s390_invalid_asce;
30
31enum {
32 PG_DIRECT_MAP_4K = 0,
33 PG_DIRECT_MAP_1M,
34 PG_DIRECT_MAP_2G,
35 PG_DIRECT_MAP_MAX
36};
37
38extern atomic_long_t direct_pages_count[PG_DIRECT_MAP_MAX];
39
40static inline void update_page_count(int level, long count)
41{
42 if (IS_ENABLED(CONFIG_PROC_FS))
43 atomic_long_add(count, &direct_pages_count[level]);
44}
45
46/*
47 * The S390 doesn't have any external MMU info: the kernel page
48 * tables contain all the necessary information.
49 */
50#define update_mmu_cache(vma, address, ptep) do { } while (0)
51#define update_mmu_cache_range(vmf, vma, addr, ptep, nr) do { } while (0)
52#define update_mmu_cache_pmd(vma, address, ptep) do { } while (0)
53
54/*
55 * ZERO_PAGE is a global shared page that is always zero; used
56 * for zero-mapped memory areas etc..
57 */
58
59extern unsigned long empty_zero_page;
60extern unsigned long zero_page_mask;
61
62#define ZERO_PAGE(vaddr) \
63 (virt_to_page((void *)(empty_zero_page + \
64 (((unsigned long)(vaddr)) &zero_page_mask))))
65#define __HAVE_COLOR_ZERO_PAGE
66
67/* TODO: s390 cannot support io_remap_pfn_range... */
68
69#define pte_ERROR(e) \
70 pr_err("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
71#define pmd_ERROR(e) \
72 pr_err("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
73#define pud_ERROR(e) \
74 pr_err("%s:%d: bad pud %016lx.\n", __FILE__, __LINE__, pud_val(e))
75#define p4d_ERROR(e) \
76 pr_err("%s:%d: bad p4d %016lx.\n", __FILE__, __LINE__, p4d_val(e))
77#define pgd_ERROR(e) \
78 pr_err("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
79
80/*
81 * The vmalloc and module area will always be on the topmost area of the
82 * kernel mapping. 512GB are reserved for vmalloc by default.
83 * At the top of the vmalloc area a 2GB area is reserved where modules
84 * will reside. That makes sure that inter module branches always
85 * happen without trampolines and in addition the placement within a
86 * 2GB frame is branch prediction unit friendly.
87 */
88extern unsigned long VMALLOC_START;
89extern unsigned long VMALLOC_END;
90#define VMALLOC_DEFAULT_SIZE ((512UL << 30) - MODULES_LEN)
91extern struct page *vmemmap;
92extern unsigned long vmemmap_size;
93
94extern unsigned long MODULES_VADDR;
95extern unsigned long MODULES_END;
96#define MODULES_VADDR MODULES_VADDR
97#define MODULES_END MODULES_END
98#define MODULES_LEN (1UL << 31)
99
100static inline int is_module_addr(void *addr)
101{
102 BUILD_BUG_ON(MODULES_LEN > (1UL << 31));
103 if (addr < (void *)MODULES_VADDR)
104 return 0;
105 if (addr > (void *)MODULES_END)
106 return 0;
107 return 1;
108}
109
110#ifdef CONFIG_KMSAN
111#define KMSAN_VMALLOC_SIZE (VMALLOC_END - VMALLOC_START)
112#define KMSAN_VMALLOC_SHADOW_START VMALLOC_END
113#define KMSAN_VMALLOC_SHADOW_END (KMSAN_VMALLOC_SHADOW_START + KMSAN_VMALLOC_SIZE)
114#define KMSAN_VMALLOC_ORIGIN_START KMSAN_VMALLOC_SHADOW_END
115#define KMSAN_VMALLOC_ORIGIN_END (KMSAN_VMALLOC_ORIGIN_START + KMSAN_VMALLOC_SIZE)
116#define KMSAN_MODULES_SHADOW_START KMSAN_VMALLOC_ORIGIN_END
117#define KMSAN_MODULES_SHADOW_END (KMSAN_MODULES_SHADOW_START + MODULES_LEN)
118#define KMSAN_MODULES_ORIGIN_START KMSAN_MODULES_SHADOW_END
119#define KMSAN_MODULES_ORIGIN_END (KMSAN_MODULES_ORIGIN_START + MODULES_LEN)
120#endif
121
122#ifdef CONFIG_RANDOMIZE_BASE
123#define KASLR_LEN (1UL << 31)
124#else
125#define KASLR_LEN 0UL
126#endif
127
128void setup_protection_map(void);
129
130/*
131 * A 64 bit pagetable entry of S390 has following format:
132 * | PFRA |0IPC| OS |
133 * 0000000000111111111122222222223333333333444444444455555555556666
134 * 0123456789012345678901234567890123456789012345678901234567890123
135 *
136 * I Page-Invalid Bit: Page is not available for address-translation
137 * P Page-Protection Bit: Store access not possible for page
138 * C Change-bit override: HW is not required to set change bit
139 *
140 * A 64 bit segmenttable entry of S390 has following format:
141 * | P-table origin | TT
142 * 0000000000111111111122222222223333333333444444444455555555556666
143 * 0123456789012345678901234567890123456789012345678901234567890123
144 *
145 * I Segment-Invalid Bit: Segment is not available for address-translation
146 * C Common-Segment Bit: Segment is not private (PoP 3-30)
147 * P Page-Protection Bit: Store access not possible for page
148 * TT Type 00
149 *
150 * A 64 bit region table entry of S390 has following format:
151 * | S-table origin | TF TTTL
152 * 0000000000111111111122222222223333333333444444444455555555556666
153 * 0123456789012345678901234567890123456789012345678901234567890123
154 *
155 * I Segment-Invalid Bit: Segment is not available for address-translation
156 * TT Type 01
157 * TF
158 * TL Table length
159 *
160 * The 64 bit regiontable origin of S390 has following format:
161 * | region table origon | DTTL
162 * 0000000000111111111122222222223333333333444444444455555555556666
163 * 0123456789012345678901234567890123456789012345678901234567890123
164 *
165 * X Space-Switch event:
166 * G Segment-Invalid Bit:
167 * P Private-Space Bit:
168 * S Storage-Alteration:
169 * R Real space
170 * TL Table-Length:
171 *
172 * A storage key has the following format:
173 * | ACC |F|R|C|0|
174 * 0 3 4 5 6 7
175 * ACC: access key
176 * F : fetch protection bit
177 * R : referenced bit
178 * C : changed bit
179 */
180
181/* Hardware bits in the page table entry */
182#define _PAGE_NOEXEC 0x100 /* HW no-execute bit */
183#define _PAGE_PROTECT 0x200 /* HW read-only bit */
184#define _PAGE_INVALID 0x400 /* HW invalid bit */
185#define _PAGE_LARGE 0x800 /* Bit to mark a large pte */
186
187/* Software bits in the page table entry */
188#define _PAGE_PRESENT 0x001 /* SW pte present bit */
189#define _PAGE_YOUNG 0x004 /* SW pte young bit */
190#define _PAGE_DIRTY 0x008 /* SW pte dirty bit */
191#define _PAGE_READ 0x010 /* SW pte read bit */
192#define _PAGE_WRITE 0x020 /* SW pte write bit */
193#define _PAGE_SPECIAL 0x040 /* SW associated with special page */
194#define _PAGE_UNUSED 0x080 /* SW bit for pgste usage state */
195
196#ifdef CONFIG_MEM_SOFT_DIRTY
197#define _PAGE_SOFT_DIRTY 0x002 /* SW pte soft dirty bit */
198#else
199#define _PAGE_SOFT_DIRTY 0x000
200#endif
201
202#define _PAGE_SW_BITS 0xffUL /* All SW bits */
203
204#define _PAGE_SWP_EXCLUSIVE _PAGE_LARGE /* SW pte exclusive swap bit */
205
206/* Set of bits not changed in pte_modify */
207#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_DIRTY | \
208 _PAGE_YOUNG | _PAGE_SOFT_DIRTY)
209
210/*
211 * Mask of bits that must not be changed with RDP. Allow only _PAGE_PROTECT
212 * HW bit and all SW bits.
213 */
214#define _PAGE_RDP_MASK ~(_PAGE_PROTECT | _PAGE_SW_BITS)
215
216/*
217 * handle_pte_fault uses pte_present and pte_none to find out the pte type
218 * WITHOUT holding the page table lock. The _PAGE_PRESENT bit is used to
219 * distinguish present from not-present ptes. It is changed only with the page
220 * table lock held.
221 *
222 * The following table gives the different possible bit combinations for
223 * the pte hardware and software bits in the last 12 bits of a pte
224 * (. unassigned bit, x don't care, t swap type):
225 *
226 * 842100000000
227 * 000084210000
228 * 000000008421
229 * .IR.uswrdy.p
230 * empty .10.00000000
231 * swap .11..ttttt.0
232 * prot-none, clean, old .11.xx0000.1
233 * prot-none, clean, young .11.xx0001.1
234 * prot-none, dirty, old .11.xx0010.1
235 * prot-none, dirty, young .11.xx0011.1
236 * read-only, clean, old .11.xx0100.1
237 * read-only, clean, young .01.xx0101.1
238 * read-only, dirty, old .11.xx0110.1
239 * read-only, dirty, young .01.xx0111.1
240 * read-write, clean, old .11.xx1100.1
241 * read-write, clean, young .01.xx1101.1
242 * read-write, dirty, old .10.xx1110.1
243 * read-write, dirty, young .00.xx1111.1
244 * HW-bits: R read-only, I invalid
245 * SW-bits: p present, y young, d dirty, r read, w write, s special,
246 * u unused, l large
247 *
248 * pte_none is true for the bit pattern .10.00000000, pte == 0x400
249 * pte_swap is true for the bit pattern .11..ooooo.0, (pte & 0x201) == 0x200
250 * pte_present is true for the bit pattern .xx.xxxxxx.1, (pte & 0x001) == 0x001
251 */
252
253/* Bits in the segment/region table address-space-control-element */
254#define _ASCE_ORIGIN ~0xfffUL/* region/segment table origin */
255#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
256#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
257#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
258#define _ASCE_REAL_SPACE 0x20 /* real space control */
259#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
260#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
261#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
262#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
263#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
264#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
265
266/* Bits in the region table entry */
267#define _REGION_ENTRY_ORIGIN ~0xfffUL/* region/segment table origin */
268#define _REGION_ENTRY_PROTECT 0x200 /* region protection bit */
269#define _REGION_ENTRY_NOEXEC 0x100 /* region no-execute bit */
270#define _REGION_ENTRY_OFFSET 0xc0 /* region table offset */
271#define _REGION_ENTRY_INVALID 0x20 /* invalid region table entry */
272#define _REGION_ENTRY_TYPE_MASK 0x0c /* region table type mask */
273#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
274#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
275#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
276#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
277
278#define _REGION1_ENTRY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_LENGTH)
279#define _REGION1_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R1 | _REGION_ENTRY_INVALID)
280#define _REGION2_ENTRY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_LENGTH)
281#define _REGION2_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R2 | _REGION_ENTRY_INVALID)
282#define _REGION3_ENTRY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_LENGTH | \
283 _REGION3_ENTRY_PRESENT)
284#define _REGION3_ENTRY_EMPTY (_REGION_ENTRY_TYPE_R3 | _REGION_ENTRY_INVALID)
285
286#define _REGION3_ENTRY_HARDWARE_BITS 0xfffffffffffff6ffUL
287#define _REGION3_ENTRY_HARDWARE_BITS_LARGE 0xffffffff8001073cUL
288#define _REGION3_ENTRY_ORIGIN_LARGE ~0x7fffffffUL /* large page address */
289#define _REGION3_ENTRY_DIRTY 0x2000 /* SW region dirty bit */
290#define _REGION3_ENTRY_YOUNG 0x1000 /* SW region young bit */
291#define _REGION3_ENTRY_COMM 0x0010 /* Common-Region, marks swap entry */
292#define _REGION3_ENTRY_LARGE 0x0400 /* RTTE-format control, large page */
293#define _REGION3_ENTRY_WRITE 0x8000 /* SW region write bit */
294#define _REGION3_ENTRY_READ 0x4000 /* SW region read bit */
295
296#ifdef CONFIG_MEM_SOFT_DIRTY
297#define _REGION3_ENTRY_SOFT_DIRTY 0x0002 /* SW region soft dirty bit */
298#else
299#define _REGION3_ENTRY_SOFT_DIRTY 0x0000 /* SW region soft dirty bit */
300#endif
301
302#define _REGION_ENTRY_BITS 0xfffffffffffff22fUL
303
304/*
305 * SW region present bit. For non-leaf region-third-table entries, bits 62-63
306 * indicate the TABLE LENGTH and both must be set to 1. But such entries
307 * would always be considered as present, so it is safe to use bit 63 as
308 * PRESENT bit for PUD.
309 */
310#define _REGION3_ENTRY_PRESENT 0x0001
311
312/* Bits in the segment table entry */
313#define _SEGMENT_ENTRY_BITS 0xfffffffffffffe3fUL
314#define _SEGMENT_ENTRY_HARDWARE_BITS 0xfffffffffffffe3cUL
315#define _SEGMENT_ENTRY_HARDWARE_BITS_LARGE 0xfffffffffff1073cUL
316#define _SEGMENT_ENTRY_ORIGIN_LARGE ~0xfffffUL /* large page address */
317#define _SEGMENT_ENTRY_ORIGIN ~0x7ffUL/* page table origin */
318#define _SEGMENT_ENTRY_PROTECT 0x200 /* segment protection bit */
319#define _SEGMENT_ENTRY_NOEXEC 0x100 /* segment no-execute bit */
320#define _SEGMENT_ENTRY_INVALID 0x20 /* invalid segment table entry */
321#define _SEGMENT_ENTRY_TYPE_MASK 0x0c /* segment table type mask */
322
323#define _SEGMENT_ENTRY (_SEGMENT_ENTRY_PRESENT)
324#define _SEGMENT_ENTRY_EMPTY (_SEGMENT_ENTRY_INVALID)
325
326#define _SEGMENT_ENTRY_DIRTY 0x2000 /* SW segment dirty bit */
327#define _SEGMENT_ENTRY_YOUNG 0x1000 /* SW segment young bit */
328
329#define _SEGMENT_ENTRY_COMM 0x0010 /* Common-Segment, marks swap entry */
330#define _SEGMENT_ENTRY_LARGE 0x0400 /* STE-format control, large page */
331#define _SEGMENT_ENTRY_WRITE 0x8000 /* SW segment write bit */
332#define _SEGMENT_ENTRY_READ 0x4000 /* SW segment read bit */
333
334#ifdef CONFIG_MEM_SOFT_DIRTY
335#define _SEGMENT_ENTRY_SOFT_DIRTY 0x0002 /* SW segment soft dirty bit */
336#else
337#define _SEGMENT_ENTRY_SOFT_DIRTY 0x0000 /* SW segment soft dirty bit */
338#endif
339
340#define _SEGMENT_ENTRY_PRESENT 0x0001 /* SW segment present bit */
341
342/* Common bits in region and segment table entries, for swap entries */
343#define _RST_ENTRY_COMM 0x0010 /* Common-Region/Segment, marks swap entry */
344#define _RST_ENTRY_INVALID 0x0020 /* invalid region/segment table entry */
345
346#define _CRST_ENTRIES 2048 /* number of region/segment table entries */
347#define _PAGE_ENTRIES 256 /* number of page table entries */
348
349#define _CRST_TABLE_SIZE (_CRST_ENTRIES * 8)
350#define _PAGE_TABLE_SIZE (_PAGE_ENTRIES * 8)
351
352#define _REGION1_SHIFT 53
353#define _REGION2_SHIFT 42
354#define _REGION3_SHIFT 31
355#define _SEGMENT_SHIFT 20
356
357#define _REGION1_INDEX (0x7ffUL << _REGION1_SHIFT)
358#define _REGION2_INDEX (0x7ffUL << _REGION2_SHIFT)
359#define _REGION3_INDEX (0x7ffUL << _REGION3_SHIFT)
360#define _SEGMENT_INDEX (0x7ffUL << _SEGMENT_SHIFT)
361#define _PAGE_INDEX (0xffUL << PAGE_SHIFT)
362
363#define _REGION1_SIZE (1UL << _REGION1_SHIFT)
364#define _REGION2_SIZE (1UL << _REGION2_SHIFT)
365#define _REGION3_SIZE (1UL << _REGION3_SHIFT)
366#define _SEGMENT_SIZE (1UL << _SEGMENT_SHIFT)
367
368#define _REGION1_MASK (~(_REGION1_SIZE - 1))
369#define _REGION2_MASK (~(_REGION2_SIZE - 1))
370#define _REGION3_MASK (~(_REGION3_SIZE - 1))
371#define _SEGMENT_MASK (~(_SEGMENT_SIZE - 1))
372
373#define PMD_SHIFT _SEGMENT_SHIFT
374#define PUD_SHIFT _REGION3_SHIFT
375#define P4D_SHIFT _REGION2_SHIFT
376#define PGDIR_SHIFT _REGION1_SHIFT
377
378#define PMD_SIZE _SEGMENT_SIZE
379#define PUD_SIZE _REGION3_SIZE
380#define P4D_SIZE _REGION2_SIZE
381#define PGDIR_SIZE _REGION1_SIZE
382
383#define PMD_MASK _SEGMENT_MASK
384#define PUD_MASK _REGION3_MASK
385#define P4D_MASK _REGION2_MASK
386#define PGDIR_MASK _REGION1_MASK
387
388#define PTRS_PER_PTE _PAGE_ENTRIES
389#define PTRS_PER_PMD _CRST_ENTRIES
390#define PTRS_PER_PUD _CRST_ENTRIES
391#define PTRS_PER_P4D _CRST_ENTRIES
392#define PTRS_PER_PGD _CRST_ENTRIES
393
394/*
395 * Segment table and region3 table entry encoding
396 * (R = read-only, I = invalid, y = young bit):
397 * dy..R...I...wr
398 * prot-none, clean, old 00..1...1...00
399 * prot-none, clean, young 01..1...1...00
400 * prot-none, dirty, old 10..1...1...00
401 * prot-none, dirty, young 11..1...1...00
402 * read-only, clean, old 00..1...1...01
403 * read-only, clean, young 01..1...0...01
404 * read-only, dirty, old 10..1...1...01
405 * read-only, dirty, young 11..1...0...01
406 * read-write, clean, old 00..1...1...11
407 * read-write, clean, young 01..1...0...11
408 * read-write, dirty, old 10..0...1...11
409 * read-write, dirty, young 11..0...0...11
410 * The segment table origin is used to distinguish empty (origin==0) from
411 * read-write, old segment table entries (origin!=0)
412 * HW-bits: R read-only, I invalid
413 * SW-bits: y young, d dirty, r read, w write
414 */
415
416/* Page status table bits for virtualization */
417#define PGSTE_ACC_BITS 0xf000000000000000UL
418#define PGSTE_FP_BIT 0x0800000000000000UL
419#define PGSTE_PCL_BIT 0x0080000000000000UL
420#define PGSTE_HR_BIT 0x0040000000000000UL
421#define PGSTE_HC_BIT 0x0020000000000000UL
422#define PGSTE_GR_BIT 0x0004000000000000UL
423#define PGSTE_GC_BIT 0x0002000000000000UL
424#define PGSTE_ST2_MASK 0x0000ffff00000000UL
425#define PGSTE_UC_BIT 0x0000000000008000UL /* user dirty (migration) */
426#define PGSTE_IN_BIT 0x0000000000004000UL /* IPTE notify bit */
427#define PGSTE_VSIE_BIT 0x0000000000002000UL /* ref'd in a shadow table */
428
429/* Guest Page State used for virtualization */
430#define _PGSTE_GPS_ZERO 0x0000000080000000UL
431#define _PGSTE_GPS_NODAT 0x0000000040000000UL
432#define _PGSTE_GPS_USAGE_MASK 0x0000000003000000UL
433#define _PGSTE_GPS_USAGE_STABLE 0x0000000000000000UL
434#define _PGSTE_GPS_USAGE_UNUSED 0x0000000001000000UL
435#define _PGSTE_GPS_USAGE_POT_VOLATILE 0x0000000002000000UL
436#define _PGSTE_GPS_USAGE_VOLATILE _PGSTE_GPS_USAGE_MASK
437
438/*
439 * A user page table pointer has the space-switch-event bit, the
440 * private-space-control bit and the storage-alteration-event-control
441 * bit set. A kernel page table pointer doesn't need them.
442 */
443#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
444 _ASCE_ALT_EVENT)
445
446/*
447 * Page protection definitions.
448 */
449#define __PAGE_NONE (_PAGE_PRESENT | _PAGE_INVALID | _PAGE_PROTECT)
450#define __PAGE_RO (_PAGE_PRESENT | _PAGE_READ | \
451 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
452#define __PAGE_RX (_PAGE_PRESENT | _PAGE_READ | \
453 _PAGE_INVALID | _PAGE_PROTECT)
454#define __PAGE_RW (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
455 _PAGE_NOEXEC | _PAGE_INVALID | _PAGE_PROTECT)
456#define __PAGE_RWX (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
457 _PAGE_INVALID | _PAGE_PROTECT)
458#define __PAGE_SHARED (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
459 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
460#define __PAGE_KERNEL (_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
461 _PAGE_YOUNG | _PAGE_DIRTY | _PAGE_NOEXEC)
462#define __PAGE_KERNEL_RO (_PAGE_PRESENT | _PAGE_READ | _PAGE_YOUNG | \
463 _PAGE_PROTECT | _PAGE_NOEXEC)
464
465extern unsigned long page_noexec_mask;
466
467#define __pgprot_page_mask(x) __pgprot((x) & page_noexec_mask)
468
469#define PAGE_NONE __pgprot_page_mask(__PAGE_NONE)
470#define PAGE_RO __pgprot_page_mask(__PAGE_RO)
471#define PAGE_RX __pgprot_page_mask(__PAGE_RX)
472#define PAGE_RW __pgprot_page_mask(__PAGE_RW)
473#define PAGE_RWX __pgprot_page_mask(__PAGE_RWX)
474#define PAGE_SHARED __pgprot_page_mask(__PAGE_SHARED)
475#define PAGE_KERNEL __pgprot_page_mask(__PAGE_KERNEL)
476#define PAGE_KERNEL_RO __pgprot_page_mask(__PAGE_KERNEL_RO)
477
478/*
479 * Segment entry (large page) protection definitions.
480 */
481#define __SEGMENT_NONE (_SEGMENT_ENTRY_PRESENT | \
482 _SEGMENT_ENTRY_INVALID | \
483 _SEGMENT_ENTRY_PROTECT)
484#define __SEGMENT_RO (_SEGMENT_ENTRY_PRESENT | \
485 _SEGMENT_ENTRY_PROTECT | \
486 _SEGMENT_ENTRY_READ | \
487 _SEGMENT_ENTRY_NOEXEC)
488#define __SEGMENT_RX (_SEGMENT_ENTRY_PRESENT | \
489 _SEGMENT_ENTRY_PROTECT | \
490 _SEGMENT_ENTRY_READ)
491#define __SEGMENT_RW (_SEGMENT_ENTRY_PRESENT | \
492 _SEGMENT_ENTRY_READ | \
493 _SEGMENT_ENTRY_WRITE | \
494 _SEGMENT_ENTRY_NOEXEC)
495#define __SEGMENT_RWX (_SEGMENT_ENTRY_PRESENT | \
496 _SEGMENT_ENTRY_READ | \
497 _SEGMENT_ENTRY_WRITE)
498#define __SEGMENT_KERNEL (_SEGMENT_ENTRY | \
499 _SEGMENT_ENTRY_LARGE | \
500 _SEGMENT_ENTRY_READ | \
501 _SEGMENT_ENTRY_WRITE | \
502 _SEGMENT_ENTRY_YOUNG | \
503 _SEGMENT_ENTRY_DIRTY | \
504 _SEGMENT_ENTRY_NOEXEC)
505#define __SEGMENT_KERNEL_RO (_SEGMENT_ENTRY | \
506 _SEGMENT_ENTRY_LARGE | \
507 _SEGMENT_ENTRY_READ | \
508 _SEGMENT_ENTRY_YOUNG | \
509 _SEGMENT_ENTRY_PROTECT | \
510 _SEGMENT_ENTRY_NOEXEC)
511
512extern unsigned long segment_noexec_mask;
513
514#define __pgprot_segment_mask(x) __pgprot((x) & segment_noexec_mask)
515
516#define SEGMENT_NONE __pgprot_segment_mask(__SEGMENT_NONE)
517#define SEGMENT_RO __pgprot_segment_mask(__SEGMENT_RO)
518#define SEGMENT_RX __pgprot_segment_mask(__SEGMENT_RX)
519#define SEGMENT_RW __pgprot_segment_mask(__SEGMENT_RW)
520#define SEGMENT_RWX __pgprot_segment_mask(__SEGMENT_RWX)
521#define SEGMENT_KERNEL __pgprot_segment_mask(__SEGMENT_KERNEL)
522#define SEGMENT_KERNEL_RO __pgprot_segment_mask(__SEGMENT_KERNEL_RO)
523
524/*
525 * Region3 entry (large page) protection definitions.
526 */
527
528#define __REGION3_KERNEL (_REGION_ENTRY_TYPE_R3 | \
529 _REGION3_ENTRY_PRESENT | \
530 _REGION3_ENTRY_LARGE | \
531 _REGION3_ENTRY_READ | \
532 _REGION3_ENTRY_WRITE | \
533 _REGION3_ENTRY_YOUNG | \
534 _REGION3_ENTRY_DIRTY | \
535 _REGION_ENTRY_NOEXEC)
536#define __REGION3_KERNEL_RO (_REGION_ENTRY_TYPE_R3 | \
537 _REGION3_ENTRY_PRESENT | \
538 _REGION3_ENTRY_LARGE | \
539 _REGION3_ENTRY_READ | \
540 _REGION3_ENTRY_YOUNG | \
541 _REGION_ENTRY_PROTECT | \
542 _REGION_ENTRY_NOEXEC)
543
544extern unsigned long region_noexec_mask;
545
546#define __pgprot_region_mask(x) __pgprot((x) & region_noexec_mask)
547
548#define REGION3_KERNEL __pgprot_region_mask(__REGION3_KERNEL)
549#define REGION3_KERNEL_RO __pgprot_region_mask(__REGION3_KERNEL_RO)
550
551static inline bool mm_p4d_folded(struct mm_struct *mm)
552{
553 return mm->context.asce_limit <= _REGION1_SIZE;
554}
555#define mm_p4d_folded(mm) mm_p4d_folded(mm)
556
557static inline bool mm_pud_folded(struct mm_struct *mm)
558{
559 return mm->context.asce_limit <= _REGION2_SIZE;
560}
561#define mm_pud_folded(mm) mm_pud_folded(mm)
562
563static inline bool mm_pmd_folded(struct mm_struct *mm)
564{
565 return mm->context.asce_limit <= _REGION3_SIZE;
566}
567#define mm_pmd_folded(mm) mm_pmd_folded(mm)
568
569static inline int mm_has_pgste(struct mm_struct *mm)
570{
571#ifdef CONFIG_PGSTE
572 if (unlikely(mm->context.has_pgste))
573 return 1;
574#endif
575 return 0;
576}
577
578static inline int mm_is_protected(struct mm_struct *mm)
579{
580#ifdef CONFIG_PGSTE
581 if (unlikely(atomic_read(&mm->context.protected_count)))
582 return 1;
583#endif
584 return 0;
585}
586
587static inline pgste_t clear_pgste_bit(pgste_t pgste, unsigned long mask)
588{
589 return __pgste(pgste_val(pgste) & ~mask);
590}
591
592static inline pgste_t set_pgste_bit(pgste_t pgste, unsigned long mask)
593{
594 return __pgste(pgste_val(pgste) | mask);
595}
596
597static inline pte_t clear_pte_bit(pte_t pte, pgprot_t prot)
598{
599 return __pte(pte_val(pte) & ~pgprot_val(prot));
600}
601
602static inline pte_t set_pte_bit(pte_t pte, pgprot_t prot)
603{
604 return __pte(pte_val(pte) | pgprot_val(prot));
605}
606
607static inline pmd_t clear_pmd_bit(pmd_t pmd, pgprot_t prot)
608{
609 return __pmd(pmd_val(pmd) & ~pgprot_val(prot));
610}
611
612static inline pmd_t set_pmd_bit(pmd_t pmd, pgprot_t prot)
613{
614 return __pmd(pmd_val(pmd) | pgprot_val(prot));
615}
616
617static inline pud_t clear_pud_bit(pud_t pud, pgprot_t prot)
618{
619 return __pud(pud_val(pud) & ~pgprot_val(prot));
620}
621
622static inline pud_t set_pud_bit(pud_t pud, pgprot_t prot)
623{
624 return __pud(pud_val(pud) | pgprot_val(prot));
625}
626
627/*
628 * As soon as the guest uses storage keys or enables PV, we deduplicate all
629 * mapped shared zeropages and prevent new shared zeropages from getting
630 * mapped.
631 */
632#define mm_forbids_zeropage mm_forbids_zeropage
633static inline int mm_forbids_zeropage(struct mm_struct *mm)
634{
635#ifdef CONFIG_PGSTE
636 if (!mm->context.allow_cow_sharing)
637 return 1;
638#endif
639 return 0;
640}
641
642static inline int mm_uses_skeys(struct mm_struct *mm)
643{
644#ifdef CONFIG_PGSTE
645 if (mm->context.uses_skeys)
646 return 1;
647#endif
648 return 0;
649}
650
651/**
652 * cspg() - Compare and Swap and Purge (CSPG)
653 * @ptr: Pointer to the value to be exchanged
654 * @old: The expected old value
655 * @new: The new value
656 *
657 * Return: True if compare and swap was successful, otherwise false.
658 */
659static inline bool cspg(unsigned long *ptr, unsigned long old, unsigned long new)
660{
661 union register_pair r1 = { .even = old, .odd = new, };
662 unsigned long address = (unsigned long)ptr | 1;
663
664 asm volatile(
665 " cspg %[r1],%[address]"
666 : [r1] "+&d" (r1.pair), "+m" (*ptr)
667 : [address] "d" (address)
668 : "cc");
669 return old == r1.even;
670}
671
672#define CRDTE_DTT_PAGE 0x00UL
673#define CRDTE_DTT_SEGMENT 0x10UL
674#define CRDTE_DTT_REGION3 0x14UL
675#define CRDTE_DTT_REGION2 0x18UL
676#define CRDTE_DTT_REGION1 0x1cUL
677
678/**
679 * crdte() - Compare and Replace DAT Table Entry
680 * @old: The expected old value
681 * @new: The new value
682 * @table: Pointer to the value to be exchanged
683 * @dtt: Table type of the table to be exchanged
684 * @address: The address mapped by the entry to be replaced
685 * @asce: The ASCE of this entry
686 *
687 * Return: True if compare and replace was successful, otherwise false.
688 */
689static inline bool crdte(unsigned long old, unsigned long new,
690 unsigned long *table, unsigned long dtt,
691 unsigned long address, unsigned long asce)
692{
693 union register_pair r1 = { .even = old, .odd = new, };
694 union register_pair r2 = { .even = __pa(table) | dtt, .odd = address, };
695
696 asm volatile(".insn rrf,0xb98f0000,%[r1],%[r2],%[asce],0"
697 : [r1] "+&d" (r1.pair)
698 : [r2] "d" (r2.pair), [asce] "a" (asce)
699 : "memory", "cc");
700 return old == r1.even;
701}
702
703/*
704 * pgd/p4d/pud/pmd/pte query functions
705 */
706static inline int pgd_folded(pgd_t pgd)
707{
708 return (pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1;
709}
710
711static inline int pgd_present(pgd_t pgd)
712{
713 if (pgd_folded(pgd))
714 return 1;
715 return (pgd_val(pgd) & _REGION_ENTRY_ORIGIN) != 0UL;
716}
717
718static inline int pgd_none(pgd_t pgd)
719{
720 if (pgd_folded(pgd))
721 return 0;
722 return (pgd_val(pgd) & _REGION_ENTRY_INVALID) != 0UL;
723}
724
725static inline int pgd_bad(pgd_t pgd)
726{
727 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R1)
728 return 0;
729 return (pgd_val(pgd) & ~_REGION_ENTRY_BITS) != 0;
730}
731
732static inline unsigned long pgd_pfn(pgd_t pgd)
733{
734 unsigned long origin_mask;
735
736 origin_mask = _REGION_ENTRY_ORIGIN;
737 return (pgd_val(pgd) & origin_mask) >> PAGE_SHIFT;
738}
739
740static inline int p4d_folded(p4d_t p4d)
741{
742 return (p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R2;
743}
744
745static inline int p4d_present(p4d_t p4d)
746{
747 if (p4d_folded(p4d))
748 return 1;
749 return (p4d_val(p4d) & _REGION_ENTRY_ORIGIN) != 0UL;
750}
751
752static inline int p4d_none(p4d_t p4d)
753{
754 if (p4d_folded(p4d))
755 return 0;
756 return p4d_val(p4d) == _REGION2_ENTRY_EMPTY;
757}
758
759static inline unsigned long p4d_pfn(p4d_t p4d)
760{
761 unsigned long origin_mask;
762
763 origin_mask = _REGION_ENTRY_ORIGIN;
764 return (p4d_val(p4d) & origin_mask) >> PAGE_SHIFT;
765}
766
767static inline int pud_folded(pud_t pud)
768{
769 return (pud_val(pud) & _REGION_ENTRY_TYPE_MASK) < _REGION_ENTRY_TYPE_R3;
770}
771
772static inline int pud_present(pud_t pud)
773{
774 if (pud_folded(pud))
775 return 1;
776 return (pud_val(pud) & _REGION3_ENTRY_PRESENT) != 0;
777}
778
779static inline int pud_none(pud_t pud)
780{
781 if (pud_folded(pud))
782 return 0;
783 return pud_val(pud) == _REGION3_ENTRY_EMPTY;
784}
785
786#define pud_leaf pud_leaf
787static inline bool pud_leaf(pud_t pud)
788{
789 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) != _REGION_ENTRY_TYPE_R3)
790 return 0;
791 return (pud_present(pud) && (pud_val(pud) & _REGION3_ENTRY_LARGE) != 0);
792}
793
794static inline int pmd_present(pmd_t pmd)
795{
796 return (pmd_val(pmd) & _SEGMENT_ENTRY_PRESENT) != 0;
797}
798
799#define pmd_leaf pmd_leaf
800static inline bool pmd_leaf(pmd_t pmd)
801{
802 return (pmd_present(pmd) && (pmd_val(pmd) & _SEGMENT_ENTRY_LARGE) != 0);
803}
804
805static inline int pmd_bad(pmd_t pmd)
806{
807 if ((pmd_val(pmd) & _SEGMENT_ENTRY_TYPE_MASK) > 0 || pmd_leaf(pmd))
808 return 1;
809 return (pmd_val(pmd) & ~_SEGMENT_ENTRY_BITS) != 0;
810}
811
812static inline int pud_bad(pud_t pud)
813{
814 unsigned long type = pud_val(pud) & _REGION_ENTRY_TYPE_MASK;
815
816 if (type > _REGION_ENTRY_TYPE_R3 || pud_leaf(pud))
817 return 1;
818 if (type < _REGION_ENTRY_TYPE_R3)
819 return 0;
820 return (pud_val(pud) & ~_REGION_ENTRY_BITS) != 0;
821}
822
823static inline int p4d_bad(p4d_t p4d)
824{
825 unsigned long type = p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK;
826
827 if (type > _REGION_ENTRY_TYPE_R2)
828 return 1;
829 if (type < _REGION_ENTRY_TYPE_R2)
830 return 0;
831 return (p4d_val(p4d) & ~_REGION_ENTRY_BITS) != 0;
832}
833
834static inline int pmd_none(pmd_t pmd)
835{
836 return pmd_val(pmd) == _SEGMENT_ENTRY_EMPTY;
837}
838
839#define pmd_write pmd_write
840static inline int pmd_write(pmd_t pmd)
841{
842 return (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE) != 0;
843}
844
845#define pud_write pud_write
846static inline int pud_write(pud_t pud)
847{
848 return (pud_val(pud) & _REGION3_ENTRY_WRITE) != 0;
849}
850
851#define pmd_dirty pmd_dirty
852static inline int pmd_dirty(pmd_t pmd)
853{
854 return (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY) != 0;
855}
856
857#define pmd_young pmd_young
858static inline int pmd_young(pmd_t pmd)
859{
860 return (pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG) != 0;
861}
862
863static inline int pte_present(pte_t pte)
864{
865 /* Bit pattern: (pte & 0x001) == 0x001 */
866 return (pte_val(pte) & _PAGE_PRESENT) != 0;
867}
868
869static inline int pte_none(pte_t pte)
870{
871 /* Bit pattern: pte == 0x400 */
872 return pte_val(pte) == _PAGE_INVALID;
873}
874
875static inline int pte_swap(pte_t pte)
876{
877 /* Bit pattern: (pte & 0x201) == 0x200 */
878 return (pte_val(pte) & (_PAGE_PROTECT | _PAGE_PRESENT))
879 == _PAGE_PROTECT;
880}
881
882static inline int pte_special(pte_t pte)
883{
884 return (pte_val(pte) & _PAGE_SPECIAL);
885}
886
887#define __HAVE_ARCH_PTE_SAME
888static inline int pte_same(pte_t a, pte_t b)
889{
890 return pte_val(a) == pte_val(b);
891}
892
893#ifdef CONFIG_NUMA_BALANCING
894static inline int pte_protnone(pte_t pte)
895{
896 return pte_present(pte) && !(pte_val(pte) & _PAGE_READ);
897}
898
899static inline int pmd_protnone(pmd_t pmd)
900{
901 /* pmd_leaf(pmd) implies pmd_present(pmd) */
902 return pmd_leaf(pmd) && !(pmd_val(pmd) & _SEGMENT_ENTRY_READ);
903}
904#endif
905
906static inline bool pte_swp_exclusive(pte_t pte)
907{
908 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
909}
910
911static inline pte_t pte_swp_mkexclusive(pte_t pte)
912{
913 return set_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
914}
915
916static inline pte_t pte_swp_clear_exclusive(pte_t pte)
917{
918 return clear_pte_bit(pte, __pgprot(_PAGE_SWP_EXCLUSIVE));
919}
920
921static inline int pte_soft_dirty(pte_t pte)
922{
923 return pte_val(pte) & _PAGE_SOFT_DIRTY;
924}
925#define pte_swp_soft_dirty pte_soft_dirty
926
927static inline pte_t pte_mksoft_dirty(pte_t pte)
928{
929 return set_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
930}
931#define pte_swp_mksoft_dirty pte_mksoft_dirty
932
933static inline pte_t pte_clear_soft_dirty(pte_t pte)
934{
935 return clear_pte_bit(pte, __pgprot(_PAGE_SOFT_DIRTY));
936}
937#define pte_swp_clear_soft_dirty pte_clear_soft_dirty
938
939static inline int pmd_soft_dirty(pmd_t pmd)
940{
941 return pmd_val(pmd) & _SEGMENT_ENTRY_SOFT_DIRTY;
942}
943
944static inline pmd_t pmd_mksoft_dirty(pmd_t pmd)
945{
946 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
947}
948
949static inline pmd_t pmd_clear_soft_dirty(pmd_t pmd)
950{
951 return clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_SOFT_DIRTY));
952}
953
954#ifdef CONFIG_ARCH_ENABLE_THP_MIGRATION
955#define pmd_swp_soft_dirty(pmd) pmd_soft_dirty(pmd)
956#define pmd_swp_mksoft_dirty(pmd) pmd_mksoft_dirty(pmd)
957#define pmd_swp_clear_soft_dirty(pmd) pmd_clear_soft_dirty(pmd)
958#endif
959
960/*
961 * query functions pte_write/pte_dirty/pte_young only work if
962 * pte_present() is true. Undefined behaviour if not..
963 */
964static inline int pte_write(pte_t pte)
965{
966 return (pte_val(pte) & _PAGE_WRITE) != 0;
967}
968
969static inline int pte_dirty(pte_t pte)
970{
971 return (pte_val(pte) & _PAGE_DIRTY) != 0;
972}
973
974static inline int pte_young(pte_t pte)
975{
976 return (pte_val(pte) & _PAGE_YOUNG) != 0;
977}
978
979#define __HAVE_ARCH_PTE_UNUSED
980static inline int pte_unused(pte_t pte)
981{
982 return pte_val(pte) & _PAGE_UNUSED;
983}
984
985/*
986 * Extract the pgprot value from the given pte while at the same time making it
987 * usable for kernel address space mappings where fault driven dirty and
988 * young/old accounting is not supported, i.e _PAGE_PROTECT and _PAGE_INVALID
989 * must not be set.
990 */
991#define pte_pgprot pte_pgprot
992static inline pgprot_t pte_pgprot(pte_t pte)
993{
994 unsigned long pte_flags = pte_val(pte) & _PAGE_CHG_MASK;
995
996 if (pte_write(pte))
997 pte_flags |= pgprot_val(PAGE_KERNEL);
998 else
999 pte_flags |= pgprot_val(PAGE_KERNEL_RO);
1000 pte_flags |= pte_val(pte) & mio_wb_bit_mask;
1001
1002 return __pgprot(pte_flags);
1003}
1004
1005/*
1006 * pgd/pmd/pte modification functions
1007 */
1008
1009static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
1010{
1011 WRITE_ONCE(*pgdp, pgd);
1012}
1013
1014static inline void set_p4d(p4d_t *p4dp, p4d_t p4d)
1015{
1016 WRITE_ONCE(*p4dp, p4d);
1017}
1018
1019static inline void set_pud(pud_t *pudp, pud_t pud)
1020{
1021 WRITE_ONCE(*pudp, pud);
1022}
1023
1024static inline void set_pmd(pmd_t *pmdp, pmd_t pmd)
1025{
1026 WRITE_ONCE(*pmdp, pmd);
1027}
1028
1029static inline void set_pte(pte_t *ptep, pte_t pte)
1030{
1031 WRITE_ONCE(*ptep, pte);
1032}
1033
1034static inline void pgd_clear(pgd_t *pgd)
1035{
1036 if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R1)
1037 set_pgd(pgd, __pgd(_REGION1_ENTRY_EMPTY));
1038}
1039
1040static inline void p4d_clear(p4d_t *p4d)
1041{
1042 if ((p4d_val(*p4d) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
1043 set_p4d(p4d, __p4d(_REGION2_ENTRY_EMPTY));
1044}
1045
1046static inline void pud_clear(pud_t *pud)
1047{
1048 if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
1049 set_pud(pud, __pud(_REGION3_ENTRY_EMPTY));
1050}
1051
1052static inline void pmd_clear(pmd_t *pmdp)
1053{
1054 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1055}
1056
1057static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
1058{
1059 set_pte(ptep, __pte(_PAGE_INVALID));
1060}
1061
1062/*
1063 * The following pte modification functions only work if
1064 * pte_present() is true. Undefined behaviour if not..
1065 */
1066static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1067{
1068 pte = clear_pte_bit(pte, __pgprot(~_PAGE_CHG_MASK));
1069 pte = set_pte_bit(pte, newprot);
1070 /*
1071 * newprot for PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX
1072 * has the invalid bit set, clear it again for readable, young pages
1073 */
1074 if ((pte_val(pte) & _PAGE_YOUNG) && (pte_val(pte) & _PAGE_READ))
1075 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
1076 /*
1077 * newprot for PAGE_RO, PAGE_RX, PAGE_RW and PAGE_RWX has the page
1078 * protection bit set, clear it again for writable, dirty pages
1079 */
1080 if ((pte_val(pte) & _PAGE_DIRTY) && (pte_val(pte) & _PAGE_WRITE))
1081 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1082 return pte;
1083}
1084
1085static inline pte_t pte_wrprotect(pte_t pte)
1086{
1087 pte = clear_pte_bit(pte, __pgprot(_PAGE_WRITE));
1088 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1089}
1090
1091static inline pte_t pte_mkwrite_novma(pte_t pte)
1092{
1093 pte = set_pte_bit(pte, __pgprot(_PAGE_WRITE));
1094 if (pte_val(pte) & _PAGE_DIRTY)
1095 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1096 return pte;
1097}
1098
1099static inline pte_t pte_mkclean(pte_t pte)
1100{
1101 pte = clear_pte_bit(pte, __pgprot(_PAGE_DIRTY));
1102 return set_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1103}
1104
1105static inline pte_t pte_mkdirty(pte_t pte)
1106{
1107 pte = set_pte_bit(pte, __pgprot(_PAGE_DIRTY | _PAGE_SOFT_DIRTY));
1108 if (pte_val(pte) & _PAGE_WRITE)
1109 pte = clear_pte_bit(pte, __pgprot(_PAGE_PROTECT));
1110 return pte;
1111}
1112
1113static inline pte_t pte_mkold(pte_t pte)
1114{
1115 pte = clear_pte_bit(pte, __pgprot(_PAGE_YOUNG));
1116 return set_pte_bit(pte, __pgprot(_PAGE_INVALID));
1117}
1118
1119static inline pte_t pte_mkyoung(pte_t pte)
1120{
1121 pte = set_pte_bit(pte, __pgprot(_PAGE_YOUNG));
1122 if (pte_val(pte) & _PAGE_READ)
1123 pte = clear_pte_bit(pte, __pgprot(_PAGE_INVALID));
1124 return pte;
1125}
1126
1127static inline pte_t pte_mkspecial(pte_t pte)
1128{
1129 return set_pte_bit(pte, __pgprot(_PAGE_SPECIAL));
1130}
1131
1132#ifdef CONFIG_HUGETLB_PAGE
1133static inline pte_t pte_mkhuge(pte_t pte)
1134{
1135 return set_pte_bit(pte, __pgprot(_PAGE_LARGE));
1136}
1137#endif
1138
1139#define IPTE_GLOBAL 0
1140#define IPTE_LOCAL 1
1141
1142#define IPTE_NODAT 0x400
1143#define IPTE_GUEST_ASCE 0x800
1144
1145static __always_inline void __ptep_rdp(unsigned long addr, pte_t *ptep, int local)
1146{
1147 unsigned long pto;
1148
1149 pto = __pa(ptep) & ~(PTRS_PER_PTE * sizeof(pte_t) - 1);
1150 asm volatile(".insn rrf,0xb98b0000,%[r1],%[r2],%%r0,%[m4]"
1151 : "+m" (*ptep)
1152 : [r1] "a" (pto), [r2] "a" (addr & PAGE_MASK),
1153 [m4] "i" (local));
1154}
1155
1156static __always_inline void __ptep_ipte(unsigned long address, pte_t *ptep,
1157 unsigned long opt, unsigned long asce,
1158 int local)
1159{
1160 unsigned long pto = __pa(ptep);
1161
1162 if (__builtin_constant_p(opt) && opt == 0) {
1163 /* Invalidation + TLB flush for the pte */
1164 asm volatile(
1165 " ipte %[r1],%[r2],0,%[m4]"
1166 : "+m" (*ptep) : [r1] "a" (pto), [r2] "a" (address),
1167 [m4] "i" (local));
1168 return;
1169 }
1170
1171 /* Invalidate ptes with options + TLB flush of the ptes */
1172 opt = opt | (asce & _ASCE_ORIGIN);
1173 asm volatile(
1174 " ipte %[r1],%[r2],%[r3],%[m4]"
1175 : [r2] "+a" (address), [r3] "+a" (opt)
1176 : [r1] "a" (pto), [m4] "i" (local) : "memory");
1177}
1178
1179static __always_inline void __ptep_ipte_range(unsigned long address, int nr,
1180 pte_t *ptep, int local)
1181{
1182 unsigned long pto = __pa(ptep);
1183
1184 /* Invalidate a range of ptes + TLB flush of the ptes */
1185 do {
1186 asm volatile(
1187 " ipte %[r1],%[r2],%[r3],%[m4]"
1188 : [r2] "+a" (address), [r3] "+a" (nr)
1189 : [r1] "a" (pto), [m4] "i" (local) : "memory");
1190 } while (nr != 255);
1191}
1192
1193/*
1194 * This is hard to understand. ptep_get_and_clear and ptep_clear_flush
1195 * both clear the TLB for the unmapped pte. The reason is that
1196 * ptep_get_and_clear is used in common code (e.g. change_pte_range)
1197 * to modify an active pte. The sequence is
1198 * 1) ptep_get_and_clear
1199 * 2) set_pte_at
1200 * 3) flush_tlb_range
1201 * On s390 the tlb needs to get flushed with the modification of the pte
1202 * if the pte is active. The only way how this can be implemented is to
1203 * have ptep_get_and_clear do the tlb flush. In exchange flush_tlb_range
1204 * is a nop.
1205 */
1206pte_t ptep_xchg_direct(struct mm_struct *, unsigned long, pte_t *, pte_t);
1207pte_t ptep_xchg_lazy(struct mm_struct *, unsigned long, pte_t *, pte_t);
1208
1209#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
1210static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
1211 unsigned long addr, pte_t *ptep)
1212{
1213 pte_t pte = *ptep;
1214
1215 pte = ptep_xchg_direct(vma->vm_mm, addr, ptep, pte_mkold(pte));
1216 return pte_young(pte);
1217}
1218
1219#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
1220static inline int ptep_clear_flush_young(struct vm_area_struct *vma,
1221 unsigned long address, pte_t *ptep)
1222{
1223 return ptep_test_and_clear_young(vma, address, ptep);
1224}
1225
1226#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
1227static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
1228 unsigned long addr, pte_t *ptep)
1229{
1230 pte_t res;
1231
1232 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
1233 /* At this point the reference through the mapping is still present */
1234 if (mm_is_protected(mm) && pte_present(res))
1235 uv_convert_from_secure_pte(res);
1236 return res;
1237}
1238
1239#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
1240pte_t ptep_modify_prot_start(struct vm_area_struct *, unsigned long, pte_t *);
1241void ptep_modify_prot_commit(struct vm_area_struct *, unsigned long,
1242 pte_t *, pte_t, pte_t);
1243
1244#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
1245static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
1246 unsigned long addr, pte_t *ptep)
1247{
1248 pte_t res;
1249
1250 res = ptep_xchg_direct(vma->vm_mm, addr, ptep, __pte(_PAGE_INVALID));
1251 /* At this point the reference through the mapping is still present */
1252 if (mm_is_protected(vma->vm_mm) && pte_present(res))
1253 uv_convert_from_secure_pte(res);
1254 return res;
1255}
1256
1257/*
1258 * The batched pte unmap code uses ptep_get_and_clear_full to clear the
1259 * ptes. Here an optimization is possible. tlb_gather_mmu flushes all
1260 * tlbs of an mm if it can guarantee that the ptes of the mm_struct
1261 * cannot be accessed while the batched unmap is running. In this case
1262 * full==1 and a simple pte_clear is enough. See tlb.h.
1263 */
1264#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
1265static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
1266 unsigned long addr,
1267 pte_t *ptep, int full)
1268{
1269 pte_t res;
1270
1271 if (full) {
1272 res = *ptep;
1273 set_pte(ptep, __pte(_PAGE_INVALID));
1274 } else {
1275 res = ptep_xchg_lazy(mm, addr, ptep, __pte(_PAGE_INVALID));
1276 }
1277 /* Nothing to do */
1278 if (!mm_is_protected(mm) || !pte_present(res))
1279 return res;
1280 /*
1281 * At this point the reference through the mapping is still present.
1282 * The notifier should have destroyed all protected vCPUs at this
1283 * point, so the destroy should be successful.
1284 */
1285 if (full && !uv_destroy_pte(res))
1286 return res;
1287 /*
1288 * If something went wrong and the page could not be destroyed, or
1289 * if this is not a mm teardown, the slower export is used as
1290 * fallback instead.
1291 */
1292 uv_convert_from_secure_pte(res);
1293 return res;
1294}
1295
1296#define __HAVE_ARCH_PTEP_SET_WRPROTECT
1297static inline void ptep_set_wrprotect(struct mm_struct *mm,
1298 unsigned long addr, pte_t *ptep)
1299{
1300 pte_t pte = *ptep;
1301
1302 if (pte_write(pte))
1303 ptep_xchg_lazy(mm, addr, ptep, pte_wrprotect(pte));
1304}
1305
1306/*
1307 * Check if PTEs only differ in _PAGE_PROTECT HW bit, but also allow SW PTE
1308 * bits in the comparison. Those might change e.g. because of dirty and young
1309 * tracking.
1310 */
1311static inline int pte_allow_rdp(pte_t old, pte_t new)
1312{
1313 /*
1314 * Only allow changes from RO to RW
1315 */
1316 if (!(pte_val(old) & _PAGE_PROTECT) || pte_val(new) & _PAGE_PROTECT)
1317 return 0;
1318
1319 return (pte_val(old) & _PAGE_RDP_MASK) == (pte_val(new) & _PAGE_RDP_MASK);
1320}
1321
1322static inline void flush_tlb_fix_spurious_fault(struct vm_area_struct *vma,
1323 unsigned long address,
1324 pte_t *ptep)
1325{
1326 /*
1327 * RDP might not have propagated the PTE protection reset to all CPUs,
1328 * so there could be spurious TLB protection faults.
1329 * NOTE: This will also be called when a racing pagetable update on
1330 * another thread already installed the correct PTE. Both cases cannot
1331 * really be distinguished.
1332 * Therefore, only do the local TLB flush when RDP can be used, and the
1333 * PTE does not have _PAGE_PROTECT set, to avoid unnecessary overhead.
1334 * A local RDP can be used to do the flush.
1335 */
1336 if (cpu_has_rdp() && !(pte_val(*ptep) & _PAGE_PROTECT))
1337 __ptep_rdp(address, ptep, 1);
1338}
1339#define flush_tlb_fix_spurious_fault flush_tlb_fix_spurious_fault
1340
1341void ptep_reset_dat_prot(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
1342 pte_t new);
1343
1344#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
1345static inline int ptep_set_access_flags(struct vm_area_struct *vma,
1346 unsigned long addr, pte_t *ptep,
1347 pte_t entry, int dirty)
1348{
1349 if (pte_same(*ptep, entry))
1350 return 0;
1351 if (cpu_has_rdp() && !mm_has_pgste(vma->vm_mm) && pte_allow_rdp(*ptep, entry))
1352 ptep_reset_dat_prot(vma->vm_mm, addr, ptep, entry);
1353 else
1354 ptep_xchg_direct(vma->vm_mm, addr, ptep, entry);
1355 return 1;
1356}
1357
1358/*
1359 * Additional functions to handle KVM guest page tables
1360 */
1361void ptep_set_pte_at(struct mm_struct *mm, unsigned long addr,
1362 pte_t *ptep, pte_t entry);
1363void ptep_set_notify(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
1364void ptep_notify(struct mm_struct *mm, unsigned long addr,
1365 pte_t *ptep, unsigned long bits);
1366int ptep_force_prot(struct mm_struct *mm, unsigned long gaddr,
1367 pte_t *ptep, int prot, unsigned long bit);
1368void ptep_zap_unused(struct mm_struct *mm, unsigned long addr,
1369 pte_t *ptep , int reset);
1370void ptep_zap_key(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
1371int ptep_shadow_pte(struct mm_struct *mm, unsigned long saddr,
1372 pte_t *sptep, pte_t *tptep, pte_t pte);
1373void ptep_unshadow_pte(struct mm_struct *mm, unsigned long saddr, pte_t *ptep);
1374
1375bool ptep_test_and_clear_uc(struct mm_struct *mm, unsigned long address,
1376 pte_t *ptep);
1377int set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1378 unsigned char key, bool nq);
1379int cond_set_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1380 unsigned char key, unsigned char *oldkey,
1381 bool nq, bool mr, bool mc);
1382int reset_guest_reference_bit(struct mm_struct *mm, unsigned long addr);
1383int get_guest_storage_key(struct mm_struct *mm, unsigned long addr,
1384 unsigned char *key);
1385
1386int set_pgste_bits(struct mm_struct *mm, unsigned long addr,
1387 unsigned long bits, unsigned long value);
1388int get_pgste(struct mm_struct *mm, unsigned long hva, unsigned long *pgstep);
1389int pgste_perform_essa(struct mm_struct *mm, unsigned long hva, int orc,
1390 unsigned long *oldpte, unsigned long *oldpgste);
1391void gmap_pmdp_invalidate(struct mm_struct *mm, unsigned long vmaddr);
1392void gmap_pmdp_idte_local(struct mm_struct *mm, unsigned long vmaddr);
1393void gmap_pmdp_idte_global(struct mm_struct *mm, unsigned long vmaddr);
1394
1395#define pgprot_writecombine pgprot_writecombine
1396pgprot_t pgprot_writecombine(pgprot_t prot);
1397
1398#define PFN_PTE_SHIFT PAGE_SHIFT
1399
1400/*
1401 * Set multiple PTEs to consecutive pages with a single call. All PTEs
1402 * are within the same folio, PMD and VMA.
1403 */
1404static inline void set_ptes(struct mm_struct *mm, unsigned long addr,
1405 pte_t *ptep, pte_t entry, unsigned int nr)
1406{
1407 if (pte_present(entry))
1408 entry = clear_pte_bit(entry, __pgprot(_PAGE_UNUSED));
1409 if (mm_has_pgste(mm)) {
1410 for (;;) {
1411 ptep_set_pte_at(mm, addr, ptep, entry);
1412 if (--nr == 0)
1413 break;
1414 ptep++;
1415 entry = __pte(pte_val(entry) + PAGE_SIZE);
1416 addr += PAGE_SIZE;
1417 }
1418 } else {
1419 for (;;) {
1420 set_pte(ptep, entry);
1421 if (--nr == 0)
1422 break;
1423 ptep++;
1424 entry = __pte(pte_val(entry) + PAGE_SIZE);
1425 }
1426 }
1427}
1428#define set_ptes set_ptes
1429
1430/*
1431 * Conversion functions: convert a page and protection to a page entry,
1432 * and a page entry and page directory to the page they refer to.
1433 */
1434static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
1435{
1436 pte_t __pte;
1437
1438 __pte = __pte(physpage | pgprot_val(pgprot));
1439 return pte_mkyoung(__pte);
1440}
1441
1442#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
1443#define p4d_index(address) (((address) >> P4D_SHIFT) & (PTRS_PER_P4D-1))
1444#define pud_index(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
1445#define pmd_index(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
1446
1447#define p4d_deref(pud) ((unsigned long)__va(p4d_val(pud) & _REGION_ENTRY_ORIGIN))
1448#define pgd_deref(pgd) ((unsigned long)__va(pgd_val(pgd) & _REGION_ENTRY_ORIGIN))
1449
1450static inline unsigned long pmd_deref(pmd_t pmd)
1451{
1452 unsigned long origin_mask;
1453
1454 origin_mask = _SEGMENT_ENTRY_ORIGIN;
1455 if (pmd_leaf(pmd))
1456 origin_mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
1457 return (unsigned long)__va(pmd_val(pmd) & origin_mask);
1458}
1459
1460static inline unsigned long pmd_pfn(pmd_t pmd)
1461{
1462 return __pa(pmd_deref(pmd)) >> PAGE_SHIFT;
1463}
1464
1465static inline unsigned long pud_deref(pud_t pud)
1466{
1467 unsigned long origin_mask;
1468
1469 origin_mask = _REGION_ENTRY_ORIGIN;
1470 if (pud_leaf(pud))
1471 origin_mask = _REGION3_ENTRY_ORIGIN_LARGE;
1472 return (unsigned long)__va(pud_val(pud) & origin_mask);
1473}
1474
1475#define pud_pfn pud_pfn
1476static inline unsigned long pud_pfn(pud_t pud)
1477{
1478 return __pa(pud_deref(pud)) >> PAGE_SHIFT;
1479}
1480
1481/*
1482 * The pgd_offset function *always* adds the index for the top-level
1483 * region/segment table. This is done to get a sequence like the
1484 * following to work:
1485 * pgdp = pgd_offset(current->mm, addr);
1486 * pgd = READ_ONCE(*pgdp);
1487 * p4dp = p4d_offset(&pgd, addr);
1488 * ...
1489 * The subsequent p4d_offset, pud_offset and pmd_offset functions
1490 * only add an index if they dereferenced the pointer.
1491 */
1492static inline pgd_t *pgd_offset_raw(pgd_t *pgd, unsigned long address)
1493{
1494 unsigned long rste;
1495 unsigned int shift;
1496
1497 /* Get the first entry of the top level table */
1498 rste = pgd_val(*pgd);
1499 /* Pick up the shift from the table type of the first entry */
1500 shift = ((rste & _REGION_ENTRY_TYPE_MASK) >> 2) * 11 + 20;
1501 return pgd + ((address >> shift) & (PTRS_PER_PGD - 1));
1502}
1503
1504#define pgd_offset(mm, address) pgd_offset_raw(READ_ONCE((mm)->pgd), address)
1505
1506static inline p4d_t *p4d_offset_lockless(pgd_t *pgdp, pgd_t pgd, unsigned long address)
1507{
1508 if ((pgd_val(pgd) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R1)
1509 return (p4d_t *) pgd_deref(pgd) + p4d_index(address);
1510 return (p4d_t *) pgdp;
1511}
1512#define p4d_offset_lockless p4d_offset_lockless
1513
1514static inline p4d_t *p4d_offset(pgd_t *pgdp, unsigned long address)
1515{
1516 return p4d_offset_lockless(pgdp, *pgdp, address);
1517}
1518
1519static inline pud_t *pud_offset_lockless(p4d_t *p4dp, p4d_t p4d, unsigned long address)
1520{
1521 if ((p4d_val(p4d) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R2)
1522 return (pud_t *) p4d_deref(p4d) + pud_index(address);
1523 return (pud_t *) p4dp;
1524}
1525#define pud_offset_lockless pud_offset_lockless
1526
1527static inline pud_t *pud_offset(p4d_t *p4dp, unsigned long address)
1528{
1529 return pud_offset_lockless(p4dp, *p4dp, address);
1530}
1531#define pud_offset pud_offset
1532
1533static inline pmd_t *pmd_offset_lockless(pud_t *pudp, pud_t pud, unsigned long address)
1534{
1535 if ((pud_val(pud) & _REGION_ENTRY_TYPE_MASK) >= _REGION_ENTRY_TYPE_R3)
1536 return (pmd_t *) pud_deref(pud) + pmd_index(address);
1537 return (pmd_t *) pudp;
1538}
1539#define pmd_offset_lockless pmd_offset_lockless
1540
1541static inline pmd_t *pmd_offset(pud_t *pudp, unsigned long address)
1542{
1543 return pmd_offset_lockless(pudp, *pudp, address);
1544}
1545#define pmd_offset pmd_offset
1546
1547static inline unsigned long pmd_page_vaddr(pmd_t pmd)
1548{
1549 return (unsigned long) pmd_deref(pmd);
1550}
1551
1552static inline bool gup_fast_permitted(unsigned long start, unsigned long end)
1553{
1554 return end <= current->mm->context.asce_limit;
1555}
1556#define gup_fast_permitted gup_fast_permitted
1557
1558#define pfn_pte(pfn, pgprot) mk_pte_phys(((pfn) << PAGE_SHIFT), (pgprot))
1559#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
1560#define pte_page(x) pfn_to_page(pte_pfn(x))
1561
1562#define pmd_page(pmd) pfn_to_page(pmd_pfn(pmd))
1563#define pud_page(pud) pfn_to_page(pud_pfn(pud))
1564#define p4d_page(p4d) pfn_to_page(p4d_pfn(p4d))
1565#define pgd_page(pgd) pfn_to_page(pgd_pfn(pgd))
1566
1567static inline pmd_t pmd_wrprotect(pmd_t pmd)
1568{
1569 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
1570 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1571}
1572
1573static inline pmd_t pmd_mkwrite_novma(pmd_t pmd)
1574{
1575 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_WRITE));
1576 if (pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY)
1577 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1578 return pmd;
1579}
1580
1581static inline pmd_t pmd_mkclean(pmd_t pmd)
1582{
1583 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY));
1584 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1585}
1586
1587static inline pmd_t pmd_mkdirty(pmd_t pmd)
1588{
1589 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_DIRTY | _SEGMENT_ENTRY_SOFT_DIRTY));
1590 if (pmd_val(pmd) & _SEGMENT_ENTRY_WRITE)
1591 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1592 return pmd;
1593}
1594
1595static inline pud_t pud_wrprotect(pud_t pud)
1596{
1597 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
1598 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
1599}
1600
1601static inline pud_t pud_mkwrite(pud_t pud)
1602{
1603 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_WRITE));
1604 if (pud_val(pud) & _REGION3_ENTRY_DIRTY)
1605 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
1606 return pud;
1607}
1608
1609static inline pud_t pud_mkclean(pud_t pud)
1610{
1611 pud = clear_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY));
1612 return set_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
1613}
1614
1615static inline pud_t pud_mkdirty(pud_t pud)
1616{
1617 pud = set_pud_bit(pud, __pgprot(_REGION3_ENTRY_DIRTY | _REGION3_ENTRY_SOFT_DIRTY));
1618 if (pud_val(pud) & _REGION3_ENTRY_WRITE)
1619 pud = clear_pud_bit(pud, __pgprot(_REGION_ENTRY_PROTECT));
1620 return pud;
1621}
1622
1623#if defined(CONFIG_TRANSPARENT_HUGEPAGE) || defined(CONFIG_HUGETLB_PAGE)
1624static inline unsigned long massage_pgprot_pmd(pgprot_t pgprot)
1625{
1626 /*
1627 * pgprot is PAGE_NONE, PAGE_RO, PAGE_RX, PAGE_RW or PAGE_RWX
1628 * (see __Pxxx / __Sxxx). Convert to segment table entry format.
1629 */
1630 if (pgprot_val(pgprot) == pgprot_val(PAGE_NONE))
1631 return pgprot_val(SEGMENT_NONE);
1632 if (pgprot_val(pgprot) == pgprot_val(PAGE_RO))
1633 return pgprot_val(SEGMENT_RO);
1634 if (pgprot_val(pgprot) == pgprot_val(PAGE_RX))
1635 return pgprot_val(SEGMENT_RX);
1636 if (pgprot_val(pgprot) == pgprot_val(PAGE_RW))
1637 return pgprot_val(SEGMENT_RW);
1638 return pgprot_val(SEGMENT_RWX);
1639}
1640
1641static inline pmd_t pmd_mkyoung(pmd_t pmd)
1642{
1643 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1644 if (pmd_val(pmd) & _SEGMENT_ENTRY_READ)
1645 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
1646 return pmd;
1647}
1648
1649static inline pmd_t pmd_mkold(pmd_t pmd)
1650{
1651 pmd = clear_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1652 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
1653}
1654
1655static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
1656{
1657 unsigned long mask;
1658
1659 mask = _SEGMENT_ENTRY_ORIGIN_LARGE;
1660 mask |= _SEGMENT_ENTRY_DIRTY;
1661 mask |= _SEGMENT_ENTRY_YOUNG;
1662 mask |= _SEGMENT_ENTRY_LARGE;
1663 mask |= _SEGMENT_ENTRY_SOFT_DIRTY;
1664 pmd = __pmd(pmd_val(pmd) & mask);
1665 pmd = set_pmd_bit(pmd, __pgprot(massage_pgprot_pmd(newprot)));
1666 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_DIRTY))
1667 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1668 if (!(pmd_val(pmd) & _SEGMENT_ENTRY_YOUNG))
1669 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_INVALID));
1670 return pmd;
1671}
1672
1673static inline pmd_t mk_pmd_phys(unsigned long physpage, pgprot_t pgprot)
1674{
1675 return __pmd(physpage + massage_pgprot_pmd(pgprot));
1676}
1677
1678#endif /* CONFIG_TRANSPARENT_HUGEPAGE || CONFIG_HUGETLB_PAGE */
1679
1680static inline void __pmdp_cspg(pmd_t *pmdp)
1681{
1682 cspg((unsigned long *)pmdp, pmd_val(*pmdp),
1683 pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
1684}
1685
1686#define IDTE_GLOBAL 0
1687#define IDTE_LOCAL 1
1688
1689#define IDTE_PTOA 0x0800
1690#define IDTE_NODAT 0x1000
1691#define IDTE_GUEST_ASCE 0x2000
1692
1693static __always_inline void __pmdp_idte(unsigned long addr, pmd_t *pmdp,
1694 unsigned long opt, unsigned long asce,
1695 int local)
1696{
1697 unsigned long sto;
1698
1699 sto = __pa(pmdp) - pmd_index(addr) * sizeof(pmd_t);
1700 if (__builtin_constant_p(opt) && opt == 0) {
1701 /* flush without guest asce */
1702 asm volatile(
1703 " idte %[r1],0,%[r2],%[m4]"
1704 : "+m" (*pmdp)
1705 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK)),
1706 [m4] "i" (local)
1707 : "cc" );
1708 } else {
1709 /* flush with guest asce */
1710 asm volatile(
1711 " idte %[r1],%[r3],%[r2],%[m4]"
1712 : "+m" (*pmdp)
1713 : [r1] "a" (sto), [r2] "a" ((addr & HPAGE_MASK) | opt),
1714 [r3] "a" (asce), [m4] "i" (local)
1715 : "cc" );
1716 }
1717}
1718
1719static __always_inline void __pudp_idte(unsigned long addr, pud_t *pudp,
1720 unsigned long opt, unsigned long asce,
1721 int local)
1722{
1723 unsigned long r3o;
1724
1725 r3o = __pa(pudp) - pud_index(addr) * sizeof(pud_t);
1726 r3o |= _ASCE_TYPE_REGION3;
1727 if (__builtin_constant_p(opt) && opt == 0) {
1728 /* flush without guest asce */
1729 asm volatile(
1730 " idte %[r1],0,%[r2],%[m4]"
1731 : "+m" (*pudp)
1732 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK)),
1733 [m4] "i" (local)
1734 : "cc");
1735 } else {
1736 /* flush with guest asce */
1737 asm volatile(
1738 " idte %[r1],%[r3],%[r2],%[m4]"
1739 : "+m" (*pudp)
1740 : [r1] "a" (r3o), [r2] "a" ((addr & PUD_MASK) | opt),
1741 [r3] "a" (asce), [m4] "i" (local)
1742 : "cc" );
1743 }
1744}
1745
1746pmd_t pmdp_xchg_direct(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
1747pmd_t pmdp_xchg_lazy(struct mm_struct *, unsigned long, pmd_t *, pmd_t);
1748pud_t pudp_xchg_direct(struct mm_struct *, unsigned long, pud_t *, pud_t);
1749
1750#ifdef CONFIG_TRANSPARENT_HUGEPAGE
1751
1752#define __HAVE_ARCH_PGTABLE_DEPOSIT
1753void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
1754 pgtable_t pgtable);
1755
1756#define __HAVE_ARCH_PGTABLE_WITHDRAW
1757pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
1758
1759#define __HAVE_ARCH_PMDP_SET_ACCESS_FLAGS
1760static inline int pmdp_set_access_flags(struct vm_area_struct *vma,
1761 unsigned long addr, pmd_t *pmdp,
1762 pmd_t entry, int dirty)
1763{
1764 VM_BUG_ON(addr & ~HPAGE_MASK);
1765
1766 entry = pmd_mkyoung(entry);
1767 if (dirty)
1768 entry = pmd_mkdirty(entry);
1769 if (pmd_val(*pmdp) == pmd_val(entry))
1770 return 0;
1771 pmdp_xchg_direct(vma->vm_mm, addr, pmdp, entry);
1772 return 1;
1773}
1774
1775#define __HAVE_ARCH_PMDP_TEST_AND_CLEAR_YOUNG
1776static inline int pmdp_test_and_clear_young(struct vm_area_struct *vma,
1777 unsigned long addr, pmd_t *pmdp)
1778{
1779 pmd_t pmd = *pmdp;
1780
1781 pmd = pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd_mkold(pmd));
1782 return pmd_young(pmd);
1783}
1784
1785#define __HAVE_ARCH_PMDP_CLEAR_YOUNG_FLUSH
1786static inline int pmdp_clear_flush_young(struct vm_area_struct *vma,
1787 unsigned long addr, pmd_t *pmdp)
1788{
1789 VM_BUG_ON(addr & ~HPAGE_MASK);
1790 return pmdp_test_and_clear_young(vma, addr, pmdp);
1791}
1792
1793static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
1794 pmd_t *pmdp, pmd_t entry)
1795{
1796 set_pmd(pmdp, entry);
1797}
1798
1799static inline pmd_t pmd_mkhuge(pmd_t pmd)
1800{
1801 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_LARGE));
1802 pmd = set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_YOUNG));
1803 return set_pmd_bit(pmd, __pgprot(_SEGMENT_ENTRY_PROTECT));
1804}
1805
1806#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR
1807static inline pmd_t pmdp_huge_get_and_clear(struct mm_struct *mm,
1808 unsigned long addr, pmd_t *pmdp)
1809{
1810 return pmdp_xchg_direct(mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1811}
1812
1813#define __HAVE_ARCH_PMDP_HUGE_GET_AND_CLEAR_FULL
1814static inline pmd_t pmdp_huge_get_and_clear_full(struct vm_area_struct *vma,
1815 unsigned long addr,
1816 pmd_t *pmdp, int full)
1817{
1818 if (full) {
1819 pmd_t pmd = *pmdp;
1820 set_pmd(pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1821 return pmd;
1822 }
1823 return pmdp_xchg_lazy(vma->vm_mm, addr, pmdp, __pmd(_SEGMENT_ENTRY_EMPTY));
1824}
1825
1826#define __HAVE_ARCH_PMDP_HUGE_CLEAR_FLUSH
1827static inline pmd_t pmdp_huge_clear_flush(struct vm_area_struct *vma,
1828 unsigned long addr, pmd_t *pmdp)
1829{
1830 return pmdp_huge_get_and_clear(vma->vm_mm, addr, pmdp);
1831}
1832
1833#define __HAVE_ARCH_PMDP_INVALIDATE
1834static inline pmd_t pmdp_invalidate(struct vm_area_struct *vma,
1835 unsigned long addr, pmd_t *pmdp)
1836{
1837 pmd_t pmd;
1838
1839 VM_WARN_ON_ONCE(!pmd_present(*pmdp));
1840 pmd = __pmd(pmd_val(*pmdp) | _SEGMENT_ENTRY_INVALID);
1841 return pmdp_xchg_direct(vma->vm_mm, addr, pmdp, pmd);
1842}
1843
1844#define __HAVE_ARCH_PMDP_SET_WRPROTECT
1845static inline void pmdp_set_wrprotect(struct mm_struct *mm,
1846 unsigned long addr, pmd_t *pmdp)
1847{
1848 pmd_t pmd = *pmdp;
1849
1850 if (pmd_write(pmd))
1851 pmd = pmdp_xchg_lazy(mm, addr, pmdp, pmd_wrprotect(pmd));
1852}
1853
1854static inline pmd_t pmdp_collapse_flush(struct vm_area_struct *vma,
1855 unsigned long address,
1856 pmd_t *pmdp)
1857{
1858 return pmdp_huge_get_and_clear(vma->vm_mm, address, pmdp);
1859}
1860#define pmdp_collapse_flush pmdp_collapse_flush
1861
1862#define pfn_pmd(pfn, pgprot) mk_pmd_phys(((pfn) << PAGE_SHIFT), (pgprot))
1863
1864static inline int pmd_trans_huge(pmd_t pmd)
1865{
1866 return pmd_leaf(pmd);
1867}
1868
1869#define has_transparent_hugepage has_transparent_hugepage
1870static inline int has_transparent_hugepage(void)
1871{
1872 return cpu_has_edat1() ? 1 : 0;
1873}
1874#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1875
1876/*
1877 * 64 bit swap entry format:
1878 * A page-table entry has some bits we have to treat in a special way.
1879 * Bits 54 and 63 are used to indicate the page type. Bit 53 marks the pte
1880 * as invalid.
1881 * A swap pte is indicated by bit pattern (pte & 0x201) == 0x200
1882 * | offset |E11XX|type |S0|
1883 * |0000000000111111111122222222223333333333444444444455|55555|55566|66|
1884 * |0123456789012345678901234567890123456789012345678901|23456|78901|23|
1885 *
1886 * Bits 0-51 store the offset.
1887 * Bit 52 (E) is used to remember PG_anon_exclusive.
1888 * Bits 57-61 store the type.
1889 * Bit 62 (S) is used for softdirty tracking.
1890 * Bits 55 and 56 (X) are unused.
1891 */
1892
1893#define __SWP_OFFSET_MASK ((1UL << 52) - 1)
1894#define __SWP_OFFSET_SHIFT 12
1895#define __SWP_TYPE_MASK ((1UL << 5) - 1)
1896#define __SWP_TYPE_SHIFT 2
1897
1898static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
1899{
1900 unsigned long pteval;
1901
1902 pteval = _PAGE_INVALID | _PAGE_PROTECT;
1903 pteval |= (offset & __SWP_OFFSET_MASK) << __SWP_OFFSET_SHIFT;
1904 pteval |= (type & __SWP_TYPE_MASK) << __SWP_TYPE_SHIFT;
1905 return __pte(pteval);
1906}
1907
1908static inline unsigned long __swp_type(swp_entry_t entry)
1909{
1910 return (entry.val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK;
1911}
1912
1913static inline unsigned long __swp_offset(swp_entry_t entry)
1914{
1915 return (entry.val >> __SWP_OFFSET_SHIFT) & __SWP_OFFSET_MASK;
1916}
1917
1918static inline swp_entry_t __swp_entry(unsigned long type, unsigned long offset)
1919{
1920 return (swp_entry_t) { pte_val(mk_swap_pte(type, offset)) };
1921}
1922
1923#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
1924#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
1925
1926/*
1927 * 64 bit swap entry format for REGION3 and SEGMENT table entries (RSTE)
1928 * Bits 59 and 63 are used to indicate the swap entry. Bit 58 marks the rste
1929 * as invalid.
1930 * A swap entry is indicated by bit pattern (rste & 0x011) == 0x010
1931 * | offset |Xtype |11TT|S0|
1932 * |0000000000111111111122222222223333333333444444444455|555555|5566|66|
1933 * |0123456789012345678901234567890123456789012345678901|234567|8901|23|
1934 *
1935 * Bits 0-51 store the offset.
1936 * Bits 53-57 store the type.
1937 * Bit 62 (S) is used for softdirty tracking.
1938 * Bits 60-61 (TT) indicate the table type: 0x01 for REGION3 and 0x00 for SEGMENT.
1939 * Bit 52 (X) is unused.
1940 */
1941
1942#define __SWP_OFFSET_MASK_RSTE ((1UL << 52) - 1)
1943#define __SWP_OFFSET_SHIFT_RSTE 12
1944#define __SWP_TYPE_MASK_RSTE ((1UL << 5) - 1)
1945#define __SWP_TYPE_SHIFT_RSTE 6
1946
1947/*
1948 * TT bits set to 0x00 == SEGMENT. For REGION3 entries, caller must add R3
1949 * bits 0x01. See also __set_huge_pte_at().
1950 */
1951static inline unsigned long mk_swap_rste(unsigned long type, unsigned long offset)
1952{
1953 unsigned long rste;
1954
1955 rste = _RST_ENTRY_INVALID | _RST_ENTRY_COMM;
1956 rste |= (offset & __SWP_OFFSET_MASK_RSTE) << __SWP_OFFSET_SHIFT_RSTE;
1957 rste |= (type & __SWP_TYPE_MASK_RSTE) << __SWP_TYPE_SHIFT_RSTE;
1958 return rste;
1959}
1960
1961static inline unsigned long __swp_type_rste(swp_entry_t entry)
1962{
1963 return (entry.val >> __SWP_TYPE_SHIFT_RSTE) & __SWP_TYPE_MASK_RSTE;
1964}
1965
1966static inline unsigned long __swp_offset_rste(swp_entry_t entry)
1967{
1968 return (entry.val >> __SWP_OFFSET_SHIFT_RSTE) & __SWP_OFFSET_MASK_RSTE;
1969}
1970
1971#define __rste_to_swp_entry(rste) ((swp_entry_t) { rste })
1972
1973/*
1974 * s390 has different layout for PTE and region / segment table entries (RSTE).
1975 * This is also true for swap entries, and their swap type and offset encoding.
1976 * For hugetlbfs PTE_MARKER support, s390 has internal __swp_type_rste() and
1977 * __swp_offset_rste() helpers to correctly handle RSTE swap entries.
1978 *
1979 * But common swap code does not know about this difference, and only uses
1980 * __swp_type(), __swp_offset() and __swp_entry() helpers for conversion between
1981 * arch-dependent and arch-independent representation of swp_entry_t for all
1982 * pagetable levels. On s390, those helpers only work for PTE swap entries.
1983 *
1984 * Therefore, implement __pmd_to_swp_entry() to build a fake PTE swap entry
1985 * and return the arch-dependent representation of that. Correspondingly,
1986 * implement __swp_entry_to_pmd() to convert that into a proper PMD swap
1987 * entry again. With this, the arch-dependent swp_entry_t representation will
1988 * always look like a PTE swap entry in common code.
1989 *
1990 * This is somewhat similar to fake PTEs in hugetlbfs code for s390, but only
1991 * requires conversion of the swap type and offset, and not all the possible
1992 * PTE bits.
1993 */
1994static inline swp_entry_t __pmd_to_swp_entry(pmd_t pmd)
1995{
1996 swp_entry_t arch_entry;
1997 pte_t pte;
1998
1999 arch_entry = __rste_to_swp_entry(pmd_val(pmd));
2000 pte = mk_swap_pte(__swp_type_rste(arch_entry), __swp_offset_rste(arch_entry));
2001 return __pte_to_swp_entry(pte);
2002}
2003
2004static inline pmd_t __swp_entry_to_pmd(swp_entry_t arch_entry)
2005{
2006 pmd_t pmd;
2007
2008 pmd = __pmd(mk_swap_rste(__swp_type(arch_entry), __swp_offset(arch_entry)));
2009 return pmd;
2010}
2011
2012extern int vmem_add_mapping(unsigned long start, unsigned long size);
2013extern void vmem_remove_mapping(unsigned long start, unsigned long size);
2014extern int __vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot, bool alloc);
2015extern int vmem_map_4k_page(unsigned long addr, unsigned long phys, pgprot_t prot);
2016extern void vmem_unmap_4k_page(unsigned long addr);
2017extern pte_t *vmem_get_alloc_pte(unsigned long addr, bool alloc);
2018extern int s390_enable_sie(void);
2019extern int s390_enable_skey(void);
2020extern void s390_reset_cmma(struct mm_struct *mm);
2021
2022/* s390 has a private copy of get unmapped area to deal with cache synonyms */
2023#define HAVE_ARCH_UNMAPPED_AREA
2024#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
2025
2026#define pmd_pgtable(pmd) \
2027 ((pgtable_t)__va(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE))
2028
2029static inline unsigned long gmap_pgste_get_pgt_addr(unsigned long *pgt)
2030{
2031 unsigned long *pgstes, res;
2032
2033 pgstes = pgt + _PAGE_ENTRIES;
2034
2035 res = (pgstes[0] & PGSTE_ST2_MASK) << 16;
2036 res |= pgstes[1] & PGSTE_ST2_MASK;
2037 res |= (pgstes[2] & PGSTE_ST2_MASK) >> 16;
2038 res |= (pgstes[3] & PGSTE_ST2_MASK) >> 32;
2039
2040 return res;
2041}
2042
2043static inline pgste_t pgste_get_lock(pte_t *ptep)
2044{
2045 unsigned long value = 0;
2046#ifdef CONFIG_PGSTE
2047 unsigned long *ptr = (unsigned long *)(ptep + PTRS_PER_PTE);
2048
2049 do {
2050 value = __atomic64_or_barrier(PGSTE_PCL_BIT, ptr);
2051 } while (value & PGSTE_PCL_BIT);
2052 value |= PGSTE_PCL_BIT;
2053#endif
2054 return __pgste(value);
2055}
2056
2057static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
2058{
2059#ifdef CONFIG_PGSTE
2060 barrier();
2061 WRITE_ONCE(*(unsigned long *)(ptep + PTRS_PER_PTE), pgste_val(pgste) & ~PGSTE_PCL_BIT);
2062#endif
2063}
2064
2065#endif /* _S390_PAGE_H */
2066

Warning: This file is not a C or C++ file. It does not have highlighting.

source code of linux/arch/s390/include/asm/pgtable.h