| 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * arch/sh/kernel/cpu/sh3/clock-sh7705.c |
| 4 | * |
| 5 | * SH7705 support for the clock framework |
| 6 | * |
| 7 | * Copyright (C) 2005 Paul Mundt |
| 8 | * |
| 9 | * FRQCR parsing hacked out of arch/sh/kernel/time.c |
| 10 | * |
| 11 | * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka |
| 12 | * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org> |
| 13 | * Copyright (C) 2002, 2003, 2004 Paul Mundt |
| 14 | * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org> |
| 15 | */ |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <asm/clock.h> |
| 19 | #include <asm/freq.h> |
| 20 | #include <asm/io.h> |
| 21 | |
| 22 | /* |
| 23 | * SH7705 uses the same divisors as the generic SH-3 case, it's just the |
| 24 | * FRQCR layout that is a bit different.. |
| 25 | */ |
| 26 | static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 }; |
| 27 | static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 }; |
| 28 | static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 }; |
| 29 | |
| 30 | static void master_clk_init(struct clk *clk) |
| 31 | { |
| 32 | clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003]; |
| 33 | } |
| 34 | |
| 35 | static struct sh_clk_ops sh7705_master_clk_ops = { |
| 36 | .init = master_clk_init, |
| 37 | }; |
| 38 | |
| 39 | static unsigned long module_clk_recalc(struct clk *clk) |
| 40 | { |
| 41 | int idx = __raw_readw(addr: FRQCR) & 0x0003; |
| 42 | return clk->parent->rate / pfc_divisors[idx]; |
| 43 | } |
| 44 | |
| 45 | static struct sh_clk_ops sh7705_module_clk_ops = { |
| 46 | .recalc = module_clk_recalc, |
| 47 | }; |
| 48 | |
| 49 | static unsigned long bus_clk_recalc(struct clk *clk) |
| 50 | { |
| 51 | int idx = (__raw_readw(FRQCR) & 0x0300) >> 8; |
| 52 | return clk->parent->rate / stc_multipliers[idx]; |
| 53 | } |
| 54 | |
| 55 | static struct sh_clk_ops sh7705_bus_clk_ops = { |
| 56 | .recalc = bus_clk_recalc, |
| 57 | }; |
| 58 | |
| 59 | static unsigned long cpu_clk_recalc(struct clk *clk) |
| 60 | { |
| 61 | int idx = (__raw_readw(FRQCR) & 0x0030) >> 4; |
| 62 | return clk->parent->rate / ifc_divisors[idx]; |
| 63 | } |
| 64 | |
| 65 | static struct sh_clk_ops sh7705_cpu_clk_ops = { |
| 66 | .recalc = cpu_clk_recalc, |
| 67 | }; |
| 68 | |
| 69 | static struct sh_clk_ops *sh7705_clk_ops[] = { |
| 70 | &sh7705_master_clk_ops, |
| 71 | &sh7705_module_clk_ops, |
| 72 | &sh7705_bus_clk_ops, |
| 73 | &sh7705_cpu_clk_ops, |
| 74 | }; |
| 75 | |
| 76 | void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx) |
| 77 | { |
| 78 | if (idx < ARRAY_SIZE(sh7705_clk_ops)) |
| 79 | *ops = sh7705_clk_ops[idx]; |
| 80 | } |
| 81 | |
| 82 | |