1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * AMD Memory Encryption Support
4 *
5 * Copyright (C) 2016 Advanced Micro Devices, Inc.
6 *
7 * Author: Tom Lendacky <thomas.lendacky@amd.com>
8 */
9
10/*
11 * Since we're dealing with identity mappings, physical and virtual
12 * addresses are the same, so override these defines which are ultimately
13 * used by the headers in misc.h.
14 */
15#define __pa(x) ((unsigned long)(x))
16#define __va(x) ((void *)((unsigned long)(x)))
17
18/*
19 * Special hack: we have to be careful, because no indirections are
20 * allowed here, and paravirt_ops is a kind of one. As it will only run in
21 * baremetal anyway, we just keep it from happening. (This list needs to
22 * be extended when new paravirt and debugging variants are added.)
23 */
24#undef CONFIG_PARAVIRT
25#undef CONFIG_PARAVIRT_XXL
26#undef CONFIG_PARAVIRT_SPINLOCKS
27
28/*
29 * This code runs before CPU feature bits are set. By default, the
30 * pgtable_l5_enabled() function uses bit X86_FEATURE_LA57 to determine if
31 * 5-level paging is active, so that won't work here. USE_EARLY_PGTABLE_L5
32 * is provided to handle this situation and, instead, use a variable that
33 * has been set by the early boot code.
34 */
35#define USE_EARLY_PGTABLE_L5
36
37#include <linux/kernel.h>
38#include <linux/mm.h>
39#include <linux/mem_encrypt.h>
40#include <linux/cc_platform.h>
41
42#include <asm/init.h>
43#include <asm/setup.h>
44#include <asm/sections.h>
45#include <asm/coco.h>
46#include <asm/sev.h>
47
48#define PGD_FLAGS _KERNPG_TABLE_NOENC
49#define P4D_FLAGS _KERNPG_TABLE_NOENC
50#define PUD_FLAGS _KERNPG_TABLE_NOENC
51#define PMD_FLAGS _KERNPG_TABLE_NOENC
52
53#define PMD_FLAGS_LARGE (__PAGE_KERNEL_LARGE_EXEC & ~_PAGE_GLOBAL)
54
55#define PMD_FLAGS_DEC PMD_FLAGS_LARGE
56#define PMD_FLAGS_DEC_WP ((PMD_FLAGS_DEC & ~_PAGE_LARGE_CACHE_MASK) | \
57 (_PAGE_PAT_LARGE | _PAGE_PWT))
58
59#define PMD_FLAGS_ENC (PMD_FLAGS_LARGE | _PAGE_ENC)
60
61#define PTE_FLAGS (__PAGE_KERNEL_EXEC & ~_PAGE_GLOBAL)
62
63#define PTE_FLAGS_DEC PTE_FLAGS
64#define PTE_FLAGS_DEC_WP ((PTE_FLAGS_DEC & ~_PAGE_CACHE_MASK) | \
65 (_PAGE_PAT | _PAGE_PWT))
66
67#define PTE_FLAGS_ENC (PTE_FLAGS | _PAGE_ENC)
68
69struct sme_populate_pgd_data {
70 void *pgtable_area;
71 pgd_t *pgd;
72
73 pmdval_t pmd_flags;
74 pteval_t pte_flags;
75 unsigned long paddr;
76
77 unsigned long vaddr;
78 unsigned long vaddr_end;
79};
80
81/*
82 * This work area lives in the .init.scratch section, which lives outside of
83 * the kernel proper. It is sized to hold the intermediate copy buffer and
84 * more than enough pagetable pages.
85 *
86 * By using this section, the kernel can be encrypted in place and it
87 * avoids any possibility of boot parameters or initramfs images being
88 * placed such that the in-place encryption logic overwrites them. This
89 * section is 2MB aligned to allow for simple pagetable setup using only
90 * PMD entries (see vmlinux.lds.S).
91 */
92static char sme_workarea[2 * PMD_SIZE] __section(".init.scratch");
93
94static void __init sme_clear_pgd(struct sme_populate_pgd_data *ppd)
95{
96 unsigned long pgd_start, pgd_end, pgd_size;
97 pgd_t *pgd_p;
98
99 pgd_start = ppd->vaddr & PGDIR_MASK;
100 pgd_end = ppd->vaddr_end & PGDIR_MASK;
101
102 pgd_size = (((pgd_end - pgd_start) / PGDIR_SIZE) + 1) * sizeof(pgd_t);
103
104 pgd_p = ppd->pgd + pgd_index(ppd->vaddr);
105
106 memset(s: pgd_p, c: 0, n: pgd_size);
107}
108
109static pud_t __init *sme_prepare_pgd(struct sme_populate_pgd_data *ppd)
110{
111 pgd_t *pgd;
112 p4d_t *p4d;
113 pud_t *pud;
114 pmd_t *pmd;
115
116 pgd = ppd->pgd + pgd_index(ppd->vaddr);
117 if (pgd_none(pgd: *pgd)) {
118 p4d = ppd->pgtable_area;
119 memset(s: p4d, c: 0, n: sizeof(*p4d) * PTRS_PER_P4D);
120 ppd->pgtable_area += sizeof(*p4d) * PTRS_PER_P4D;
121 set_pgd(pgd, __pgd(PGD_FLAGS | __pa(p4d)));
122 }
123
124 p4d = p4d_offset(pgd, address: ppd->vaddr);
125 if (p4d_none(p4d: *p4d)) {
126 pud = ppd->pgtable_area;
127 memset(s: pud, c: 0, n: sizeof(*pud) * PTRS_PER_PUD);
128 ppd->pgtable_area += sizeof(*pud) * PTRS_PER_PUD;
129 set_p4d(p4d, __p4d(P4D_FLAGS | __pa(pud)));
130 }
131
132 pud = pud_offset(p4d, address: ppd->vaddr);
133 if (pud_none(pud: *pud)) {
134 pmd = ppd->pgtable_area;
135 memset(s: pmd, c: 0, n: sizeof(*pmd) * PTRS_PER_PMD);
136 ppd->pgtable_area += sizeof(*pmd) * PTRS_PER_PMD;
137 set_pud(pud, __pud(PUD_FLAGS | __pa(pmd)));
138 }
139
140 if (pud_leaf(pud: *pud))
141 return NULL;
142
143 return pud;
144}
145
146static void __init sme_populate_pgd_large(struct sme_populate_pgd_data *ppd)
147{
148 pud_t *pud;
149 pmd_t *pmd;
150
151 pud = sme_prepare_pgd(ppd);
152 if (!pud)
153 return;
154
155 pmd = pmd_offset(pud, address: ppd->vaddr);
156 if (pmd_leaf(pte: *pmd))
157 return;
158
159 set_pmd(pmd, __pmd(ppd->paddr | ppd->pmd_flags));
160}
161
162static void __init sme_populate_pgd(struct sme_populate_pgd_data *ppd)
163{
164 pud_t *pud;
165 pmd_t *pmd;
166 pte_t *pte;
167
168 pud = sme_prepare_pgd(ppd);
169 if (!pud)
170 return;
171
172 pmd = pmd_offset(pud, address: ppd->vaddr);
173 if (pmd_none(pmd: *pmd)) {
174 pte = ppd->pgtable_area;
175 memset(s: pte, c: 0, n: sizeof(*pte) * PTRS_PER_PTE);
176 ppd->pgtable_area += sizeof(*pte) * PTRS_PER_PTE;
177 set_pmd(pmd, __pmd(PMD_FLAGS | __pa(pte)));
178 }
179
180 if (pmd_leaf(pte: *pmd))
181 return;
182
183 pte = pte_offset_kernel(pmd, address: ppd->vaddr);
184 if (pte_none(pte: *pte))
185 set_pte(pte, __pte(ppd->paddr | ppd->pte_flags));
186}
187
188static void __init __sme_map_range_pmd(struct sme_populate_pgd_data *ppd)
189{
190 while (ppd->vaddr < ppd->vaddr_end) {
191 sme_populate_pgd_large(ppd);
192
193 ppd->vaddr += PMD_SIZE;
194 ppd->paddr += PMD_SIZE;
195 }
196}
197
198static void __init __sme_map_range_pte(struct sme_populate_pgd_data *ppd)
199{
200 while (ppd->vaddr < ppd->vaddr_end) {
201 sme_populate_pgd(ppd);
202
203 ppd->vaddr += PAGE_SIZE;
204 ppd->paddr += PAGE_SIZE;
205 }
206}
207
208static void __init __sme_map_range(struct sme_populate_pgd_data *ppd,
209 pmdval_t pmd_flags, pteval_t pte_flags)
210{
211 unsigned long vaddr_end;
212
213 ppd->pmd_flags = pmd_flags;
214 ppd->pte_flags = pte_flags;
215
216 /* Save original end value since we modify the struct value */
217 vaddr_end = ppd->vaddr_end;
218
219 /* If start is not 2MB aligned, create PTE entries */
220 ppd->vaddr_end = ALIGN(ppd->vaddr, PMD_SIZE);
221 __sme_map_range_pte(ppd);
222
223 /* Create PMD entries */
224 ppd->vaddr_end = vaddr_end & PMD_MASK;
225 __sme_map_range_pmd(ppd);
226
227 /* If end is not 2MB aligned, create PTE entries */
228 ppd->vaddr_end = vaddr_end;
229 __sme_map_range_pte(ppd);
230}
231
232static void __init sme_map_range_encrypted(struct sme_populate_pgd_data *ppd)
233{
234 __sme_map_range(ppd, PMD_FLAGS_ENC, PTE_FLAGS_ENC);
235}
236
237static void __init sme_map_range_decrypted(struct sme_populate_pgd_data *ppd)
238{
239 __sme_map_range(ppd, PMD_FLAGS_DEC, PTE_FLAGS_DEC);
240}
241
242static void __init sme_map_range_decrypted_wp(struct sme_populate_pgd_data *ppd)
243{
244 __sme_map_range(ppd, PMD_FLAGS_DEC_WP, PTE_FLAGS_DEC_WP);
245}
246
247static unsigned long __init sme_pgtable_calc(unsigned long len)
248{
249 unsigned long entries = 0, tables = 0;
250
251 /*
252 * Perform a relatively simplistic calculation of the pagetable
253 * entries that are needed. Those mappings will be covered mostly
254 * by 2MB PMD entries so we can conservatively calculate the required
255 * number of P4D, PUD and PMD structures needed to perform the
256 * mappings. For mappings that are not 2MB aligned, PTE mappings
257 * would be needed for the start and end portion of the address range
258 * that fall outside of the 2MB alignment. This results in, at most,
259 * two extra pages to hold PTE entries for each range that is mapped.
260 * Incrementing the count for each covers the case where the addresses
261 * cross entries.
262 */
263
264 /* PGDIR_SIZE is equal to P4D_SIZE on 4-level machine. */
265 if (PTRS_PER_P4D > 1)
266 entries += (DIV_ROUND_UP(len, PGDIR_SIZE) + 1) * sizeof(p4d_t) * PTRS_PER_P4D;
267 entries += (DIV_ROUND_UP(len, P4D_SIZE) + 1) * sizeof(pud_t) * PTRS_PER_PUD;
268 entries += (DIV_ROUND_UP(len, PUD_SIZE) + 1) * sizeof(pmd_t) * PTRS_PER_PMD;
269 entries += 2 * sizeof(pte_t) * PTRS_PER_PTE;
270
271 /*
272 * Now calculate the added pagetable structures needed to populate
273 * the new pagetables.
274 */
275
276 if (PTRS_PER_P4D > 1)
277 tables += DIV_ROUND_UP(entries, PGDIR_SIZE) * sizeof(p4d_t) * PTRS_PER_P4D;
278 tables += DIV_ROUND_UP(entries, P4D_SIZE) * sizeof(pud_t) * PTRS_PER_PUD;
279 tables += DIV_ROUND_UP(entries, PUD_SIZE) * sizeof(pmd_t) * PTRS_PER_PMD;
280
281 return entries + tables;
282}
283
284void __init sme_encrypt_kernel(struct boot_params *bp)
285{
286 unsigned long workarea_start, workarea_end, workarea_len;
287 unsigned long execute_start, execute_end, execute_len;
288 unsigned long kernel_start, kernel_end, kernel_len;
289 unsigned long initrd_start, initrd_end, initrd_len;
290 struct sme_populate_pgd_data ppd;
291 unsigned long pgtable_area_len;
292 unsigned long decrypted_base;
293
294 /*
295 * This is early code, use an open coded check for SME instead of
296 * using cc_platform_has(). This eliminates worries about removing
297 * instrumentation or checking boot_cpu_data in the cc_platform_has()
298 * function.
299 */
300 if (!sme_get_me_mask() || sev_status & MSR_AMD64_SEV_ENABLED)
301 return;
302
303 /*
304 * Prepare for encrypting the kernel and initrd by building new
305 * pagetables with the necessary attributes needed to encrypt the
306 * kernel in place.
307 *
308 * One range of virtual addresses will map the memory occupied
309 * by the kernel and initrd as encrypted.
310 *
311 * Another range of virtual addresses will map the memory occupied
312 * by the kernel and initrd as decrypted and write-protected.
313 *
314 * The use of write-protect attribute will prevent any of the
315 * memory from being cached.
316 */
317
318 kernel_start = (unsigned long)rip_rel_ptr(p: _text);
319 kernel_end = ALIGN((unsigned long)rip_rel_ptr(_end), PMD_SIZE);
320 kernel_len = kernel_end - kernel_start;
321
322 initrd_start = 0;
323 initrd_end = 0;
324 initrd_len = 0;
325#ifdef CONFIG_BLK_DEV_INITRD
326 initrd_len = (unsigned long)bp->hdr.ramdisk_size |
327 ((unsigned long)bp->ext_ramdisk_size << 32);
328 if (initrd_len) {
329 initrd_start = (unsigned long)bp->hdr.ramdisk_image |
330 ((unsigned long)bp->ext_ramdisk_image << 32);
331 initrd_end = PAGE_ALIGN(initrd_start + initrd_len);
332 initrd_len = initrd_end - initrd_start;
333 }
334#endif
335
336 /*
337 * Calculate required number of workarea bytes needed:
338 * executable encryption area size:
339 * stack page (PAGE_SIZE)
340 * encryption routine page (PAGE_SIZE)
341 * intermediate copy buffer (PMD_SIZE)
342 * pagetable structures for the encryption of the kernel
343 * pagetable structures for workarea (in case not currently mapped)
344 */
345 execute_start = workarea_start = (unsigned long)rip_rel_ptr(p: sme_workarea);
346 execute_end = execute_start + (PAGE_SIZE * 2) + PMD_SIZE;
347 execute_len = execute_end - execute_start;
348
349 /*
350 * One PGD for both encrypted and decrypted mappings and a set of
351 * PUDs and PMDs for each of the encrypted and decrypted mappings.
352 */
353 pgtable_area_len = sizeof(pgd_t) * PTRS_PER_PGD;
354 pgtable_area_len += sme_pgtable_calc(len: execute_end - kernel_start) * 2;
355 if (initrd_len)
356 pgtable_area_len += sme_pgtable_calc(len: initrd_len) * 2;
357
358 /* PUDs and PMDs needed in the current pagetables for the workarea */
359 pgtable_area_len += sme_pgtable_calc(len: execute_len + pgtable_area_len);
360
361 /*
362 * The total workarea includes the executable encryption area and
363 * the pagetable area. The start of the workarea is already 2MB
364 * aligned, align the end of the workarea on a 2MB boundary so that
365 * we don't try to create/allocate PTE entries from the workarea
366 * before it is mapped.
367 */
368 workarea_len = execute_len + pgtable_area_len;
369 workarea_end = ALIGN(workarea_start + workarea_len, PMD_SIZE);
370
371 /*
372 * Set the address to the start of where newly created pagetable
373 * structures (PGDs, PUDs and PMDs) will be allocated. New pagetable
374 * structures are created when the workarea is added to the current
375 * pagetables and when the new encrypted and decrypted kernel
376 * mappings are populated.
377 */
378 ppd.pgtable_area = (void *)execute_end;
379
380 /*
381 * Make sure the current pagetable structure has entries for
382 * addressing the workarea.
383 */
384 ppd.pgd = (pgd_t *)native_read_cr3_pa();
385 ppd.paddr = workarea_start;
386 ppd.vaddr = workarea_start;
387 ppd.vaddr_end = workarea_end;
388 sme_map_range_decrypted(ppd: &ppd);
389
390 /* Flush the TLB - no globals so cr3 is enough */
391 native_write_cr3(val: __native_read_cr3());
392
393 /*
394 * A new pagetable structure is being built to allow for the kernel
395 * and initrd to be encrypted. It starts with an empty PGD that will
396 * then be populated with new PUDs and PMDs as the encrypted and
397 * decrypted kernel mappings are created.
398 */
399 ppd.pgd = ppd.pgtable_area;
400 memset(s: ppd.pgd, c: 0, n: sizeof(pgd_t) * PTRS_PER_PGD);
401 ppd.pgtable_area += sizeof(pgd_t) * PTRS_PER_PGD;
402
403 /*
404 * A different PGD index/entry must be used to get different
405 * pagetable entries for the decrypted mapping. Choose the next
406 * PGD index and convert it to a virtual address to be used as
407 * the base of the mapping.
408 */
409 decrypted_base = (pgd_index(workarea_end) + 1) & (PTRS_PER_PGD - 1);
410 if (initrd_len) {
411 unsigned long check_base;
412
413 check_base = (pgd_index(initrd_end) + 1) & (PTRS_PER_PGD - 1);
414 decrypted_base = max(decrypted_base, check_base);
415 }
416 decrypted_base <<= PGDIR_SHIFT;
417
418 /* Add encrypted kernel (identity) mappings */
419 ppd.paddr = kernel_start;
420 ppd.vaddr = kernel_start;
421 ppd.vaddr_end = kernel_end;
422 sme_map_range_encrypted(ppd: &ppd);
423
424 /* Add decrypted, write-protected kernel (non-identity) mappings */
425 ppd.paddr = kernel_start;
426 ppd.vaddr = kernel_start + decrypted_base;
427 ppd.vaddr_end = kernel_end + decrypted_base;
428 sme_map_range_decrypted_wp(ppd: &ppd);
429
430 if (initrd_len) {
431 /* Add encrypted initrd (identity) mappings */
432 ppd.paddr = initrd_start;
433 ppd.vaddr = initrd_start;
434 ppd.vaddr_end = initrd_end;
435 sme_map_range_encrypted(ppd: &ppd);
436 /*
437 * Add decrypted, write-protected initrd (non-identity) mappings
438 */
439 ppd.paddr = initrd_start;
440 ppd.vaddr = initrd_start + decrypted_base;
441 ppd.vaddr_end = initrd_end + decrypted_base;
442 sme_map_range_decrypted_wp(ppd: &ppd);
443 }
444
445 /* Add decrypted workarea mappings to both kernel mappings */
446 ppd.paddr = workarea_start;
447 ppd.vaddr = workarea_start;
448 ppd.vaddr_end = workarea_end;
449 sme_map_range_decrypted(ppd: &ppd);
450
451 ppd.paddr = workarea_start;
452 ppd.vaddr = workarea_start + decrypted_base;
453 ppd.vaddr_end = workarea_end + decrypted_base;
454 sme_map_range_decrypted(ppd: &ppd);
455
456 /* Perform the encryption */
457 sme_encrypt_execute(encrypted_kernel_vaddr: kernel_start, decrypted_kernel_vaddr: kernel_start + decrypted_base,
458 kernel_len, encryption_wa: workarea_start, encryption_pgd: (unsigned long)ppd.pgd);
459
460 if (initrd_len)
461 sme_encrypt_execute(encrypted_kernel_vaddr: initrd_start, decrypted_kernel_vaddr: initrd_start + decrypted_base,
462 kernel_len: initrd_len, encryption_wa: workarea_start,
463 encryption_pgd: (unsigned long)ppd.pgd);
464
465 /*
466 * At this point we are running encrypted. Remove the mappings for
467 * the decrypted areas - all that is needed for this is to remove
468 * the PGD entry/entries.
469 */
470 ppd.vaddr = kernel_start + decrypted_base;
471 ppd.vaddr_end = kernel_end + decrypted_base;
472 sme_clear_pgd(ppd: &ppd);
473
474 if (initrd_len) {
475 ppd.vaddr = initrd_start + decrypted_base;
476 ppd.vaddr_end = initrd_end + decrypted_base;
477 sme_clear_pgd(ppd: &ppd);
478 }
479
480 ppd.vaddr = workarea_start + decrypted_base;
481 ppd.vaddr_end = workarea_end + decrypted_base;
482 sme_clear_pgd(ppd: &ppd);
483
484 /* Flush the TLB - no globals so cr3 is enough */
485 native_write_cr3(val: __native_read_cr3());
486}
487
488void __init sme_enable(struct boot_params *bp)
489{
490 unsigned int eax, ebx, ecx, edx;
491 unsigned long feature_mask;
492 unsigned long me_mask;
493 bool snp_en;
494 u64 msr;
495
496 snp_en = snp_init(bp);
497
498 /* Check for the SME/SEV support leaf */
499 eax = 0x80000000;
500 ecx = 0;
501 native_cpuid(eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
502 if (eax < 0x8000001f)
503 return;
504
505#define AMD_SME_BIT BIT(0)
506#define AMD_SEV_BIT BIT(1)
507
508 /*
509 * Check for the SME/SEV feature:
510 * CPUID Fn8000_001F[EAX]
511 * - Bit 0 - Secure Memory Encryption support
512 * - Bit 1 - Secure Encrypted Virtualization support
513 * CPUID Fn8000_001F[EBX]
514 * - Bits 5:0 - Pagetable bit position used to indicate encryption
515 */
516 eax = 0x8000001f;
517 ecx = 0;
518 native_cpuid(eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
519 /* Check whether SEV or SME is supported */
520 if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT)))
521 return;
522
523 me_mask = 1UL << (ebx & 0x3f);
524 sev_snp_needs_sfw = !(ebx & BIT(31));
525
526 /* Check the SEV MSR whether SEV or SME is enabled */
527 sev_status = msr = native_rdmsrq(MSR_AMD64_SEV);
528 feature_mask = (msr & MSR_AMD64_SEV_ENABLED) ? AMD_SEV_BIT : AMD_SME_BIT;
529
530 /*
531 * Any discrepancies between the presence of a CC blob and SNP
532 * enablement abort the guest.
533 */
534 if (snp_en ^ !!(msr & MSR_AMD64_SEV_SNP_ENABLED))
535 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED);
536
537 /* Check if memory encryption is enabled */
538 if (feature_mask == AMD_SME_BIT) {
539 if (!(bp->hdr.xloadflags & XLF_MEM_ENCRYPTION))
540 return;
541
542 /*
543 * No SME if Hypervisor bit is set. This check is here to
544 * prevent a guest from trying to enable SME. For running as a
545 * KVM guest the MSR_AMD64_SYSCFG will be sufficient, but there
546 * might be other hypervisors which emulate that MSR as non-zero
547 * or even pass it through to the guest.
548 * A malicious hypervisor can still trick a guest into this
549 * path, but there is no way to protect against that.
550 */
551 eax = 1;
552 ecx = 0;
553 native_cpuid(eax: &eax, ebx: &ebx, ecx: &ecx, edx: &edx);
554 if (ecx & BIT(31))
555 return;
556
557 /* For SME, check the SYSCFG MSR */
558 msr = native_rdmsrq(MSR_AMD64_SYSCFG);
559 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
560 return;
561 }
562
563 sme_me_mask = me_mask;
564 physical_mask &= ~me_mask;
565 cc_vendor = CC_VENDOR_AMD;
566 cc_set_mask(mask: me_mask);
567}
568
569#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
570/* Local version for startup code, which never operates on user page tables */
571pgd_t __pti_set_user_pgtbl(pgd_t *pgdp, pgd_t pgd)
572{
573 return pgd;
574}
575#endif
576

source code of linux/arch/x86/boot/startup/sme.c