1 | /* |
2 | * This file is subject to the terms and conditions of the GNU General Public |
3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. |
5 | * |
6 | * HPE UV MMR definitions |
7 | * |
8 | * (C) Copyright 2020 Hewlett Packard Enterprise Development LP |
9 | * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved. |
10 | */ |
11 | |
12 | #ifndef _ASM_X86_UV_UV_MMRS_H |
13 | #define _ASM_X86_UV_UV_MMRS_H |
14 | |
15 | /* |
16 | * This file contains MMR definitions for all UV hubs types. |
17 | * |
18 | * To minimize coding differences between hub types, the symbols are |
19 | * grouped by architecture types. |
20 | * |
21 | * UVH - definitions common to all UV hub types. |
22 | * UVXH - definitions common to UVX class (2, 3, 4). |
23 | * UVYH - definitions common to UVY class (5). |
24 | * UV5H - definitions specific to UV type 5 hub. |
25 | * UV4AH - definitions specific to UV type 4A hub. |
26 | * UV4H - definitions specific to UV type 4 hub. |
27 | * UV3H - definitions specific to UV type 3 hub. |
28 | * UV2H - definitions specific to UV type 2 hub. |
29 | * |
30 | * If the MMR exists on all hub types but have different addresses, |
31 | * use a conditional operator to define the value at runtime. Any |
32 | * that are not defined are blank. |
33 | * (UV4A variations only generated if different from uv4) |
34 | * #define UVHxxx ( |
35 | * is_uv(UV5) ? UV5Hxxx value : |
36 | * is_uv(UV4A) ? UV4AHxxx value : |
37 | * is_uv(UV4) ? UV4Hxxx value : |
38 | * is_uv(UV3) ? UV3Hxxx value : |
39 | * is_uv(UV2) ? UV2Hxxx value : |
40 | * <ucv> or <undef value>) |
41 | * |
42 | * Class UVX has UVs (2|3|4|4A). |
43 | * Class UVY has UVs (5). |
44 | * |
45 | * union uvh_xxx { |
46 | * unsigned long v; |
47 | * struct uvh_xxx_s { # Common fields only |
48 | * } s; |
49 | * struct uv5h_xxx_s { # Full UV5 definition (*) |
50 | * } s5; |
51 | * struct uv4ah_xxx_s { # Full UV4A definition (*) |
52 | * } s4a; |
53 | * struct uv4h_xxx_s { # Full UV4 definition (*) |
54 | * } s4; |
55 | * struct uv3h_xxx_s { # Full UV3 definition (*) |
56 | * } s3; |
57 | * struct uv2h_xxx_s { # Full UV2 definition (*) |
58 | * } s2; |
59 | * }; |
60 | * (* - if present and different than the common struct) |
61 | * |
62 | * Only essential differences are enumerated. For example, if the address is |
63 | * the same for all UV's, only a single #define is generated. Likewise, |
64 | * if the contents is the same for all hubs, only the "s" structure is |
65 | * generated. |
66 | * |
67 | * (GEN Flags: undefs=function) |
68 | */ |
69 | |
70 | /* UV bit masks */ |
71 | #define UV2 (1 << 0) |
72 | #define UV3 (1 << 1) |
73 | #define UV4 (1 << 2) |
74 | #define UV4A (1 << 3) |
75 | #define UV5 (1 << 4) |
76 | #define UVX (UV2|UV3|UV4) |
77 | #define UVY (UV5) |
78 | #define UV_ANY (~0) |
79 | |
80 | |
81 | |
82 | |
83 | #define UV_MMR_ENABLE (1UL << 63) |
84 | |
85 | #define UV1_HUB_PART_NUMBER 0x88a5 |
86 | #define UV2_HUB_PART_NUMBER 0x8eb8 |
87 | #define UV2_HUB_PART_NUMBER_X 0x1111 |
88 | #define UV3_HUB_PART_NUMBER 0x9578 |
89 | #define UV3_HUB_PART_NUMBER_X 0x4321 |
90 | #define UV4_HUB_PART_NUMBER 0x99a1 |
91 | #define UV5_HUB_PART_NUMBER 0xa171 |
92 | |
93 | /* Error function to catch undefined references */ |
94 | extern unsigned long uv_undefined(char *str); |
95 | |
96 | /* ========================================================================= */ |
97 | /* UVH_EVENT_OCCURRED0 */ |
98 | /* ========================================================================= */ |
99 | #define UVH_EVENT_OCCURRED0 0x70000UL |
100 | |
101 | /* UVH common defines*/ |
102 | #define UVH_EVENT_OCCURRED0_LB_HCERR_SHFT 0 |
103 | #define UVH_EVENT_OCCURRED0_LB_HCERR_MASK 0x0000000000000001UL |
104 | |
105 | /* UVXH common defines */ |
106 | #define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 |
107 | #define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL |
108 | #define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 |
109 | #define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL |
110 | #define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 |
111 | #define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL |
112 | #define UVXH_EVENT_OCCURRED0_GR0_HCERR_SHFT 5 |
113 | #define UVXH_EVENT_OCCURRED0_GR0_HCERR_MASK 0x0000000000000020UL |
114 | #define UVXH_EVENT_OCCURRED0_GR1_HCERR_SHFT 6 |
115 | #define UVXH_EVENT_OCCURRED0_GR1_HCERR_MASK 0x0000000000000040UL |
116 | #define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 |
117 | #define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL |
118 | #define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 |
119 | #define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL |
120 | #define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 |
121 | #define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL |
122 | #define UVXH_EVENT_OCCURRED0_RH_AOERR0_SHFT 11 |
123 | #define UVXH_EVENT_OCCURRED0_RH_AOERR0_MASK 0x0000000000000800UL |
124 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 |
125 | #define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL |
126 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 |
127 | #define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL |
128 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 |
129 | #define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL |
130 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 |
131 | #define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL |
132 | #define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 |
133 | #define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL |
134 | |
135 | /* UVYH common defines */ |
136 | #define UVYH_EVENT_OCCURRED0_KT_HCERR_SHFT 1 |
137 | #define UVYH_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL |
138 | #define UVYH_EVENT_OCCURRED0_RH0_HCERR_SHFT 2 |
139 | #define UVYH_EVENT_OCCURRED0_RH0_HCERR_MASK 0x0000000000000004UL |
140 | #define UVYH_EVENT_OCCURRED0_RH1_HCERR_SHFT 3 |
141 | #define UVYH_EVENT_OCCURRED0_RH1_HCERR_MASK 0x0000000000000008UL |
142 | #define UVYH_EVENT_OCCURRED0_LH0_HCERR_SHFT 4 |
143 | #define UVYH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000010UL |
144 | #define UVYH_EVENT_OCCURRED0_LH1_HCERR_SHFT 5 |
145 | #define UVYH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000020UL |
146 | #define UVYH_EVENT_OCCURRED0_LH2_HCERR_SHFT 6 |
147 | #define UVYH_EVENT_OCCURRED0_LH2_HCERR_MASK 0x0000000000000040UL |
148 | #define UVYH_EVENT_OCCURRED0_LH3_HCERR_SHFT 7 |
149 | #define UVYH_EVENT_OCCURRED0_LH3_HCERR_MASK 0x0000000000000080UL |
150 | #define UVYH_EVENT_OCCURRED0_XB_HCERR_SHFT 8 |
151 | #define UVYH_EVENT_OCCURRED0_XB_HCERR_MASK 0x0000000000000100UL |
152 | #define UVYH_EVENT_OCCURRED0_RDM_HCERR_SHFT 9 |
153 | #define UVYH_EVENT_OCCURRED0_RDM_HCERR_MASK 0x0000000000000200UL |
154 | #define UVYH_EVENT_OCCURRED0_NI0_HCERR_SHFT 10 |
155 | #define UVYH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000400UL |
156 | #define UVYH_EVENT_OCCURRED0_NI1_HCERR_SHFT 11 |
157 | #define UVYH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000800UL |
158 | #define UVYH_EVENT_OCCURRED0_LB_AOERR0_SHFT 12 |
159 | #define UVYH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000001000UL |
160 | #define UVYH_EVENT_OCCURRED0_KT_AOERR0_SHFT 13 |
161 | #define UVYH_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000002000UL |
162 | #define UVYH_EVENT_OCCURRED0_RH0_AOERR0_SHFT 14 |
163 | #define UVYH_EVENT_OCCURRED0_RH0_AOERR0_MASK 0x0000000000004000UL |
164 | #define UVYH_EVENT_OCCURRED0_RH1_AOERR0_SHFT 15 |
165 | #define UVYH_EVENT_OCCURRED0_RH1_AOERR0_MASK 0x0000000000008000UL |
166 | #define UVYH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 16 |
167 | #define UVYH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000010000UL |
168 | #define UVYH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 17 |
169 | #define UVYH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000020000UL |
170 | #define UVYH_EVENT_OCCURRED0_LH2_AOERR0_SHFT 18 |
171 | #define UVYH_EVENT_OCCURRED0_LH2_AOERR0_MASK 0x0000000000040000UL |
172 | #define UVYH_EVENT_OCCURRED0_LH3_AOERR0_SHFT 19 |
173 | #define UVYH_EVENT_OCCURRED0_LH3_AOERR0_MASK 0x0000000000080000UL |
174 | #define UVYH_EVENT_OCCURRED0_XB_AOERR0_SHFT 20 |
175 | #define UVYH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000100000UL |
176 | #define UVYH_EVENT_OCCURRED0_RDM_AOERR0_SHFT 21 |
177 | #define UVYH_EVENT_OCCURRED0_RDM_AOERR0_MASK 0x0000000000200000UL |
178 | #define UVYH_EVENT_OCCURRED0_RT0_AOERR0_SHFT 22 |
179 | #define UVYH_EVENT_OCCURRED0_RT0_AOERR0_MASK 0x0000000000400000UL |
180 | #define UVYH_EVENT_OCCURRED0_RT1_AOERR0_SHFT 23 |
181 | #define UVYH_EVENT_OCCURRED0_RT1_AOERR0_MASK 0x0000000000800000UL |
182 | #define UVYH_EVENT_OCCURRED0_NI0_AOERR0_SHFT 24 |
183 | #define UVYH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000001000000UL |
184 | #define UVYH_EVENT_OCCURRED0_NI1_AOERR0_SHFT 25 |
185 | #define UVYH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000002000000UL |
186 | #define UVYH_EVENT_OCCURRED0_LB_AOERR1_SHFT 26 |
187 | #define UVYH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000004000000UL |
188 | #define UVYH_EVENT_OCCURRED0_KT_AOERR1_SHFT 27 |
189 | #define UVYH_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000008000000UL |
190 | #define UVYH_EVENT_OCCURRED0_RH0_AOERR1_SHFT 28 |
191 | #define UVYH_EVENT_OCCURRED0_RH0_AOERR1_MASK 0x0000000010000000UL |
192 | #define UVYH_EVENT_OCCURRED0_RH1_AOERR1_SHFT 29 |
193 | #define UVYH_EVENT_OCCURRED0_RH1_AOERR1_MASK 0x0000000020000000UL |
194 | #define UVYH_EVENT_OCCURRED0_LH0_AOERR1_SHFT 30 |
195 | #define UVYH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000040000000UL |
196 | #define UVYH_EVENT_OCCURRED0_LH1_AOERR1_SHFT 31 |
197 | #define UVYH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000080000000UL |
198 | #define UVYH_EVENT_OCCURRED0_LH2_AOERR1_SHFT 32 |
199 | #define UVYH_EVENT_OCCURRED0_LH2_AOERR1_MASK 0x0000000100000000UL |
200 | #define UVYH_EVENT_OCCURRED0_LH3_AOERR1_SHFT 33 |
201 | #define UVYH_EVENT_OCCURRED0_LH3_AOERR1_MASK 0x0000000200000000UL |
202 | #define UVYH_EVENT_OCCURRED0_XB_AOERR1_SHFT 34 |
203 | #define UVYH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000400000000UL |
204 | #define UVYH_EVENT_OCCURRED0_RDM_AOERR1_SHFT 35 |
205 | #define UVYH_EVENT_OCCURRED0_RDM_AOERR1_MASK 0x0000000800000000UL |
206 | #define UVYH_EVENT_OCCURRED0_RT0_AOERR1_SHFT 36 |
207 | #define UVYH_EVENT_OCCURRED0_RT0_AOERR1_MASK 0x0000001000000000UL |
208 | #define UVYH_EVENT_OCCURRED0_RT1_AOERR1_SHFT 37 |
209 | #define UVYH_EVENT_OCCURRED0_RT1_AOERR1_MASK 0x0000002000000000UL |
210 | #define UVYH_EVENT_OCCURRED0_NI0_AOERR1_SHFT 38 |
211 | #define UVYH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000004000000000UL |
212 | #define UVYH_EVENT_OCCURRED0_NI1_AOERR1_SHFT 39 |
213 | #define UVYH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000008000000000UL |
214 | #define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 40 |
215 | #define UVYH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000010000000000UL |
216 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 41 |
217 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000020000000000UL |
218 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 42 |
219 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000040000000000UL |
220 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 43 |
221 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000080000000000UL |
222 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 44 |
223 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000100000000000UL |
224 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 45 |
225 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000200000000000UL |
226 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 46 |
227 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000400000000000UL |
228 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 47 |
229 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000800000000000UL |
230 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 48 |
231 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0001000000000000UL |
232 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 49 |
233 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0002000000000000UL |
234 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 50 |
235 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0004000000000000UL |
236 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 51 |
237 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0008000000000000UL |
238 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 52 |
239 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0010000000000000UL |
240 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 53 |
241 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0020000000000000UL |
242 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 54 |
243 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0040000000000000UL |
244 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 55 |
245 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0080000000000000UL |
246 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 56 |
247 | #define UVYH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0100000000000000UL |
248 | #define UVYH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 57 |
249 | #define UVYH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0200000000000000UL |
250 | #define UVYH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 58 |
251 | #define UVYH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0400000000000000UL |
252 | #define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 59 |
253 | #define UVYH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0800000000000000UL |
254 | #define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 60 |
255 | #define UVYH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x1000000000000000UL |
256 | #define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 61 |
257 | #define UVYH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x2000000000000000UL |
258 | |
259 | /* UV4 unique defines */ |
260 | #define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1 |
261 | #define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL |
262 | #define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10 |
263 | #define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL |
264 | #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17 |
265 | #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL |
266 | #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18 |
267 | #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL |
268 | #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19 |
269 | #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL |
270 | #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20 |
271 | #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL |
272 | #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21 |
273 | #define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL |
274 | #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22 |
275 | #define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL |
276 | #define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23 |
277 | #define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL |
278 | #define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24 |
279 | #define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL |
280 | #define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25 |
281 | #define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL |
282 | #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26 |
283 | #define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL |
284 | #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27 |
285 | #define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL |
286 | #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28 |
287 | #define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL |
288 | #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29 |
289 | #define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL |
290 | #define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30 |
291 | #define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL |
292 | #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31 |
293 | #define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL |
294 | #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32 |
295 | #define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL |
296 | #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33 |
297 | #define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL |
298 | #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34 |
299 | #define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL |
300 | #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35 |
301 | #define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL |
302 | #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36 |
303 | #define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL |
304 | #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37 |
305 | #define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL |
306 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38 |
307 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL |
308 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39 |
309 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL |
310 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40 |
311 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL |
312 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41 |
313 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL |
314 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42 |
315 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL |
316 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43 |
317 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL |
318 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44 |
319 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL |
320 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45 |
321 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL |
322 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46 |
323 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL |
324 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47 |
325 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL |
326 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48 |
327 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL |
328 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49 |
329 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL |
330 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50 |
331 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL |
332 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51 |
333 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL |
334 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52 |
335 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL |
336 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53 |
337 | #define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL |
338 | #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54 |
339 | #define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL |
340 | #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55 |
341 | #define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL |
342 | #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56 |
343 | #define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL |
344 | #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57 |
345 | #define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL |
346 | #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58 |
347 | #define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL |
348 | #define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59 |
349 | #define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL |
350 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60 |
351 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL |
352 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61 |
353 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL |
354 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62 |
355 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL |
356 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63 |
357 | #define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL |
358 | |
359 | /* UV3 unique defines */ |
360 | #define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 |
361 | #define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL |
362 | #define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 |
363 | #define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL |
364 | #define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 |
365 | #define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL |
366 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 |
367 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL |
368 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 |
369 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL |
370 | #define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 |
371 | #define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL |
372 | #define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 |
373 | #define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL |
374 | #define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 |
375 | #define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL |
376 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 |
377 | #define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL |
378 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 |
379 | #define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL |
380 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 |
381 | #define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL |
382 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 |
383 | #define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL |
384 | #define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 |
385 | #define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL |
386 | #define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 |
387 | #define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL |
388 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 |
389 | #define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL |
390 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 |
391 | #define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL |
392 | #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 |
393 | #define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL |
394 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 |
395 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL |
396 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 |
397 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL |
398 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 |
399 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL |
400 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 |
401 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL |
402 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 |
403 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL |
404 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 |
405 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL |
406 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 |
407 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL |
408 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 |
409 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL |
410 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 |
411 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL |
412 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 |
413 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL |
414 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 |
415 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL |
416 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 |
417 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL |
418 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 |
419 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL |
420 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 |
421 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL |
422 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 |
423 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL |
424 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 |
425 | #define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL |
426 | #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 |
427 | #define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL |
428 | #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 |
429 | #define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL |
430 | #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 |
431 | #define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL |
432 | #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 |
433 | #define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL |
434 | #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 |
435 | #define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL |
436 | #define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53 |
437 | #define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL |
438 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 |
439 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL |
440 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 |
441 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL |
442 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 |
443 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL |
444 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 |
445 | #define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL |
446 | #define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 |
447 | #define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL |
448 | |
449 | /* UV2 unique defines */ |
450 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1 |
451 | #define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL |
452 | #define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10 |
453 | #define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL |
454 | #define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17 |
455 | #define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL |
456 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18 |
457 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL |
458 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19 |
459 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL |
460 | #define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20 |
461 | #define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL |
462 | #define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21 |
463 | #define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL |
464 | #define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22 |
465 | #define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL |
466 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23 |
467 | #define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL |
468 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24 |
469 | #define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL |
470 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25 |
471 | #define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL |
472 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26 |
473 | #define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL |
474 | #define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27 |
475 | #define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL |
476 | #define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28 |
477 | #define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL |
478 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29 |
479 | #define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL |
480 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30 |
481 | #define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL |
482 | #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31 |
483 | #define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL |
484 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32 |
485 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL |
486 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33 |
487 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL |
488 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34 |
489 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL |
490 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35 |
491 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL |
492 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36 |
493 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL |
494 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37 |
495 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL |
496 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38 |
497 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL |
498 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39 |
499 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL |
500 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40 |
501 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL |
502 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41 |
503 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL |
504 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42 |
505 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL |
506 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43 |
507 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL |
508 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44 |
509 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL |
510 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45 |
511 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL |
512 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46 |
513 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL |
514 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47 |
515 | #define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL |
516 | #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48 |
517 | #define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL |
518 | #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49 |
519 | #define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL |
520 | #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50 |
521 | #define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL |
522 | #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51 |
523 | #define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL |
524 | #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52 |
525 | #define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL |
526 | #define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53 |
527 | #define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL |
528 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54 |
529 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL |
530 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55 |
531 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL |
532 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56 |
533 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL |
534 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57 |
535 | #define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL |
536 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58 |
537 | #define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL |
538 | |
539 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_MASK ( \ |
540 | is_uv(UV4) ? 0x1000000000000000UL : \ |
541 | is_uv(UV3) ? 0x0040000000000000UL : \ |
542 | is_uv(UV2) ? 0x0040000000000000UL : \ |
543 | 0) |
544 | #define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \ |
545 | is_uv(UV4) ? 60 : \ |
546 | is_uv(UV3) ? 54 : \ |
547 | is_uv(UV2) ? 54 : \ |
548 | -1) |
549 | |
550 | union uvh_event_occurred0_u { |
551 | unsigned long v; |
552 | |
553 | /* UVH common struct */ |
554 | struct uvh_event_occurred0_s { |
555 | unsigned long lb_hcerr:1; /* RW */ |
556 | unsigned long rsvd_1_63:63; |
557 | } s; |
558 | |
559 | /* UVXH common struct */ |
560 | struct uvxh_event_occurred0_s { |
561 | unsigned long lb_hcerr:1; /* RW */ |
562 | unsigned long rsvd_1:1; |
563 | unsigned long rh_hcerr:1; /* RW */ |
564 | unsigned long lh0_hcerr:1; /* RW */ |
565 | unsigned long lh1_hcerr:1; /* RW */ |
566 | unsigned long gr0_hcerr:1; /* RW */ |
567 | unsigned long gr1_hcerr:1; /* RW */ |
568 | unsigned long ni0_hcerr:1; /* RW */ |
569 | unsigned long ni1_hcerr:1; /* RW */ |
570 | unsigned long lb_aoerr0:1; /* RW */ |
571 | unsigned long rsvd_10:1; |
572 | unsigned long rh_aoerr0:1; /* RW */ |
573 | unsigned long lh0_aoerr0:1; /* RW */ |
574 | unsigned long lh1_aoerr0:1; /* RW */ |
575 | unsigned long gr0_aoerr0:1; /* RW */ |
576 | unsigned long gr1_aoerr0:1; /* RW */ |
577 | unsigned long xb_aoerr0:1; /* RW */ |
578 | unsigned long rsvd_17_63:47; |
579 | } sx; |
580 | |
581 | /* UVYH common struct */ |
582 | struct uvyh_event_occurred0_s { |
583 | unsigned long lb_hcerr:1; /* RW */ |
584 | unsigned long kt_hcerr:1; /* RW */ |
585 | unsigned long rh0_hcerr:1; /* RW */ |
586 | unsigned long rh1_hcerr:1; /* RW */ |
587 | unsigned long lh0_hcerr:1; /* RW */ |
588 | unsigned long lh1_hcerr:1; /* RW */ |
589 | unsigned long lh2_hcerr:1; /* RW */ |
590 | unsigned long lh3_hcerr:1; /* RW */ |
591 | unsigned long xb_hcerr:1; /* RW */ |
592 | unsigned long rdm_hcerr:1; /* RW */ |
593 | unsigned long ni0_hcerr:1; /* RW */ |
594 | unsigned long ni1_hcerr:1; /* RW */ |
595 | unsigned long lb_aoerr0:1; /* RW */ |
596 | unsigned long kt_aoerr0:1; /* RW */ |
597 | unsigned long rh0_aoerr0:1; /* RW */ |
598 | unsigned long rh1_aoerr0:1; /* RW */ |
599 | unsigned long lh0_aoerr0:1; /* RW */ |
600 | unsigned long lh1_aoerr0:1; /* RW */ |
601 | unsigned long lh2_aoerr0:1; /* RW */ |
602 | unsigned long lh3_aoerr0:1; /* RW */ |
603 | unsigned long xb_aoerr0:1; /* RW */ |
604 | unsigned long rdm_aoerr0:1; /* RW */ |
605 | unsigned long rt0_aoerr0:1; /* RW */ |
606 | unsigned long rt1_aoerr0:1; /* RW */ |
607 | unsigned long ni0_aoerr0:1; /* RW */ |
608 | unsigned long ni1_aoerr0:1; /* RW */ |
609 | unsigned long lb_aoerr1:1; /* RW */ |
610 | unsigned long kt_aoerr1:1; /* RW */ |
611 | unsigned long rh0_aoerr1:1; /* RW */ |
612 | unsigned long rh1_aoerr1:1; /* RW */ |
613 | unsigned long lh0_aoerr1:1; /* RW */ |
614 | unsigned long lh1_aoerr1:1; /* RW */ |
615 | unsigned long lh2_aoerr1:1; /* RW */ |
616 | unsigned long lh3_aoerr1:1; /* RW */ |
617 | unsigned long xb_aoerr1:1; /* RW */ |
618 | unsigned long rdm_aoerr1:1; /* RW */ |
619 | unsigned long rt0_aoerr1:1; /* RW */ |
620 | unsigned long rt1_aoerr1:1; /* RW */ |
621 | unsigned long ni0_aoerr1:1; /* RW */ |
622 | unsigned long ni1_aoerr1:1; /* RW */ |
623 | unsigned long system_shutdown_int:1; /* RW */ |
624 | unsigned long lb_irq_int_0:1; /* RW */ |
625 | unsigned long lb_irq_int_1:1; /* RW */ |
626 | unsigned long lb_irq_int_2:1; /* RW */ |
627 | unsigned long lb_irq_int_3:1; /* RW */ |
628 | unsigned long lb_irq_int_4:1; /* RW */ |
629 | unsigned long lb_irq_int_5:1; /* RW */ |
630 | unsigned long lb_irq_int_6:1; /* RW */ |
631 | unsigned long lb_irq_int_7:1; /* RW */ |
632 | unsigned long lb_irq_int_8:1; /* RW */ |
633 | unsigned long lb_irq_int_9:1; /* RW */ |
634 | unsigned long lb_irq_int_10:1; /* RW */ |
635 | unsigned long lb_irq_int_11:1; /* RW */ |
636 | unsigned long lb_irq_int_12:1; /* RW */ |
637 | unsigned long lb_irq_int_13:1; /* RW */ |
638 | unsigned long lb_irq_int_14:1; /* RW */ |
639 | unsigned long lb_irq_int_15:1; /* RW */ |
640 | unsigned long l1_nmi_int:1; /* RW */ |
641 | unsigned long stop_clock:1; /* RW */ |
642 | unsigned long asic_to_l1:1; /* RW */ |
643 | unsigned long l1_to_asic:1; /* RW */ |
644 | unsigned long la_seq_trigger:1; /* RW */ |
645 | unsigned long rsvd_62_63:2; |
646 | } sy; |
647 | |
648 | /* UV5 unique struct */ |
649 | struct uv5h_event_occurred0_s { |
650 | unsigned long lb_hcerr:1; /* RW */ |
651 | unsigned long kt_hcerr:1; /* RW */ |
652 | unsigned long rh0_hcerr:1; /* RW */ |
653 | unsigned long rh1_hcerr:1; /* RW */ |
654 | unsigned long lh0_hcerr:1; /* RW */ |
655 | unsigned long lh1_hcerr:1; /* RW */ |
656 | unsigned long lh2_hcerr:1; /* RW */ |
657 | unsigned long lh3_hcerr:1; /* RW */ |
658 | unsigned long xb_hcerr:1; /* RW */ |
659 | unsigned long rdm_hcerr:1; /* RW */ |
660 | unsigned long ni0_hcerr:1; /* RW */ |
661 | unsigned long ni1_hcerr:1; /* RW */ |
662 | unsigned long lb_aoerr0:1; /* RW */ |
663 | unsigned long kt_aoerr0:1; /* RW */ |
664 | unsigned long rh0_aoerr0:1; /* RW */ |
665 | unsigned long rh1_aoerr0:1; /* RW */ |
666 | unsigned long lh0_aoerr0:1; /* RW */ |
667 | unsigned long lh1_aoerr0:1; /* RW */ |
668 | unsigned long lh2_aoerr0:1; /* RW */ |
669 | unsigned long lh3_aoerr0:1; /* RW */ |
670 | unsigned long xb_aoerr0:1; /* RW */ |
671 | unsigned long rdm_aoerr0:1; /* RW */ |
672 | unsigned long rt0_aoerr0:1; /* RW */ |
673 | unsigned long rt1_aoerr0:1; /* RW */ |
674 | unsigned long ni0_aoerr0:1; /* RW */ |
675 | unsigned long ni1_aoerr0:1; /* RW */ |
676 | unsigned long lb_aoerr1:1; /* RW */ |
677 | unsigned long kt_aoerr1:1; /* RW */ |
678 | unsigned long rh0_aoerr1:1; /* RW */ |
679 | unsigned long rh1_aoerr1:1; /* RW */ |
680 | unsigned long lh0_aoerr1:1; /* RW */ |
681 | unsigned long lh1_aoerr1:1; /* RW */ |
682 | unsigned long lh2_aoerr1:1; /* RW */ |
683 | unsigned long lh3_aoerr1:1; /* RW */ |
684 | unsigned long xb_aoerr1:1; /* RW */ |
685 | unsigned long rdm_aoerr1:1; /* RW */ |
686 | unsigned long rt0_aoerr1:1; /* RW */ |
687 | unsigned long rt1_aoerr1:1; /* RW */ |
688 | unsigned long ni0_aoerr1:1; /* RW */ |
689 | unsigned long ni1_aoerr1:1; /* RW */ |
690 | unsigned long system_shutdown_int:1; /* RW */ |
691 | unsigned long lb_irq_int_0:1; /* RW */ |
692 | unsigned long lb_irq_int_1:1; /* RW */ |
693 | unsigned long lb_irq_int_2:1; /* RW */ |
694 | unsigned long lb_irq_int_3:1; /* RW */ |
695 | unsigned long lb_irq_int_4:1; /* RW */ |
696 | unsigned long lb_irq_int_5:1; /* RW */ |
697 | unsigned long lb_irq_int_6:1; /* RW */ |
698 | unsigned long lb_irq_int_7:1; /* RW */ |
699 | unsigned long lb_irq_int_8:1; /* RW */ |
700 | unsigned long lb_irq_int_9:1; /* RW */ |
701 | unsigned long lb_irq_int_10:1; /* RW */ |
702 | unsigned long lb_irq_int_11:1; /* RW */ |
703 | unsigned long lb_irq_int_12:1; /* RW */ |
704 | unsigned long lb_irq_int_13:1; /* RW */ |
705 | unsigned long lb_irq_int_14:1; /* RW */ |
706 | unsigned long lb_irq_int_15:1; /* RW */ |
707 | unsigned long l1_nmi_int:1; /* RW */ |
708 | unsigned long stop_clock:1; /* RW */ |
709 | unsigned long asic_to_l1:1; /* RW */ |
710 | unsigned long l1_to_asic:1; /* RW */ |
711 | unsigned long la_seq_trigger:1; /* RW */ |
712 | unsigned long rsvd_62_63:2; |
713 | } s5; |
714 | |
715 | /* UV4 unique struct */ |
716 | struct uv4h_event_occurred0_s { |
717 | unsigned long lb_hcerr:1; /* RW */ |
718 | unsigned long kt_hcerr:1; /* RW */ |
719 | unsigned long rh_hcerr:1; /* RW */ |
720 | unsigned long lh0_hcerr:1; /* RW */ |
721 | unsigned long lh1_hcerr:1; /* RW */ |
722 | unsigned long gr0_hcerr:1; /* RW */ |
723 | unsigned long gr1_hcerr:1; /* RW */ |
724 | unsigned long ni0_hcerr:1; /* RW */ |
725 | unsigned long ni1_hcerr:1; /* RW */ |
726 | unsigned long lb_aoerr0:1; /* RW */ |
727 | unsigned long kt_aoerr0:1; /* RW */ |
728 | unsigned long rh_aoerr0:1; /* RW */ |
729 | unsigned long lh0_aoerr0:1; /* RW */ |
730 | unsigned long lh1_aoerr0:1; /* RW */ |
731 | unsigned long gr0_aoerr0:1; /* RW */ |
732 | unsigned long gr1_aoerr0:1; /* RW */ |
733 | unsigned long xb_aoerr0:1; /* RW */ |
734 | unsigned long rtq0_aoerr0:1; /* RW */ |
735 | unsigned long rtq1_aoerr0:1; /* RW */ |
736 | unsigned long rtq2_aoerr0:1; /* RW */ |
737 | unsigned long rtq3_aoerr0:1; /* RW */ |
738 | unsigned long ni0_aoerr0:1; /* RW */ |
739 | unsigned long ni1_aoerr0:1; /* RW */ |
740 | unsigned long lb_aoerr1:1; /* RW */ |
741 | unsigned long kt_aoerr1:1; /* RW */ |
742 | unsigned long rh_aoerr1:1; /* RW */ |
743 | unsigned long lh0_aoerr1:1; /* RW */ |
744 | unsigned long lh1_aoerr1:1; /* RW */ |
745 | unsigned long gr0_aoerr1:1; /* RW */ |
746 | unsigned long gr1_aoerr1:1; /* RW */ |
747 | unsigned long xb_aoerr1:1; /* RW */ |
748 | unsigned long rtq0_aoerr1:1; /* RW */ |
749 | unsigned long rtq1_aoerr1:1; /* RW */ |
750 | unsigned long rtq2_aoerr1:1; /* RW */ |
751 | unsigned long rtq3_aoerr1:1; /* RW */ |
752 | unsigned long ni0_aoerr1:1; /* RW */ |
753 | unsigned long ni1_aoerr1:1; /* RW */ |
754 | unsigned long system_shutdown_int:1; /* RW */ |
755 | unsigned long lb_irq_int_0:1; /* RW */ |
756 | unsigned long lb_irq_int_1:1; /* RW */ |
757 | unsigned long lb_irq_int_2:1; /* RW */ |
758 | unsigned long lb_irq_int_3:1; /* RW */ |
759 | unsigned long lb_irq_int_4:1; /* RW */ |
760 | unsigned long lb_irq_int_5:1; /* RW */ |
761 | unsigned long lb_irq_int_6:1; /* RW */ |
762 | unsigned long lb_irq_int_7:1; /* RW */ |
763 | unsigned long lb_irq_int_8:1; /* RW */ |
764 | unsigned long lb_irq_int_9:1; /* RW */ |
765 | unsigned long lb_irq_int_10:1; /* RW */ |
766 | unsigned long lb_irq_int_11:1; /* RW */ |
767 | unsigned long lb_irq_int_12:1; /* RW */ |
768 | unsigned long lb_irq_int_13:1; /* RW */ |
769 | unsigned long lb_irq_int_14:1; /* RW */ |
770 | unsigned long lb_irq_int_15:1; /* RW */ |
771 | unsigned long l1_nmi_int:1; /* RW */ |
772 | unsigned long stop_clock:1; /* RW */ |
773 | unsigned long asic_to_l1:1; /* RW */ |
774 | unsigned long l1_to_asic:1; /* RW */ |
775 | unsigned long la_seq_trigger:1; /* RW */ |
776 | unsigned long ipi_int:1; /* RW */ |
777 | unsigned long extio_int0:1; /* RW */ |
778 | unsigned long extio_int1:1; /* RW */ |
779 | unsigned long extio_int2:1; /* RW */ |
780 | unsigned long extio_int3:1; /* RW */ |
781 | } s4; |
782 | |
783 | /* UV3 unique struct */ |
784 | struct uv3h_event_occurred0_s { |
785 | unsigned long lb_hcerr:1; /* RW */ |
786 | unsigned long qp_hcerr:1; /* RW */ |
787 | unsigned long rh_hcerr:1; /* RW */ |
788 | unsigned long lh0_hcerr:1; /* RW */ |
789 | unsigned long lh1_hcerr:1; /* RW */ |
790 | unsigned long gr0_hcerr:1; /* RW */ |
791 | unsigned long gr1_hcerr:1; /* RW */ |
792 | unsigned long ni0_hcerr:1; /* RW */ |
793 | unsigned long ni1_hcerr:1; /* RW */ |
794 | unsigned long lb_aoerr0:1; /* RW */ |
795 | unsigned long qp_aoerr0:1; /* RW */ |
796 | unsigned long rh_aoerr0:1; /* RW */ |
797 | unsigned long lh0_aoerr0:1; /* RW */ |
798 | unsigned long lh1_aoerr0:1; /* RW */ |
799 | unsigned long gr0_aoerr0:1; /* RW */ |
800 | unsigned long gr1_aoerr0:1; /* RW */ |
801 | unsigned long xb_aoerr0:1; /* RW */ |
802 | unsigned long rt_aoerr0:1; /* RW */ |
803 | unsigned long ni0_aoerr0:1; /* RW */ |
804 | unsigned long ni1_aoerr0:1; /* RW */ |
805 | unsigned long lb_aoerr1:1; /* RW */ |
806 | unsigned long qp_aoerr1:1; /* RW */ |
807 | unsigned long rh_aoerr1:1; /* RW */ |
808 | unsigned long lh0_aoerr1:1; /* RW */ |
809 | unsigned long lh1_aoerr1:1; /* RW */ |
810 | unsigned long gr0_aoerr1:1; /* RW */ |
811 | unsigned long gr1_aoerr1:1; /* RW */ |
812 | unsigned long xb_aoerr1:1; /* RW */ |
813 | unsigned long rt_aoerr1:1; /* RW */ |
814 | unsigned long ni0_aoerr1:1; /* RW */ |
815 | unsigned long ni1_aoerr1:1; /* RW */ |
816 | unsigned long system_shutdown_int:1; /* RW */ |
817 | unsigned long lb_irq_int_0:1; /* RW */ |
818 | unsigned long lb_irq_int_1:1; /* RW */ |
819 | unsigned long lb_irq_int_2:1; /* RW */ |
820 | unsigned long lb_irq_int_3:1; /* RW */ |
821 | unsigned long lb_irq_int_4:1; /* RW */ |
822 | unsigned long lb_irq_int_5:1; /* RW */ |
823 | unsigned long lb_irq_int_6:1; /* RW */ |
824 | unsigned long lb_irq_int_7:1; /* RW */ |
825 | unsigned long lb_irq_int_8:1; /* RW */ |
826 | unsigned long lb_irq_int_9:1; /* RW */ |
827 | unsigned long lb_irq_int_10:1; /* RW */ |
828 | unsigned long lb_irq_int_11:1; /* RW */ |
829 | unsigned long lb_irq_int_12:1; /* RW */ |
830 | unsigned long lb_irq_int_13:1; /* RW */ |
831 | unsigned long lb_irq_int_14:1; /* RW */ |
832 | unsigned long lb_irq_int_15:1; /* RW */ |
833 | unsigned long l1_nmi_int:1; /* RW */ |
834 | unsigned long stop_clock:1; /* RW */ |
835 | unsigned long asic_to_l1:1; /* RW */ |
836 | unsigned long l1_to_asic:1; /* RW */ |
837 | unsigned long la_seq_trigger:1; /* RW */ |
838 | unsigned long ipi_int:1; /* RW */ |
839 | unsigned long extio_int0:1; /* RW */ |
840 | unsigned long extio_int1:1; /* RW */ |
841 | unsigned long extio_int2:1; /* RW */ |
842 | unsigned long extio_int3:1; /* RW */ |
843 | unsigned long profile_int:1; /* RW */ |
844 | unsigned long rsvd_59_63:5; |
845 | } s3; |
846 | |
847 | /* UV2 unique struct */ |
848 | struct uv2h_event_occurred0_s { |
849 | unsigned long lb_hcerr:1; /* RW */ |
850 | unsigned long qp_hcerr:1; /* RW */ |
851 | unsigned long rh_hcerr:1; /* RW */ |
852 | unsigned long lh0_hcerr:1; /* RW */ |
853 | unsigned long lh1_hcerr:1; /* RW */ |
854 | unsigned long gr0_hcerr:1; /* RW */ |
855 | unsigned long gr1_hcerr:1; /* RW */ |
856 | unsigned long ni0_hcerr:1; /* RW */ |
857 | unsigned long ni1_hcerr:1; /* RW */ |
858 | unsigned long lb_aoerr0:1; /* RW */ |
859 | unsigned long qp_aoerr0:1; /* RW */ |
860 | unsigned long rh_aoerr0:1; /* RW */ |
861 | unsigned long lh0_aoerr0:1; /* RW */ |
862 | unsigned long lh1_aoerr0:1; /* RW */ |
863 | unsigned long gr0_aoerr0:1; /* RW */ |
864 | unsigned long gr1_aoerr0:1; /* RW */ |
865 | unsigned long xb_aoerr0:1; /* RW */ |
866 | unsigned long rt_aoerr0:1; /* RW */ |
867 | unsigned long ni0_aoerr0:1; /* RW */ |
868 | unsigned long ni1_aoerr0:1; /* RW */ |
869 | unsigned long lb_aoerr1:1; /* RW */ |
870 | unsigned long qp_aoerr1:1; /* RW */ |
871 | unsigned long rh_aoerr1:1; /* RW */ |
872 | unsigned long lh0_aoerr1:1; /* RW */ |
873 | unsigned long lh1_aoerr1:1; /* RW */ |
874 | unsigned long gr0_aoerr1:1; /* RW */ |
875 | unsigned long gr1_aoerr1:1; /* RW */ |
876 | unsigned long xb_aoerr1:1; /* RW */ |
877 | unsigned long rt_aoerr1:1; /* RW */ |
878 | unsigned long ni0_aoerr1:1; /* RW */ |
879 | unsigned long ni1_aoerr1:1; /* RW */ |
880 | unsigned long system_shutdown_int:1; /* RW */ |
881 | unsigned long lb_irq_int_0:1; /* RW */ |
882 | unsigned long lb_irq_int_1:1; /* RW */ |
883 | unsigned long lb_irq_int_2:1; /* RW */ |
884 | unsigned long lb_irq_int_3:1; /* RW */ |
885 | unsigned long lb_irq_int_4:1; /* RW */ |
886 | unsigned long lb_irq_int_5:1; /* RW */ |
887 | unsigned long lb_irq_int_6:1; /* RW */ |
888 | unsigned long lb_irq_int_7:1; /* RW */ |
889 | unsigned long lb_irq_int_8:1; /* RW */ |
890 | unsigned long lb_irq_int_9:1; /* RW */ |
891 | unsigned long lb_irq_int_10:1; /* RW */ |
892 | unsigned long lb_irq_int_11:1; /* RW */ |
893 | unsigned long lb_irq_int_12:1; /* RW */ |
894 | unsigned long lb_irq_int_13:1; /* RW */ |
895 | unsigned long lb_irq_int_14:1; /* RW */ |
896 | unsigned long lb_irq_int_15:1; /* RW */ |
897 | unsigned long l1_nmi_int:1; /* RW */ |
898 | unsigned long stop_clock:1; /* RW */ |
899 | unsigned long asic_to_l1:1; /* RW */ |
900 | unsigned long l1_to_asic:1; /* RW */ |
901 | unsigned long la_seq_trigger:1; /* RW */ |
902 | unsigned long ipi_int:1; /* RW */ |
903 | unsigned long extio_int0:1; /* RW */ |
904 | unsigned long extio_int1:1; /* RW */ |
905 | unsigned long extio_int2:1; /* RW */ |
906 | unsigned long extio_int3:1; /* RW */ |
907 | unsigned long profile_int:1; /* RW */ |
908 | unsigned long rsvd_59_63:5; |
909 | } s2; |
910 | }; |
911 | |
912 | /* ========================================================================= */ |
913 | /* UVH_EVENT_OCCURRED0_ALIAS */ |
914 | /* ========================================================================= */ |
915 | #define UVH_EVENT_OCCURRED0_ALIAS 0x70008UL |
916 | |
917 | |
918 | /* ========================================================================= */ |
919 | /* UVH_EVENT_OCCURRED1 */ |
920 | /* ========================================================================= */ |
921 | #define UVH_EVENT_OCCURRED1 0x70080UL |
922 | |
923 | |
924 | |
925 | /* UVYH common defines */ |
926 | #define UVYH_EVENT_OCCURRED1_IPI_INT_SHFT 0 |
927 | #define UVYH_EVENT_OCCURRED1_IPI_INT_MASK 0x0000000000000001UL |
928 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT0_SHFT 1 |
929 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT0_MASK 0x0000000000000002UL |
930 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT1_SHFT 2 |
931 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT1_MASK 0x0000000000000004UL |
932 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT2_SHFT 3 |
933 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT2_MASK 0x0000000000000008UL |
934 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT3_SHFT 4 |
935 | #define UVYH_EVENT_OCCURRED1_EXTIO_INT3_MASK 0x0000000000000010UL |
936 | #define UVYH_EVENT_OCCURRED1_PROFILE_INT_SHFT 5 |
937 | #define UVYH_EVENT_OCCURRED1_PROFILE_INT_MASK 0x0000000000000020UL |
938 | #define UVYH_EVENT_OCCURRED1_BAU_DATA_SHFT 6 |
939 | #define UVYH_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000040UL |
940 | #define UVYH_EVENT_OCCURRED1_PROC_GENERAL_SHFT 7 |
941 | #define UVYH_EVENT_OCCURRED1_PROC_GENERAL_MASK 0x0000000000000080UL |
942 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_SHFT 8 |
943 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT0_MASK 0x0000000000000100UL |
944 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_SHFT 9 |
945 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT1_MASK 0x0000000000000200UL |
946 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_SHFT 10 |
947 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT2_MASK 0x0000000000000400UL |
948 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_SHFT 11 |
949 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT3_MASK 0x0000000000000800UL |
950 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_SHFT 12 |
951 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT4_MASK 0x0000000000001000UL |
952 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_SHFT 13 |
953 | #define UVYH_EVENT_OCCURRED1_XH_TLB_INT5_MASK 0x0000000000002000UL |
954 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_SHFT 14 |
955 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT0_MASK 0x0000000000004000UL |
956 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_SHFT 15 |
957 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT1_MASK 0x0000000000008000UL |
958 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_SHFT 16 |
959 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT2_MASK 0x0000000000010000UL |
960 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_SHFT 17 |
961 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT3_MASK 0x0000000000020000UL |
962 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_SHFT 18 |
963 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT4_MASK 0x0000000000040000UL |
964 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_SHFT 19 |
965 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT5_MASK 0x0000000000080000UL |
966 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_SHFT 20 |
967 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT6_MASK 0x0000000000100000UL |
968 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_SHFT 21 |
969 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT7_MASK 0x0000000000200000UL |
970 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_SHFT 22 |
971 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT8_MASK 0x0000000000400000UL |
972 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_SHFT 23 |
973 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT9_MASK 0x0000000000800000UL |
974 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_SHFT 24 |
975 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT10_MASK 0x0000000001000000UL |
976 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_SHFT 25 |
977 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT11_MASK 0x0000000002000000UL |
978 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_SHFT 26 |
979 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT12_MASK 0x0000000004000000UL |
980 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_SHFT 27 |
981 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT13_MASK 0x0000000008000000UL |
982 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_SHFT 28 |
983 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT14_MASK 0x0000000010000000UL |
984 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_SHFT 29 |
985 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT15_MASK 0x0000000020000000UL |
986 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_SHFT 30 |
987 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT16_MASK 0x0000000040000000UL |
988 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_SHFT 31 |
989 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT17_MASK 0x0000000080000000UL |
990 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_SHFT 32 |
991 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT18_MASK 0x0000000100000000UL |
992 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_SHFT 33 |
993 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT19_MASK 0x0000000200000000UL |
994 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_SHFT 34 |
995 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT20_MASK 0x0000000400000000UL |
996 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_SHFT 35 |
997 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT21_MASK 0x0000000800000000UL |
998 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_SHFT 36 |
999 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT22_MASK 0x0000001000000000UL |
1000 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_SHFT 37 |
1001 | #define UVYH_EVENT_OCCURRED1_RDM_TLB_INT23_MASK 0x0000002000000000UL |
1002 | |
1003 | /* UV4 unique defines */ |
1004 | #define UV4H_EVENT_OCCURRED1_PROFILE_INT_SHFT 0 |
1005 | #define UV4H_EVENT_OCCURRED1_PROFILE_INT_MASK 0x0000000000000001UL |
1006 | #define UV4H_EVENT_OCCURRED1_BAU_DATA_SHFT 1 |
1007 | #define UV4H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000002UL |
1008 | #define UV4H_EVENT_OCCURRED1_PROC_GENERAL_SHFT 2 |
1009 | #define UV4H_EVENT_OCCURRED1_PROC_GENERAL_MASK 0x0000000000000004UL |
1010 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT 3 |
1011 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000000008UL |
1012 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT 4 |
1013 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000000010UL |
1014 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT 5 |
1015 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000000020UL |
1016 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT 6 |
1017 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000000040UL |
1018 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT 7 |
1019 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000000080UL |
1020 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT 8 |
1021 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000000100UL |
1022 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT 9 |
1023 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000000000200UL |
1024 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT 10 |
1025 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000000000400UL |
1026 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT 11 |
1027 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000000000800UL |
1028 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT 12 |
1029 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000000001000UL |
1030 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT 13 |
1031 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000000002000UL |
1032 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT 14 |
1033 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000000004000UL |
1034 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT 15 |
1035 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000000008000UL |
1036 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT 16 |
1037 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000000010000UL |
1038 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT 17 |
1039 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000000020000UL |
1040 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT 18 |
1041 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000000040000UL |
1042 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_SHFT 19 |
1043 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT16_MASK 0x0000000000080000UL |
1044 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_SHFT 20 |
1045 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT17_MASK 0x0000000000100000UL |
1046 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_SHFT 21 |
1047 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT18_MASK 0x0000000000200000UL |
1048 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_SHFT 22 |
1049 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT19_MASK 0x0000000000400000UL |
1050 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_SHFT 23 |
1051 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT20_MASK 0x0000000000800000UL |
1052 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_SHFT 24 |
1053 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT21_MASK 0x0000000001000000UL |
1054 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_SHFT 25 |
1055 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT22_MASK 0x0000000002000000UL |
1056 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_SHFT 26 |
1057 | #define UV4H_EVENT_OCCURRED1_GR0_TLB_INT23_MASK 0x0000000004000000UL |
1058 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT 27 |
1059 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000008000000UL |
1060 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT 28 |
1061 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000010000000UL |
1062 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT 29 |
1063 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000000020000000UL |
1064 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT 30 |
1065 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000000040000000UL |
1066 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT 31 |
1067 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000000080000000UL |
1068 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT 32 |
1069 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000000100000000UL |
1070 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT 33 |
1071 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000000200000000UL |
1072 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT 34 |
1073 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000000400000000UL |
1074 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT 35 |
1075 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000000800000000UL |
1076 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT 36 |
1077 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000001000000000UL |
1078 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT 37 |
1079 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000002000000000UL |
1080 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT 38 |
1081 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000004000000000UL |
1082 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT 39 |
1083 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000008000000000UL |
1084 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT 40 |
1085 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000010000000000UL |
1086 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT 41 |
1087 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0000020000000000UL |
1088 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT 42 |
1089 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0000040000000000UL |
1090 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_SHFT 43 |
1091 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT16_MASK 0x0000080000000000UL |
1092 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_SHFT 44 |
1093 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT17_MASK 0x0000100000000000UL |
1094 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_SHFT 45 |
1095 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT18_MASK 0x0000200000000000UL |
1096 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_SHFT 46 |
1097 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT19_MASK 0x0000400000000000UL |
1098 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_SHFT 47 |
1099 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT20_MASK 0x0000800000000000UL |
1100 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_SHFT 48 |
1101 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT21_MASK 0x0001000000000000UL |
1102 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_SHFT 49 |
1103 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT22_MASK 0x0002000000000000UL |
1104 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_SHFT 50 |
1105 | #define UV4H_EVENT_OCCURRED1_GR1_TLB_INT23_MASK 0x0004000000000000UL |
1106 | |
1107 | /* UV3 unique defines */ |
1108 | #define UV3H_EVENT_OCCURRED1_BAU_DATA_SHFT 0 |
1109 | #define UV3H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000001UL |
1110 | #define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT 1 |
1111 | #define UV3H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL |
1112 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2 |
1113 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL |
1114 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3 |
1115 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL |
1116 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4 |
1117 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL |
1118 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5 |
1119 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL |
1120 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6 |
1121 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL |
1122 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7 |
1123 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL |
1124 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8 |
1125 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL |
1126 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9 |
1127 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL |
1128 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10 |
1129 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL |
1130 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11 |
1131 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL |
1132 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12 |
1133 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL |
1134 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13 |
1135 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL |
1136 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14 |
1137 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL |
1138 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15 |
1139 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL |
1140 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16 |
1141 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL |
1142 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17 |
1143 | #define UV3H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL |
1144 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT 18 |
1145 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000040000UL |
1146 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT 19 |
1147 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000080000UL |
1148 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT 20 |
1149 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000100000UL |
1150 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT 21 |
1151 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000200000UL |
1152 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT 22 |
1153 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000400000UL |
1154 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT 23 |
1155 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000800000UL |
1156 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT 24 |
1157 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000001000000UL |
1158 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT 25 |
1159 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000002000000UL |
1160 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT 26 |
1161 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000004000000UL |
1162 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT 27 |
1163 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000008000000UL |
1164 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT 28 |
1165 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000010000000UL |
1166 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT 29 |
1167 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000020000000UL |
1168 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT 30 |
1169 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000040000000UL |
1170 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT 31 |
1171 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000080000000UL |
1172 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT 32 |
1173 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000100000000UL |
1174 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT 33 |
1175 | #define UV3H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000200000000UL |
1176 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT 34 |
1177 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000400000000UL |
1178 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT 35 |
1179 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000800000000UL |
1180 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT 36 |
1181 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000001000000000UL |
1182 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT 37 |
1183 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000002000000000UL |
1184 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT 38 |
1185 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000004000000000UL |
1186 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT 39 |
1187 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000008000000000UL |
1188 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT 40 |
1189 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000010000000000UL |
1190 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT 41 |
1191 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000020000000000UL |
1192 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT 42 |
1193 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000040000000000UL |
1194 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT 43 |
1195 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000080000000000UL |
1196 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT 44 |
1197 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000100000000000UL |
1198 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT 45 |
1199 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000200000000000UL |
1200 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT 46 |
1201 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000400000000000UL |
1202 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT 47 |
1203 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000800000000000UL |
1204 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT 48 |
1205 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0001000000000000UL |
1206 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT 49 |
1207 | #define UV3H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0002000000000000UL |
1208 | #define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT 50 |
1209 | #define UV3H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK 0x0004000000000000UL |
1210 | #define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT 51 |
1211 | #define UV3H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK 0x0008000000000000UL |
1212 | |
1213 | /* UV2 unique defines */ |
1214 | #define UV2H_EVENT_OCCURRED1_BAU_DATA_SHFT 0 |
1215 | #define UV2H_EVENT_OCCURRED1_BAU_DATA_MASK 0x0000000000000001UL |
1216 | #define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_SHFT 1 |
1217 | #define UV2H_EVENT_OCCURRED1_POWER_MANAGEMENT_REQ_MASK 0x0000000000000002UL |
1218 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_SHFT 2 |
1219 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000004UL |
1220 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_SHFT 3 |
1221 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000008UL |
1222 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_SHFT 4 |
1223 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000010UL |
1224 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_SHFT 5 |
1225 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000020UL |
1226 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_SHFT 6 |
1227 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000040UL |
1228 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_SHFT 7 |
1229 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000080UL |
1230 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_SHFT 8 |
1231 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000100UL |
1232 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_SHFT 9 |
1233 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000200UL |
1234 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_SHFT 10 |
1235 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000400UL |
1236 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_SHFT 11 |
1237 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000800UL |
1238 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_SHFT 12 |
1239 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000001000UL |
1240 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_SHFT 13 |
1241 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000002000UL |
1242 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_SHFT 14 |
1243 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000004000UL |
1244 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_SHFT 15 |
1245 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000008000UL |
1246 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_SHFT 16 |
1247 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000010000UL |
1248 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_SHFT 17 |
1249 | #define UV2H_EVENT_OCCURRED1_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000020000UL |
1250 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_SHFT 18 |
1251 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT0_MASK 0x0000000000040000UL |
1252 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_SHFT 19 |
1253 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT1_MASK 0x0000000000080000UL |
1254 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_SHFT 20 |
1255 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT2_MASK 0x0000000000100000UL |
1256 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_SHFT 21 |
1257 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT3_MASK 0x0000000000200000UL |
1258 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_SHFT 22 |
1259 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT4_MASK 0x0000000000400000UL |
1260 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_SHFT 23 |
1261 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT5_MASK 0x0000000000800000UL |
1262 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_SHFT 24 |
1263 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT6_MASK 0x0000000001000000UL |
1264 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_SHFT 25 |
1265 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT7_MASK 0x0000000002000000UL |
1266 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_SHFT 26 |
1267 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT8_MASK 0x0000000004000000UL |
1268 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_SHFT 27 |
1269 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT9_MASK 0x0000000008000000UL |
1270 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_SHFT 28 |
1271 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT10_MASK 0x0000000010000000UL |
1272 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_SHFT 29 |
1273 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT11_MASK 0x0000000020000000UL |
1274 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_SHFT 30 |
1275 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT12_MASK 0x0000000040000000UL |
1276 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_SHFT 31 |
1277 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT13_MASK 0x0000000080000000UL |
1278 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_SHFT 32 |
1279 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT14_MASK 0x0000000100000000UL |
1280 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_SHFT 33 |
1281 | #define UV2H_EVENT_OCCURRED1_GR0_TLB_INT15_MASK 0x0000000200000000UL |
1282 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_SHFT 34 |
1283 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT0_MASK 0x0000000400000000UL |
1284 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_SHFT 35 |
1285 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT1_MASK 0x0000000800000000UL |
1286 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_SHFT 36 |
1287 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT2_MASK 0x0000001000000000UL |
1288 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_SHFT 37 |
1289 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT3_MASK 0x0000002000000000UL |
1290 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_SHFT 38 |
1291 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT4_MASK 0x0000004000000000UL |
1292 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_SHFT 39 |
1293 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT5_MASK 0x0000008000000000UL |
1294 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_SHFT 40 |
1295 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT6_MASK 0x0000010000000000UL |
1296 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_SHFT 41 |
1297 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT7_MASK 0x0000020000000000UL |
1298 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_SHFT 42 |
1299 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT8_MASK 0x0000040000000000UL |
1300 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_SHFT 43 |
1301 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT9_MASK 0x0000080000000000UL |
1302 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_SHFT 44 |
1303 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT10_MASK 0x0000100000000000UL |
1304 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_SHFT 45 |
1305 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT11_MASK 0x0000200000000000UL |
1306 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_SHFT 46 |
1307 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT12_MASK 0x0000400000000000UL |
1308 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_SHFT 47 |
1309 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT13_MASK 0x0000800000000000UL |
1310 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_SHFT 48 |
1311 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT14_MASK 0x0001000000000000UL |
1312 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_SHFT 49 |
1313 | #define UV2H_EVENT_OCCURRED1_GR1_TLB_INT15_MASK 0x0002000000000000UL |
1314 | #define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_SHFT 50 |
1315 | #define UV2H_EVENT_OCCURRED1_RTC_INTERVAL_INT_MASK 0x0004000000000000UL |
1316 | #define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_SHFT 51 |
1317 | #define UV2H_EVENT_OCCURRED1_BAU_DASHBOARD_INT_MASK 0x0008000000000000UL |
1318 | |
1319 | #define UVH_EVENT_OCCURRED1_EXTIO_INT0_MASK ( \ |
1320 | is_uv(UV5) ? 0x0000000000000002UL : \ |
1321 | 0) |
1322 | #define UVH_EVENT_OCCURRED1_EXTIO_INT0_SHFT ( \ |
1323 | is_uv(UV5) ? 1 : \ |
1324 | -1) |
1325 | |
1326 | union uvyh_event_occurred1_u { |
1327 | unsigned long v; |
1328 | |
1329 | /* UVYH common struct */ |
1330 | struct uvyh_event_occurred1_s { |
1331 | unsigned long ipi_int:1; /* RW */ |
1332 | unsigned long extio_int0:1; /* RW */ |
1333 | unsigned long extio_int1:1; /* RW */ |
1334 | unsigned long extio_int2:1; /* RW */ |
1335 | unsigned long extio_int3:1; /* RW */ |
1336 | unsigned long profile_int:1; /* RW */ |
1337 | unsigned long bau_data:1; /* RW */ |
1338 | unsigned long proc_general:1; /* RW */ |
1339 | unsigned long xh_tlb_int0:1; /* RW */ |
1340 | unsigned long xh_tlb_int1:1; /* RW */ |
1341 | unsigned long xh_tlb_int2:1; /* RW */ |
1342 | unsigned long xh_tlb_int3:1; /* RW */ |
1343 | unsigned long xh_tlb_int4:1; /* RW */ |
1344 | unsigned long xh_tlb_int5:1; /* RW */ |
1345 | unsigned long rdm_tlb_int0:1; /* RW */ |
1346 | unsigned long rdm_tlb_int1:1; /* RW */ |
1347 | unsigned long rdm_tlb_int2:1; /* RW */ |
1348 | unsigned long rdm_tlb_int3:1; /* RW */ |
1349 | unsigned long rdm_tlb_int4:1; /* RW */ |
1350 | unsigned long rdm_tlb_int5:1; /* RW */ |
1351 | unsigned long rdm_tlb_int6:1; /* RW */ |
1352 | unsigned long rdm_tlb_int7:1; /* RW */ |
1353 | unsigned long rdm_tlb_int8:1; /* RW */ |
1354 | unsigned long rdm_tlb_int9:1; /* RW */ |
1355 | unsigned long rdm_tlb_int10:1; /* RW */ |
1356 | unsigned long rdm_tlb_int11:1; /* RW */ |
1357 | unsigned long rdm_tlb_int12:1; /* RW */ |
1358 | unsigned long rdm_tlb_int13:1; /* RW */ |
1359 | unsigned long rdm_tlb_int14:1; /* RW */ |
1360 | unsigned long rdm_tlb_int15:1; /* RW */ |
1361 | unsigned long rdm_tlb_int16:1; /* RW */ |
1362 | unsigned long rdm_tlb_int17:1; /* RW */ |
1363 | unsigned long rdm_tlb_int18:1; /* RW */ |
1364 | unsigned long rdm_tlb_int19:1; /* RW */ |
1365 | unsigned long rdm_tlb_int20:1; /* RW */ |
1366 | unsigned long rdm_tlb_int21:1; /* RW */ |
1367 | unsigned long rdm_tlb_int22:1; /* RW */ |
1368 | unsigned long rdm_tlb_int23:1; /* RW */ |
1369 | unsigned long rsvd_38_63:26; |
1370 | } sy; |
1371 | |
1372 | /* UV5 unique struct */ |
1373 | struct uv5h_event_occurred1_s { |
1374 | unsigned long ipi_int:1; /* RW */ |
1375 | unsigned long extio_int0:1; /* RW */ |
1376 | unsigned long extio_int1:1; /* RW */ |
1377 | unsigned long extio_int2:1; /* RW */ |
1378 | unsigned long extio_int3:1; /* RW */ |
1379 | unsigned long profile_int:1; /* RW */ |
1380 | unsigned long bau_data:1; /* RW */ |
1381 | unsigned long proc_general:1; /* RW */ |
1382 | unsigned long xh_tlb_int0:1; /* RW */ |
1383 | unsigned long xh_tlb_int1:1; /* RW */ |
1384 | unsigned long xh_tlb_int2:1; /* RW */ |
1385 | unsigned long xh_tlb_int3:1; /* RW */ |
1386 | unsigned long xh_tlb_int4:1; /* RW */ |
1387 | unsigned long xh_tlb_int5:1; /* RW */ |
1388 | unsigned long rdm_tlb_int0:1; /* RW */ |
1389 | unsigned long rdm_tlb_int1:1; /* RW */ |
1390 | unsigned long rdm_tlb_int2:1; /* RW */ |
1391 | unsigned long rdm_tlb_int3:1; /* RW */ |
1392 | unsigned long rdm_tlb_int4:1; /* RW */ |
1393 | unsigned long rdm_tlb_int5:1; /* RW */ |
1394 | unsigned long rdm_tlb_int6:1; /* RW */ |
1395 | unsigned long rdm_tlb_int7:1; /* RW */ |
1396 | unsigned long rdm_tlb_int8:1; /* RW */ |
1397 | unsigned long rdm_tlb_int9:1; /* RW */ |
1398 | unsigned long rdm_tlb_int10:1; /* RW */ |
1399 | unsigned long rdm_tlb_int11:1; /* RW */ |
1400 | unsigned long rdm_tlb_int12:1; /* RW */ |
1401 | unsigned long rdm_tlb_int13:1; /* RW */ |
1402 | unsigned long rdm_tlb_int14:1; /* RW */ |
1403 | unsigned long rdm_tlb_int15:1; /* RW */ |
1404 | unsigned long rdm_tlb_int16:1; /* RW */ |
1405 | unsigned long rdm_tlb_int17:1; /* RW */ |
1406 | unsigned long rdm_tlb_int18:1; /* RW */ |
1407 | unsigned long rdm_tlb_int19:1; /* RW */ |
1408 | unsigned long rdm_tlb_int20:1; /* RW */ |
1409 | unsigned long rdm_tlb_int21:1; /* RW */ |
1410 | unsigned long rdm_tlb_int22:1; /* RW */ |
1411 | unsigned long rdm_tlb_int23:1; /* RW */ |
1412 | unsigned long rsvd_38_63:26; |
1413 | } s5; |
1414 | |
1415 | /* UV4 unique struct */ |
1416 | struct uv4h_event_occurred1_s { |
1417 | unsigned long profile_int:1; /* RW */ |
1418 | unsigned long bau_data:1; /* RW */ |
1419 | unsigned long proc_general:1; /* RW */ |
1420 | unsigned long gr0_tlb_int0:1; /* RW */ |
1421 | unsigned long gr0_tlb_int1:1; /* RW */ |
1422 | unsigned long gr0_tlb_int2:1; /* RW */ |
1423 | unsigned long gr0_tlb_int3:1; /* RW */ |
1424 | unsigned long gr0_tlb_int4:1; /* RW */ |
1425 | unsigned long gr0_tlb_int5:1; /* RW */ |
1426 | unsigned long gr0_tlb_int6:1; /* RW */ |
1427 | unsigned long gr0_tlb_int7:1; /* RW */ |
1428 | unsigned long gr0_tlb_int8:1; /* RW */ |
1429 | unsigned long gr0_tlb_int9:1; /* RW */ |
1430 | unsigned long gr0_tlb_int10:1; /* RW */ |
1431 | unsigned long gr0_tlb_int11:1; /* RW */ |
1432 | unsigned long gr0_tlb_int12:1; /* RW */ |
1433 | unsigned long gr0_tlb_int13:1; /* RW */ |
1434 | unsigned long gr0_tlb_int14:1; /* RW */ |
1435 | unsigned long gr0_tlb_int15:1; /* RW */ |
1436 | unsigned long gr0_tlb_int16:1; /* RW */ |
1437 | unsigned long gr0_tlb_int17:1; /* RW */ |
1438 | unsigned long gr0_tlb_int18:1; /* RW */ |
1439 | unsigned long gr0_tlb_int19:1; /* RW */ |
1440 | unsigned long gr0_tlb_int20:1; /* RW */ |
1441 | unsigned long gr0_tlb_int21:1; /* RW */ |
1442 | unsigned long gr0_tlb_int22:1; /* RW */ |
1443 | unsigned long gr0_tlb_int23:1; /* RW */ |
1444 | unsigned long gr1_tlb_int0:1; /* RW */ |
1445 | unsigned long gr1_tlb_int1:1; /* RW */ |
1446 | unsigned long gr1_tlb_int2:1; /* RW */ |
1447 | unsigned long gr1_tlb_int3:1; /* RW */ |
1448 | unsigned long gr1_tlb_int4:1; /* RW */ |
1449 | unsigned long gr1_tlb_int5:1; /* RW */ |
1450 | unsigned long gr1_tlb_int6:1; /* RW */ |
1451 | unsigned long gr1_tlb_int7:1; /* RW */ |
1452 | unsigned long gr1_tlb_int8:1; /* RW */ |
1453 | unsigned long gr1_tlb_int9:1; /* RW */ |
1454 | unsigned long gr1_tlb_int10:1; /* RW */ |
1455 | unsigned long gr1_tlb_int11:1; /* RW */ |
1456 | unsigned long gr1_tlb_int12:1; /* RW */ |
1457 | unsigned long gr1_tlb_int13:1; /* RW */ |
1458 | unsigned long gr1_tlb_int14:1; /* RW */ |
1459 | unsigned long gr1_tlb_int15:1; /* RW */ |
1460 | unsigned long gr1_tlb_int16:1; /* RW */ |
1461 | unsigned long gr1_tlb_int17:1; /* RW */ |
1462 | unsigned long gr1_tlb_int18:1; /* RW */ |
1463 | unsigned long gr1_tlb_int19:1; /* RW */ |
1464 | unsigned long gr1_tlb_int20:1; /* RW */ |
1465 | unsigned long gr1_tlb_int21:1; /* RW */ |
1466 | unsigned long gr1_tlb_int22:1; /* RW */ |
1467 | unsigned long gr1_tlb_int23:1; /* RW */ |
1468 | unsigned long rsvd_51_63:13; |
1469 | } s4; |
1470 | |
1471 | /* UV3 unique struct */ |
1472 | struct uv3h_event_occurred1_s { |
1473 | unsigned long bau_data:1; /* RW */ |
1474 | unsigned long power_management_req:1; /* RW */ |
1475 | unsigned long message_accelerator_int0:1; /* RW */ |
1476 | unsigned long message_accelerator_int1:1; /* RW */ |
1477 | unsigned long message_accelerator_int2:1; /* RW */ |
1478 | unsigned long message_accelerator_int3:1; /* RW */ |
1479 | unsigned long message_accelerator_int4:1; /* RW */ |
1480 | unsigned long message_accelerator_int5:1; /* RW */ |
1481 | unsigned long message_accelerator_int6:1; /* RW */ |
1482 | unsigned long message_accelerator_int7:1; /* RW */ |
1483 | unsigned long message_accelerator_int8:1; /* RW */ |
1484 | unsigned long message_accelerator_int9:1; /* RW */ |
1485 | unsigned long message_accelerator_int10:1; /* RW */ |
1486 | unsigned long message_accelerator_int11:1; /* RW */ |
1487 | unsigned long message_accelerator_int12:1; /* RW */ |
1488 | unsigned long message_accelerator_int13:1; /* RW */ |
1489 | unsigned long message_accelerator_int14:1; /* RW */ |
1490 | unsigned long message_accelerator_int15:1; /* RW */ |
1491 | unsigned long gr0_tlb_int0:1; /* RW */ |
1492 | unsigned long gr0_tlb_int1:1; /* RW */ |
1493 | unsigned long gr0_tlb_int2:1; /* RW */ |
1494 | unsigned long gr0_tlb_int3:1; /* RW */ |
1495 | unsigned long gr0_tlb_int4:1; /* RW */ |
1496 | unsigned long gr0_tlb_int5:1; /* RW */ |
1497 | unsigned long gr0_tlb_int6:1; /* RW */ |
1498 | unsigned long gr0_tlb_int7:1; /* RW */ |
1499 | unsigned long gr0_tlb_int8:1; /* RW */ |
1500 | unsigned long gr0_tlb_int9:1; /* RW */ |
1501 | unsigned long gr0_tlb_int10:1; /* RW */ |
1502 | unsigned long gr0_tlb_int11:1; /* RW */ |
1503 | unsigned long gr0_tlb_int12:1; /* RW */ |
1504 | unsigned long gr0_tlb_int13:1; /* RW */ |
1505 | unsigned long gr0_tlb_int14:1; /* RW */ |
1506 | unsigned long gr0_tlb_int15:1; /* RW */ |
1507 | unsigned long gr1_tlb_int0:1; /* RW */ |
1508 | unsigned long gr1_tlb_int1:1; /* RW */ |
1509 | unsigned long gr1_tlb_int2:1; /* RW */ |
1510 | unsigned long gr1_tlb_int3:1; /* RW */ |
1511 | unsigned long gr1_tlb_int4:1; /* RW */ |
1512 | unsigned long gr1_tlb_int5:1; /* RW */ |
1513 | unsigned long gr1_tlb_int6:1; /* RW */ |
1514 | unsigned long gr1_tlb_int7:1; /* RW */ |
1515 | unsigned long gr1_tlb_int8:1; /* RW */ |
1516 | unsigned long gr1_tlb_int9:1; /* RW */ |
1517 | unsigned long gr1_tlb_int10:1; /* RW */ |
1518 | unsigned long gr1_tlb_int11:1; /* RW */ |
1519 | unsigned long gr1_tlb_int12:1; /* RW */ |
1520 | unsigned long gr1_tlb_int13:1; /* RW */ |
1521 | unsigned long gr1_tlb_int14:1; /* RW */ |
1522 | unsigned long gr1_tlb_int15:1; /* RW */ |
1523 | unsigned long rtc_interval_int:1; /* RW */ |
1524 | unsigned long bau_dashboard_int:1; /* RW */ |
1525 | unsigned long rsvd_52_63:12; |
1526 | } s3; |
1527 | |
1528 | /* UV2 unique struct */ |
1529 | struct uv2h_event_occurred1_s { |
1530 | unsigned long bau_data:1; /* RW */ |
1531 | unsigned long power_management_req:1; /* RW */ |
1532 | unsigned long message_accelerator_int0:1; /* RW */ |
1533 | unsigned long message_accelerator_int1:1; /* RW */ |
1534 | unsigned long message_accelerator_int2:1; /* RW */ |
1535 | unsigned long message_accelerator_int3:1; /* RW */ |
1536 | unsigned long message_accelerator_int4:1; /* RW */ |
1537 | unsigned long message_accelerator_int5:1; /* RW */ |
1538 | unsigned long message_accelerator_int6:1; /* RW */ |
1539 | unsigned long message_accelerator_int7:1; /* RW */ |
1540 | unsigned long message_accelerator_int8:1; /* RW */ |
1541 | unsigned long message_accelerator_int9:1; /* RW */ |
1542 | unsigned long message_accelerator_int10:1; /* RW */ |
1543 | unsigned long message_accelerator_int11:1; /* RW */ |
1544 | unsigned long message_accelerator_int12:1; /* RW */ |
1545 | unsigned long message_accelerator_int13:1; /* RW */ |
1546 | unsigned long message_accelerator_int14:1; /* RW */ |
1547 | unsigned long message_accelerator_int15:1; /* RW */ |
1548 | unsigned long gr0_tlb_int0:1; /* RW */ |
1549 | unsigned long gr0_tlb_int1:1; /* RW */ |
1550 | unsigned long gr0_tlb_int2:1; /* RW */ |
1551 | unsigned long gr0_tlb_int3:1; /* RW */ |
1552 | unsigned long gr0_tlb_int4:1; /* RW */ |
1553 | unsigned long gr0_tlb_int5:1; /* RW */ |
1554 | unsigned long gr0_tlb_int6:1; /* RW */ |
1555 | unsigned long gr0_tlb_int7:1; /* RW */ |
1556 | unsigned long gr0_tlb_int8:1; /* RW */ |
1557 | unsigned long gr0_tlb_int9:1; /* RW */ |
1558 | unsigned long gr0_tlb_int10:1; /* RW */ |
1559 | unsigned long gr0_tlb_int11:1; /* RW */ |
1560 | unsigned long gr0_tlb_int12:1; /* RW */ |
1561 | unsigned long gr0_tlb_int13:1; /* RW */ |
1562 | unsigned long gr0_tlb_int14:1; /* RW */ |
1563 | unsigned long gr0_tlb_int15:1; /* RW */ |
1564 | unsigned long gr1_tlb_int0:1; /* RW */ |
1565 | unsigned long gr1_tlb_int1:1; /* RW */ |
1566 | unsigned long gr1_tlb_int2:1; /* RW */ |
1567 | unsigned long gr1_tlb_int3:1; /* RW */ |
1568 | unsigned long gr1_tlb_int4:1; /* RW */ |
1569 | unsigned long gr1_tlb_int5:1; /* RW */ |
1570 | unsigned long gr1_tlb_int6:1; /* RW */ |
1571 | unsigned long gr1_tlb_int7:1; /* RW */ |
1572 | unsigned long gr1_tlb_int8:1; /* RW */ |
1573 | unsigned long gr1_tlb_int9:1; /* RW */ |
1574 | unsigned long gr1_tlb_int10:1; /* RW */ |
1575 | unsigned long gr1_tlb_int11:1; /* RW */ |
1576 | unsigned long gr1_tlb_int12:1; /* RW */ |
1577 | unsigned long gr1_tlb_int13:1; /* RW */ |
1578 | unsigned long gr1_tlb_int14:1; /* RW */ |
1579 | unsigned long gr1_tlb_int15:1; /* RW */ |
1580 | unsigned long rtc_interval_int:1; /* RW */ |
1581 | unsigned long bau_dashboard_int:1; /* RW */ |
1582 | unsigned long rsvd_52_63:12; |
1583 | } s2; |
1584 | }; |
1585 | |
1586 | /* ========================================================================= */ |
1587 | /* UVH_EVENT_OCCURRED1_ALIAS */ |
1588 | /* ========================================================================= */ |
1589 | #define UVH_EVENT_OCCURRED1_ALIAS 0x70088UL |
1590 | |
1591 | |
1592 | /* ========================================================================= */ |
1593 | /* UVH_EVENT_OCCURRED2 */ |
1594 | /* ========================================================================= */ |
1595 | #define UVH_EVENT_OCCURRED2 0x70100UL |
1596 | |
1597 | |
1598 | |
1599 | /* UVYH common defines */ |
1600 | #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 0 |
1601 | #define UVYH_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000000001UL |
1602 | #define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 1 |
1603 | #define UVYH_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000000002UL |
1604 | #define UVYH_EVENT_OCCURRED2_RTC_0_SHFT 2 |
1605 | #define UVYH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000004UL |
1606 | #define UVYH_EVENT_OCCURRED2_RTC_1_SHFT 3 |
1607 | #define UVYH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000008UL |
1608 | #define UVYH_EVENT_OCCURRED2_RTC_2_SHFT 4 |
1609 | #define UVYH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000010UL |
1610 | #define UVYH_EVENT_OCCURRED2_RTC_3_SHFT 5 |
1611 | #define UVYH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000020UL |
1612 | #define UVYH_EVENT_OCCURRED2_RTC_4_SHFT 6 |
1613 | #define UVYH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000040UL |
1614 | #define UVYH_EVENT_OCCURRED2_RTC_5_SHFT 7 |
1615 | #define UVYH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000080UL |
1616 | #define UVYH_EVENT_OCCURRED2_RTC_6_SHFT 8 |
1617 | #define UVYH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000100UL |
1618 | #define UVYH_EVENT_OCCURRED2_RTC_7_SHFT 9 |
1619 | #define UVYH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000200UL |
1620 | #define UVYH_EVENT_OCCURRED2_RTC_8_SHFT 10 |
1621 | #define UVYH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000400UL |
1622 | #define UVYH_EVENT_OCCURRED2_RTC_9_SHFT 11 |
1623 | #define UVYH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000800UL |
1624 | #define UVYH_EVENT_OCCURRED2_RTC_10_SHFT 12 |
1625 | #define UVYH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000001000UL |
1626 | #define UVYH_EVENT_OCCURRED2_RTC_11_SHFT 13 |
1627 | #define UVYH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000002000UL |
1628 | #define UVYH_EVENT_OCCURRED2_RTC_12_SHFT 14 |
1629 | #define UVYH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000004000UL |
1630 | #define UVYH_EVENT_OCCURRED2_RTC_13_SHFT 15 |
1631 | #define UVYH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000008000UL |
1632 | #define UVYH_EVENT_OCCURRED2_RTC_14_SHFT 16 |
1633 | #define UVYH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000010000UL |
1634 | #define UVYH_EVENT_OCCURRED2_RTC_15_SHFT 17 |
1635 | #define UVYH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000020000UL |
1636 | #define UVYH_EVENT_OCCURRED2_RTC_16_SHFT 18 |
1637 | #define UVYH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000040000UL |
1638 | #define UVYH_EVENT_OCCURRED2_RTC_17_SHFT 19 |
1639 | #define UVYH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000080000UL |
1640 | #define UVYH_EVENT_OCCURRED2_RTC_18_SHFT 20 |
1641 | #define UVYH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000100000UL |
1642 | #define UVYH_EVENT_OCCURRED2_RTC_19_SHFT 21 |
1643 | #define UVYH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000200000UL |
1644 | #define UVYH_EVENT_OCCURRED2_RTC_20_SHFT 22 |
1645 | #define UVYH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000400000UL |
1646 | #define UVYH_EVENT_OCCURRED2_RTC_21_SHFT 23 |
1647 | #define UVYH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000800000UL |
1648 | #define UVYH_EVENT_OCCURRED2_RTC_22_SHFT 24 |
1649 | #define UVYH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000001000000UL |
1650 | #define UVYH_EVENT_OCCURRED2_RTC_23_SHFT 25 |
1651 | #define UVYH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000002000000UL |
1652 | #define UVYH_EVENT_OCCURRED2_RTC_24_SHFT 26 |
1653 | #define UVYH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000004000000UL |
1654 | #define UVYH_EVENT_OCCURRED2_RTC_25_SHFT 27 |
1655 | #define UVYH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000008000000UL |
1656 | #define UVYH_EVENT_OCCURRED2_RTC_26_SHFT 28 |
1657 | #define UVYH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000010000000UL |
1658 | #define UVYH_EVENT_OCCURRED2_RTC_27_SHFT 29 |
1659 | #define UVYH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000020000000UL |
1660 | #define UVYH_EVENT_OCCURRED2_RTC_28_SHFT 30 |
1661 | #define UVYH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000040000000UL |
1662 | #define UVYH_EVENT_OCCURRED2_RTC_29_SHFT 31 |
1663 | #define UVYH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000080000000UL |
1664 | #define UVYH_EVENT_OCCURRED2_RTC_30_SHFT 32 |
1665 | #define UVYH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000100000000UL |
1666 | #define UVYH_EVENT_OCCURRED2_RTC_31_SHFT 33 |
1667 | #define UVYH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000200000000UL |
1668 | |
1669 | /* UV4 unique defines */ |
1670 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0 |
1671 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL |
1672 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1 |
1673 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL |
1674 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2 |
1675 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL |
1676 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3 |
1677 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL |
1678 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4 |
1679 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL |
1680 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5 |
1681 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL |
1682 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6 |
1683 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL |
1684 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7 |
1685 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL |
1686 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8 |
1687 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL |
1688 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9 |
1689 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL |
1690 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10 |
1691 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL |
1692 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11 |
1693 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL |
1694 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12 |
1695 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL |
1696 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13 |
1697 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL |
1698 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14 |
1699 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL |
1700 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15 |
1701 | #define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL |
1702 | #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16 |
1703 | #define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL |
1704 | #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17 |
1705 | #define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL |
1706 | #define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18 |
1707 | #define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL |
1708 | #define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19 |
1709 | #define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL |
1710 | #define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20 |
1711 | #define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL |
1712 | #define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21 |
1713 | #define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL |
1714 | #define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22 |
1715 | #define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL |
1716 | #define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23 |
1717 | #define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL |
1718 | #define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24 |
1719 | #define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL |
1720 | #define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25 |
1721 | #define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL |
1722 | #define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26 |
1723 | #define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL |
1724 | #define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27 |
1725 | #define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL |
1726 | #define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28 |
1727 | #define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL |
1728 | #define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29 |
1729 | #define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL |
1730 | #define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30 |
1731 | #define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL |
1732 | #define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31 |
1733 | #define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL |
1734 | #define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32 |
1735 | #define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL |
1736 | #define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33 |
1737 | #define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL |
1738 | #define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34 |
1739 | #define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL |
1740 | #define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35 |
1741 | #define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL |
1742 | #define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36 |
1743 | #define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL |
1744 | #define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37 |
1745 | #define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL |
1746 | #define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38 |
1747 | #define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL |
1748 | #define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39 |
1749 | #define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL |
1750 | #define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40 |
1751 | #define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL |
1752 | #define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41 |
1753 | #define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL |
1754 | #define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42 |
1755 | #define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL |
1756 | #define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43 |
1757 | #define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL |
1758 | #define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44 |
1759 | #define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL |
1760 | #define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45 |
1761 | #define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL |
1762 | #define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46 |
1763 | #define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL |
1764 | #define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47 |
1765 | #define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL |
1766 | #define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48 |
1767 | #define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL |
1768 | #define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49 |
1769 | #define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL |
1770 | |
1771 | /* UV3 unique defines */ |
1772 | #define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0 |
1773 | #define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL |
1774 | #define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1 |
1775 | #define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL |
1776 | #define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2 |
1777 | #define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL |
1778 | #define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3 |
1779 | #define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL |
1780 | #define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4 |
1781 | #define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL |
1782 | #define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5 |
1783 | #define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL |
1784 | #define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6 |
1785 | #define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL |
1786 | #define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7 |
1787 | #define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL |
1788 | #define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8 |
1789 | #define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL |
1790 | #define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9 |
1791 | #define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL |
1792 | #define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10 |
1793 | #define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL |
1794 | #define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11 |
1795 | #define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL |
1796 | #define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12 |
1797 | #define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL |
1798 | #define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13 |
1799 | #define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL |
1800 | #define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14 |
1801 | #define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL |
1802 | #define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15 |
1803 | #define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL |
1804 | #define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16 |
1805 | #define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL |
1806 | #define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17 |
1807 | #define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL |
1808 | #define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18 |
1809 | #define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL |
1810 | #define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19 |
1811 | #define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL |
1812 | #define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20 |
1813 | #define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL |
1814 | #define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21 |
1815 | #define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL |
1816 | #define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22 |
1817 | #define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL |
1818 | #define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23 |
1819 | #define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL |
1820 | #define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24 |
1821 | #define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL |
1822 | #define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25 |
1823 | #define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL |
1824 | #define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26 |
1825 | #define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL |
1826 | #define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27 |
1827 | #define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL |
1828 | #define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28 |
1829 | #define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL |
1830 | #define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29 |
1831 | #define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL |
1832 | #define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30 |
1833 | #define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL |
1834 | #define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31 |
1835 | #define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL |
1836 | |
1837 | /* UV2 unique defines */ |
1838 | #define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0 |
1839 | #define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL |
1840 | #define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1 |
1841 | #define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL |
1842 | #define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2 |
1843 | #define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL |
1844 | #define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3 |
1845 | #define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL |
1846 | #define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4 |
1847 | #define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL |
1848 | #define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5 |
1849 | #define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL |
1850 | #define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6 |
1851 | #define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL |
1852 | #define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7 |
1853 | #define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL |
1854 | #define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8 |
1855 | #define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL |
1856 | #define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9 |
1857 | #define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL |
1858 | #define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10 |
1859 | #define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL |
1860 | #define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11 |
1861 | #define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL |
1862 | #define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12 |
1863 | #define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL |
1864 | #define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13 |
1865 | #define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL |
1866 | #define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14 |
1867 | #define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL |
1868 | #define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15 |
1869 | #define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL |
1870 | #define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16 |
1871 | #define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL |
1872 | #define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17 |
1873 | #define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL |
1874 | #define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18 |
1875 | #define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL |
1876 | #define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19 |
1877 | #define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL |
1878 | #define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20 |
1879 | #define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL |
1880 | #define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21 |
1881 | #define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL |
1882 | #define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22 |
1883 | #define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL |
1884 | #define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23 |
1885 | #define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL |
1886 | #define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24 |
1887 | #define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL |
1888 | #define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25 |
1889 | #define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL |
1890 | #define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26 |
1891 | #define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL |
1892 | #define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27 |
1893 | #define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL |
1894 | #define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28 |
1895 | #define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL |
1896 | #define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29 |
1897 | #define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL |
1898 | #define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30 |
1899 | #define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL |
1900 | #define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31 |
1901 | #define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL |
1902 | |
1903 | #define UVH_EVENT_OCCURRED2_RTC_1_MASK ( \ |
1904 | is_uv(UV5) ? 0x0000000000000008UL : \ |
1905 | is_uv(UV4) ? 0x0000000000080000UL : \ |
1906 | is_uv(UV3) ? 0x0000000000000002UL : \ |
1907 | is_uv(UV2) ? 0x0000000000000002UL : \ |
1908 | 0) |
1909 | #define UVH_EVENT_OCCURRED2_RTC_1_SHFT ( \ |
1910 | is_uv(UV5) ? 3 : \ |
1911 | is_uv(UV4) ? 19 : \ |
1912 | is_uv(UV3) ? 1 : \ |
1913 | is_uv(UV2) ? 1 : \ |
1914 | -1) |
1915 | |
1916 | union uvyh_event_occurred2_u { |
1917 | unsigned long v; |
1918 | |
1919 | /* UVYH common struct */ |
1920 | struct uvyh_event_occurred2_s { |
1921 | unsigned long rtc_interval_int:1; /* RW */ |
1922 | unsigned long bau_dashboard_int:1; /* RW */ |
1923 | unsigned long rtc_0:1; /* RW */ |
1924 | unsigned long rtc_1:1; /* RW */ |
1925 | unsigned long rtc_2:1; /* RW */ |
1926 | unsigned long rtc_3:1; /* RW */ |
1927 | unsigned long rtc_4:1; /* RW */ |
1928 | unsigned long rtc_5:1; /* RW */ |
1929 | unsigned long rtc_6:1; /* RW */ |
1930 | unsigned long rtc_7:1; /* RW */ |
1931 | unsigned long rtc_8:1; /* RW */ |
1932 | unsigned long rtc_9:1; /* RW */ |
1933 | unsigned long rtc_10:1; /* RW */ |
1934 | unsigned long rtc_11:1; /* RW */ |
1935 | unsigned long rtc_12:1; /* RW */ |
1936 | unsigned long rtc_13:1; /* RW */ |
1937 | unsigned long rtc_14:1; /* RW */ |
1938 | unsigned long rtc_15:1; /* RW */ |
1939 | unsigned long rtc_16:1; /* RW */ |
1940 | unsigned long rtc_17:1; /* RW */ |
1941 | unsigned long rtc_18:1; /* RW */ |
1942 | unsigned long rtc_19:1; /* RW */ |
1943 | unsigned long rtc_20:1; /* RW */ |
1944 | unsigned long rtc_21:1; /* RW */ |
1945 | unsigned long rtc_22:1; /* RW */ |
1946 | unsigned long rtc_23:1; /* RW */ |
1947 | unsigned long rtc_24:1; /* RW */ |
1948 | unsigned long rtc_25:1; /* RW */ |
1949 | unsigned long rtc_26:1; /* RW */ |
1950 | unsigned long rtc_27:1; /* RW */ |
1951 | unsigned long rtc_28:1; /* RW */ |
1952 | unsigned long rtc_29:1; /* RW */ |
1953 | unsigned long rtc_30:1; /* RW */ |
1954 | unsigned long rtc_31:1; /* RW */ |
1955 | unsigned long rsvd_34_63:30; |
1956 | } sy; |
1957 | |
1958 | /* UV5 unique struct */ |
1959 | struct uv5h_event_occurred2_s { |
1960 | unsigned long rtc_interval_int:1; /* RW */ |
1961 | unsigned long bau_dashboard_int:1; /* RW */ |
1962 | unsigned long rtc_0:1; /* RW */ |
1963 | unsigned long rtc_1:1; /* RW */ |
1964 | unsigned long rtc_2:1; /* RW */ |
1965 | unsigned long rtc_3:1; /* RW */ |
1966 | unsigned long rtc_4:1; /* RW */ |
1967 | unsigned long rtc_5:1; /* RW */ |
1968 | unsigned long rtc_6:1; /* RW */ |
1969 | unsigned long rtc_7:1; /* RW */ |
1970 | unsigned long rtc_8:1; /* RW */ |
1971 | unsigned long rtc_9:1; /* RW */ |
1972 | unsigned long rtc_10:1; /* RW */ |
1973 | unsigned long rtc_11:1; /* RW */ |
1974 | unsigned long rtc_12:1; /* RW */ |
1975 | unsigned long rtc_13:1; /* RW */ |
1976 | unsigned long rtc_14:1; /* RW */ |
1977 | unsigned long rtc_15:1; /* RW */ |
1978 | unsigned long rtc_16:1; /* RW */ |
1979 | unsigned long rtc_17:1; /* RW */ |
1980 | unsigned long rtc_18:1; /* RW */ |
1981 | unsigned long rtc_19:1; /* RW */ |
1982 | unsigned long rtc_20:1; /* RW */ |
1983 | unsigned long rtc_21:1; /* RW */ |
1984 | unsigned long rtc_22:1; /* RW */ |
1985 | unsigned long rtc_23:1; /* RW */ |
1986 | unsigned long rtc_24:1; /* RW */ |
1987 | unsigned long rtc_25:1; /* RW */ |
1988 | unsigned long rtc_26:1; /* RW */ |
1989 | unsigned long rtc_27:1; /* RW */ |
1990 | unsigned long rtc_28:1; /* RW */ |
1991 | unsigned long rtc_29:1; /* RW */ |
1992 | unsigned long rtc_30:1; /* RW */ |
1993 | unsigned long rtc_31:1; /* RW */ |
1994 | unsigned long rsvd_34_63:30; |
1995 | } s5; |
1996 | |
1997 | /* UV4 unique struct */ |
1998 | struct uv4h_event_occurred2_s { |
1999 | unsigned long message_accelerator_int0:1; /* RW */ |
2000 | unsigned long message_accelerator_int1:1; /* RW */ |
2001 | unsigned long message_accelerator_int2:1; /* RW */ |
2002 | unsigned long message_accelerator_int3:1; /* RW */ |
2003 | unsigned long message_accelerator_int4:1; /* RW */ |
2004 | unsigned long message_accelerator_int5:1; /* RW */ |
2005 | unsigned long message_accelerator_int6:1; /* RW */ |
2006 | unsigned long message_accelerator_int7:1; /* RW */ |
2007 | unsigned long message_accelerator_int8:1; /* RW */ |
2008 | unsigned long message_accelerator_int9:1; /* RW */ |
2009 | unsigned long message_accelerator_int10:1; /* RW */ |
2010 | unsigned long message_accelerator_int11:1; /* RW */ |
2011 | unsigned long message_accelerator_int12:1; /* RW */ |
2012 | unsigned long message_accelerator_int13:1; /* RW */ |
2013 | unsigned long message_accelerator_int14:1; /* RW */ |
2014 | unsigned long message_accelerator_int15:1; /* RW */ |
2015 | unsigned long rtc_interval_int:1; /* RW */ |
2016 | unsigned long bau_dashboard_int:1; /* RW */ |
2017 | unsigned long rtc_0:1; /* RW */ |
2018 | unsigned long rtc_1:1; /* RW */ |
2019 | unsigned long rtc_2:1; /* RW */ |
2020 | unsigned long rtc_3:1; /* RW */ |
2021 | unsigned long rtc_4:1; /* RW */ |
2022 | unsigned long rtc_5:1; /* RW */ |
2023 | unsigned long rtc_6:1; /* RW */ |
2024 | unsigned long rtc_7:1; /* RW */ |
2025 | unsigned long rtc_8:1; /* RW */ |
2026 | unsigned long rtc_9:1; /* RW */ |
2027 | unsigned long rtc_10:1; /* RW */ |
2028 | unsigned long rtc_11:1; /* RW */ |
2029 | unsigned long rtc_12:1; /* RW */ |
2030 | unsigned long rtc_13:1; /* RW */ |
2031 | unsigned long rtc_14:1; /* RW */ |
2032 | unsigned long rtc_15:1; /* RW */ |
2033 | unsigned long rtc_16:1; /* RW */ |
2034 | unsigned long rtc_17:1; /* RW */ |
2035 | unsigned long rtc_18:1; /* RW */ |
2036 | unsigned long rtc_19:1; /* RW */ |
2037 | unsigned long rtc_20:1; /* RW */ |
2038 | unsigned long rtc_21:1; /* RW */ |
2039 | unsigned long rtc_22:1; /* RW */ |
2040 | unsigned long rtc_23:1; /* RW */ |
2041 | unsigned long rtc_24:1; /* RW */ |
2042 | unsigned long rtc_25:1; /* RW */ |
2043 | unsigned long rtc_26:1; /* RW */ |
2044 | unsigned long rtc_27:1; /* RW */ |
2045 | unsigned long rtc_28:1; /* RW */ |
2046 | unsigned long rtc_29:1; /* RW */ |
2047 | unsigned long rtc_30:1; /* RW */ |
2048 | unsigned long rtc_31:1; /* RW */ |
2049 | unsigned long rsvd_50_63:14; |
2050 | } s4; |
2051 | |
2052 | /* UV3 unique struct */ |
2053 | struct uv3h_event_occurred2_s { |
2054 | unsigned long rtc_0:1; /* RW */ |
2055 | unsigned long rtc_1:1; /* RW */ |
2056 | unsigned long rtc_2:1; /* RW */ |
2057 | unsigned long rtc_3:1; /* RW */ |
2058 | unsigned long rtc_4:1; /* RW */ |
2059 | unsigned long rtc_5:1; /* RW */ |
2060 | unsigned long rtc_6:1; /* RW */ |
2061 | unsigned long rtc_7:1; /* RW */ |
2062 | unsigned long rtc_8:1; /* RW */ |
2063 | unsigned long rtc_9:1; /* RW */ |
2064 | unsigned long rtc_10:1; /* RW */ |
2065 | unsigned long rtc_11:1; /* RW */ |
2066 | unsigned long rtc_12:1; /* RW */ |
2067 | unsigned long rtc_13:1; /* RW */ |
2068 | unsigned long rtc_14:1; /* RW */ |
2069 | unsigned long rtc_15:1; /* RW */ |
2070 | unsigned long rtc_16:1; /* RW */ |
2071 | unsigned long rtc_17:1; /* RW */ |
2072 | unsigned long rtc_18:1; /* RW */ |
2073 | unsigned long rtc_19:1; /* RW */ |
2074 | unsigned long rtc_20:1; /* RW */ |
2075 | unsigned long rtc_21:1; /* RW */ |
2076 | unsigned long rtc_22:1; /* RW */ |
2077 | unsigned long rtc_23:1; /* RW */ |
2078 | unsigned long rtc_24:1; /* RW */ |
2079 | unsigned long rtc_25:1; /* RW */ |
2080 | unsigned long rtc_26:1; /* RW */ |
2081 | unsigned long rtc_27:1; /* RW */ |
2082 | unsigned long rtc_28:1; /* RW */ |
2083 | unsigned long rtc_29:1; /* RW */ |
2084 | unsigned long rtc_30:1; /* RW */ |
2085 | unsigned long rtc_31:1; /* RW */ |
2086 | unsigned long rsvd_32_63:32; |
2087 | } s3; |
2088 | |
2089 | /* UV2 unique struct */ |
2090 | struct uv2h_event_occurred2_s { |
2091 | unsigned long rtc_0:1; /* RW */ |
2092 | unsigned long rtc_1:1; /* RW */ |
2093 | unsigned long rtc_2:1; /* RW */ |
2094 | unsigned long rtc_3:1; /* RW */ |
2095 | unsigned long rtc_4:1; /* RW */ |
2096 | unsigned long rtc_5:1; /* RW */ |
2097 | unsigned long rtc_6:1; /* RW */ |
2098 | unsigned long rtc_7:1; /* RW */ |
2099 | unsigned long rtc_8:1; /* RW */ |
2100 | unsigned long rtc_9:1; /* RW */ |
2101 | unsigned long rtc_10:1; /* RW */ |
2102 | unsigned long rtc_11:1; /* RW */ |
2103 | unsigned long rtc_12:1; /* RW */ |
2104 | unsigned long rtc_13:1; /* RW */ |
2105 | unsigned long rtc_14:1; /* RW */ |
2106 | unsigned long rtc_15:1; /* RW */ |
2107 | unsigned long rtc_16:1; /* RW */ |
2108 | unsigned long rtc_17:1; /* RW */ |
2109 | unsigned long rtc_18:1; /* RW */ |
2110 | unsigned long rtc_19:1; /* RW */ |
2111 | unsigned long rtc_20:1; /* RW */ |
2112 | unsigned long rtc_21:1; /* RW */ |
2113 | unsigned long rtc_22:1; /* RW */ |
2114 | unsigned long rtc_23:1; /* RW */ |
2115 | unsigned long rtc_24:1; /* RW */ |
2116 | unsigned long rtc_25:1; /* RW */ |
2117 | unsigned long rtc_26:1; /* RW */ |
2118 | unsigned long rtc_27:1; /* RW */ |
2119 | unsigned long rtc_28:1; /* RW */ |
2120 | unsigned long rtc_29:1; /* RW */ |
2121 | unsigned long rtc_30:1; /* RW */ |
2122 | unsigned long rtc_31:1; /* RW */ |
2123 | unsigned long rsvd_32_63:32; |
2124 | } s2; |
2125 | }; |
2126 | |
2127 | /* ========================================================================= */ |
2128 | /* UVH_EVENT_OCCURRED2_ALIAS */ |
2129 | /* ========================================================================= */ |
2130 | #define UVH_EVENT_OCCURRED2_ALIAS 0x70108UL |
2131 | |
2132 | |
2133 | /* ========================================================================= */ |
2134 | /* UVH_EXTIO_INT0_BROADCAST */ |
2135 | /* ========================================================================= */ |
2136 | #define UVH_EXTIO_INT0_BROADCAST 0x61448UL |
2137 | |
2138 | /* UVH common defines*/ |
2139 | #define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 |
2140 | #define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL |
2141 | |
2142 | |
2143 | union uvh_extio_int0_broadcast_u { |
2144 | unsigned long v; |
2145 | |
2146 | /* UVH common struct */ |
2147 | struct uvh_extio_int0_broadcast_s { |
2148 | unsigned long enable:1; /* RW */ |
2149 | unsigned long rsvd_1_63:63; |
2150 | } s; |
2151 | |
2152 | /* UV5 unique struct */ |
2153 | struct uv5h_extio_int0_broadcast_s { |
2154 | unsigned long enable:1; /* RW */ |
2155 | unsigned long rsvd_1_63:63; |
2156 | } s5; |
2157 | |
2158 | /* UV4 unique struct */ |
2159 | struct uv4h_extio_int0_broadcast_s { |
2160 | unsigned long enable:1; /* RW */ |
2161 | unsigned long rsvd_1_63:63; |
2162 | } s4; |
2163 | |
2164 | /* UV3 unique struct */ |
2165 | struct uv3h_extio_int0_broadcast_s { |
2166 | unsigned long enable:1; /* RW */ |
2167 | unsigned long rsvd_1_63:63; |
2168 | } s3; |
2169 | |
2170 | /* UV2 unique struct */ |
2171 | struct uv2h_extio_int0_broadcast_s { |
2172 | unsigned long enable:1; /* RW */ |
2173 | unsigned long rsvd_1_63:63; |
2174 | } s2; |
2175 | }; |
2176 | |
2177 | /* ========================================================================= */ |
2178 | /* UVH_GR0_GAM_GR_CONFIG */ |
2179 | /* ========================================================================= */ |
2180 | #define UVH_GR0_GAM_GR_CONFIG ( \ |
2181 | is_uv(UV5) ? 0x600028UL : \ |
2182 | is_uv(UV4) ? 0x600028UL : \ |
2183 | is_uv(UV3) ? 0xc00028UL : \ |
2184 | is_uv(UV2) ? 0xc00028UL : \ |
2185 | 0) |
2186 | |
2187 | |
2188 | |
2189 | /* UVYH common defines */ |
2190 | #define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 |
2191 | #define UVYH_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL |
2192 | |
2193 | /* UV4 unique defines */ |
2194 | #define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 |
2195 | #define UV4H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL |
2196 | |
2197 | /* UV3 unique defines */ |
2198 | #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_SHFT 0 |
2199 | #define UV3H_GR0_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL |
2200 | #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_SHFT 10 |
2201 | #define UV3H_GR0_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL |
2202 | |
2203 | /* UV2 unique defines */ |
2204 | #define UV2H_GR0_GAM_GR_CONFIG_N_GR_SHFT 0 |
2205 | #define UV2H_GR0_GAM_GR_CONFIG_N_GR_MASK 0x000000000000000fUL |
2206 | |
2207 | |
2208 | union uvyh_gr0_gam_gr_config_u { |
2209 | unsigned long v; |
2210 | |
2211 | /* UVYH common struct */ |
2212 | struct uvyh_gr0_gam_gr_config_s { |
2213 | unsigned long rsvd_0_9:10; |
2214 | unsigned long subspace:1; /* RW */ |
2215 | unsigned long rsvd_11_63:53; |
2216 | } sy; |
2217 | |
2218 | /* UV5 unique struct */ |
2219 | struct uv5h_gr0_gam_gr_config_s { |
2220 | unsigned long rsvd_0_9:10; |
2221 | unsigned long subspace:1; /* RW */ |
2222 | unsigned long rsvd_11_63:53; |
2223 | } s5; |
2224 | |
2225 | /* UV4 unique struct */ |
2226 | struct uv4h_gr0_gam_gr_config_s { |
2227 | unsigned long rsvd_0_9:10; |
2228 | unsigned long subspace:1; /* RW */ |
2229 | unsigned long rsvd_11_63:53; |
2230 | } s4; |
2231 | |
2232 | /* UV3 unique struct */ |
2233 | struct uv3h_gr0_gam_gr_config_s { |
2234 | unsigned long m_skt:6; /* RW */ |
2235 | unsigned long undef_6_9:4; /* Undefined */ |
2236 | unsigned long subspace:1; /* RW */ |
2237 | unsigned long reserved:53; |
2238 | } s3; |
2239 | |
2240 | /* UV2 unique struct */ |
2241 | struct uv2h_gr0_gam_gr_config_s { |
2242 | unsigned long n_gr:4; /* RW */ |
2243 | unsigned long reserved:60; |
2244 | } s2; |
2245 | }; |
2246 | |
2247 | /* ========================================================================= */ |
2248 | /* UVH_GR0_TLB_INT0_CONFIG */ |
2249 | /* ========================================================================= */ |
2250 | #define UVH_GR0_TLB_INT0_CONFIG ( \ |
2251 | is_uv(UV4) ? 0x61b00UL : \ |
2252 | is_uv(UV3) ? 0x61b00UL : \ |
2253 | is_uv(UV2) ? 0x61b00UL : \ |
2254 | uv_undefined("UVH_GR0_TLB_INT0_CONFIG")) |
2255 | |
2256 | |
2257 | /* UVXH common defines */ |
2258 | #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_SHFT 0 |
2259 | #define UVXH_GR0_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
2260 | #define UVXH_GR0_TLB_INT0_CONFIG_DM_SHFT 8 |
2261 | #define UVXH_GR0_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL |
2262 | #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_SHFT 11 |
2263 | #define UVXH_GR0_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
2264 | #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_SHFT 12 |
2265 | #define UVXH_GR0_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL |
2266 | #define UVXH_GR0_TLB_INT0_CONFIG_P_SHFT 13 |
2267 | #define UVXH_GR0_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL |
2268 | #define UVXH_GR0_TLB_INT0_CONFIG_T_SHFT 15 |
2269 | #define UVXH_GR0_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL |
2270 | #define UVXH_GR0_TLB_INT0_CONFIG_M_SHFT 16 |
2271 | #define UVXH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
2272 | #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_SHFT 32 |
2273 | #define UVXH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
2274 | |
2275 | |
2276 | union uvh_gr0_tlb_int0_config_u { |
2277 | unsigned long v; |
2278 | |
2279 | /* UVH common struct */ |
2280 | struct uvh_gr0_tlb_int0_config_s { |
2281 | unsigned long vector_:8; /* RW */ |
2282 | unsigned long dm:3; /* RW */ |
2283 | unsigned long destmode:1; /* RW */ |
2284 | unsigned long status:1; /* RO */ |
2285 | unsigned long p:1; /* RO */ |
2286 | unsigned long rsvd_14:1; |
2287 | unsigned long t:1; /* RO */ |
2288 | unsigned long m:1; /* RW */ |
2289 | unsigned long rsvd_17_31:15; |
2290 | unsigned long apic_id:32; /* RW */ |
2291 | } s; |
2292 | |
2293 | /* UVXH common struct */ |
2294 | struct uvxh_gr0_tlb_int0_config_s { |
2295 | unsigned long vector_:8; /* RW */ |
2296 | unsigned long dm:3; /* RW */ |
2297 | unsigned long destmode:1; /* RW */ |
2298 | unsigned long status:1; /* RO */ |
2299 | unsigned long p:1; /* RO */ |
2300 | unsigned long rsvd_14:1; |
2301 | unsigned long t:1; /* RO */ |
2302 | unsigned long m:1; /* RW */ |
2303 | unsigned long rsvd_17_31:15; |
2304 | unsigned long apic_id:32; /* RW */ |
2305 | } sx; |
2306 | |
2307 | /* UV4 unique struct */ |
2308 | struct uv4h_gr0_tlb_int0_config_s { |
2309 | unsigned long vector_:8; /* RW */ |
2310 | unsigned long dm:3; /* RW */ |
2311 | unsigned long destmode:1; /* RW */ |
2312 | unsigned long status:1; /* RO */ |
2313 | unsigned long p:1; /* RO */ |
2314 | unsigned long rsvd_14:1; |
2315 | unsigned long t:1; /* RO */ |
2316 | unsigned long m:1; /* RW */ |
2317 | unsigned long rsvd_17_31:15; |
2318 | unsigned long apic_id:32; /* RW */ |
2319 | } s4; |
2320 | |
2321 | /* UV3 unique struct */ |
2322 | struct uv3h_gr0_tlb_int0_config_s { |
2323 | unsigned long vector_:8; /* RW */ |
2324 | unsigned long dm:3; /* RW */ |
2325 | unsigned long destmode:1; /* RW */ |
2326 | unsigned long status:1; /* RO */ |
2327 | unsigned long p:1; /* RO */ |
2328 | unsigned long rsvd_14:1; |
2329 | unsigned long t:1; /* RO */ |
2330 | unsigned long m:1; /* RW */ |
2331 | unsigned long rsvd_17_31:15; |
2332 | unsigned long apic_id:32; /* RW */ |
2333 | } s3; |
2334 | |
2335 | /* UV2 unique struct */ |
2336 | struct uv2h_gr0_tlb_int0_config_s { |
2337 | unsigned long vector_:8; /* RW */ |
2338 | unsigned long dm:3; /* RW */ |
2339 | unsigned long destmode:1; /* RW */ |
2340 | unsigned long status:1; /* RO */ |
2341 | unsigned long p:1; /* RO */ |
2342 | unsigned long rsvd_14:1; |
2343 | unsigned long t:1; /* RO */ |
2344 | unsigned long m:1; /* RW */ |
2345 | unsigned long rsvd_17_31:15; |
2346 | unsigned long apic_id:32; /* RW */ |
2347 | } s2; |
2348 | }; |
2349 | |
2350 | /* ========================================================================= */ |
2351 | /* UVH_GR0_TLB_INT1_CONFIG */ |
2352 | /* ========================================================================= */ |
2353 | #define UVH_GR0_TLB_INT1_CONFIG ( \ |
2354 | is_uv(UV4) ? 0x61b40UL : \ |
2355 | is_uv(UV3) ? 0x61b40UL : \ |
2356 | is_uv(UV2) ? 0x61b40UL : \ |
2357 | uv_undefined("UVH_GR0_TLB_INT1_CONFIG")) |
2358 | |
2359 | |
2360 | /* UVXH common defines */ |
2361 | #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_SHFT 0 |
2362 | #define UVXH_GR0_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
2363 | #define UVXH_GR0_TLB_INT1_CONFIG_DM_SHFT 8 |
2364 | #define UVXH_GR0_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL |
2365 | #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_SHFT 11 |
2366 | #define UVXH_GR0_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
2367 | #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_SHFT 12 |
2368 | #define UVXH_GR0_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL |
2369 | #define UVXH_GR0_TLB_INT1_CONFIG_P_SHFT 13 |
2370 | #define UVXH_GR0_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL |
2371 | #define UVXH_GR0_TLB_INT1_CONFIG_T_SHFT 15 |
2372 | #define UVXH_GR0_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL |
2373 | #define UVXH_GR0_TLB_INT1_CONFIG_M_SHFT 16 |
2374 | #define UVXH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
2375 | #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_SHFT 32 |
2376 | #define UVXH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
2377 | |
2378 | |
2379 | union uvh_gr0_tlb_int1_config_u { |
2380 | unsigned long v; |
2381 | |
2382 | /* UVH common struct */ |
2383 | struct uvh_gr0_tlb_int1_config_s { |
2384 | unsigned long vector_:8; /* RW */ |
2385 | unsigned long dm:3; /* RW */ |
2386 | unsigned long destmode:1; /* RW */ |
2387 | unsigned long status:1; /* RO */ |
2388 | unsigned long p:1; /* RO */ |
2389 | unsigned long rsvd_14:1; |
2390 | unsigned long t:1; /* RO */ |
2391 | unsigned long m:1; /* RW */ |
2392 | unsigned long rsvd_17_31:15; |
2393 | unsigned long apic_id:32; /* RW */ |
2394 | } s; |
2395 | |
2396 | /* UVXH common struct */ |
2397 | struct uvxh_gr0_tlb_int1_config_s { |
2398 | unsigned long vector_:8; /* RW */ |
2399 | unsigned long dm:3; /* RW */ |
2400 | unsigned long destmode:1; /* RW */ |
2401 | unsigned long status:1; /* RO */ |
2402 | unsigned long p:1; /* RO */ |
2403 | unsigned long rsvd_14:1; |
2404 | unsigned long t:1; /* RO */ |
2405 | unsigned long m:1; /* RW */ |
2406 | unsigned long rsvd_17_31:15; |
2407 | unsigned long apic_id:32; /* RW */ |
2408 | } sx; |
2409 | |
2410 | /* UV4 unique struct */ |
2411 | struct uv4h_gr0_tlb_int1_config_s { |
2412 | unsigned long vector_:8; /* RW */ |
2413 | unsigned long dm:3; /* RW */ |
2414 | unsigned long destmode:1; /* RW */ |
2415 | unsigned long status:1; /* RO */ |
2416 | unsigned long p:1; /* RO */ |
2417 | unsigned long rsvd_14:1; |
2418 | unsigned long t:1; /* RO */ |
2419 | unsigned long m:1; /* RW */ |
2420 | unsigned long rsvd_17_31:15; |
2421 | unsigned long apic_id:32; /* RW */ |
2422 | } s4; |
2423 | |
2424 | /* UV3 unique struct */ |
2425 | struct uv3h_gr0_tlb_int1_config_s { |
2426 | unsigned long vector_:8; /* RW */ |
2427 | unsigned long dm:3; /* RW */ |
2428 | unsigned long destmode:1; /* RW */ |
2429 | unsigned long status:1; /* RO */ |
2430 | unsigned long p:1; /* RO */ |
2431 | unsigned long rsvd_14:1; |
2432 | unsigned long t:1; /* RO */ |
2433 | unsigned long m:1; /* RW */ |
2434 | unsigned long rsvd_17_31:15; |
2435 | unsigned long apic_id:32; /* RW */ |
2436 | } s3; |
2437 | |
2438 | /* UV2 unique struct */ |
2439 | struct uv2h_gr0_tlb_int1_config_s { |
2440 | unsigned long vector_:8; /* RW */ |
2441 | unsigned long dm:3; /* RW */ |
2442 | unsigned long destmode:1; /* RW */ |
2443 | unsigned long status:1; /* RO */ |
2444 | unsigned long p:1; /* RO */ |
2445 | unsigned long rsvd_14:1; |
2446 | unsigned long t:1; /* RO */ |
2447 | unsigned long m:1; /* RW */ |
2448 | unsigned long rsvd_17_31:15; |
2449 | unsigned long apic_id:32; /* RW */ |
2450 | } s2; |
2451 | }; |
2452 | |
2453 | /* ========================================================================= */ |
2454 | /* UVH_GR1_TLB_INT0_CONFIG */ |
2455 | /* ========================================================================= */ |
2456 | #define UVH_GR1_TLB_INT0_CONFIG ( \ |
2457 | is_uv(UV4) ? 0x62100UL : \ |
2458 | is_uv(UV3) ? 0x61f00UL : \ |
2459 | is_uv(UV2) ? 0x61f00UL : \ |
2460 | uv_undefined("UVH_GR1_TLB_INT0_CONFIG")) |
2461 | |
2462 | |
2463 | /* UVXH common defines */ |
2464 | #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 |
2465 | #define UVXH_GR1_TLB_INT0_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
2466 | #define UVXH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 |
2467 | #define UVXH_GR1_TLB_INT0_CONFIG_DM_MASK 0x0000000000000700UL |
2468 | #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_SHFT 11 |
2469 | #define UVXH_GR1_TLB_INT0_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
2470 | #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_SHFT 12 |
2471 | #define UVXH_GR1_TLB_INT0_CONFIG_STATUS_MASK 0x0000000000001000UL |
2472 | #define UVXH_GR1_TLB_INT0_CONFIG_P_SHFT 13 |
2473 | #define UVXH_GR1_TLB_INT0_CONFIG_P_MASK 0x0000000000002000UL |
2474 | #define UVXH_GR1_TLB_INT0_CONFIG_T_SHFT 15 |
2475 | #define UVXH_GR1_TLB_INT0_CONFIG_T_MASK 0x0000000000008000UL |
2476 | #define UVXH_GR1_TLB_INT0_CONFIG_M_SHFT 16 |
2477 | #define UVXH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL |
2478 | #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_SHFT 32 |
2479 | #define UVXH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
2480 | |
2481 | |
2482 | union uvh_gr1_tlb_int0_config_u { |
2483 | unsigned long v; |
2484 | |
2485 | /* UVH common struct */ |
2486 | struct uvh_gr1_tlb_int0_config_s { |
2487 | unsigned long vector_:8; /* RW */ |
2488 | unsigned long dm:3; /* RW */ |
2489 | unsigned long destmode:1; /* RW */ |
2490 | unsigned long status:1; /* RO */ |
2491 | unsigned long p:1; /* RO */ |
2492 | unsigned long rsvd_14:1; |
2493 | unsigned long t:1; /* RO */ |
2494 | unsigned long m:1; /* RW */ |
2495 | unsigned long rsvd_17_31:15; |
2496 | unsigned long apic_id:32; /* RW */ |
2497 | } s; |
2498 | |
2499 | /* UVXH common struct */ |
2500 | struct uvxh_gr1_tlb_int0_config_s { |
2501 | unsigned long vector_:8; /* RW */ |
2502 | unsigned long dm:3; /* RW */ |
2503 | unsigned long destmode:1; /* RW */ |
2504 | unsigned long status:1; /* RO */ |
2505 | unsigned long p:1; /* RO */ |
2506 | unsigned long rsvd_14:1; |
2507 | unsigned long t:1; /* RO */ |
2508 | unsigned long m:1; /* RW */ |
2509 | unsigned long rsvd_17_31:15; |
2510 | unsigned long apic_id:32; /* RW */ |
2511 | } sx; |
2512 | |
2513 | /* UV4 unique struct */ |
2514 | struct uv4h_gr1_tlb_int0_config_s { |
2515 | unsigned long vector_:8; /* RW */ |
2516 | unsigned long dm:3; /* RW */ |
2517 | unsigned long destmode:1; /* RW */ |
2518 | unsigned long status:1; /* RO */ |
2519 | unsigned long p:1; /* RO */ |
2520 | unsigned long rsvd_14:1; |
2521 | unsigned long t:1; /* RO */ |
2522 | unsigned long m:1; /* RW */ |
2523 | unsigned long rsvd_17_31:15; |
2524 | unsigned long apic_id:32; /* RW */ |
2525 | } s4; |
2526 | |
2527 | /* UV3 unique struct */ |
2528 | struct uv3h_gr1_tlb_int0_config_s { |
2529 | unsigned long vector_:8; /* RW */ |
2530 | unsigned long dm:3; /* RW */ |
2531 | unsigned long destmode:1; /* RW */ |
2532 | unsigned long status:1; /* RO */ |
2533 | unsigned long p:1; /* RO */ |
2534 | unsigned long rsvd_14:1; |
2535 | unsigned long t:1; /* RO */ |
2536 | unsigned long m:1; /* RW */ |
2537 | unsigned long rsvd_17_31:15; |
2538 | unsigned long apic_id:32; /* RW */ |
2539 | } s3; |
2540 | |
2541 | /* UV2 unique struct */ |
2542 | struct uv2h_gr1_tlb_int0_config_s { |
2543 | unsigned long vector_:8; /* RW */ |
2544 | unsigned long dm:3; /* RW */ |
2545 | unsigned long destmode:1; /* RW */ |
2546 | unsigned long status:1; /* RO */ |
2547 | unsigned long p:1; /* RO */ |
2548 | unsigned long rsvd_14:1; |
2549 | unsigned long t:1; /* RO */ |
2550 | unsigned long m:1; /* RW */ |
2551 | unsigned long rsvd_17_31:15; |
2552 | unsigned long apic_id:32; /* RW */ |
2553 | } s2; |
2554 | }; |
2555 | |
2556 | /* ========================================================================= */ |
2557 | /* UVH_GR1_TLB_INT1_CONFIG */ |
2558 | /* ========================================================================= */ |
2559 | #define UVH_GR1_TLB_INT1_CONFIG ( \ |
2560 | is_uv(UV4) ? 0x62140UL : \ |
2561 | is_uv(UV3) ? 0x61f40UL : \ |
2562 | is_uv(UV2) ? 0x61f40UL : \ |
2563 | uv_undefined("UVH_GR1_TLB_INT1_CONFIG")) |
2564 | |
2565 | |
2566 | /* UVXH common defines */ |
2567 | #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 |
2568 | #define UVXH_GR1_TLB_INT1_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
2569 | #define UVXH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 |
2570 | #define UVXH_GR1_TLB_INT1_CONFIG_DM_MASK 0x0000000000000700UL |
2571 | #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_SHFT 11 |
2572 | #define UVXH_GR1_TLB_INT1_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
2573 | #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_SHFT 12 |
2574 | #define UVXH_GR1_TLB_INT1_CONFIG_STATUS_MASK 0x0000000000001000UL |
2575 | #define UVXH_GR1_TLB_INT1_CONFIG_P_SHFT 13 |
2576 | #define UVXH_GR1_TLB_INT1_CONFIG_P_MASK 0x0000000000002000UL |
2577 | #define UVXH_GR1_TLB_INT1_CONFIG_T_SHFT 15 |
2578 | #define UVXH_GR1_TLB_INT1_CONFIG_T_MASK 0x0000000000008000UL |
2579 | #define UVXH_GR1_TLB_INT1_CONFIG_M_SHFT 16 |
2580 | #define UVXH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL |
2581 | #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_SHFT 32 |
2582 | #define UVXH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
2583 | |
2584 | |
2585 | union uvh_gr1_tlb_int1_config_u { |
2586 | unsigned long v; |
2587 | |
2588 | /* UVH common struct */ |
2589 | struct uvh_gr1_tlb_int1_config_s { |
2590 | unsigned long vector_:8; /* RW */ |
2591 | unsigned long dm:3; /* RW */ |
2592 | unsigned long destmode:1; /* RW */ |
2593 | unsigned long status:1; /* RO */ |
2594 | unsigned long p:1; /* RO */ |
2595 | unsigned long rsvd_14:1; |
2596 | unsigned long t:1; /* RO */ |
2597 | unsigned long m:1; /* RW */ |
2598 | unsigned long rsvd_17_31:15; |
2599 | unsigned long apic_id:32; /* RW */ |
2600 | } s; |
2601 | |
2602 | /* UVXH common struct */ |
2603 | struct uvxh_gr1_tlb_int1_config_s { |
2604 | unsigned long vector_:8; /* RW */ |
2605 | unsigned long dm:3; /* RW */ |
2606 | unsigned long destmode:1; /* RW */ |
2607 | unsigned long status:1; /* RO */ |
2608 | unsigned long p:1; /* RO */ |
2609 | unsigned long rsvd_14:1; |
2610 | unsigned long t:1; /* RO */ |
2611 | unsigned long m:1; /* RW */ |
2612 | unsigned long rsvd_17_31:15; |
2613 | unsigned long apic_id:32; /* RW */ |
2614 | } sx; |
2615 | |
2616 | /* UV4 unique struct */ |
2617 | struct uv4h_gr1_tlb_int1_config_s { |
2618 | unsigned long vector_:8; /* RW */ |
2619 | unsigned long dm:3; /* RW */ |
2620 | unsigned long destmode:1; /* RW */ |
2621 | unsigned long status:1; /* RO */ |
2622 | unsigned long p:1; /* RO */ |
2623 | unsigned long rsvd_14:1; |
2624 | unsigned long t:1; /* RO */ |
2625 | unsigned long m:1; /* RW */ |
2626 | unsigned long rsvd_17_31:15; |
2627 | unsigned long apic_id:32; /* RW */ |
2628 | } s4; |
2629 | |
2630 | /* UV3 unique struct */ |
2631 | struct uv3h_gr1_tlb_int1_config_s { |
2632 | unsigned long vector_:8; /* RW */ |
2633 | unsigned long dm:3; /* RW */ |
2634 | unsigned long destmode:1; /* RW */ |
2635 | unsigned long status:1; /* RO */ |
2636 | unsigned long p:1; /* RO */ |
2637 | unsigned long rsvd_14:1; |
2638 | unsigned long t:1; /* RO */ |
2639 | unsigned long m:1; /* RW */ |
2640 | unsigned long rsvd_17_31:15; |
2641 | unsigned long apic_id:32; /* RW */ |
2642 | } s3; |
2643 | |
2644 | /* UV2 unique struct */ |
2645 | struct uv2h_gr1_tlb_int1_config_s { |
2646 | unsigned long vector_:8; /* RW */ |
2647 | unsigned long dm:3; /* RW */ |
2648 | unsigned long destmode:1; /* RW */ |
2649 | unsigned long status:1; /* RO */ |
2650 | unsigned long p:1; /* RO */ |
2651 | unsigned long rsvd_14:1; |
2652 | unsigned long t:1; /* RO */ |
2653 | unsigned long m:1; /* RW */ |
2654 | unsigned long rsvd_17_31:15; |
2655 | unsigned long apic_id:32; /* RW */ |
2656 | } s2; |
2657 | }; |
2658 | |
2659 | /* ========================================================================= */ |
2660 | /* UVH_INT_CMPB */ |
2661 | /* ========================================================================= */ |
2662 | #define UVH_INT_CMPB 0x22080UL |
2663 | |
2664 | /* UVH common defines*/ |
2665 | #define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 |
2666 | #define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL |
2667 | |
2668 | |
2669 | union uvh_int_cmpb_u { |
2670 | unsigned long v; |
2671 | |
2672 | /* UVH common struct */ |
2673 | struct uvh_int_cmpb_s { |
2674 | unsigned long real_time_cmpb:56; /* RW */ |
2675 | unsigned long rsvd_56_63:8; |
2676 | } s; |
2677 | |
2678 | /* UV5 unique struct */ |
2679 | struct uv5h_int_cmpb_s { |
2680 | unsigned long real_time_cmpb:56; /* RW */ |
2681 | unsigned long rsvd_56_63:8; |
2682 | } s5; |
2683 | |
2684 | /* UV4 unique struct */ |
2685 | struct uv4h_int_cmpb_s { |
2686 | unsigned long real_time_cmpb:56; /* RW */ |
2687 | unsigned long rsvd_56_63:8; |
2688 | } s4; |
2689 | |
2690 | /* UV3 unique struct */ |
2691 | struct uv3h_int_cmpb_s { |
2692 | unsigned long real_time_cmpb:56; /* RW */ |
2693 | unsigned long rsvd_56_63:8; |
2694 | } s3; |
2695 | |
2696 | /* UV2 unique struct */ |
2697 | struct uv2h_int_cmpb_s { |
2698 | unsigned long real_time_cmpb:56; /* RW */ |
2699 | unsigned long rsvd_56_63:8; |
2700 | } s2; |
2701 | }; |
2702 | |
2703 | /* ========================================================================= */ |
2704 | /* UVH_IPI_INT */ |
2705 | /* ========================================================================= */ |
2706 | #define UVH_IPI_INT 0x60500UL |
2707 | |
2708 | /* UVH common defines*/ |
2709 | #define UVH_IPI_INT_VECTOR_SHFT 0 |
2710 | #define UVH_IPI_INT_VECTOR_MASK 0x00000000000000ffUL |
2711 | #define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 |
2712 | #define UVH_IPI_INT_DELIVERY_MODE_MASK 0x0000000000000700UL |
2713 | #define UVH_IPI_INT_DESTMODE_SHFT 11 |
2714 | #define UVH_IPI_INT_DESTMODE_MASK 0x0000000000000800UL |
2715 | #define UVH_IPI_INT_APIC_ID_SHFT 16 |
2716 | #define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL |
2717 | #define UVH_IPI_INT_SEND_SHFT 63 |
2718 | #define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL |
2719 | |
2720 | |
2721 | union uvh_ipi_int_u { |
2722 | unsigned long v; |
2723 | |
2724 | /* UVH common struct */ |
2725 | struct uvh_ipi_int_s { |
2726 | unsigned long vector_:8; /* RW */ |
2727 | unsigned long delivery_mode:3; /* RW */ |
2728 | unsigned long destmode:1; /* RW */ |
2729 | unsigned long rsvd_12_15:4; |
2730 | unsigned long apic_id:32; /* RW */ |
2731 | unsigned long rsvd_48_62:15; |
2732 | unsigned long send:1; /* WP */ |
2733 | } s; |
2734 | |
2735 | /* UV5 unique struct */ |
2736 | struct uv5h_ipi_int_s { |
2737 | unsigned long vector_:8; /* RW */ |
2738 | unsigned long delivery_mode:3; /* RW */ |
2739 | unsigned long destmode:1; /* RW */ |
2740 | unsigned long rsvd_12_15:4; |
2741 | unsigned long apic_id:32; /* RW */ |
2742 | unsigned long rsvd_48_62:15; |
2743 | unsigned long send:1; /* WP */ |
2744 | } s5; |
2745 | |
2746 | /* UV4 unique struct */ |
2747 | struct uv4h_ipi_int_s { |
2748 | unsigned long vector_:8; /* RW */ |
2749 | unsigned long delivery_mode:3; /* RW */ |
2750 | unsigned long destmode:1; /* RW */ |
2751 | unsigned long rsvd_12_15:4; |
2752 | unsigned long apic_id:32; /* RW */ |
2753 | unsigned long rsvd_48_62:15; |
2754 | unsigned long send:1; /* WP */ |
2755 | } s4; |
2756 | |
2757 | /* UV3 unique struct */ |
2758 | struct uv3h_ipi_int_s { |
2759 | unsigned long vector_:8; /* RW */ |
2760 | unsigned long delivery_mode:3; /* RW */ |
2761 | unsigned long destmode:1; /* RW */ |
2762 | unsigned long rsvd_12_15:4; |
2763 | unsigned long apic_id:32; /* RW */ |
2764 | unsigned long rsvd_48_62:15; |
2765 | unsigned long send:1; /* WP */ |
2766 | } s3; |
2767 | |
2768 | /* UV2 unique struct */ |
2769 | struct uv2h_ipi_int_s { |
2770 | unsigned long vector_:8; /* RW */ |
2771 | unsigned long delivery_mode:3; /* RW */ |
2772 | unsigned long destmode:1; /* RW */ |
2773 | unsigned long rsvd_12_15:4; |
2774 | unsigned long apic_id:32; /* RW */ |
2775 | unsigned long rsvd_48_62:15; |
2776 | unsigned long send:1; /* WP */ |
2777 | } s2; |
2778 | }; |
2779 | |
2780 | /* ========================================================================= */ |
2781 | /* UVH_NODE_ID */ |
2782 | /* ========================================================================= */ |
2783 | #define UVH_NODE_ID 0x0UL |
2784 | |
2785 | /* UVH common defines*/ |
2786 | #define UVH_NODE_ID_FORCE1_SHFT 0 |
2787 | #define UVH_NODE_ID_FORCE1_MASK 0x0000000000000001UL |
2788 | #define UVH_NODE_ID_MANUFACTURER_SHFT 1 |
2789 | #define UVH_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL |
2790 | #define UVH_NODE_ID_PART_NUMBER_SHFT 12 |
2791 | #define UVH_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL |
2792 | #define UVH_NODE_ID_REVISION_SHFT 28 |
2793 | #define UVH_NODE_ID_REVISION_MASK 0x00000000f0000000UL |
2794 | #define UVH_NODE_ID_NODE_ID_SHFT 32 |
2795 | #define UVH_NODE_ID_NI_PORT_SHFT 57 |
2796 | |
2797 | /* UVXH common defines */ |
2798 | #define UVXH_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL |
2799 | #define UVXH_NODE_ID_NODES_PER_BIT_SHFT 50 |
2800 | #define UVXH_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL |
2801 | #define UVXH_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL |
2802 | |
2803 | /* UVYH common defines */ |
2804 | #define UVYH_NODE_ID_NODE_ID_MASK 0x0000007f00000000UL |
2805 | #define UVYH_NODE_ID_NI_PORT_MASK 0x7e00000000000000UL |
2806 | |
2807 | /* UV4 unique defines */ |
2808 | #define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48 |
2809 | #define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL |
2810 | #define UV4H_NODE_ID_RESERVED_2_SHFT 49 |
2811 | #define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL |
2812 | |
2813 | /* UV3 unique defines */ |
2814 | #define UV3H_NODE_ID_ROUTER_SELECT_SHFT 48 |
2815 | #define UV3H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL |
2816 | #define UV3H_NODE_ID_RESERVED_2_SHFT 49 |
2817 | #define UV3H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL |
2818 | |
2819 | |
2820 | union uvh_node_id_u { |
2821 | unsigned long v; |
2822 | |
2823 | /* UVH common struct */ |
2824 | struct uvh_node_id_s { |
2825 | unsigned long force1:1; /* RO */ |
2826 | unsigned long manufacturer:11; /* RO */ |
2827 | unsigned long part_number:16; /* RO */ |
2828 | unsigned long revision:4; /* RO */ |
2829 | unsigned long rsvd_32_63:32; |
2830 | } s; |
2831 | |
2832 | /* UVXH common struct */ |
2833 | struct uvxh_node_id_s { |
2834 | unsigned long force1:1; /* RO */ |
2835 | unsigned long manufacturer:11; /* RO */ |
2836 | unsigned long part_number:16; /* RO */ |
2837 | unsigned long revision:4; /* RO */ |
2838 | unsigned long node_id:15; /* RW */ |
2839 | unsigned long rsvd_47_49:3; |
2840 | unsigned long nodes_per_bit:7; /* RO */ |
2841 | unsigned long ni_port:5; /* RO */ |
2842 | unsigned long rsvd_62_63:2; |
2843 | } sx; |
2844 | |
2845 | /* UVYH common struct */ |
2846 | struct uvyh_node_id_s { |
2847 | unsigned long force1:1; /* RO */ |
2848 | unsigned long manufacturer:11; /* RO */ |
2849 | unsigned long part_number:16; /* RO */ |
2850 | unsigned long revision:4; /* RO */ |
2851 | unsigned long node_id:7; /* RW */ |
2852 | unsigned long rsvd_39_56:18; |
2853 | unsigned long ni_port:6; /* RO */ |
2854 | unsigned long rsvd_63:1; |
2855 | } sy; |
2856 | |
2857 | /* UV5 unique struct */ |
2858 | struct uv5h_node_id_s { |
2859 | unsigned long force1:1; /* RO */ |
2860 | unsigned long manufacturer:11; /* RO */ |
2861 | unsigned long part_number:16; /* RO */ |
2862 | unsigned long revision:4; /* RO */ |
2863 | unsigned long node_id:7; /* RW */ |
2864 | unsigned long rsvd_39_56:18; |
2865 | unsigned long ni_port:6; /* RO */ |
2866 | unsigned long rsvd_63:1; |
2867 | } s5; |
2868 | |
2869 | /* UV4 unique struct */ |
2870 | struct uv4h_node_id_s { |
2871 | unsigned long force1:1; /* RO */ |
2872 | unsigned long manufacturer:11; /* RO */ |
2873 | unsigned long part_number:16; /* RO */ |
2874 | unsigned long revision:4; /* RO */ |
2875 | unsigned long node_id:15; /* RW */ |
2876 | unsigned long rsvd_47:1; |
2877 | unsigned long router_select:1; /* RO */ |
2878 | unsigned long rsvd_49:1; |
2879 | unsigned long nodes_per_bit:7; /* RO */ |
2880 | unsigned long ni_port:5; /* RO */ |
2881 | unsigned long rsvd_62_63:2; |
2882 | } s4; |
2883 | |
2884 | /* UV3 unique struct */ |
2885 | struct uv3h_node_id_s { |
2886 | unsigned long force1:1; /* RO */ |
2887 | unsigned long manufacturer:11; /* RO */ |
2888 | unsigned long part_number:16; /* RO */ |
2889 | unsigned long revision:4; /* RO */ |
2890 | unsigned long node_id:15; /* RW */ |
2891 | unsigned long rsvd_47:1; |
2892 | unsigned long router_select:1; /* RO */ |
2893 | unsigned long rsvd_49:1; |
2894 | unsigned long nodes_per_bit:7; /* RO */ |
2895 | unsigned long ni_port:5; /* RO */ |
2896 | unsigned long rsvd_62_63:2; |
2897 | } s3; |
2898 | |
2899 | /* UV2 unique struct */ |
2900 | struct uv2h_node_id_s { |
2901 | unsigned long force1:1; /* RO */ |
2902 | unsigned long manufacturer:11; /* RO */ |
2903 | unsigned long part_number:16; /* RO */ |
2904 | unsigned long revision:4; /* RO */ |
2905 | unsigned long node_id:15; /* RW */ |
2906 | unsigned long rsvd_47_49:3; |
2907 | unsigned long nodes_per_bit:7; /* RO */ |
2908 | unsigned long ni_port:5; /* RO */ |
2909 | unsigned long rsvd_62_63:2; |
2910 | } s2; |
2911 | }; |
2912 | |
2913 | /* ========================================================================= */ |
2914 | /* UVH_NODE_PRESENT_0 */ |
2915 | /* ========================================================================= */ |
2916 | #define UVH_NODE_PRESENT_0 ( \ |
2917 | is_uv(UV5) ? 0x1400UL : \ |
2918 | 0) |
2919 | |
2920 | |
2921 | /* UVYH common defines */ |
2922 | #define UVYH_NODE_PRESENT_0_NODES_SHFT 0 |
2923 | #define UVYH_NODE_PRESENT_0_NODES_MASK 0xffffffffffffffffUL |
2924 | |
2925 | |
2926 | union uvh_node_present_0_u { |
2927 | unsigned long v; |
2928 | |
2929 | /* UVH common struct */ |
2930 | struct uvh_node_present_0_s { |
2931 | unsigned long nodes:64; /* RW */ |
2932 | } s; |
2933 | |
2934 | /* UVYH common struct */ |
2935 | struct uvyh_node_present_0_s { |
2936 | unsigned long nodes:64; /* RW */ |
2937 | } sy; |
2938 | |
2939 | /* UV5 unique struct */ |
2940 | struct uv5h_node_present_0_s { |
2941 | unsigned long nodes:64; /* RW */ |
2942 | } s5; |
2943 | }; |
2944 | |
2945 | /* ========================================================================= */ |
2946 | /* UVH_NODE_PRESENT_1 */ |
2947 | /* ========================================================================= */ |
2948 | #define UVH_NODE_PRESENT_1 ( \ |
2949 | is_uv(UV5) ? 0x1408UL : \ |
2950 | 0) |
2951 | |
2952 | |
2953 | /* UVYH common defines */ |
2954 | #define UVYH_NODE_PRESENT_1_NODES_SHFT 0 |
2955 | #define UVYH_NODE_PRESENT_1_NODES_MASK 0xffffffffffffffffUL |
2956 | |
2957 | |
2958 | union uvh_node_present_1_u { |
2959 | unsigned long v; |
2960 | |
2961 | /* UVH common struct */ |
2962 | struct uvh_node_present_1_s { |
2963 | unsigned long nodes:64; /* RW */ |
2964 | } s; |
2965 | |
2966 | /* UVYH common struct */ |
2967 | struct uvyh_node_present_1_s { |
2968 | unsigned long nodes:64; /* RW */ |
2969 | } sy; |
2970 | |
2971 | /* UV5 unique struct */ |
2972 | struct uv5h_node_present_1_s { |
2973 | unsigned long nodes:64; /* RW */ |
2974 | } s5; |
2975 | }; |
2976 | |
2977 | /* ========================================================================= */ |
2978 | /* UVH_NODE_PRESENT_TABLE */ |
2979 | /* ========================================================================= */ |
2980 | #define UVH_NODE_PRESENT_TABLE ( \ |
2981 | is_uv(UV4) ? 0x1400UL : \ |
2982 | is_uv(UV3) ? 0x1400UL : \ |
2983 | is_uv(UV2) ? 0x1400UL : \ |
2984 | 0) |
2985 | |
2986 | #define UVH_NODE_PRESENT_TABLE_DEPTH ( \ |
2987 | is_uv(UV4) ? 4 : \ |
2988 | is_uv(UV3) ? 16 : \ |
2989 | is_uv(UV2) ? 16 : \ |
2990 | 0) |
2991 | |
2992 | |
2993 | /* UVXH common defines */ |
2994 | #define UVXH_NODE_PRESENT_TABLE_NODES_SHFT 0 |
2995 | #define UVXH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL |
2996 | |
2997 | |
2998 | union uvh_node_present_table_u { |
2999 | unsigned long v; |
3000 | |
3001 | /* UVH common struct */ |
3002 | struct uvh_node_present_table_s { |
3003 | unsigned long nodes:64; /* RW */ |
3004 | } s; |
3005 | |
3006 | /* UVXH common struct */ |
3007 | struct uvxh_node_present_table_s { |
3008 | unsigned long nodes:64; /* RW */ |
3009 | } sx; |
3010 | |
3011 | /* UV4 unique struct */ |
3012 | struct uv4h_node_present_table_s { |
3013 | unsigned long nodes:64; /* RW */ |
3014 | } s4; |
3015 | |
3016 | /* UV3 unique struct */ |
3017 | struct uv3h_node_present_table_s { |
3018 | unsigned long nodes:64; /* RW */ |
3019 | } s3; |
3020 | |
3021 | /* UV2 unique struct */ |
3022 | struct uv2h_node_present_table_s { |
3023 | unsigned long nodes:64; /* RW */ |
3024 | } s2; |
3025 | }; |
3026 | |
3027 | /* ========================================================================= */ |
3028 | /* UVH_RH10_GAM_ADDR_MAP_CONFIG */ |
3029 | /* ========================================================================= */ |
3030 | #define UVH_RH10_GAM_ADDR_MAP_CONFIG ( \ |
3031 | is_uv(UV5) ? 0x470000UL : \ |
3032 | 0) |
3033 | |
3034 | |
3035 | /* UVYH common defines */ |
3036 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT 6 |
3037 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_N_SKT_MASK 0x00000000000001c0UL |
3038 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_SHFT 12 |
3039 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_LS_ENABLE_MASK 0x0000000000001000UL |
3040 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_SHFT 16 |
3041 | #define UVYH_RH10_GAM_ADDR_MAP_CONFIG_MK_TME_KEYID_BITS_MASK 0x00000000000f0000UL |
3042 | |
3043 | |
3044 | union uvh_rh10_gam_addr_map_config_u { |
3045 | unsigned long v; |
3046 | |
3047 | /* UVH common struct */ |
3048 | struct uvh_rh10_gam_addr_map_config_s { |
3049 | unsigned long undef_0_5:6; /* Undefined */ |
3050 | unsigned long n_skt:3; /* RW */ |
3051 | unsigned long undef_9_11:3; /* Undefined */ |
3052 | unsigned long ls_enable:1; /* RW */ |
3053 | unsigned long undef_13_15:3; /* Undefined */ |
3054 | unsigned long mk_tme_keyid_bits:4; /* RW */ |
3055 | unsigned long rsvd_20_63:44; |
3056 | } s; |
3057 | |
3058 | /* UVYH common struct */ |
3059 | struct uvyh_rh10_gam_addr_map_config_s { |
3060 | unsigned long undef_0_5:6; /* Undefined */ |
3061 | unsigned long n_skt:3; /* RW */ |
3062 | unsigned long undef_9_11:3; /* Undefined */ |
3063 | unsigned long ls_enable:1; /* RW */ |
3064 | unsigned long undef_13_15:3; /* Undefined */ |
3065 | unsigned long mk_tme_keyid_bits:4; /* RW */ |
3066 | unsigned long rsvd_20_63:44; |
3067 | } sy; |
3068 | |
3069 | /* UV5 unique struct */ |
3070 | struct uv5h_rh10_gam_addr_map_config_s { |
3071 | unsigned long undef_0_5:6; /* Undefined */ |
3072 | unsigned long n_skt:3; /* RW */ |
3073 | unsigned long undef_9_11:3; /* Undefined */ |
3074 | unsigned long ls_enable:1; /* RW */ |
3075 | unsigned long undef_13_15:3; /* Undefined */ |
3076 | unsigned long mk_tme_keyid_bits:4; /* RW */ |
3077 | } s5; |
3078 | }; |
3079 | |
3080 | /* ========================================================================= */ |
3081 | /* UVH_RH10_GAM_GRU_OVERLAY_CONFIG */ |
3082 | /* ========================================================================= */ |
3083 | #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG ( \ |
3084 | is_uv(UV5) ? 0x4700b0UL : \ |
3085 | 0) |
3086 | |
3087 | |
3088 | /* UVYH common defines */ |
3089 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 25 |
3090 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffe000000UL |
3091 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT 52 |
3092 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK 0x0070000000000000UL |
3093 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3094 | #define UVYH_RH10_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3095 | |
3096 | #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK ( \ |
3097 | is_uv(UV5) ? 0x000ffffffe000000UL : \ |
3098 | 0) |
3099 | #define UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT ( \ |
3100 | is_uv(UV5) ? 25 : \ |
3101 | -1) |
3102 | |
3103 | union uvh_rh10_gam_gru_overlay_config_u { |
3104 | unsigned long v; |
3105 | |
3106 | /* UVH common struct */ |
3107 | struct uvh_rh10_gam_gru_overlay_config_s { |
3108 | unsigned long undef_0_24:25; /* Undefined */ |
3109 | unsigned long base:27; /* RW */ |
3110 | unsigned long n_gru:3; /* RW */ |
3111 | unsigned long undef_55_62:8; /* Undefined */ |
3112 | unsigned long enable:1; /* RW */ |
3113 | } s; |
3114 | |
3115 | /* UVYH common struct */ |
3116 | struct uvyh_rh10_gam_gru_overlay_config_s { |
3117 | unsigned long undef_0_24:25; /* Undefined */ |
3118 | unsigned long base:27; /* RW */ |
3119 | unsigned long n_gru:3; /* RW */ |
3120 | unsigned long undef_55_62:8; /* Undefined */ |
3121 | unsigned long enable:1; /* RW */ |
3122 | } sy; |
3123 | |
3124 | /* UV5 unique struct */ |
3125 | struct uv5h_rh10_gam_gru_overlay_config_s { |
3126 | unsigned long undef_0_24:25; /* Undefined */ |
3127 | unsigned long base:27; /* RW */ |
3128 | unsigned long n_gru:3; /* RW */ |
3129 | unsigned long undef_55_62:8; /* Undefined */ |
3130 | unsigned long enable:1; /* RW */ |
3131 | } s5; |
3132 | }; |
3133 | |
3134 | /* ========================================================================= */ |
3135 | /* UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0 */ |
3136 | /* ========================================================================= */ |
3137 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0 ( \ |
3138 | is_uv(UV5) ? 0x473000UL : \ |
3139 | 0) |
3140 | |
3141 | |
3142 | /* UVYH common defines */ |
3143 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT 26 |
3144 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x000ffffffc000000UL |
3145 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT 52 |
3146 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x03f0000000000000UL |
3147 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT 63 |
3148 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL |
3149 | |
3150 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK ( \ |
3151 | is_uv(UV5) ? 0x000ffffffc000000UL : \ |
3152 | 0) |
3153 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT ( \ |
3154 | is_uv(UV5) ? 26 : \ |
3155 | -1) |
3156 | |
3157 | union uvh_rh10_gam_mmioh_overlay_config0_u { |
3158 | unsigned long v; |
3159 | |
3160 | /* UVH common struct */ |
3161 | struct uvh_rh10_gam_mmioh_overlay_config0_s { |
3162 | unsigned long rsvd_0_25:26; |
3163 | unsigned long base:26; /* RW */ |
3164 | unsigned long m_io:6; /* RW */ |
3165 | unsigned long n_io:4; |
3166 | unsigned long undef_62:1; /* Undefined */ |
3167 | unsigned long enable:1; /* RW */ |
3168 | } s; |
3169 | |
3170 | /* UVYH common struct */ |
3171 | struct uvyh_rh10_gam_mmioh_overlay_config0_s { |
3172 | unsigned long rsvd_0_25:26; |
3173 | unsigned long base:26; /* RW */ |
3174 | unsigned long m_io:6; /* RW */ |
3175 | unsigned long n_io:4; |
3176 | unsigned long undef_62:1; /* Undefined */ |
3177 | unsigned long enable:1; /* RW */ |
3178 | } sy; |
3179 | |
3180 | /* UV5 unique struct */ |
3181 | struct uv5h_rh10_gam_mmioh_overlay_config0_s { |
3182 | unsigned long rsvd_0_25:26; |
3183 | unsigned long base:26; /* RW */ |
3184 | unsigned long m_io:6; /* RW */ |
3185 | unsigned long n_io:4; |
3186 | unsigned long undef_62:1; /* Undefined */ |
3187 | unsigned long enable:1; /* RW */ |
3188 | } s5; |
3189 | }; |
3190 | |
3191 | /* ========================================================================= */ |
3192 | /* UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1 */ |
3193 | /* ========================================================================= */ |
3194 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1 ( \ |
3195 | is_uv(UV5) ? 0x474000UL : \ |
3196 | 0) |
3197 | |
3198 | |
3199 | /* UVYH common defines */ |
3200 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT 26 |
3201 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x000ffffffc000000UL |
3202 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT 52 |
3203 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x03f0000000000000UL |
3204 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT 63 |
3205 | #define UVYH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL |
3206 | |
3207 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK ( \ |
3208 | is_uv(UV5) ? 0x000ffffffc000000UL : \ |
3209 | 0) |
3210 | #define UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT ( \ |
3211 | is_uv(UV5) ? 26 : \ |
3212 | -1) |
3213 | |
3214 | union uvh_rh10_gam_mmioh_overlay_config1_u { |
3215 | unsigned long v; |
3216 | |
3217 | /* UVH common struct */ |
3218 | struct uvh_rh10_gam_mmioh_overlay_config1_s { |
3219 | unsigned long rsvd_0_25:26; |
3220 | unsigned long base:26; /* RW */ |
3221 | unsigned long m_io:6; /* RW */ |
3222 | unsigned long n_io:4; |
3223 | unsigned long undef_62:1; /* Undefined */ |
3224 | unsigned long enable:1; /* RW */ |
3225 | } s; |
3226 | |
3227 | /* UVYH common struct */ |
3228 | struct uvyh_rh10_gam_mmioh_overlay_config1_s { |
3229 | unsigned long rsvd_0_25:26; |
3230 | unsigned long base:26; /* RW */ |
3231 | unsigned long m_io:6; /* RW */ |
3232 | unsigned long n_io:4; |
3233 | unsigned long undef_62:1; /* Undefined */ |
3234 | unsigned long enable:1; /* RW */ |
3235 | } sy; |
3236 | |
3237 | /* UV5 unique struct */ |
3238 | struct uv5h_rh10_gam_mmioh_overlay_config1_s { |
3239 | unsigned long rsvd_0_25:26; |
3240 | unsigned long base:26; /* RW */ |
3241 | unsigned long m_io:6; /* RW */ |
3242 | unsigned long n_io:4; |
3243 | unsigned long undef_62:1; /* Undefined */ |
3244 | unsigned long enable:1; /* RW */ |
3245 | } s5; |
3246 | }; |
3247 | |
3248 | /* ========================================================================= */ |
3249 | /* UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0 */ |
3250 | /* ========================================================================= */ |
3251 | #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0 ( \ |
3252 | is_uv(UV5) ? 0x473800UL : \ |
3253 | 0) |
3254 | |
3255 | #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH ( \ |
3256 | is_uv(UV5) ? 128 : \ |
3257 | 0) |
3258 | |
3259 | |
3260 | /* UVYH common defines */ |
3261 | #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0 |
3262 | #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x000000000000007fUL |
3263 | |
3264 | |
3265 | union uvh_rh10_gam_mmioh_redirect_config0_u { |
3266 | unsigned long v; |
3267 | |
3268 | /* UVH common struct */ |
3269 | struct uvh_rh10_gam_mmioh_redirect_config0_s { |
3270 | unsigned long nasid:7; /* RW */ |
3271 | unsigned long rsvd_7_63:57; |
3272 | } s; |
3273 | |
3274 | /* UVYH common struct */ |
3275 | struct uvyh_rh10_gam_mmioh_redirect_config0_s { |
3276 | unsigned long nasid:7; /* RW */ |
3277 | unsigned long rsvd_7_63:57; |
3278 | } sy; |
3279 | |
3280 | /* UV5 unique struct */ |
3281 | struct uv5h_rh10_gam_mmioh_redirect_config0_s { |
3282 | unsigned long nasid:7; /* RW */ |
3283 | unsigned long rsvd_7_63:57; |
3284 | } s5; |
3285 | }; |
3286 | |
3287 | /* ========================================================================= */ |
3288 | /* UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1 */ |
3289 | /* ========================================================================= */ |
3290 | #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1 ( \ |
3291 | is_uv(UV5) ? 0x474800UL : \ |
3292 | 0) |
3293 | |
3294 | #define UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH ( \ |
3295 | is_uv(UV5) ? 128 : \ |
3296 | 0) |
3297 | |
3298 | |
3299 | /* UVYH common defines */ |
3300 | #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0 |
3301 | #define UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x000000000000007fUL |
3302 | |
3303 | |
3304 | union uvh_rh10_gam_mmioh_redirect_config1_u { |
3305 | unsigned long v; |
3306 | |
3307 | /* UVH common struct */ |
3308 | struct uvh_rh10_gam_mmioh_redirect_config1_s { |
3309 | unsigned long nasid:7; /* RW */ |
3310 | unsigned long rsvd_7_63:57; |
3311 | } s; |
3312 | |
3313 | /* UVYH common struct */ |
3314 | struct uvyh_rh10_gam_mmioh_redirect_config1_s { |
3315 | unsigned long nasid:7; /* RW */ |
3316 | unsigned long rsvd_7_63:57; |
3317 | } sy; |
3318 | |
3319 | /* UV5 unique struct */ |
3320 | struct uv5h_rh10_gam_mmioh_redirect_config1_s { |
3321 | unsigned long nasid:7; /* RW */ |
3322 | unsigned long rsvd_7_63:57; |
3323 | } s5; |
3324 | }; |
3325 | |
3326 | /* ========================================================================= */ |
3327 | /* UVH_RH10_GAM_MMR_OVERLAY_CONFIG */ |
3328 | /* ========================================================================= */ |
3329 | #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG ( \ |
3330 | is_uv(UV5) ? 0x470090UL : \ |
3331 | 0) |
3332 | |
3333 | |
3334 | /* UVYH common defines */ |
3335 | #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT 25 |
3336 | #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK 0x000ffffffe000000UL |
3337 | #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3338 | #define UVYH_RH10_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3339 | |
3340 | #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_MASK ( \ |
3341 | is_uv(UV5) ? 0x000ffffffe000000UL : \ |
3342 | 0) |
3343 | #define UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT ( \ |
3344 | is_uv(UV5) ? 25 : \ |
3345 | -1) |
3346 | |
3347 | union uvh_rh10_gam_mmr_overlay_config_u { |
3348 | unsigned long v; |
3349 | |
3350 | /* UVH common struct */ |
3351 | struct uvh_rh10_gam_mmr_overlay_config_s { |
3352 | unsigned long undef_0_24:25; /* Undefined */ |
3353 | unsigned long base:27; /* RW */ |
3354 | unsigned long undef_52_62:11; /* Undefined */ |
3355 | unsigned long enable:1; /* RW */ |
3356 | } s; |
3357 | |
3358 | /* UVYH common struct */ |
3359 | struct uvyh_rh10_gam_mmr_overlay_config_s { |
3360 | unsigned long undef_0_24:25; /* Undefined */ |
3361 | unsigned long base:27; /* RW */ |
3362 | unsigned long undef_52_62:11; /* Undefined */ |
3363 | unsigned long enable:1; /* RW */ |
3364 | } sy; |
3365 | |
3366 | /* UV5 unique struct */ |
3367 | struct uv5h_rh10_gam_mmr_overlay_config_s { |
3368 | unsigned long undef_0_24:25; /* Undefined */ |
3369 | unsigned long base:27; /* RW */ |
3370 | unsigned long undef_52_62:11; /* Undefined */ |
3371 | unsigned long enable:1; /* RW */ |
3372 | } s5; |
3373 | }; |
3374 | |
3375 | /* ========================================================================= */ |
3376 | /* UVH_RH_GAM_ADDR_MAP_CONFIG */ |
3377 | /* ========================================================================= */ |
3378 | #define UVH_RH_GAM_ADDR_MAP_CONFIG ( \ |
3379 | is_uv(UV4) ? 0x480000UL : \ |
3380 | is_uv(UV3) ? 0x1600000UL : \ |
3381 | is_uv(UV2) ? 0x1600000UL : \ |
3382 | 0) |
3383 | |
3384 | |
3385 | /* UVXH common defines */ |
3386 | #define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_SHFT 6 |
3387 | #define UVXH_RH_GAM_ADDR_MAP_CONFIG_N_SKT_MASK 0x00000000000003c0UL |
3388 | |
3389 | /* UV3 unique defines */ |
3390 | #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT 0 |
3391 | #define UV3H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL |
3392 | |
3393 | /* UV2 unique defines */ |
3394 | #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_SHFT 0 |
3395 | #define UV2H_RH_GAM_ADDR_MAP_CONFIG_M_SKT_MASK 0x000000000000003fUL |
3396 | |
3397 | |
3398 | union uvh_rh_gam_addr_map_config_u { |
3399 | unsigned long v; |
3400 | |
3401 | /* UVH common struct */ |
3402 | struct uvh_rh_gam_addr_map_config_s { |
3403 | unsigned long rsvd_0_5:6; |
3404 | unsigned long n_skt:4; /* RW */ |
3405 | unsigned long rsvd_10_63:54; |
3406 | } s; |
3407 | |
3408 | /* UVXH common struct */ |
3409 | struct uvxh_rh_gam_addr_map_config_s { |
3410 | unsigned long rsvd_0_5:6; |
3411 | unsigned long n_skt:4; /* RW */ |
3412 | unsigned long rsvd_10_63:54; |
3413 | } sx; |
3414 | |
3415 | /* UV4 unique struct */ |
3416 | struct uv4h_rh_gam_addr_map_config_s { |
3417 | unsigned long rsvd_0_5:6; |
3418 | unsigned long n_skt:4; /* RW */ |
3419 | unsigned long rsvd_10_63:54; |
3420 | } s4; |
3421 | |
3422 | /* UV3 unique struct */ |
3423 | struct uv3h_rh_gam_addr_map_config_s { |
3424 | unsigned long m_skt:6; /* RW */ |
3425 | unsigned long n_skt:4; /* RW */ |
3426 | unsigned long rsvd_10_63:54; |
3427 | } s3; |
3428 | |
3429 | /* UV2 unique struct */ |
3430 | struct uv2h_rh_gam_addr_map_config_s { |
3431 | unsigned long m_skt:6; /* RW */ |
3432 | unsigned long n_skt:4; /* RW */ |
3433 | unsigned long rsvd_10_63:54; |
3434 | } s2; |
3435 | }; |
3436 | |
3437 | /* ========================================================================= */ |
3438 | /* UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG */ |
3439 | /* ========================================================================= */ |
3440 | #define UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG ( \ |
3441 | is_uv(UV4) ? 0x4800c8UL : \ |
3442 | is_uv(UV3) ? 0x16000c8UL : \ |
3443 | is_uv(UV2) ? 0x16000c8UL : \ |
3444 | 0) |
3445 | |
3446 | |
3447 | /* UVXH common defines */ |
3448 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_SHFT 24 |
3449 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
3450 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_SHFT 48 |
3451 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
3452 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3453 | #define UVXH_RH_GAM_ALIAS_0_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3454 | |
3455 | |
3456 | union uvh_rh_gam_alias_0_overlay_config_u { |
3457 | unsigned long v; |
3458 | |
3459 | /* UVH common struct */ |
3460 | struct uvh_rh_gam_alias_0_overlay_config_s { |
3461 | unsigned long rsvd_0_23:24; |
3462 | unsigned long base:8; /* RW */ |
3463 | unsigned long rsvd_32_47:16; |
3464 | unsigned long m_alias:5; /* RW */ |
3465 | unsigned long rsvd_53_62:10; |
3466 | unsigned long enable:1; /* RW */ |
3467 | } s; |
3468 | |
3469 | /* UVXH common struct */ |
3470 | struct uvxh_rh_gam_alias_0_overlay_config_s { |
3471 | unsigned long rsvd_0_23:24; |
3472 | unsigned long base:8; /* RW */ |
3473 | unsigned long rsvd_32_47:16; |
3474 | unsigned long m_alias:5; /* RW */ |
3475 | unsigned long rsvd_53_62:10; |
3476 | unsigned long enable:1; /* RW */ |
3477 | } sx; |
3478 | |
3479 | /* UV4 unique struct */ |
3480 | struct uv4h_rh_gam_alias_0_overlay_config_s { |
3481 | unsigned long rsvd_0_23:24; |
3482 | unsigned long base:8; /* RW */ |
3483 | unsigned long rsvd_32_47:16; |
3484 | unsigned long m_alias:5; /* RW */ |
3485 | unsigned long rsvd_53_62:10; |
3486 | unsigned long enable:1; /* RW */ |
3487 | } s4; |
3488 | |
3489 | /* UV3 unique struct */ |
3490 | struct uv3h_rh_gam_alias_0_overlay_config_s { |
3491 | unsigned long rsvd_0_23:24; |
3492 | unsigned long base:8; /* RW */ |
3493 | unsigned long rsvd_32_47:16; |
3494 | unsigned long m_alias:5; /* RW */ |
3495 | unsigned long rsvd_53_62:10; |
3496 | unsigned long enable:1; /* RW */ |
3497 | } s3; |
3498 | |
3499 | /* UV2 unique struct */ |
3500 | struct uv2h_rh_gam_alias_0_overlay_config_s { |
3501 | unsigned long rsvd_0_23:24; |
3502 | unsigned long base:8; /* RW */ |
3503 | unsigned long rsvd_32_47:16; |
3504 | unsigned long m_alias:5; /* RW */ |
3505 | unsigned long rsvd_53_62:10; |
3506 | unsigned long enable:1; /* RW */ |
3507 | } s2; |
3508 | }; |
3509 | |
3510 | /* ========================================================================= */ |
3511 | /* UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG */ |
3512 | /* ========================================================================= */ |
3513 | #define UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG ( \ |
3514 | is_uv(UV4) ? 0x4800d0UL : \ |
3515 | is_uv(UV3) ? 0x16000d0UL : \ |
3516 | is_uv(UV2) ? 0x16000d0UL : \ |
3517 | 0) |
3518 | |
3519 | |
3520 | /* UVXH common defines */ |
3521 | #define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 24 |
3522 | #define UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL |
3523 | |
3524 | |
3525 | union uvh_rh_gam_alias_0_redirect_config_u { |
3526 | unsigned long v; |
3527 | |
3528 | /* UVH common struct */ |
3529 | struct uvh_rh_gam_alias_0_redirect_config_s { |
3530 | unsigned long rsvd_0_23:24; |
3531 | unsigned long dest_base:22; /* RW */ |
3532 | unsigned long rsvd_46_63:18; |
3533 | } s; |
3534 | |
3535 | /* UVXH common struct */ |
3536 | struct uvxh_rh_gam_alias_0_redirect_config_s { |
3537 | unsigned long rsvd_0_23:24; |
3538 | unsigned long dest_base:22; /* RW */ |
3539 | unsigned long rsvd_46_63:18; |
3540 | } sx; |
3541 | |
3542 | /* UV4 unique struct */ |
3543 | struct uv4h_rh_gam_alias_0_redirect_config_s { |
3544 | unsigned long rsvd_0_23:24; |
3545 | unsigned long dest_base:22; /* RW */ |
3546 | unsigned long rsvd_46_63:18; |
3547 | } s4; |
3548 | |
3549 | /* UV3 unique struct */ |
3550 | struct uv3h_rh_gam_alias_0_redirect_config_s { |
3551 | unsigned long rsvd_0_23:24; |
3552 | unsigned long dest_base:22; /* RW */ |
3553 | unsigned long rsvd_46_63:18; |
3554 | } s3; |
3555 | |
3556 | /* UV2 unique struct */ |
3557 | struct uv2h_rh_gam_alias_0_redirect_config_s { |
3558 | unsigned long rsvd_0_23:24; |
3559 | unsigned long dest_base:22; /* RW */ |
3560 | unsigned long rsvd_46_63:18; |
3561 | } s2; |
3562 | }; |
3563 | |
3564 | /* ========================================================================= */ |
3565 | /* UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG */ |
3566 | /* ========================================================================= */ |
3567 | #define UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG ( \ |
3568 | is_uv(UV4) ? 0x4800d8UL : \ |
3569 | is_uv(UV3) ? 0x16000d8UL : \ |
3570 | is_uv(UV2) ? 0x16000d8UL : \ |
3571 | 0) |
3572 | |
3573 | |
3574 | /* UVXH common defines */ |
3575 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_SHFT 24 |
3576 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
3577 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_SHFT 48 |
3578 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
3579 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3580 | #define UVXH_RH_GAM_ALIAS_1_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3581 | |
3582 | |
3583 | union uvh_rh_gam_alias_1_overlay_config_u { |
3584 | unsigned long v; |
3585 | |
3586 | /* UVH common struct */ |
3587 | struct uvh_rh_gam_alias_1_overlay_config_s { |
3588 | unsigned long rsvd_0_23:24; |
3589 | unsigned long base:8; /* RW */ |
3590 | unsigned long rsvd_32_47:16; |
3591 | unsigned long m_alias:5; /* RW */ |
3592 | unsigned long rsvd_53_62:10; |
3593 | unsigned long enable:1; /* RW */ |
3594 | } s; |
3595 | |
3596 | /* UVXH common struct */ |
3597 | struct uvxh_rh_gam_alias_1_overlay_config_s { |
3598 | unsigned long rsvd_0_23:24; |
3599 | unsigned long base:8; /* RW */ |
3600 | unsigned long rsvd_32_47:16; |
3601 | unsigned long m_alias:5; /* RW */ |
3602 | unsigned long rsvd_53_62:10; |
3603 | unsigned long enable:1; /* RW */ |
3604 | } sx; |
3605 | |
3606 | /* UV4 unique struct */ |
3607 | struct uv4h_rh_gam_alias_1_overlay_config_s { |
3608 | unsigned long rsvd_0_23:24; |
3609 | unsigned long base:8; /* RW */ |
3610 | unsigned long rsvd_32_47:16; |
3611 | unsigned long m_alias:5; /* RW */ |
3612 | unsigned long rsvd_53_62:10; |
3613 | unsigned long enable:1; /* RW */ |
3614 | } s4; |
3615 | |
3616 | /* UV3 unique struct */ |
3617 | struct uv3h_rh_gam_alias_1_overlay_config_s { |
3618 | unsigned long rsvd_0_23:24; |
3619 | unsigned long base:8; /* RW */ |
3620 | unsigned long rsvd_32_47:16; |
3621 | unsigned long m_alias:5; /* RW */ |
3622 | unsigned long rsvd_53_62:10; |
3623 | unsigned long enable:1; /* RW */ |
3624 | } s3; |
3625 | |
3626 | /* UV2 unique struct */ |
3627 | struct uv2h_rh_gam_alias_1_overlay_config_s { |
3628 | unsigned long rsvd_0_23:24; |
3629 | unsigned long base:8; /* RW */ |
3630 | unsigned long rsvd_32_47:16; |
3631 | unsigned long m_alias:5; /* RW */ |
3632 | unsigned long rsvd_53_62:10; |
3633 | unsigned long enable:1; /* RW */ |
3634 | } s2; |
3635 | }; |
3636 | |
3637 | /* ========================================================================= */ |
3638 | /* UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG */ |
3639 | /* ========================================================================= */ |
3640 | #define UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG ( \ |
3641 | is_uv(UV4) ? 0x4800e0UL : \ |
3642 | is_uv(UV3) ? 0x16000e0UL : \ |
3643 | is_uv(UV2) ? 0x16000e0UL : \ |
3644 | 0) |
3645 | |
3646 | |
3647 | /* UVXH common defines */ |
3648 | #define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_SHFT 24 |
3649 | #define UVXH_RH_GAM_ALIAS_1_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL |
3650 | |
3651 | |
3652 | union uvh_rh_gam_alias_1_redirect_config_u { |
3653 | unsigned long v; |
3654 | |
3655 | /* UVH common struct */ |
3656 | struct uvh_rh_gam_alias_1_redirect_config_s { |
3657 | unsigned long rsvd_0_23:24; |
3658 | unsigned long dest_base:22; /* RW */ |
3659 | unsigned long rsvd_46_63:18; |
3660 | } s; |
3661 | |
3662 | /* UVXH common struct */ |
3663 | struct uvxh_rh_gam_alias_1_redirect_config_s { |
3664 | unsigned long rsvd_0_23:24; |
3665 | unsigned long dest_base:22; /* RW */ |
3666 | unsigned long rsvd_46_63:18; |
3667 | } sx; |
3668 | |
3669 | /* UV4 unique struct */ |
3670 | struct uv4h_rh_gam_alias_1_redirect_config_s { |
3671 | unsigned long rsvd_0_23:24; |
3672 | unsigned long dest_base:22; /* RW */ |
3673 | unsigned long rsvd_46_63:18; |
3674 | } s4; |
3675 | |
3676 | /* UV3 unique struct */ |
3677 | struct uv3h_rh_gam_alias_1_redirect_config_s { |
3678 | unsigned long rsvd_0_23:24; |
3679 | unsigned long dest_base:22; /* RW */ |
3680 | unsigned long rsvd_46_63:18; |
3681 | } s3; |
3682 | |
3683 | /* UV2 unique struct */ |
3684 | struct uv2h_rh_gam_alias_1_redirect_config_s { |
3685 | unsigned long rsvd_0_23:24; |
3686 | unsigned long dest_base:22; /* RW */ |
3687 | unsigned long rsvd_46_63:18; |
3688 | } s2; |
3689 | }; |
3690 | |
3691 | /* ========================================================================= */ |
3692 | /* UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG */ |
3693 | /* ========================================================================= */ |
3694 | #define UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG ( \ |
3695 | is_uv(UV4) ? 0x4800e8UL : \ |
3696 | is_uv(UV3) ? 0x16000e8UL : \ |
3697 | is_uv(UV2) ? 0x16000e8UL : \ |
3698 | 0) |
3699 | |
3700 | |
3701 | /* UVXH common defines */ |
3702 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_SHFT 24 |
3703 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_BASE_MASK 0x00000000ff000000UL |
3704 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_SHFT 48 |
3705 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_M_ALIAS_MASK 0x001f000000000000UL |
3706 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3707 | #define UVXH_RH_GAM_ALIAS_2_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3708 | |
3709 | |
3710 | union uvh_rh_gam_alias_2_overlay_config_u { |
3711 | unsigned long v; |
3712 | |
3713 | /* UVH common struct */ |
3714 | struct uvh_rh_gam_alias_2_overlay_config_s { |
3715 | unsigned long rsvd_0_23:24; |
3716 | unsigned long base:8; /* RW */ |
3717 | unsigned long rsvd_32_47:16; |
3718 | unsigned long m_alias:5; /* RW */ |
3719 | unsigned long rsvd_53_62:10; |
3720 | unsigned long enable:1; /* RW */ |
3721 | } s; |
3722 | |
3723 | /* UVXH common struct */ |
3724 | struct uvxh_rh_gam_alias_2_overlay_config_s { |
3725 | unsigned long rsvd_0_23:24; |
3726 | unsigned long base:8; /* RW */ |
3727 | unsigned long rsvd_32_47:16; |
3728 | unsigned long m_alias:5; /* RW */ |
3729 | unsigned long rsvd_53_62:10; |
3730 | unsigned long enable:1; /* RW */ |
3731 | } sx; |
3732 | |
3733 | /* UV4 unique struct */ |
3734 | struct uv4h_rh_gam_alias_2_overlay_config_s { |
3735 | unsigned long rsvd_0_23:24; |
3736 | unsigned long base:8; /* RW */ |
3737 | unsigned long rsvd_32_47:16; |
3738 | unsigned long m_alias:5; /* RW */ |
3739 | unsigned long rsvd_53_62:10; |
3740 | unsigned long enable:1; /* RW */ |
3741 | } s4; |
3742 | |
3743 | /* UV3 unique struct */ |
3744 | struct uv3h_rh_gam_alias_2_overlay_config_s { |
3745 | unsigned long rsvd_0_23:24; |
3746 | unsigned long base:8; /* RW */ |
3747 | unsigned long rsvd_32_47:16; |
3748 | unsigned long m_alias:5; /* RW */ |
3749 | unsigned long rsvd_53_62:10; |
3750 | unsigned long enable:1; /* RW */ |
3751 | } s3; |
3752 | |
3753 | /* UV2 unique struct */ |
3754 | struct uv2h_rh_gam_alias_2_overlay_config_s { |
3755 | unsigned long rsvd_0_23:24; |
3756 | unsigned long base:8; /* RW */ |
3757 | unsigned long rsvd_32_47:16; |
3758 | unsigned long m_alias:5; /* RW */ |
3759 | unsigned long rsvd_53_62:10; |
3760 | unsigned long enable:1; /* RW */ |
3761 | } s2; |
3762 | }; |
3763 | |
3764 | /* ========================================================================= */ |
3765 | /* UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG */ |
3766 | /* ========================================================================= */ |
3767 | #define UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG ( \ |
3768 | is_uv(UV4) ? 0x4800f0UL : \ |
3769 | is_uv(UV3) ? 0x16000f0UL : \ |
3770 | is_uv(UV2) ? 0x16000f0UL : \ |
3771 | 0) |
3772 | |
3773 | |
3774 | /* UVXH common defines */ |
3775 | #define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_SHFT 24 |
3776 | #define UVXH_RH_GAM_ALIAS_2_REDIRECT_CONFIG_DEST_BASE_MASK 0x00003fffff000000UL |
3777 | |
3778 | |
3779 | union uvh_rh_gam_alias_2_redirect_config_u { |
3780 | unsigned long v; |
3781 | |
3782 | /* UVH common struct */ |
3783 | struct uvh_rh_gam_alias_2_redirect_config_s { |
3784 | unsigned long rsvd_0_23:24; |
3785 | unsigned long dest_base:22; /* RW */ |
3786 | unsigned long rsvd_46_63:18; |
3787 | } s; |
3788 | |
3789 | /* UVXH common struct */ |
3790 | struct uvxh_rh_gam_alias_2_redirect_config_s { |
3791 | unsigned long rsvd_0_23:24; |
3792 | unsigned long dest_base:22; /* RW */ |
3793 | unsigned long rsvd_46_63:18; |
3794 | } sx; |
3795 | |
3796 | /* UV4 unique struct */ |
3797 | struct uv4h_rh_gam_alias_2_redirect_config_s { |
3798 | unsigned long rsvd_0_23:24; |
3799 | unsigned long dest_base:22; /* RW */ |
3800 | unsigned long rsvd_46_63:18; |
3801 | } s4; |
3802 | |
3803 | /* UV3 unique struct */ |
3804 | struct uv3h_rh_gam_alias_2_redirect_config_s { |
3805 | unsigned long rsvd_0_23:24; |
3806 | unsigned long dest_base:22; /* RW */ |
3807 | unsigned long rsvd_46_63:18; |
3808 | } s3; |
3809 | |
3810 | /* UV2 unique struct */ |
3811 | struct uv2h_rh_gam_alias_2_redirect_config_s { |
3812 | unsigned long rsvd_0_23:24; |
3813 | unsigned long dest_base:22; /* RW */ |
3814 | unsigned long rsvd_46_63:18; |
3815 | } s2; |
3816 | }; |
3817 | |
3818 | /* ========================================================================= */ |
3819 | /* UVH_RH_GAM_GRU_OVERLAY_CONFIG */ |
3820 | /* ========================================================================= */ |
3821 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG ( \ |
3822 | is_uv(UV4) ? 0x480010UL : \ |
3823 | is_uv(UV3) ? 0x1600010UL : \ |
3824 | is_uv(UV2) ? 0x1600010UL : \ |
3825 | 0) |
3826 | |
3827 | |
3828 | /* UVXH common defines */ |
3829 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_SHFT 52 |
3830 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_N_GRU_MASK 0x00f0000000000000UL |
3831 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3832 | #define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3833 | |
3834 | /* UV4A unique defines */ |
3835 | #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 26 |
3836 | #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffc000000UL |
3837 | |
3838 | /* UV4 unique defines */ |
3839 | #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 26 |
3840 | #define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffffc000000UL |
3841 | |
3842 | /* UV3 unique defines */ |
3843 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 28 |
3844 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffff0000000UL |
3845 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_SHFT 62 |
3846 | #define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MODE_MASK 0x4000000000000000UL |
3847 | |
3848 | /* UV2 unique defines */ |
3849 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 28 |
3850 | #define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x00003ffff0000000UL |
3851 | |
3852 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK ( \ |
3853 | is_uv(UV4A) ? 0x000ffffffc000000UL : \ |
3854 | is_uv(UV4) ? 0x00003ffffc000000UL : \ |
3855 | is_uv(UV3) ? 0x00003ffff0000000UL : \ |
3856 | is_uv(UV2) ? 0x00003ffff0000000UL : \ |
3857 | 0) |
3858 | #define UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT ( \ |
3859 | is_uv(UV4) ? 26 : \ |
3860 | is_uv(UV3) ? 28 : \ |
3861 | is_uv(UV2) ? 28 : \ |
3862 | -1) |
3863 | |
3864 | union uvh_rh_gam_gru_overlay_config_u { |
3865 | unsigned long v; |
3866 | |
3867 | /* UVH common struct */ |
3868 | struct uvh_rh_gam_gru_overlay_config_s { |
3869 | unsigned long rsvd_0_45:46; |
3870 | unsigned long rsvd_46_51:6; |
3871 | unsigned long n_gru:4; /* RW */ |
3872 | unsigned long rsvd_56_62:7; |
3873 | unsigned long enable:1; /* RW */ |
3874 | } s; |
3875 | |
3876 | /* UVXH common struct */ |
3877 | struct uvxh_rh_gam_gru_overlay_config_s { |
3878 | unsigned long rsvd_0_45:46; |
3879 | unsigned long rsvd_46_51:6; |
3880 | unsigned long n_gru:4; /* RW */ |
3881 | unsigned long rsvd_56_62:7; |
3882 | unsigned long enable:1; /* RW */ |
3883 | } sx; |
3884 | |
3885 | /* UV4A unique struct */ |
3886 | struct uv4ah_rh_gam_gru_overlay_config_s { |
3887 | unsigned long rsvd_0_24:25; |
3888 | unsigned long undef_25:1; /* Undefined */ |
3889 | unsigned long base:26; /* RW */ |
3890 | unsigned long n_gru:4; /* RW */ |
3891 | unsigned long rsvd_56_62:7; |
3892 | unsigned long enable:1; /* RW */ |
3893 | } s4a; |
3894 | |
3895 | /* UV4 unique struct */ |
3896 | struct uv4h_rh_gam_gru_overlay_config_s { |
3897 | unsigned long rsvd_0_24:25; |
3898 | unsigned long undef_25:1; /* Undefined */ |
3899 | unsigned long base:20; /* RW */ |
3900 | unsigned long rsvd_46_51:6; |
3901 | unsigned long n_gru:4; /* RW */ |
3902 | unsigned long rsvd_56_62:7; |
3903 | unsigned long enable:1; /* RW */ |
3904 | } s4; |
3905 | |
3906 | /* UV3 unique struct */ |
3907 | struct uv3h_rh_gam_gru_overlay_config_s { |
3908 | unsigned long rsvd_0_27:28; |
3909 | unsigned long base:18; /* RW */ |
3910 | unsigned long rsvd_46_51:6; |
3911 | unsigned long n_gru:4; /* RW */ |
3912 | unsigned long rsvd_56_61:6; |
3913 | unsigned long mode:1; /* RW */ |
3914 | unsigned long enable:1; /* RW */ |
3915 | } s3; |
3916 | |
3917 | /* UV2 unique struct */ |
3918 | struct uv2h_rh_gam_gru_overlay_config_s { |
3919 | unsigned long rsvd_0_27:28; |
3920 | unsigned long base:18; /* RW */ |
3921 | unsigned long rsvd_46_51:6; |
3922 | unsigned long n_gru:4; /* RW */ |
3923 | unsigned long rsvd_56_62:7; |
3924 | unsigned long enable:1; /* RW */ |
3925 | } s2; |
3926 | }; |
3927 | |
3928 | /* ========================================================================= */ |
3929 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG */ |
3930 | /* ========================================================================= */ |
3931 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG ( \ |
3932 | is_uv(UV2) ? 0x1600030UL : \ |
3933 | 0) |
3934 | |
3935 | |
3936 | |
3937 | /* UV2 unique defines */ |
3938 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT 27 |
3939 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_MASK 0x00003ffff8000000UL |
3940 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_SHFT 46 |
3941 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_M_IO_MASK 0x000fc00000000000UL |
3942 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_SHFT 52 |
3943 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_N_IO_MASK 0x00f0000000000000UL |
3944 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_SHFT 63 |
3945 | #define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
3946 | |
3947 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT ( \ |
3948 | is_uv(UV2) ? 27 : \ |
3949 | uv_undefined("UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT")) |
3950 | |
3951 | union uvh_rh_gam_mmioh_overlay_config_u { |
3952 | unsigned long v; |
3953 | |
3954 | /* UVH common struct */ |
3955 | struct uvh_rh_gam_mmioh_overlay_config_s { |
3956 | unsigned long rsvd_0_26:27; |
3957 | unsigned long base:19; /* RW */ |
3958 | unsigned long m_io:6; /* RW */ |
3959 | unsigned long n_io:4; /* RW */ |
3960 | unsigned long rsvd_56_62:7; |
3961 | unsigned long enable:1; /* RW */ |
3962 | } s; |
3963 | |
3964 | /* UVXH common struct */ |
3965 | struct uvxh_rh_gam_mmioh_overlay_config_s { |
3966 | unsigned long rsvd_0_26:27; |
3967 | unsigned long base:19; /* RW */ |
3968 | unsigned long m_io:6; /* RW */ |
3969 | unsigned long n_io:4; /* RW */ |
3970 | unsigned long rsvd_56_62:7; |
3971 | unsigned long enable:1; /* RW */ |
3972 | } sx; |
3973 | |
3974 | /* UV2 unique struct */ |
3975 | struct uv2h_rh_gam_mmioh_overlay_config_s { |
3976 | unsigned long rsvd_0_26:27; |
3977 | unsigned long base:19; /* RW */ |
3978 | unsigned long m_io:6; /* RW */ |
3979 | unsigned long n_io:4; /* RW */ |
3980 | unsigned long rsvd_56_62:7; |
3981 | unsigned long enable:1; /* RW */ |
3982 | } s2; |
3983 | }; |
3984 | |
3985 | /* ========================================================================= */ |
3986 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0 */ |
3987 | /* ========================================================================= */ |
3988 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0 ( \ |
3989 | is_uv(UV4) ? 0x483000UL : \ |
3990 | is_uv(UV3) ? 0x1603000UL : \ |
3991 | 0) |
3992 | |
3993 | /* UV4A unique defines */ |
3994 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT 26 |
3995 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x000ffffffc000000UL |
3996 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT 52 |
3997 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x03f0000000000000UL |
3998 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT 63 |
3999 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL |
4000 | |
4001 | /* UV4 unique defines */ |
4002 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT 26 |
4003 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x00003ffffc000000UL |
4004 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT 46 |
4005 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x000fc00000000000UL |
4006 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT 63 |
4007 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL |
4008 | |
4009 | /* UV3 unique defines */ |
4010 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT 26 |
4011 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK 0x00003ffffc000000UL |
4012 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_SHFT 46 |
4013 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_M_IO_MASK 0x000fc00000000000UL |
4014 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_SHFT 63 |
4015 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_ENABLE_MASK 0x8000000000000000UL |
4016 | |
4017 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK ( \ |
4018 | is_uv(UV4A) ? 0x000ffffffc000000UL : \ |
4019 | is_uv(UV4) ? 0x00003ffffc000000UL : \ |
4020 | is_uv(UV3) ? 0x00003ffffc000000UL : \ |
4021 | 0) |
4022 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT ( \ |
4023 | is_uv(UV4) ? 26 : \ |
4024 | is_uv(UV3) ? 26 : \ |
4025 | -1) |
4026 | |
4027 | union uvh_rh_gam_mmioh_overlay_config0_u { |
4028 | unsigned long v; |
4029 | |
4030 | /* UVH common struct */ |
4031 | struct uvh_rh_gam_mmioh_overlay_config0_s { |
4032 | unsigned long rsvd_0_25:26; |
4033 | unsigned long base:20; /* RW */ |
4034 | unsigned long m_io:6; /* RW */ |
4035 | unsigned long n_io:4; |
4036 | unsigned long rsvd_56_62:7; |
4037 | unsigned long enable:1; /* RW */ |
4038 | } s; |
4039 | |
4040 | /* UVXH common struct */ |
4041 | struct uvxh_rh_gam_mmioh_overlay_config0_s { |
4042 | unsigned long rsvd_0_25:26; |
4043 | unsigned long base:20; /* RW */ |
4044 | unsigned long m_io:6; /* RW */ |
4045 | unsigned long n_io:4; |
4046 | unsigned long rsvd_56_62:7; |
4047 | unsigned long enable:1; /* RW */ |
4048 | } sx; |
4049 | |
4050 | /* UV4A unique struct */ |
4051 | struct uv4ah_rh_gam_mmioh_overlay_config0_mmr_s { |
4052 | unsigned long rsvd_0_25:26; |
4053 | unsigned long base:26; /* RW */ |
4054 | unsigned long m_io:6; /* RW */ |
4055 | unsigned long n_io:4; |
4056 | unsigned long undef_62:1; /* Undefined */ |
4057 | unsigned long enable:1; /* RW */ |
4058 | } s4a; |
4059 | |
4060 | /* UV4 unique struct */ |
4061 | struct uv4h_rh_gam_mmioh_overlay_config0_s { |
4062 | unsigned long rsvd_0_25:26; |
4063 | unsigned long base:20; /* RW */ |
4064 | unsigned long m_io:6; /* RW */ |
4065 | unsigned long n_io:4; |
4066 | unsigned long rsvd_56_62:7; |
4067 | unsigned long enable:1; /* RW */ |
4068 | } s4; |
4069 | |
4070 | /* UV3 unique struct */ |
4071 | struct uv3h_rh_gam_mmioh_overlay_config0_s { |
4072 | unsigned long rsvd_0_25:26; |
4073 | unsigned long base:20; /* RW */ |
4074 | unsigned long m_io:6; /* RW */ |
4075 | unsigned long n_io:4; |
4076 | unsigned long rsvd_56_62:7; |
4077 | unsigned long enable:1; /* RW */ |
4078 | } s3; |
4079 | }; |
4080 | |
4081 | /* ========================================================================= */ |
4082 | /* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1 */ |
4083 | /* ========================================================================= */ |
4084 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1 ( \ |
4085 | is_uv(UV4) ? 0x484000UL : \ |
4086 | is_uv(UV3) ? 0x1604000UL : \ |
4087 | 0) |
4088 | |
4089 | /* UV4A unique defines */ |
4090 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT 26 |
4091 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x000ffffffc000000UL |
4092 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT 52 |
4093 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x03f0000000000000UL |
4094 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT 63 |
4095 | #define UV4AH_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL |
4096 | |
4097 | /* UV4 unique defines */ |
4098 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT 26 |
4099 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x00003ffffc000000UL |
4100 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT 46 |
4101 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x000fc00000000000UL |
4102 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT 63 |
4103 | #define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL |
4104 | |
4105 | /* UV3 unique defines */ |
4106 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT 26 |
4107 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK 0x00003ffffc000000UL |
4108 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_SHFT 46 |
4109 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_M_IO_MASK 0x000fc00000000000UL |
4110 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_SHFT 63 |
4111 | #define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_ENABLE_MASK 0x8000000000000000UL |
4112 | |
4113 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK ( \ |
4114 | is_uv(UV4A) ? 0x000ffffffc000000UL : \ |
4115 | is_uv(UV4) ? 0x00003ffffc000000UL : \ |
4116 | is_uv(UV3) ? 0x00003ffffc000000UL : \ |
4117 | 0) |
4118 | #define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT ( \ |
4119 | is_uv(UV4) ? 26 : \ |
4120 | is_uv(UV3) ? 26 : \ |
4121 | -1) |
4122 | |
4123 | union uvh_rh_gam_mmioh_overlay_config1_u { |
4124 | unsigned long v; |
4125 | |
4126 | /* UVH common struct */ |
4127 | struct uvh_rh_gam_mmioh_overlay_config1_s { |
4128 | unsigned long rsvd_0_25:26; |
4129 | unsigned long base:20; /* RW */ |
4130 | unsigned long m_io:6; /* RW */ |
4131 | unsigned long n_io:4; |
4132 | unsigned long rsvd_56_62:7; |
4133 | unsigned long enable:1; /* RW */ |
4134 | } s; |
4135 | |
4136 | /* UVXH common struct */ |
4137 | struct uvxh_rh_gam_mmioh_overlay_config1_s { |
4138 | unsigned long rsvd_0_25:26; |
4139 | unsigned long base:20; /* RW */ |
4140 | unsigned long m_io:6; /* RW */ |
4141 | unsigned long n_io:4; |
4142 | unsigned long rsvd_56_62:7; |
4143 | unsigned long enable:1; /* RW */ |
4144 | } sx; |
4145 | |
4146 | /* UV4A unique struct */ |
4147 | struct uv4ah_rh_gam_mmioh_overlay_config1_mmr_s { |
4148 | unsigned long rsvd_0_25:26; |
4149 | unsigned long base:26; /* RW */ |
4150 | unsigned long m_io:6; /* RW */ |
4151 | unsigned long n_io:4; |
4152 | unsigned long undef_62:1; /* Undefined */ |
4153 | unsigned long enable:1; /* RW */ |
4154 | } s4a; |
4155 | |
4156 | /* UV4 unique struct */ |
4157 | struct uv4h_rh_gam_mmioh_overlay_config1_s { |
4158 | unsigned long rsvd_0_25:26; |
4159 | unsigned long base:20; /* RW */ |
4160 | unsigned long m_io:6; /* RW */ |
4161 | unsigned long n_io:4; |
4162 | unsigned long rsvd_56_62:7; |
4163 | unsigned long enable:1; /* RW */ |
4164 | } s4; |
4165 | |
4166 | /* UV3 unique struct */ |
4167 | struct uv3h_rh_gam_mmioh_overlay_config1_s { |
4168 | unsigned long rsvd_0_25:26; |
4169 | unsigned long base:20; /* RW */ |
4170 | unsigned long m_io:6; /* RW */ |
4171 | unsigned long n_io:4; |
4172 | unsigned long rsvd_56_62:7; |
4173 | unsigned long enable:1; /* RW */ |
4174 | } s3; |
4175 | }; |
4176 | |
4177 | /* ========================================================================= */ |
4178 | /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0 */ |
4179 | /* ========================================================================= */ |
4180 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0 ( \ |
4181 | is_uv(UV4) ? 0x483800UL : \ |
4182 | is_uv(UV3) ? 0x1603800UL : \ |
4183 | 0) |
4184 | |
4185 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH ( \ |
4186 | is_uv(UV4) ? 128 : \ |
4187 | is_uv(UV3) ? 128 : \ |
4188 | 0) |
4189 | |
4190 | /* UV4A unique defines */ |
4191 | #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0 |
4192 | #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000000fffUL |
4193 | |
4194 | /* UV4 unique defines */ |
4195 | #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0 |
4196 | #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000007fffUL |
4197 | |
4198 | /* UV3 unique defines */ |
4199 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_SHFT 0 |
4200 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK 0x0000000000007fffUL |
4201 | |
4202 | /* UVH common defines */ |
4203 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK ( \ |
4204 | is_uv(UV4A) ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK : \ |
4205 | is_uv(UV4) ? UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK : \ |
4206 | is_uv(UV3) ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK : \ |
4207 | 0) |
4208 | |
4209 | |
4210 | union uvh_rh_gam_mmioh_redirect_config0_u { |
4211 | unsigned long v; |
4212 | |
4213 | /* UVH common struct */ |
4214 | struct uvh_rh_gam_mmioh_redirect_config0_s { |
4215 | unsigned long nasid:15; /* RW */ |
4216 | unsigned long rsvd_15_63:49; |
4217 | } s; |
4218 | |
4219 | /* UVXH common struct */ |
4220 | struct uvxh_rh_gam_mmioh_redirect_config0_s { |
4221 | unsigned long nasid:15; /* RW */ |
4222 | unsigned long rsvd_15_63:49; |
4223 | } sx; |
4224 | |
4225 | struct uv4ah_rh_gam_mmioh_redirect_config0_s { |
4226 | unsigned long nasid:12; /* RW */ |
4227 | unsigned long rsvd_12_63:52; |
4228 | } s4a; |
4229 | |
4230 | /* UV4 unique struct */ |
4231 | struct uv4h_rh_gam_mmioh_redirect_config0_s { |
4232 | unsigned long nasid:15; /* RW */ |
4233 | unsigned long rsvd_15_63:49; |
4234 | } s4; |
4235 | |
4236 | /* UV3 unique struct */ |
4237 | struct uv3h_rh_gam_mmioh_redirect_config0_s { |
4238 | unsigned long nasid:15; /* RW */ |
4239 | unsigned long rsvd_15_63:49; |
4240 | } s3; |
4241 | }; |
4242 | |
4243 | /* ========================================================================= */ |
4244 | /* UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1 */ |
4245 | /* ========================================================================= */ |
4246 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1 ( \ |
4247 | is_uv(UV4) ? 0x484800UL : \ |
4248 | is_uv(UV3) ? 0x1604800UL : \ |
4249 | 0) |
4250 | |
4251 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH ( \ |
4252 | is_uv(UV4) ? 128 : \ |
4253 | is_uv(UV3) ? 128 : \ |
4254 | 0) |
4255 | |
4256 | /* UV4A unique defines */ |
4257 | #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0 |
4258 | #define UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000000fffUL |
4259 | |
4260 | /* UV4 unique defines */ |
4261 | #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0 |
4262 | #define UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000007fffUL |
4263 | |
4264 | /* UV3 unique defines */ |
4265 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_SHFT 0 |
4266 | #define UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK 0x0000000000007fffUL |
4267 | |
4268 | /* UVH common defines */ |
4269 | #define UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK ( \ |
4270 | is_uv(UV4A) ? UV4AH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK : \ |
4271 | is_uv(UV4) ? UV4H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK : \ |
4272 | is_uv(UV3) ? UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK : \ |
4273 | 0) |
4274 | |
4275 | |
4276 | union uvh_rh_gam_mmioh_redirect_config1_u { |
4277 | unsigned long v; |
4278 | |
4279 | /* UVH common struct */ |
4280 | struct uvh_rh_gam_mmioh_redirect_config1_s { |
4281 | unsigned long nasid:15; /* RW */ |
4282 | unsigned long rsvd_15_63:49; |
4283 | } s; |
4284 | |
4285 | /* UVXH common struct */ |
4286 | struct uvxh_rh_gam_mmioh_redirect_config1_s { |
4287 | unsigned long nasid:15; /* RW */ |
4288 | unsigned long rsvd_15_63:49; |
4289 | } sx; |
4290 | |
4291 | struct uv4ah_rh_gam_mmioh_redirect_config1_s { |
4292 | unsigned long nasid:12; /* RW */ |
4293 | unsigned long rsvd_12_63:52; |
4294 | } s4a; |
4295 | |
4296 | /* UV4 unique struct */ |
4297 | struct uv4h_rh_gam_mmioh_redirect_config1_s { |
4298 | unsigned long nasid:15; /* RW */ |
4299 | unsigned long rsvd_15_63:49; |
4300 | } s4; |
4301 | |
4302 | /* UV3 unique struct */ |
4303 | struct uv3h_rh_gam_mmioh_redirect_config1_s { |
4304 | unsigned long nasid:15; /* RW */ |
4305 | unsigned long rsvd_15_63:49; |
4306 | } s3; |
4307 | }; |
4308 | |
4309 | /* ========================================================================= */ |
4310 | /* UVH_RH_GAM_MMR_OVERLAY_CONFIG */ |
4311 | /* ========================================================================= */ |
4312 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG ( \ |
4313 | is_uv(UV4) ? 0x480028UL : \ |
4314 | is_uv(UV3) ? 0x1600028UL : \ |
4315 | is_uv(UV2) ? 0x1600028UL : \ |
4316 | 0) |
4317 | |
4318 | |
4319 | /* UVXH common defines */ |
4320 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT 26 |
4321 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK ( \ |
4322 | is_uv(UV4A) ? 0x000ffffffc000000UL : \ |
4323 | is_uv(UV4) ? 0x00003ffffc000000UL : \ |
4324 | is_uv(UV3) ? 0x00003ffffc000000UL : \ |
4325 | is_uv(UV2) ? 0x00003ffffc000000UL : \ |
4326 | 0) |
4327 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_SHFT 63 |
4328 | #define UVXH_RH_GAM_MMR_OVERLAY_CONFIG_ENABLE_MASK 0x8000000000000000UL |
4329 | |
4330 | /* UV4A unique defines */ |
4331 | #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT 26 |
4332 | #define UV4AH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK 0x000ffffffc000000UL |
4333 | |
4334 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_MASK ( \ |
4335 | is_uv(UV4A) ? 0x000ffffffc000000UL : \ |
4336 | is_uv(UV4) ? 0x00003ffffc000000UL : \ |
4337 | is_uv(UV3) ? 0x00003ffffc000000UL : \ |
4338 | is_uv(UV2) ? 0x00003ffffc000000UL : \ |
4339 | 0) |
4340 | |
4341 | #define UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT ( \ |
4342 | is_uv(UV4) ? 26 : \ |
4343 | is_uv(UV3) ? 26 : \ |
4344 | is_uv(UV2) ? 26 : \ |
4345 | -1) |
4346 | |
4347 | union uvh_rh_gam_mmr_overlay_config_u { |
4348 | unsigned long v; |
4349 | |
4350 | /* UVH common struct */ |
4351 | struct uvh_rh_gam_mmr_overlay_config_s { |
4352 | unsigned long rsvd_0_25:26; |
4353 | unsigned long base:20; /* RW */ |
4354 | unsigned long rsvd_46_62:17; |
4355 | unsigned long enable:1; /* RW */ |
4356 | } s; |
4357 | |
4358 | /* UVXH common struct */ |
4359 | struct uvxh_rh_gam_mmr_overlay_config_s { |
4360 | unsigned long rsvd_0_25:26; |
4361 | unsigned long base:20; /* RW */ |
4362 | unsigned long rsvd_46_62:17; |
4363 | unsigned long enable:1; /* RW */ |
4364 | } sx; |
4365 | |
4366 | /* UV4 unique struct */ |
4367 | struct uv4h_rh_gam_mmr_overlay_config_s { |
4368 | unsigned long rsvd_0_25:26; |
4369 | unsigned long base:20; /* RW */ |
4370 | unsigned long rsvd_46_62:17; |
4371 | unsigned long enable:1; /* RW */ |
4372 | } s4; |
4373 | |
4374 | /* UV3 unique struct */ |
4375 | struct uv3h_rh_gam_mmr_overlay_config_s { |
4376 | unsigned long rsvd_0_25:26; |
4377 | unsigned long base:20; /* RW */ |
4378 | unsigned long rsvd_46_62:17; |
4379 | unsigned long enable:1; /* RW */ |
4380 | } s3; |
4381 | |
4382 | /* UV2 unique struct */ |
4383 | struct uv2h_rh_gam_mmr_overlay_config_s { |
4384 | unsigned long rsvd_0_25:26; |
4385 | unsigned long base:20; /* RW */ |
4386 | unsigned long rsvd_46_62:17; |
4387 | unsigned long enable:1; /* RW */ |
4388 | } s2; |
4389 | }; |
4390 | |
4391 | /* ========================================================================= */ |
4392 | /* UVH_RTC */ |
4393 | /* ========================================================================= */ |
4394 | #define UVH_RTC ( \ |
4395 | is_uv(UV5) ? 0xe0000UL : \ |
4396 | is_uv(UV4) ? 0xe0000UL : \ |
4397 | is_uv(UV3) ? 0x340000UL : \ |
4398 | is_uv(UV2) ? 0x340000UL : \ |
4399 | 0) |
4400 | |
4401 | /* UVH common defines*/ |
4402 | #define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 |
4403 | #define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL |
4404 | |
4405 | |
4406 | union uvh_rtc_u { |
4407 | unsigned long v; |
4408 | |
4409 | /* UVH common struct */ |
4410 | struct uvh_rtc_s { |
4411 | unsigned long real_time_clock:56; /* RW */ |
4412 | unsigned long rsvd_56_63:8; |
4413 | } s; |
4414 | |
4415 | /* UV5 unique struct */ |
4416 | struct uv5h_rtc_s { |
4417 | unsigned long real_time_clock:56; /* RW */ |
4418 | unsigned long rsvd_56_63:8; |
4419 | } s5; |
4420 | |
4421 | /* UV4 unique struct */ |
4422 | struct uv4h_rtc_s { |
4423 | unsigned long real_time_clock:56; /* RW */ |
4424 | unsigned long rsvd_56_63:8; |
4425 | } s4; |
4426 | |
4427 | /* UV3 unique struct */ |
4428 | struct uv3h_rtc_s { |
4429 | unsigned long real_time_clock:56; /* RW */ |
4430 | unsigned long rsvd_56_63:8; |
4431 | } s3; |
4432 | |
4433 | /* UV2 unique struct */ |
4434 | struct uv2h_rtc_s { |
4435 | unsigned long real_time_clock:56; /* RW */ |
4436 | unsigned long rsvd_56_63:8; |
4437 | } s2; |
4438 | }; |
4439 | |
4440 | /* ========================================================================= */ |
4441 | /* UVH_RTC1_INT_CONFIG */ |
4442 | /* ========================================================================= */ |
4443 | #define UVH_RTC1_INT_CONFIG 0x615c0UL |
4444 | |
4445 | /* UVH common defines*/ |
4446 | #define UVH_RTC1_INT_CONFIG_VECTOR_SHFT 0 |
4447 | #define UVH_RTC1_INT_CONFIG_VECTOR_MASK 0x00000000000000ffUL |
4448 | #define UVH_RTC1_INT_CONFIG_DM_SHFT 8 |
4449 | #define UVH_RTC1_INT_CONFIG_DM_MASK 0x0000000000000700UL |
4450 | #define UVH_RTC1_INT_CONFIG_DESTMODE_SHFT 11 |
4451 | #define UVH_RTC1_INT_CONFIG_DESTMODE_MASK 0x0000000000000800UL |
4452 | #define UVH_RTC1_INT_CONFIG_STATUS_SHFT 12 |
4453 | #define UVH_RTC1_INT_CONFIG_STATUS_MASK 0x0000000000001000UL |
4454 | #define UVH_RTC1_INT_CONFIG_P_SHFT 13 |
4455 | #define UVH_RTC1_INT_CONFIG_P_MASK 0x0000000000002000UL |
4456 | #define UVH_RTC1_INT_CONFIG_T_SHFT 15 |
4457 | #define UVH_RTC1_INT_CONFIG_T_MASK 0x0000000000008000UL |
4458 | #define UVH_RTC1_INT_CONFIG_M_SHFT 16 |
4459 | #define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL |
4460 | #define UVH_RTC1_INT_CONFIG_APIC_ID_SHFT 32 |
4461 | #define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL |
4462 | |
4463 | |
4464 | union uvh_rtc1_int_config_u { |
4465 | unsigned long v; |
4466 | |
4467 | /* UVH common struct */ |
4468 | struct uvh_rtc1_int_config_s { |
4469 | unsigned long vector_:8; /* RW */ |
4470 | unsigned long dm:3; /* RW */ |
4471 | unsigned long destmode:1; /* RW */ |
4472 | unsigned long status:1; /* RO */ |
4473 | unsigned long p:1; /* RO */ |
4474 | unsigned long rsvd_14:1; |
4475 | unsigned long t:1; /* RO */ |
4476 | unsigned long m:1; /* RW */ |
4477 | unsigned long rsvd_17_31:15; |
4478 | unsigned long apic_id:32; /* RW */ |
4479 | } s; |
4480 | |
4481 | /* UV5 unique struct */ |
4482 | struct uv5h_rtc1_int_config_s { |
4483 | unsigned long vector_:8; /* RW */ |
4484 | unsigned long dm:3; /* RW */ |
4485 | unsigned long destmode:1; /* RW */ |
4486 | unsigned long status:1; /* RO */ |
4487 | unsigned long p:1; /* RO */ |
4488 | unsigned long rsvd_14:1; |
4489 | unsigned long t:1; /* RO */ |
4490 | unsigned long m:1; /* RW */ |
4491 | unsigned long rsvd_17_31:15; |
4492 | unsigned long apic_id:32; /* RW */ |
4493 | } s5; |
4494 | |
4495 | /* UV4 unique struct */ |
4496 | struct uv4h_rtc1_int_config_s { |
4497 | unsigned long vector_:8; /* RW */ |
4498 | unsigned long dm:3; /* RW */ |
4499 | unsigned long destmode:1; /* RW */ |
4500 | unsigned long status:1; /* RO */ |
4501 | unsigned long p:1; /* RO */ |
4502 | unsigned long rsvd_14:1; |
4503 | unsigned long t:1; /* RO */ |
4504 | unsigned long m:1; /* RW */ |
4505 | unsigned long rsvd_17_31:15; |
4506 | unsigned long apic_id:32; /* RW */ |
4507 | } s4; |
4508 | |
4509 | /* UV3 unique struct */ |
4510 | struct uv3h_rtc1_int_config_s { |
4511 | unsigned long vector_:8; /* RW */ |
4512 | unsigned long dm:3; /* RW */ |
4513 | unsigned long destmode:1; /* RW */ |
4514 | unsigned long status:1; /* RO */ |
4515 | unsigned long p:1; /* RO */ |
4516 | unsigned long rsvd_14:1; |
4517 | unsigned long t:1; /* RO */ |
4518 | unsigned long m:1; /* RW */ |
4519 | unsigned long rsvd_17_31:15; |
4520 | unsigned long apic_id:32; /* RW */ |
4521 | } s3; |
4522 | |
4523 | /* UV2 unique struct */ |
4524 | struct uv2h_rtc1_int_config_s { |
4525 | unsigned long vector_:8; /* RW */ |
4526 | unsigned long dm:3; /* RW */ |
4527 | unsigned long destmode:1; /* RW */ |
4528 | unsigned long status:1; /* RO */ |
4529 | unsigned long p:1; /* RO */ |
4530 | unsigned long rsvd_14:1; |
4531 | unsigned long t:1; /* RO */ |
4532 | unsigned long m:1; /* RW */ |
4533 | unsigned long rsvd_17_31:15; |
4534 | unsigned long apic_id:32; /* RW */ |
4535 | } s2; |
4536 | }; |
4537 | |
4538 | /* ========================================================================= */ |
4539 | /* UVH_SCRATCH5 */ |
4540 | /* ========================================================================= */ |
4541 | #define UVH_SCRATCH5 ( \ |
4542 | is_uv(UV5) ? 0xb0200UL : \ |
4543 | is_uv(UV4) ? 0xb0200UL : \ |
4544 | is_uv(UV3) ? 0x2d0200UL : \ |
4545 | is_uv(UV2) ? 0x2d0200UL : \ |
4546 | 0) |
4547 | #define UV5H_SCRATCH5 0xb0200UL |
4548 | #define UV4H_SCRATCH5 0xb0200UL |
4549 | #define UV3H_SCRATCH5 0x2d0200UL |
4550 | #define UV2H_SCRATCH5 0x2d0200UL |
4551 | |
4552 | /* UVH common defines*/ |
4553 | #define UVH_SCRATCH5_SCRATCH5_SHFT 0 |
4554 | #define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4555 | |
4556 | /* UVXH common defines */ |
4557 | #define UVXH_SCRATCH5_SCRATCH5_SHFT 0 |
4558 | #define UVXH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4559 | |
4560 | /* UVYH common defines */ |
4561 | #define UVYH_SCRATCH5_SCRATCH5_SHFT 0 |
4562 | #define UVYH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4563 | |
4564 | /* UV5 unique defines */ |
4565 | #define UV5H_SCRATCH5_SCRATCH5_SHFT 0 |
4566 | #define UV5H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4567 | |
4568 | /* UV4 unique defines */ |
4569 | #define UV4H_SCRATCH5_SCRATCH5_SHFT 0 |
4570 | #define UV4H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4571 | |
4572 | /* UV3 unique defines */ |
4573 | #define UV3H_SCRATCH5_SCRATCH5_SHFT 0 |
4574 | #define UV3H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4575 | |
4576 | /* UV2 unique defines */ |
4577 | #define UV2H_SCRATCH5_SCRATCH5_SHFT 0 |
4578 | #define UV2H_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL |
4579 | |
4580 | |
4581 | union uvh_scratch5_u { |
4582 | unsigned long v; |
4583 | |
4584 | /* UVH common struct */ |
4585 | struct uvh_scratch5_s { |
4586 | unsigned long scratch5:64; /* RW */ |
4587 | } s; |
4588 | |
4589 | /* UVXH common struct */ |
4590 | struct uvxh_scratch5_s { |
4591 | unsigned long scratch5:64; /* RW */ |
4592 | } sx; |
4593 | |
4594 | /* UVYH common struct */ |
4595 | struct uvyh_scratch5_s { |
4596 | unsigned long scratch5:64; /* RW */ |
4597 | } sy; |
4598 | |
4599 | /* UV5 unique struct */ |
4600 | struct uv5h_scratch5_s { |
4601 | unsigned long scratch5:64; /* RW */ |
4602 | } s5; |
4603 | |
4604 | /* UV4 unique struct */ |
4605 | struct uv4h_scratch5_s { |
4606 | unsigned long scratch5:64; /* RW */ |
4607 | } s4; |
4608 | |
4609 | /* UV3 unique struct */ |
4610 | struct uv3h_scratch5_s { |
4611 | unsigned long scratch5:64; /* RW */ |
4612 | } s3; |
4613 | |
4614 | /* UV2 unique struct */ |
4615 | struct uv2h_scratch5_s { |
4616 | unsigned long scratch5:64; /* RW */ |
4617 | } s2; |
4618 | }; |
4619 | |
4620 | /* ========================================================================= */ |
4621 | /* UVH_SCRATCH5_ALIAS */ |
4622 | /* ========================================================================= */ |
4623 | #define UVH_SCRATCH5_ALIAS ( \ |
4624 | is_uv(UV5) ? 0xb0208UL : \ |
4625 | is_uv(UV4) ? 0xb0208UL : \ |
4626 | is_uv(UV3) ? 0x2d0208UL : \ |
4627 | is_uv(UV2) ? 0x2d0208UL : \ |
4628 | 0) |
4629 | #define UV5H_SCRATCH5_ALIAS 0xb0208UL |
4630 | #define UV4H_SCRATCH5_ALIAS 0xb0208UL |
4631 | #define UV3H_SCRATCH5_ALIAS 0x2d0208UL |
4632 | #define UV2H_SCRATCH5_ALIAS 0x2d0208UL |
4633 | |
4634 | |
4635 | /* ========================================================================= */ |
4636 | /* UVH_SCRATCH5_ALIAS_2 */ |
4637 | /* ========================================================================= */ |
4638 | #define UVH_SCRATCH5_ALIAS_2 ( \ |
4639 | is_uv(UV5) ? 0xb0210UL : \ |
4640 | is_uv(UV4) ? 0xb0210UL : \ |
4641 | is_uv(UV3) ? 0x2d0210UL : \ |
4642 | is_uv(UV2) ? 0x2d0210UL : \ |
4643 | 0) |
4644 | #define UV5H_SCRATCH5_ALIAS_2 0xb0210UL |
4645 | #define UV4H_SCRATCH5_ALIAS_2 0xb0210UL |
4646 | #define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL |
4647 | #define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL |
4648 | |
4649 | |
4650 | |
4651 | #endif /* _ASM_X86_UV_UV_MMRS_H */ |
4652 | |