| 1 | /****************************************************************************** |
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| 2 | * arch-x86/cpuid.h |
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| 3 | * |
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| 4 | * CPUID interface to Xen. |
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| 5 | * |
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| 6 | * Permission is hereby granted, free of charge, to any person obtaining a copy |
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| 7 | * of this software and associated documentation files (the "Software"), to |
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| 8 | * deal in the Software without restriction, including without limitation the |
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| 9 | * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or |
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| 10 | * sell copies of the Software, and to permit persons to whom the Software is |
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| 11 | * furnished to do so, subject to the following conditions: |
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| 12 | * |
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| 13 | * The above copyright notice and this permission notice shall be included in |
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| 14 | * all copies or substantial portions of the Software. |
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| 15 | * |
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| 16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE |
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| 19 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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| 22 | * DEALINGS IN THE SOFTWARE. |
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| 23 | * |
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| 24 | * Copyright (c) 2007 Citrix Systems, Inc. |
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| 25 | * |
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| 26 | * Authors: |
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| 27 | * Keir Fraser <keir@xen.org> |
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| 28 | */ |
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| 29 | |
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| 30 | #ifndef __XEN_PUBLIC_ARCH_X86_CPUID_H__ |
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| 31 | #define __XEN_PUBLIC_ARCH_X86_CPUID_H__ |
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| 32 | |
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| 33 | /* |
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| 34 | * For compatibility with other hypervisor interfaces, the Xen cpuid leaves |
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| 35 | * can be found at the first otherwise unused 0x100 aligned boundary starting |
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| 36 | * from 0x40000000. |
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| 37 | * |
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| 38 | * e.g If viridian extensions are enabled for an HVM domain, the Xen cpuid |
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| 39 | * leaves will start at 0x40000100 |
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| 40 | */ |
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| 41 | |
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| 42 | #define XEN_CPUID_FIRST_LEAF 0x40000000 |
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| 43 | #define XEN_CPUID_LEAF(i) (XEN_CPUID_FIRST_LEAF + (i)) |
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| 44 | |
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| 45 | /* |
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| 46 | * Leaf 1 (0x40000x00) |
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| 47 | * EAX: Largest Xen-information leaf. All leaves up to an including @EAX |
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| 48 | * are supported by the Xen host. |
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| 49 | * EBX-EDX: "XenVMMXenVMM" signature, allowing positive identification |
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| 50 | * of a Xen host. |
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| 51 | */ |
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| 52 | #define XEN_CPUID_SIGNATURE_EBX 0x566e6558 /* "XenV" */ |
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| 53 | #define XEN_CPUID_SIGNATURE_ECX 0x65584d4d /* "MMXe" */ |
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| 54 | #define XEN_CPUID_SIGNATURE_EDX 0x4d4d566e /* "nVMM" */ |
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| 55 | |
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| 56 | /* |
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| 57 | * Leaf 2 (0x40000x01) |
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| 58 | * EAX[31:16]: Xen major version. |
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| 59 | * EAX[15: 0]: Xen minor version. |
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| 60 | * EBX-EDX: Reserved (currently all zeroes). |
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| 61 | */ |
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| 62 | |
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| 63 | /* |
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| 64 | * Leaf 3 (0x40000x02) |
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| 65 | * EAX: Number of hypercall transfer pages. This register is always guaranteed |
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| 66 | * to specify one hypercall page. |
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| 67 | * EBX: Base address of Xen-specific MSRs. |
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| 68 | * ECX: Features 1. Unused bits are set to zero. |
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| 69 | * EDX: Features 2. Unused bits are set to zero. |
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| 70 | */ |
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| 71 | |
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| 72 | /* Does the host support MMU_PT_UPDATE_PRESERVE_AD for this guest? */ |
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| 73 | #define _XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD 0 |
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| 74 | #define XEN_CPUID_FEAT1_MMU_PT_UPDATE_PRESERVE_AD (1u<<0) |
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| 75 | |
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| 76 | /* |
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| 77 | * Leaf 4 (0x40000x03) |
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| 78 | * Sub-leaf 0: EAX: bit 0: emulated tsc |
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| 79 | * bit 1: host tsc is known to be reliable |
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| 80 | * bit 2: RDTSCP instruction available |
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| 81 | * EBX: tsc_mode: 0=default (emulate if necessary), 1=emulate, |
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| 82 | * 2=no emulation, 3=no emulation + TSC_AUX support |
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| 83 | * ECX: guest tsc frequency in kHz |
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| 84 | * EDX: guest tsc incarnation (migration count) |
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| 85 | * Sub-leaf 1: EAX: tsc offset low part |
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| 86 | * EBX: tsc offset high part |
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| 87 | * ECX: multiplicator for tsc->ns conversion |
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| 88 | * EDX: shift amount for tsc->ns conversion |
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| 89 | * Sub-leaf 2: EAX: host tsc frequency in kHz |
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| 90 | */ |
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| 91 | |
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| 92 | #define XEN_CPUID_TSC_EMULATED (1u << 0) |
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| 93 | #define XEN_CPUID_HOST_TSC_RELIABLE (1u << 1) |
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| 94 | #define XEN_CPUID_RDTSCP_INSTR_AVAIL (1u << 2) |
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| 95 | |
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| 96 | #define XEN_CPUID_TSC_MODE_DEFAULT (0) |
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| 97 | #define XEN_CPUID_TSC_MODE_ALWAYS_EMULATE (1u) |
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| 98 | #define XEN_CPUID_TSC_MODE_NEVER_EMULATE (2u) |
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| 99 | #define XEN_CPUID_TSC_MODE_PVRDTSCP (3u) |
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| 100 | |
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| 101 | /* |
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| 102 | * Leaf 5 (0x40000x04) |
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| 103 | * HVM-specific features |
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| 104 | * Sub-leaf 0: EAX: Features |
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| 105 | * Sub-leaf 0: EBX: vcpu id (iff EAX has XEN_HVM_CPUID_VCPU_ID_PRESENT flag) |
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| 106 | * Sub-leaf 0: ECX: domain id (iff EAX has XEN_HVM_CPUID_DOMID_PRESENT flag) |
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| 107 | */ |
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| 108 | #define XEN_HVM_CPUID_APIC_ACCESS_VIRT (1u << 0) /* Virtualized APIC registers */ |
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| 109 | #define XEN_HVM_CPUID_X2APIC_VIRT (1u << 1) /* Virtualized x2APIC accesses */ |
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| 110 | /* Memory mapped from other domains has valid IOMMU entries */ |
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| 111 | #define XEN_HVM_CPUID_IOMMU_MAPPINGS (1u << 2) |
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| 112 | #define XEN_HVM_CPUID_VCPU_ID_PRESENT (1u << 3) /* vcpu id is present in EBX */ |
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| 113 | #define XEN_HVM_CPUID_DOMID_PRESENT (1u << 4) /* domid is present in ECX */ |
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| 114 | /* |
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| 115 | * With interrupt format set to 0 (non-remappable) bits 55:49 from the |
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| 116 | * IO-APIC RTE and bits 11:5 from the MSI address can be used to store |
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| 117 | * high bits for the Destination ID. This expands the Destination ID |
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| 118 | * field from 8 to 15 bits, allowing to target APIC IDs up 32768. |
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| 119 | */ |
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| 120 | #define XEN_HVM_CPUID_EXT_DEST_ID (1u << 5) |
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| 121 | /* |
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| 122 | * Per-vCPU event channel upcalls work correctly with physical IRQs |
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| 123 | * bound to event channels. |
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| 124 | */ |
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| 125 | #define XEN_HVM_CPUID_UPCALL_VECTOR (1u << 6) |
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| 126 | |
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| 127 | /* |
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| 128 | * Leaf 6 (0x40000x05) |
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| 129 | * PV-specific parameters |
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| 130 | * Sub-leaf 0: EAX: max available sub-leaf |
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| 131 | * Sub-leaf 0: EBX: bits 0-7: max machine address width |
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| 132 | */ |
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| 133 | |
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| 134 | /* Max. address width in bits taking memory hotplug into account. */ |
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| 135 | #define XEN_CPUID_MACHINE_ADDRESS_WIDTH_MASK (0xffu << 0) |
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| 136 | |
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| 137 | #define XEN_CPUID_MAX_NUM_LEAVES 5 |
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| 138 | |
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| 139 | #endif /* __XEN_PUBLIC_ARCH_X86_CPUID_H__ */ |
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| 140 | |
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