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| 1 | /* |
|---|---|
| 2 | * tie.h -- compile-time HAL definitions dependent on CORE & TIE configuration |
| 3 | * |
| 4 | * NOTE: This header file is not meant to be included directly. |
| 5 | */ |
| 6 | |
| 7 | /* This header file describes this specific Xtensa processor's TIE extensions |
| 8 | that extend basic Xtensa core functionality. It is customized to this |
| 9 | Xtensa processor configuration. |
| 10 | |
| 11 | Copyright (c) 1999-2015 Cadence Design Systems Inc. |
| 12 | |
| 13 | Permission is hereby granted, free of charge, to any person obtaining |
| 14 | a copy of this software and associated documentation files (the |
| 15 | "Software"), to deal in the Software without restriction, including |
| 16 | without limitation the rights to use, copy, modify, merge, publish, |
| 17 | distribute, sublicense, and/or sell copies of the Software, and to |
| 18 | permit persons to whom the Software is furnished to do so, subject to |
| 19 | the following conditions: |
| 20 | |
| 21 | The above copyright notice and this permission notice shall be included |
| 22 | in all copies or substantial portions of the Software. |
| 23 | |
| 24 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 25 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 26 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 27 | IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY |
| 28 | CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
| 29 | TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
| 30 | SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ |
| 31 | |
| 32 | #ifndef _XTENSA_CORE_TIE_H |
| 33 | #define _XTENSA_CORE_TIE_H |
| 34 | |
| 35 | #define XCHAL_CP_NUM 2 /* number of coprocessors */ |
| 36 | #define XCHAL_CP_MAX 8 /* max CP ID + 1 (0 if none) */ |
| 37 | #define XCHAL_CP_MASK 0x82 /* bitmask of all CPs by ID */ |
| 38 | #define XCHAL_CP_PORT_MASK 0x80 /* bitmask of only port CPs */ |
| 39 | |
| 40 | /* Basic parameters of each coprocessor: */ |
| 41 | #define XCHAL_CP1_NAME "AudioEngineLX" |
| 42 | #define XCHAL_CP1_IDENT AudioEngineLX |
| 43 | #define XCHAL_CP1_SA_SIZE 120 /* size of state save area */ |
| 44 | #define XCHAL_CP1_SA_ALIGN 8 /* min alignment of save area */ |
| 45 | #define XCHAL_CP_ID_AUDIOENGINELX 1 /* coprocessor ID (0..7) */ |
| 46 | #define XCHAL_CP7_NAME "XTIOP" |
| 47 | #define XCHAL_CP7_IDENT XTIOP |
| 48 | #define XCHAL_CP7_SA_SIZE 0 /* size of state save area */ |
| 49 | #define XCHAL_CP7_SA_ALIGN 1 /* min alignment of save area */ |
| 50 | #define XCHAL_CP_ID_XTIOP 7 /* coprocessor ID (0..7) */ |
| 51 | |
| 52 | /* Filler info for unassigned coprocessors, to simplify arrays etc: */ |
| 53 | #define XCHAL_CP0_SA_SIZE 0 |
| 54 | #define XCHAL_CP0_SA_ALIGN 1 |
| 55 | #define XCHAL_CP2_SA_SIZE 0 |
| 56 | #define XCHAL_CP2_SA_ALIGN 1 |
| 57 | #define XCHAL_CP3_SA_SIZE 0 |
| 58 | #define XCHAL_CP3_SA_ALIGN 1 |
| 59 | #define XCHAL_CP4_SA_SIZE 0 |
| 60 | #define XCHAL_CP4_SA_ALIGN 1 |
| 61 | #define XCHAL_CP5_SA_SIZE 0 |
| 62 | #define XCHAL_CP5_SA_ALIGN 1 |
| 63 | #define XCHAL_CP6_SA_SIZE 0 |
| 64 | #define XCHAL_CP6_SA_ALIGN 1 |
| 65 | |
| 66 | /* Save area for non-coprocessor optional and custom (TIE) state: */ |
| 67 | #define XCHAL_NCP_SA_SIZE 36 |
| 68 | #define XCHAL_NCP_SA_ALIGN 4 |
| 69 | |
| 70 | /* Total save area for optional and custom state (NCP + CPn): */ |
| 71 | #define XCHAL_TOTAL_SA_SIZE 160 /* with 16-byte align padding */ |
| 72 | #define XCHAL_TOTAL_SA_ALIGN 8 /* actual minimum alignment */ |
| 73 | |
| 74 | /* |
| 75 | * Detailed contents of save areas. |
| 76 | * NOTE: caller must define the XCHAL_SA_REG macro (not defined here) |
| 77 | * before expanding the XCHAL_xxx_SA_LIST() macros. |
| 78 | * |
| 79 | * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize, |
| 80 | * dbnum,base,regnum,bitsz,gapsz,reset,x...) |
| 81 | * |
| 82 | * s = passed from XCHAL_*_LIST(s), eg. to select how to expand |
| 83 | * ccused = set if used by compiler without special options or code |
| 84 | * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global) |
| 85 | * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg) |
| 86 | * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg) |
| 87 | * name = lowercase reg name (no quotes) |
| 88 | * galign = group byte alignment (power of 2) (galign >= align) |
| 89 | * align = register byte alignment (power of 2) |
| 90 | * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz) |
| 91 | * (not including any pad bytes required to galign this or next reg) |
| 92 | * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>) |
| 93 | * base = reg shortname w/o index (or sr=special, ur=TIE user reg) |
| 94 | * regnum = reg index in regfile, or special/TIE-user reg number |
| 95 | * bitsz = number of significant bits (regfile width, or ur/sr mask bits) |
| 96 | * gapsz = intervening bits, if bitsz bits not stored contiguously |
| 97 | * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize) |
| 98 | * reset = register reset value (or 0 if undefined at reset) |
| 99 | * x = reserved for future use (0 until then) |
| 100 | * |
| 101 | * To filter out certain registers, e.g. to expand only the non-global |
| 102 | * registers used by the compiler, you can do something like this: |
| 103 | * |
| 104 | * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p) |
| 105 | * #define SELCC0(p...) |
| 106 | * #define SELCC1(abikind,p...) SELAK##abikind(p) |
| 107 | * #define SELAK0(p...) REG(p) |
| 108 | * #define SELAK1(p...) REG(p) |
| 109 | * #define SELAK2(p...) |
| 110 | * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \ |
| 111 | * ...what you want to expand... |
| 112 | */ |
| 113 | |
| 114 | #define XCHAL_NCP_SA_NUM 9 |
| 115 | #define XCHAL_NCP_SA_LIST(s) \ |
| 116 | XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \ |
| 117 | XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \ |
| 118 | XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \ |
| 119 | XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \ |
| 120 | XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \ |
| 121 | XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \ |
| 122 | XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \ |
| 123 | XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \ |
| 124 | XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0) |
| 125 | |
| 126 | #define XCHAL_CP0_SA_NUM 0 |
| 127 | #define XCHAL_CP0_SA_LIST(s) /* empty */ |
| 128 | |
| 129 | #define XCHAL_CP1_SA_NUM 18 |
| 130 | #define XCHAL_CP1_SA_LIST(s) \ |
| 131 | XCHAL_SA_REG(s,0,0,1,0, ae_ovf_sar, 8, 4, 4,0x03F0, ur,240, 7,0,0,0) \ |
| 132 | XCHAL_SA_REG(s,0,0,1,0, ae_bithead, 4, 4, 4,0x03F1, ur,241, 32,0,0,0) \ |
| 133 | XCHAL_SA_REG(s,0,0,1,0,ae_ts_fts_bu_bp, 4, 4, 4,0x03F2, ur,242, 16,0,0,0) \ |
| 134 | XCHAL_SA_REG(s,0,0,1,0, ae_sd_no, 4, 4, 4,0x03F3, ur,243, 28,0,0,0) \ |
| 135 | XCHAL_SA_REG(s,0,0,1,0, ae_cbegin0, 4, 4, 4,0x03F6, ur,246, 32,0,0,0) \ |
| 136 | XCHAL_SA_REG(s,0,0,1,0, ae_cend0, 4, 4, 4,0x03F7, ur,247, 32,0,0,0) \ |
| 137 | XCHAL_SA_REG(s,0,0,2,0, aep0, 8, 8, 8,0x0060, aep,0 , 48,0,0,0) \ |
| 138 | XCHAL_SA_REG(s,0,0,2,0, aep1, 8, 8, 8,0x0061, aep,1 , 48,0,0,0) \ |
| 139 | XCHAL_SA_REG(s,0,0,2,0, aep2, 8, 8, 8,0x0062, aep,2 , 48,0,0,0) \ |
| 140 | XCHAL_SA_REG(s,0,0,2,0, aep3, 8, 8, 8,0x0063, aep,3 , 48,0,0,0) \ |
| 141 | XCHAL_SA_REG(s,0,0,2,0, aep4, 8, 8, 8,0x0064, aep,4 , 48,0,0,0) \ |
| 142 | XCHAL_SA_REG(s,0,0,2,0, aep5, 8, 8, 8,0x0065, aep,5 , 48,0,0,0) \ |
| 143 | XCHAL_SA_REG(s,0,0,2,0, aep6, 8, 8, 8,0x0066, aep,6 , 48,0,0,0) \ |
| 144 | XCHAL_SA_REG(s,0,0,2,0, aep7, 8, 8, 8,0x0067, aep,7 , 48,0,0,0) \ |
| 145 | XCHAL_SA_REG(s,0,0,2,0, aeq0, 8, 8, 8,0x0068, aeq,0 , 56,0,0,0) \ |
| 146 | XCHAL_SA_REG(s,0,0,2,0, aeq1, 8, 8, 8,0x0069, aeq,1 , 56,0,0,0) \ |
| 147 | XCHAL_SA_REG(s,0,0,2,0, aeq2, 8, 8, 8,0x006A, aeq,2 , 56,0,0,0) \ |
| 148 | XCHAL_SA_REG(s,0,0,2,0, aeq3, 8, 8, 8,0x006B, aeq,3 , 56,0,0,0) |
| 149 | |
| 150 | #define XCHAL_CP2_SA_NUM 0 |
| 151 | #define XCHAL_CP2_SA_LIST(s) /* empty */ |
| 152 | |
| 153 | #define XCHAL_CP3_SA_NUM 0 |
| 154 | #define XCHAL_CP3_SA_LIST(s) /* empty */ |
| 155 | |
| 156 | #define XCHAL_CP4_SA_NUM 0 |
| 157 | #define XCHAL_CP4_SA_LIST(s) /* empty */ |
| 158 | |
| 159 | #define XCHAL_CP5_SA_NUM 0 |
| 160 | #define XCHAL_CP5_SA_LIST(s) /* empty */ |
| 161 | |
| 162 | #define XCHAL_CP6_SA_NUM 0 |
| 163 | #define XCHAL_CP6_SA_LIST(s) /* empty */ |
| 164 | |
| 165 | #define XCHAL_CP7_SA_NUM 0 |
| 166 | #define XCHAL_CP7_SA_LIST(s) /* empty */ |
| 167 | |
| 168 | /* Byte length of instruction from its first nibble (op0 field), per FLIX. */ |
| 169 | #define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,3,8 |
| 170 | /* Byte length of instruction from its first byte, per FLIX. */ |
| 171 | #define XCHAL_BYTE0_FORMAT_LENGTHS \ |
| 172 | 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\ |
| 173 | 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\ |
| 174 | 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\ |
| 175 | 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,\ |
| 176 | 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\ |
| 177 | 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\ |
| 178 | 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2, 2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,2,\ |
| 179 | 3,3,3,3,3,3,3,3,3,3,3,3,3,3,3,3, 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8 |
| 180 | |
| 181 | #endif /*_XTENSA_CORE_TIE_H*/ |
| 182 | |
| 183 |
Warning: That file was not part of the compilation database. It may have many parsing errors.