1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2022 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8#ifndef GOYAP_H_
9#define GOYAP_H_
10
11#include <uapi/drm/habanalabs_accel.h>
12#include <linux/habanalabs/hl_boot_if.h>
13#include "../common/habanalabs.h"
14#include "../include/goya/goya_packets.h"
15#include "../include/goya/goya.h"
16#include "../include/goya/goya_async_events.h"
17#include "../include/goya/goya_fw_if.h"
18
19#define NUMBER_OF_CMPLT_QUEUES 5
20#define NUMBER_OF_EXT_HW_QUEUES 5
21#define NUMBER_OF_CPU_HW_QUEUES 1
22#define NUMBER_OF_INT_HW_QUEUES 9
23#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
24 NUMBER_OF_CPU_HW_QUEUES + \
25 NUMBER_OF_INT_HW_QUEUES)
26
27/*
28 * Number of MSIX interrupts IDS:
29 * Each completion queue has 1 ID
30 * The event queue has 1 ID
31 */
32#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + 1)
33
34#if (NUMBER_OF_INTERRUPTS > GOYA_MSIX_ENTRIES)
35#error "Number of MSIX interrupts must be smaller or equal to GOYA_MSIX_ENTRIES"
36#endif
37
38#define QMAN_FENCE_TIMEOUT_USEC 10000 /* 10 ms */
39
40#define QMAN_STOP_TIMEOUT_USEC 100000 /* 100 ms */
41
42#define CORESIGHT_TIMEOUT_USEC 100000 /* 100 ms */
43
44#define GOYA_CPU_TIMEOUT_USEC 15000000 /* 15s */
45
46#define TPC_ENABLED_MASK 0xFF
47
48#define PLL_HIGH_DEFAULT 1575000000 /* 1.575 GHz */
49
50#define MAX_POWER_DEFAULT 200000 /* 200W */
51
52#define DC_POWER_DEFAULT 20000 /* 20W */
53
54#define DRAM_PHYS_DEFAULT_SIZE 0x100000000ull /* 4GB */
55
56#define GOYA_DEFAULT_CARD_NAME "HL1000"
57
58#define GOYA_MAX_PENDING_CS 64
59
60#if !IS_MAX_PENDING_CS_VALID(GOYA_MAX_PENDING_CS)
61#error "GOYA_MAX_PENDING_CS must be power of 2 and greater than 1"
62#endif
63
64/* DRAM Memory Map */
65
66#define CPU_FW_IMAGE_SIZE 0x10000000 /* 256MB */
67#define MMU_PAGE_TABLES_SIZE 0x0FC00000 /* 252MB */
68#define MMU_DRAM_DEFAULT_PAGE_SIZE 0x00200000 /* 2MB */
69#define MMU_CACHE_MNG_SIZE 0x00001000 /* 4KB */
70
71#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
72#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
73#define MMU_DRAM_DEFAULT_PAGE_ADDR (MMU_PAGE_TABLES_ADDR + \
74 MMU_PAGE_TABLES_SIZE)
75#define MMU_CACHE_MNG_ADDR (MMU_DRAM_DEFAULT_PAGE_ADDR + \
76 MMU_DRAM_DEFAULT_PAGE_SIZE)
77#define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + \
78 MMU_CACHE_MNG_SIZE)
79
80#define DRAM_BASE_ADDR_USER 0x20000000
81
82#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
83#error "Driver must reserve no more than 512MB"
84#endif
85
86/*
87 * SRAM Memory Map for Driver
88 *
89 * Driver occupies DRIVER_SRAM_SIZE bytes from the start of SRAM. It is used for
90 * MME/TPC QMANs
91 *
92 */
93
94#define MME_QMAN_BASE_OFFSET 0x000000 /* Must be 0 */
95#define MME_QMAN_LENGTH 64
96#define TPC_QMAN_LENGTH 64
97
98#define TPC0_QMAN_BASE_OFFSET (MME_QMAN_BASE_OFFSET + \
99 (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
100#define TPC1_QMAN_BASE_OFFSET (TPC0_QMAN_BASE_OFFSET + \
101 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
102#define TPC2_QMAN_BASE_OFFSET (TPC1_QMAN_BASE_OFFSET + \
103 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
104#define TPC3_QMAN_BASE_OFFSET (TPC2_QMAN_BASE_OFFSET + \
105 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
106#define TPC4_QMAN_BASE_OFFSET (TPC3_QMAN_BASE_OFFSET + \
107 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
108#define TPC5_QMAN_BASE_OFFSET (TPC4_QMAN_BASE_OFFSET + \
109 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
110#define TPC6_QMAN_BASE_OFFSET (TPC5_QMAN_BASE_OFFSET + \
111 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
112#define TPC7_QMAN_BASE_OFFSET (TPC6_QMAN_BASE_OFFSET + \
113 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
114
115#define SRAM_DRIVER_RES_OFFSET (TPC7_QMAN_BASE_OFFSET + \
116 (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE))
117
118#if (SRAM_DRIVER_RES_OFFSET >= GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START)
119#error "MME/TPC QMANs SRAM space exceeds limit"
120#endif
121
122#define SRAM_USER_BASE_OFFSET GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START
123
124/* Virtual address space */
125#define VA_HOST_SPACE_START 0x1000000000000ull /* 256TB */
126#define VA_HOST_SPACE_END 0x3FF8000000000ull /* 1PB - 1TB */
127#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
128 VA_HOST_SPACE_START) /* 767TB */
129
130#define VA_DDR_SPACE_START 0x800000000ull /* 32GB */
131#define VA_DDR_SPACE_END 0x2000000000ull /* 128GB */
132#define VA_DDR_SPACE_SIZE (VA_DDR_SPACE_END - \
133 VA_DDR_SPACE_START) /* 128GB */
134
135#if (HL_CPU_ACCESSIBLE_MEM_SIZE != SZ_2M)
136#error "HL_CPU_ACCESSIBLE_MEM_SIZE must be exactly 2MB to enable MMU mapping"
137#endif
138
139#define VA_CPU_ACCESSIBLE_MEM_ADDR 0x8000000000ull
140
141#define DMA_MAX_TRANSFER_SIZE U32_MAX
142
143#define HW_CAP_PLL 0x00000001
144#define HW_CAP_DDR_0 0x00000002
145#define HW_CAP_DDR_1 0x00000004
146#define HW_CAP_MME 0x00000008
147#define HW_CAP_CPU 0x00000010
148#define HW_CAP_DMA 0x00000020
149#define HW_CAP_MSIX 0x00000040
150#define HW_CAP_CPU_Q 0x00000080
151#define HW_CAP_MMU 0x00000100
152#define HW_CAP_TPC_MBIST 0x00000200
153#define HW_CAP_GOLDEN 0x00000400
154#define HW_CAP_TPC 0x00000800
155
156struct goya_work_freq {
157 struct hl_device *hdev;
158 struct delayed_work work_freq;
159};
160
161struct goya_device {
162 /* TODO: remove hw_queues_lock after moving to scheduler code */
163 spinlock_t hw_queues_lock;
164 struct goya_work_freq *goya_work;
165
166 u64 mme_clk;
167 u64 tpc_clk;
168 u64 ic_clk;
169
170 u64 ddr_bar_cur_addr;
171 u32 events_stat[GOYA_ASYNC_EVENT_ID_SIZE];
172 u32 events_stat_aggregate[GOYA_ASYNC_EVENT_ID_SIZE];
173 u32 hw_cap_initialized;
174 u8 device_cpu_mmu_mappings_done;
175
176 enum hl_pll_frequency curr_pll_profile;
177 enum hl_pm_mng_profile pm_mng_profile;
178};
179
180int goya_set_fixed_properties(struct hl_device *hdev);
181int goya_mmu_init(struct hl_device *hdev);
182void goya_init_dma_qmans(struct hl_device *hdev);
183void goya_init_mme_qmans(struct hl_device *hdev);
184void goya_init_tpc_qmans(struct hl_device *hdev);
185int goya_init_cpu_queues(struct hl_device *hdev);
186void goya_init_security(struct hl_device *hdev);
187void goya_ack_protection_bits_errors(struct hl_device *hdev);
188int goya_late_init(struct hl_device *hdev);
189void goya_late_fini(struct hl_device *hdev);
190
191void goya_ring_doorbell(struct hl_device *hdev, u32 hw_queue_id, u32 pi);
192void goya_pqe_write(struct hl_device *hdev, __le64 *pqe, struct hl_bd *bd);
193void goya_update_eq_ci(struct hl_device *hdev, u32 val);
194void goya_restore_phase_topology(struct hl_device *hdev);
195int goya_context_switch(struct hl_device *hdev, u32 asid);
196
197int goya_debugfs_i2c_read(struct hl_device *hdev, u8 i2c_bus,
198 u8 i2c_addr, u8 i2c_reg, u32 *val);
199int goya_debugfs_i2c_write(struct hl_device *hdev, u8 i2c_bus,
200 u8 i2c_addr, u8 i2c_reg, u32 val);
201void goya_debugfs_led_set(struct hl_device *hdev, u8 led, u8 state);
202
203int goya_test_queue(struct hl_device *hdev, u32 hw_queue_id);
204int goya_test_queues(struct hl_device *hdev);
205int goya_test_cpu_queue(struct hl_device *hdev);
206int goya_send_cpu_message(struct hl_device *hdev, u32 *msg, u16 len,
207 u32 timeout, u64 *result);
208
209long goya_get_temperature(struct hl_device *hdev, int sensor_index, u32 attr);
210long goya_get_voltage(struct hl_device *hdev, int sensor_index, u32 attr);
211long goya_get_current(struct hl_device *hdev, int sensor_index, u32 attr);
212long goya_get_fan_speed(struct hl_device *hdev, int sensor_index, u32 attr);
213long goya_get_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr);
214void goya_set_pwm_info(struct hl_device *hdev, int sensor_index, u32 attr,
215 long value);
216u64 goya_get_max_power(struct hl_device *hdev);
217void goya_set_max_power(struct hl_device *hdev, u64 value);
218
219void goya_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
220void goya_add_device_attr(struct hl_device *hdev, struct attribute_group *dev_clk_attr_grp,
221 struct attribute_group *dev_vrm_attr_grp);
222int goya_cpucp_info_get(struct hl_device *hdev);
223int goya_debug_coresight(struct hl_device *hdev, struct hl_ctx *ctx, void *data);
224void goya_halt_coresight(struct hl_device *hdev, struct hl_ctx *ctx);
225
226int goya_suspend(struct hl_device *hdev);
227int goya_resume(struct hl_device *hdev);
228
229void goya_handle_eqe(struct hl_device *hdev, struct hl_eq_entry *eq_entry);
230void *goya_get_events_stat(struct hl_device *hdev, bool aggregate, u32 *size);
231
232void goya_add_end_of_cb_packets(struct hl_device *hdev, void *kernel_address,
233 u32 len, u32 original_len, u64 cq_addr, u32 cq_val,
234 u32 msix_vec, bool eb);
235int goya_cs_parser(struct hl_device *hdev, struct hl_cs_parser *parser);
236int goya_scrub_device_mem(struct hl_device *hdev);
237void *goya_get_int_queue_base(struct hl_device *hdev, u32 queue_id,
238 dma_addr_t *dma_handle, u16 *queue_len);
239u32 goya_get_dma_desc_list_size(struct hl_device *hdev, struct sg_table *sgt);
240int goya_send_heartbeat(struct hl_device *hdev);
241void *goya_cpu_accessible_dma_pool_alloc(struct hl_device *hdev, size_t size,
242 dma_addr_t *dma_handle);
243void goya_cpu_accessible_dma_pool_free(struct hl_device *hdev, size_t size,
244 void *vaddr);
245void goya_mmu_remove_device_cpu_mappings(struct hl_device *hdev);
246
247u32 goya_get_queue_id_for_cq(struct hl_device *hdev, u32 cq_idx);
248u64 goya_get_device_time(struct hl_device *hdev);
249int goya_set_frequency(struct hl_device *hdev, enum hl_pll_frequency freq);
250
251#endif /* GOYAP_H_ */
252

source code of linux/drivers/accel/habanalabs/goya/goyaP.h