1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_DMA2_CORE_REGS_H_
14#define ASIC_REG_DMA2_CORE_REGS_H_
15
16/*
17 *****************************************
18 * DMA2_CORE (Prototype: DMA_CORE)
19 *****************************************
20 */
21
22#define mmDMA2_CORE_CFG_0 0x540000
23
24#define mmDMA2_CORE_CFG_1 0x540004
25
26#define mmDMA2_CORE_LBW_MAX_OUTSTAND 0x540008
27
28#define mmDMA2_CORE_SRC_BASE_LO 0x540014
29
30#define mmDMA2_CORE_SRC_BASE_HI 0x540018
31
32#define mmDMA2_CORE_DST_BASE_LO 0x54001C
33
34#define mmDMA2_CORE_DST_BASE_HI 0x540020
35
36#define mmDMA2_CORE_SRC_TSIZE_1 0x54002C
37
38#define mmDMA2_CORE_SRC_STRIDE_1 0x540030
39
40#define mmDMA2_CORE_SRC_TSIZE_2 0x540034
41
42#define mmDMA2_CORE_SRC_STRIDE_2 0x540038
43
44#define mmDMA2_CORE_SRC_TSIZE_3 0x54003C
45
46#define mmDMA2_CORE_SRC_STRIDE_3 0x540040
47
48#define mmDMA2_CORE_SRC_TSIZE_4 0x540044
49
50#define mmDMA2_CORE_SRC_STRIDE_4 0x540048
51
52#define mmDMA2_CORE_SRC_TSIZE_0 0x54004C
53
54#define mmDMA2_CORE_DST_TSIZE_1 0x540054
55
56#define mmDMA2_CORE_DST_STRIDE_1 0x540058
57
58#define mmDMA2_CORE_DST_TSIZE_2 0x54005C
59
60#define mmDMA2_CORE_DST_STRIDE_2 0x540060
61
62#define mmDMA2_CORE_DST_TSIZE_3 0x540064
63
64#define mmDMA2_CORE_DST_STRIDE_3 0x540068
65
66#define mmDMA2_CORE_DST_TSIZE_4 0x54006C
67
68#define mmDMA2_CORE_DST_STRIDE_4 0x540070
69
70#define mmDMA2_CORE_DST_TSIZE_0 0x540074
71
72#define mmDMA2_CORE_COMMIT 0x540078
73
74#define mmDMA2_CORE_WR_COMP_WDATA 0x54007C
75
76#define mmDMA2_CORE_WR_COMP_ADDR_LO 0x540080
77
78#define mmDMA2_CORE_WR_COMP_ADDR_HI 0x540084
79
80#define mmDMA2_CORE_WR_COMP_AWUSER_31_11 0x540088
81
82#define mmDMA2_CORE_TE_NUMROWS 0x540094
83
84#define mmDMA2_CORE_PROT 0x5400B8
85
86#define mmDMA2_CORE_SECURE_PROPS 0x5400F0
87
88#define mmDMA2_CORE_NON_SECURE_PROPS 0x5400F4
89
90#define mmDMA2_CORE_RD_MAX_OUTSTAND 0x540100
91
92#define mmDMA2_CORE_RD_MAX_SIZE 0x540104
93
94#define mmDMA2_CORE_RD_ARCACHE 0x540108
95
96#define mmDMA2_CORE_RD_ARUSER_31_11 0x540110
97
98#define mmDMA2_CORE_RD_INFLIGHTS 0x540114
99
100#define mmDMA2_CORE_WR_MAX_OUTSTAND 0x540120
101
102#define mmDMA2_CORE_WR_MAX_AWID 0x540124
103
104#define mmDMA2_CORE_WR_AWCACHE 0x540128
105
106#define mmDMA2_CORE_WR_AWUSER_31_11 0x540130
107
108#define mmDMA2_CORE_WR_INFLIGHTS 0x540134
109
110#define mmDMA2_CORE_RD_RATE_LIM_CFG_0 0x540150
111
112#define mmDMA2_CORE_RD_RATE_LIM_CFG_1 0x540154
113
114#define mmDMA2_CORE_WR_RATE_LIM_CFG_0 0x540158
115
116#define mmDMA2_CORE_WR_RATE_LIM_CFG_1 0x54015C
117
118#define mmDMA2_CORE_ERR_CFG 0x540160
119
120#define mmDMA2_CORE_ERR_CAUSE 0x540164
121
122#define mmDMA2_CORE_ERRMSG_ADDR_LO 0x540170
123
124#define mmDMA2_CORE_ERRMSG_ADDR_HI 0x540174
125
126#define mmDMA2_CORE_ERRMSG_WDATA 0x540178
127
128#define mmDMA2_CORE_STS0 0x540190
129
130#define mmDMA2_CORE_STS1 0x540194
131
132#define mmDMA2_CORE_RD_DBGMEM_ADD 0x540200
133
134#define mmDMA2_CORE_RD_DBGMEM_DATA_WR 0x540204
135
136#define mmDMA2_CORE_RD_DBGMEM_DATA_RD 0x540208
137
138#define mmDMA2_CORE_RD_DBGMEM_CTRL 0x54020C
139
140#define mmDMA2_CORE_RD_DBGMEM_RC 0x540210
141
142#define mmDMA2_CORE_DBG_HBW_AXI_AR_CNT 0x540220
143
144#define mmDMA2_CORE_DBG_HBW_AXI_AW_CNT 0x540224
145
146#define mmDMA2_CORE_DBG_LBW_AXI_AW_CNT 0x540228
147
148#define mmDMA2_CORE_DBG_DESC_CNT 0x54022C
149
150#define mmDMA2_CORE_DBG_STS 0x540230
151
152#define mmDMA2_CORE_DBG_RD_DESC_ID 0x540234
153
154#define mmDMA2_CORE_DBG_WR_DESC_ID 0x540238
155
156#endif /* ASIC_REG_DMA2_CORE_REGS_H_ */
157

source code of linux/drivers/accel/habanalabs/include/gaudi/asic_reg/dma2_core_regs.h