1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_DMA3_CORE_REGS_H_
14#define ASIC_REG_DMA3_CORE_REGS_H_
15
16/*
17 *****************************************
18 * DMA3_CORE (Prototype: DMA_CORE)
19 *****************************************
20 */
21
22#define mmDMA3_CORE_CFG_0 0x560000
23
24#define mmDMA3_CORE_CFG_1 0x560004
25
26#define mmDMA3_CORE_LBW_MAX_OUTSTAND 0x560008
27
28#define mmDMA3_CORE_SRC_BASE_LO 0x560014
29
30#define mmDMA3_CORE_SRC_BASE_HI 0x560018
31
32#define mmDMA3_CORE_DST_BASE_LO 0x56001C
33
34#define mmDMA3_CORE_DST_BASE_HI 0x560020
35
36#define mmDMA3_CORE_SRC_TSIZE_1 0x56002C
37
38#define mmDMA3_CORE_SRC_STRIDE_1 0x560030
39
40#define mmDMA3_CORE_SRC_TSIZE_2 0x560034
41
42#define mmDMA3_CORE_SRC_STRIDE_2 0x560038
43
44#define mmDMA3_CORE_SRC_TSIZE_3 0x56003C
45
46#define mmDMA3_CORE_SRC_STRIDE_3 0x560040
47
48#define mmDMA3_CORE_SRC_TSIZE_4 0x560044
49
50#define mmDMA3_CORE_SRC_STRIDE_4 0x560048
51
52#define mmDMA3_CORE_SRC_TSIZE_0 0x56004C
53
54#define mmDMA3_CORE_DST_TSIZE_1 0x560054
55
56#define mmDMA3_CORE_DST_STRIDE_1 0x560058
57
58#define mmDMA3_CORE_DST_TSIZE_2 0x56005C
59
60#define mmDMA3_CORE_DST_STRIDE_2 0x560060
61
62#define mmDMA3_CORE_DST_TSIZE_3 0x560064
63
64#define mmDMA3_CORE_DST_STRIDE_3 0x560068
65
66#define mmDMA3_CORE_DST_TSIZE_4 0x56006C
67
68#define mmDMA3_CORE_DST_STRIDE_4 0x560070
69
70#define mmDMA3_CORE_DST_TSIZE_0 0x560074
71
72#define mmDMA3_CORE_COMMIT 0x560078
73
74#define mmDMA3_CORE_WR_COMP_WDATA 0x56007C
75
76#define mmDMA3_CORE_WR_COMP_ADDR_LO 0x560080
77
78#define mmDMA3_CORE_WR_COMP_ADDR_HI 0x560084
79
80#define mmDMA3_CORE_WR_COMP_AWUSER_31_11 0x560088
81
82#define mmDMA3_CORE_TE_NUMROWS 0x560094
83
84#define mmDMA3_CORE_PROT 0x5600B8
85
86#define mmDMA3_CORE_SECURE_PROPS 0x5600F0
87
88#define mmDMA3_CORE_NON_SECURE_PROPS 0x5600F4
89
90#define mmDMA3_CORE_RD_MAX_OUTSTAND 0x560100
91
92#define mmDMA3_CORE_RD_MAX_SIZE 0x560104
93
94#define mmDMA3_CORE_RD_ARCACHE 0x560108
95
96#define mmDMA3_CORE_RD_ARUSER_31_11 0x560110
97
98#define mmDMA3_CORE_RD_INFLIGHTS 0x560114
99
100#define mmDMA3_CORE_WR_MAX_OUTSTAND 0x560120
101
102#define mmDMA3_CORE_WR_MAX_AWID 0x560124
103
104#define mmDMA3_CORE_WR_AWCACHE 0x560128
105
106#define mmDMA3_CORE_WR_AWUSER_31_11 0x560130
107
108#define mmDMA3_CORE_WR_INFLIGHTS 0x560134
109
110#define mmDMA3_CORE_RD_RATE_LIM_CFG_0 0x560150
111
112#define mmDMA3_CORE_RD_RATE_LIM_CFG_1 0x560154
113
114#define mmDMA3_CORE_WR_RATE_LIM_CFG_0 0x560158
115
116#define mmDMA3_CORE_WR_RATE_LIM_CFG_1 0x56015C
117
118#define mmDMA3_CORE_ERR_CFG 0x560160
119
120#define mmDMA3_CORE_ERR_CAUSE 0x560164
121
122#define mmDMA3_CORE_ERRMSG_ADDR_LO 0x560170
123
124#define mmDMA3_CORE_ERRMSG_ADDR_HI 0x560174
125
126#define mmDMA3_CORE_ERRMSG_WDATA 0x560178
127
128#define mmDMA3_CORE_STS0 0x560190
129
130#define mmDMA3_CORE_STS1 0x560194
131
132#define mmDMA3_CORE_RD_DBGMEM_ADD 0x560200
133
134#define mmDMA3_CORE_RD_DBGMEM_DATA_WR 0x560204
135
136#define mmDMA3_CORE_RD_DBGMEM_DATA_RD 0x560208
137
138#define mmDMA3_CORE_RD_DBGMEM_CTRL 0x56020C
139
140#define mmDMA3_CORE_RD_DBGMEM_RC 0x560210
141
142#define mmDMA3_CORE_DBG_HBW_AXI_AR_CNT 0x560220
143
144#define mmDMA3_CORE_DBG_HBW_AXI_AW_CNT 0x560224
145
146#define mmDMA3_CORE_DBG_LBW_AXI_AW_CNT 0x560228
147
148#define mmDMA3_CORE_DBG_DESC_CNT 0x56022C
149
150#define mmDMA3_CORE_DBG_STS 0x560230
151
152#define mmDMA3_CORE_DBG_RD_DESC_ID 0x560234
153
154#define mmDMA3_CORE_DBG_WR_DESC_ID 0x560238
155
156#endif /* ASIC_REG_DMA3_CORE_REGS_H_ */
157

source code of linux/drivers/accel/habanalabs/include/gaudi/asic_reg/dma3_core_regs.h