| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef ASIC_REG_GAUDI_REGS_H_ |
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| 9 | #define ASIC_REG_GAUDI_REGS_H_ |
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| 10 | |
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| 11 | #include "gaudi_blocks.h" |
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| 12 | #include "psoc_global_conf_regs.h" |
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| 13 | #include "psoc_timestamp_regs.h" |
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| 14 | #include "cpu_if_regs.h" |
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| 15 | #include "mmu_up_regs.h" |
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| 16 | #include "stlb_regs.h" |
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| 17 | #include "dma0_qm_regs.h" |
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| 18 | #include "dma1_qm_regs.h" |
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| 19 | #include "dma2_qm_regs.h" |
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| 20 | #include "dma3_qm_regs.h" |
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| 21 | #include "dma4_qm_regs.h" |
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| 22 | #include "dma5_qm_regs.h" |
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| 23 | #include "dma6_qm_regs.h" |
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| 24 | #include "dma7_qm_regs.h" |
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| 25 | #include "dma0_core_regs.h" |
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| 26 | #include "dma1_core_regs.h" |
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| 27 | #include "dma2_core_regs.h" |
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| 28 | #include "dma3_core_regs.h" |
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| 29 | #include "dma4_core_regs.h" |
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| 30 | #include "dma5_core_regs.h" |
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| 31 | #include "dma6_core_regs.h" |
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| 32 | #include "dma7_core_regs.h" |
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| 33 | #include "mme0_ctrl_regs.h" |
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| 34 | #include "mme1_ctrl_regs.h" |
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| 35 | #include "mme2_ctrl_regs.h" |
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| 36 | #include "mme3_ctrl_regs.h" |
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| 37 | #include "mme0_qm_regs.h" |
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| 38 | #include "mme2_qm_regs.h" |
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| 39 | #include "tpc0_cfg_regs.h" |
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| 40 | #include "tpc1_cfg_regs.h" |
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| 41 | #include "tpc2_cfg_regs.h" |
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| 42 | #include "tpc3_cfg_regs.h" |
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| 43 | #include "tpc4_cfg_regs.h" |
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| 44 | #include "tpc5_cfg_regs.h" |
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| 45 | #include "tpc6_cfg_regs.h" |
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| 46 | #include "tpc7_cfg_regs.h" |
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| 47 | #include "tpc0_qm_regs.h" |
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| 48 | #include "tpc1_qm_regs.h" |
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| 49 | #include "tpc2_qm_regs.h" |
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| 50 | #include "tpc3_qm_regs.h" |
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| 51 | #include "tpc4_qm_regs.h" |
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| 52 | #include "tpc5_qm_regs.h" |
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| 53 | #include "tpc6_qm_regs.h" |
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| 54 | #include "tpc7_qm_regs.h" |
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| 55 | #include "dma_if_e_n_down_ch0_regs.h" |
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| 56 | #include "dma_if_e_n_down_ch1_regs.h" |
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| 57 | #include "dma_if_e_s_down_ch0_regs.h" |
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| 58 | #include "dma_if_e_s_down_ch1_regs.h" |
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| 59 | #include "dma_if_w_n_down_ch0_regs.h" |
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| 60 | #include "dma_if_w_n_down_ch1_regs.h" |
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| 61 | #include "dma_if_w_s_down_ch0_regs.h" |
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| 62 | #include "dma_if_w_s_down_ch1_regs.h" |
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| 63 | #include "dma_if_e_n_regs.h" |
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| 64 | #include "dma_if_e_s_regs.h" |
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| 65 | #include "dma_if_w_n_regs.h" |
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| 66 | #include "dma_if_w_s_regs.h" |
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| 67 | #include "nif_rtr_ctrl_0_regs.h" |
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| 68 | #include "nif_rtr_ctrl_1_regs.h" |
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| 69 | #include "nif_rtr_ctrl_2_regs.h" |
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| 70 | #include "nif_rtr_ctrl_3_regs.h" |
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| 71 | #include "nif_rtr_ctrl_4_regs.h" |
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| 72 | #include "nif_rtr_ctrl_5_regs.h" |
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| 73 | #include "nif_rtr_ctrl_6_regs.h" |
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| 74 | #include "nif_rtr_ctrl_7_regs.h" |
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| 75 | #include "sif_rtr_ctrl_0_regs.h" |
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| 76 | #include "sif_rtr_ctrl_1_regs.h" |
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| 77 | #include "sif_rtr_ctrl_2_regs.h" |
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| 78 | #include "sif_rtr_ctrl_3_regs.h" |
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| 79 | #include "sif_rtr_ctrl_4_regs.h" |
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| 80 | #include "sif_rtr_ctrl_5_regs.h" |
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| 81 | #include "sif_rtr_ctrl_6_regs.h" |
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| 82 | #include "sif_rtr_ctrl_7_regs.h" |
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| 83 | #include "psoc_etr_regs.h" |
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| 84 | #include "psoc_cpu_pll_regs.h" |
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| 85 | |
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| 86 | #include "dma0_qm_masks.h" |
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| 87 | #include "mme0_qm_masks.h" |
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| 88 | #include "tpc0_qm_masks.h" |
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| 89 | #include "dma0_core_masks.h" |
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| 90 | #include "tpc0_cfg_masks.h" |
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| 91 | #include "psoc_global_conf_masks.h" |
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| 92 | |
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| 93 | #include "nic0_qm0_regs.h" |
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| 94 | #include "nic1_qm0_regs.h" |
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| 95 | #include "nic2_qm0_regs.h" |
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| 96 | #include "nic3_qm0_regs.h" |
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| 97 | #include "nic4_qm0_regs.h" |
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| 98 | #include "nic0_qm1_regs.h" |
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| 99 | #include "nic1_qm1_regs.h" |
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| 100 | #include "nic2_qm1_regs.h" |
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| 101 | #include "nic3_qm1_regs.h" |
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| 102 | #include "nic4_qm1_regs.h" |
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| 103 | |
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| 104 | #include "nic0_qm0_masks.h" |
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| 105 | |
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| 106 | #define GAUDI_ECC_MEM_SEL_OFFSET 0xF18 |
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| 107 | #define GAUDI_ECC_ADDRESS_OFFSET 0xF1C |
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| 108 | #define GAUDI_ECC_SYNDROME_OFFSET 0xF20 |
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| 109 | #define GAUDI_ECC_MEM_INFO_CLR_OFFSET 0xF28 |
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| 110 | #define GAUDI_ECC_MEM_INFO_CLR_SERR_MASK BIT(8) |
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| 111 | #define GAUDI_ECC_MEM_INFO_CLR_DERR_MASK BIT(9) |
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| 112 | #define GAUDI_ECC_SERR0_OFFSET 0xF30 |
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| 113 | #define GAUDI_ECC_DERR0_OFFSET 0xF40 |
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| 114 | |
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| 115 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x492000 |
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| 116 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x494000 |
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| 117 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x494800 |
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| 118 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x495000 |
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| 119 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_ARM_0 0x495800 |
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| 120 | #define mmSYNC_MNGR_W_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x496000 |
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| 121 | #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4B2000 |
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| 122 | #define mmSYNC_MNGR_E_S_SYNC_MNGR_OBJS_MON_STATUS_0 0x4B6000 |
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| 123 | #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4D2000 |
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| 124 | #define mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4D6000 |
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| 125 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0 0x4F2000 |
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| 126 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_1 0x4F2004 |
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| 127 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 0x4F3FFC |
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| 128 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRL_0 0x4F4000 |
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| 129 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_ADDRH_0 0x4F4800 |
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| 130 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_PAY_DATA_0 0x4F5000 |
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| 131 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_ARM_0 0x4F5800 |
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| 132 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0 0x4F6000 |
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| 133 | #define mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 0x4F67FC |
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| 134 | |
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| 135 | #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x300400 |
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| 136 | #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x310400 |
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| 137 | #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x320400 |
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| 138 | #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x330400 |
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| 139 | #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x340400 |
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| 140 | #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x350400 |
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| 141 | #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x360400 |
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| 142 | #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x370400 |
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| 143 | |
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| 144 | #define mmSIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x300490 |
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| 145 | #define mmSIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x310490 |
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| 146 | #define mmSIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x320490 |
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| 147 | #define mmSIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x330490 |
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| 148 | #define mmSIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x340490 |
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| 149 | #define mmSIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x350490 |
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| 150 | #define mmSIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x360490 |
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| 151 | #define mmSIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x370490 |
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| 152 | |
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| 153 | #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x300410 |
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| 154 | #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x310410 |
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| 155 | #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x320410 |
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| 156 | #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x330410 |
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| 157 | #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x340410 |
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| 158 | #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x350410 |
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| 159 | #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x360410 |
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| 160 | #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x370410 |
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| 161 | |
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| 162 | #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x300450 |
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| 163 | #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x310450 |
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| 164 | #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x320450 |
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| 165 | #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x330450 |
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| 166 | #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x340450 |
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| 167 | #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x350450 |
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| 168 | #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x360450 |
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| 169 | #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x370450 |
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| 170 | |
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| 171 | #define mmSIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3004A0 |
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| 172 | #define mmSIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3104A0 |
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| 173 | #define mmSIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3204A0 |
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| 174 | #define mmSIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3304A0 |
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| 175 | #define mmSIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3404A0 |
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| 176 | #define mmSIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3504A0 |
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| 177 | #define mmSIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3604A0 |
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| 178 | #define mmSIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3704A0 |
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| 179 | |
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| 180 | #define mmSIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3004E0 |
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| 181 | #define mmSIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3104E0 |
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| 182 | #define mmSIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3204E0 |
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| 183 | #define mmSIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3304E0 |
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| 184 | #define mmSIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3404E0 |
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| 185 | #define mmSIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3504E0 |
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| 186 | #define mmSIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3604E0 |
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| 187 | #define mmSIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3704E0 |
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| 188 | |
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| 189 | #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AW 0x380400 |
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| 190 | #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AW 0x390400 |
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| 191 | #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AW 0x3A0400 |
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| 192 | #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AW 0x3B0400 |
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| 193 | #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AW 0x3C0400 |
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| 194 | #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AW 0x3D0400 |
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| 195 | #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AW 0x3E0400 |
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| 196 | #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AW 0x3F0400 |
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| 197 | |
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| 198 | #define mmNIF_RTR_0_LBW_RANGE_PROT_HIT_AR 0x380490 |
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| 199 | #define mmNIF_RTR_1_LBW_RANGE_PROT_HIT_AR 0x390490 |
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| 200 | #define mmNIF_RTR_2_LBW_RANGE_PROT_HIT_AR 0x3A0490 |
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| 201 | #define mmNIF_RTR_3_LBW_RANGE_PROT_HIT_AR 0x3B0490 |
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| 202 | #define mmNIF_RTR_4_LBW_RANGE_PROT_HIT_AR 0x3C0490 |
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| 203 | #define mmNIF_RTR_5_LBW_RANGE_PROT_HIT_AR 0x3D0490 |
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| 204 | #define mmNIF_RTR_6_LBW_RANGE_PROT_HIT_AR 0x3E0490 |
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| 205 | #define mmNIF_RTR_7_LBW_RANGE_PROT_HIT_AR 0x3F0490 |
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| 206 | |
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| 207 | #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AW_0 0x380410 |
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| 208 | #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AW_0 0x390410 |
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| 209 | #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AW_0 0x3A0410 |
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| 210 | #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AW_0 0x3B0410 |
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| 211 | #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AW_0 0x3C0410 |
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| 212 | #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AW_0 0x3D0410 |
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| 213 | #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AW_0 0x3E0410 |
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| 214 | #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AW_0 0x3F0410 |
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| 215 | |
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| 216 | #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AW_0 0x380450 |
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| 217 | #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AW_0 0x390450 |
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| 218 | #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AW_0 0x3A0450 |
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| 219 | #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AW_0 0x3B0450 |
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| 220 | #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AW_0 0x3C0450 |
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| 221 | #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AW_0 0x3D0450 |
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| 222 | #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AW_0 0x3E0450 |
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| 223 | #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AW_0 0x3F0450 |
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| 224 | |
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| 225 | #define mmNIF_RTR_0_LBW_RANGE_PROT_MIN_AR_0 0x3804A0 |
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| 226 | #define mmNIF_RTR_1_LBW_RANGE_PROT_MIN_AR_0 0x3904A0 |
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| 227 | #define mmNIF_RTR_2_LBW_RANGE_PROT_MIN_AR_0 0x3A04A0 |
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| 228 | #define mmNIF_RTR_3_LBW_RANGE_PROT_MIN_AR_0 0x3B04A0 |
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| 229 | #define mmNIF_RTR_4_LBW_RANGE_PROT_MIN_AR_0 0x3C04A0 |
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| 230 | #define mmNIF_RTR_5_LBW_RANGE_PROT_MIN_AR_0 0x3D04A0 |
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| 231 | #define mmNIF_RTR_6_LBW_RANGE_PROT_MIN_AR_0 0x3E04A0 |
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| 232 | #define mmNIF_RTR_7_LBW_RANGE_PROT_MIN_AR_0 0x3F04A0 |
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| 233 | |
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| 234 | #define mmNIF_RTR_0_LBW_RANGE_PROT_MAX_AR_0 0x3804E0 |
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| 235 | #define mmNIF_RTR_1_LBW_RANGE_PROT_MAX_AR_0 0x3904E0 |
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| 236 | #define mmNIF_RTR_2_LBW_RANGE_PROT_MAX_AR_0 0x3A04E0 |
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| 237 | #define mmNIF_RTR_3_LBW_RANGE_PROT_MAX_AR_0 0x3B04E0 |
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| 238 | #define mmNIF_RTR_4_LBW_RANGE_PROT_MAX_AR_0 0x3C04E0 |
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| 239 | #define mmNIF_RTR_5_LBW_RANGE_PROT_MAX_AR_0 0x3D04E0 |
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| 240 | #define mmNIF_RTR_6_LBW_RANGE_PROT_MAX_AR_0 0x3E04E0 |
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| 241 | #define mmNIF_RTR_7_LBW_RANGE_PROT_MAX_AR_0 0x3F04E0 |
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| 242 | |
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| 243 | #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_0 0x489030 |
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| 244 | #define mmDMA_IF_W_S_DOWN_RSP_MID_WGHT_1 0x489034 |
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| 245 | |
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| 246 | #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_0 0x4A9030 |
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| 247 | #define mmDMA_IF_E_S_DOWN_RSP_MID_WGHT_1 0x4A9034 |
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| 248 | |
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| 249 | #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_0 0x4C9030 |
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| 250 | #define mmDMA_IF_W_N_DOWN_RSP_MID_WGHT_1 0x4C9034 |
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| 251 | |
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| 252 | #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_0 0x4E9030 |
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| 253 | #define mmDMA_IF_E_N_DOWN_RSP_MID_WGHT_1 0x4E9034 |
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| 254 | |
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| 255 | #define mmMME1_QM_GLBL_CFG0 0xE8000 |
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| 256 | #define mmMME1_QM_GLBL_STS0 0xE8038 |
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| 257 | |
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| 258 | #define mmMME0_SBAB_SB_STALL 0x4002C |
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| 259 | #define mmMME0_SBAB_ARUSER0 0x40034 |
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| 260 | #define mmMME0_SBAB_ARUSER1 0x40038 |
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| 261 | #define mmMME0_SBAB_PROT 0x40050 |
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| 262 | |
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| 263 | #define mmMME1_SBAB_SB_STALL 0xC002C |
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| 264 | #define mmMME1_SBAB_ARUSER0 0xC0034 |
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| 265 | #define mmMME1_SBAB_ARUSER1 0xC0038 |
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| 266 | #define mmMME1_SBAB_PROT 0xC0050 |
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| 267 | |
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| 268 | #define mmMME2_SBAB_SB_STALL 0x14002C |
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| 269 | #define mmMME2_SBAB_ARUSER0 0x140034 |
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| 270 | #define mmMME2_SBAB_ARUSER1 0x140038 |
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| 271 | #define mmMME2_SBAB_PROT 0x140050 |
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| 272 | |
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| 273 | #define mmMME3_SBAB_SB_STALL 0x1C002C |
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| 274 | #define mmMME3_SBAB_ARUSER0 0x1C0034 |
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| 275 | #define mmMME3_SBAB_ARUSER1 0x1C0038 |
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| 276 | #define mmMME3_SBAB_PROT 0x1C0050 |
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| 277 | |
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| 278 | #define mmMME0_ACC_ACC_STALL 0x20028 |
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| 279 | #define mmMME0_ACC_WBC 0x20038 |
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| 280 | #define mmMME0_ACC_PROT 0x20050 |
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| 281 | |
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| 282 | #define mmMME1_ACC_ACC_STALL 0xA0028 |
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| 283 | #define mmMME1_ACC_WBC 0xA0038 |
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| 284 | #define mmMME1_ACC_PROT 0xA0050 |
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| 285 | |
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| 286 | #define mmMME2_ACC_ACC_STALL 0x120028 |
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| 287 | #define mmMME2_ACC_WBC 0x120038 |
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| 288 | #define mmMME2_ACC_PROT 0x120050 |
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| 289 | |
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| 290 | #define mmMME3_ACC_ACC_STALL 0x1A0028 |
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| 291 | #define mmMME3_ACC_WBC 0x1A0038 |
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| 292 | #define mmMME3_ACC_PROT 0x1A0050 |
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| 293 | |
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| 294 | #define mmGIC_DISTRIBUTOR__5_GICD_SETSPI_NSR 0x800040 |
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| 295 | |
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| 296 | #define mmPSOC_EFUSE_READ 0xC4A000 |
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| 297 | #define mmPSOC_EFUSE_DATA_0 0xC4A080 |
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| 298 | |
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| 299 | #define mmPCIE_WRAP_MAX_OUTSTAND 0xC01B20 |
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| 300 | #define mmPCIE_WRAP_LBW_PROT_OVR 0xC01B48 |
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| 301 | #define mmPCIE_WRAP_HBW_DRAIN_CFG 0xC01D54 |
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| 302 | #define mmPCIE_WRAP_LBW_DRAIN_CFG 0xC01D5C |
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| 303 | |
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| 304 | #define mmPCIE_MSI_INTR_0 0xC13000 |
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| 305 | |
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| 306 | #define mmPCIE_DBI_DEVICE_ID_VENDOR_ID_REG 0xC02000 |
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| 307 | |
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| 308 | #define mmPCIE_AUX_FLR_CTRL 0xC07394 |
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| 309 | #define mmPCIE_AUX_DBI 0xC07490 |
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| 310 | |
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| 311 | #define mmPCIE_CORE_MSI_REQ 0xC04100 |
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| 312 | |
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| 313 | #define mmPSOC_PCI_PLL_NR 0xC72100 |
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| 314 | #define mmSRAM_W_PLL_NR 0x4C8100 |
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| 315 | #define mmPSOC_HBM_PLL_NR 0xC74100 |
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| 316 | #define mmNIC0_PLL_NR 0xCF9100 |
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| 317 | #define mmDMA_W_PLL_NR 0x487100 |
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| 318 | #define mmMESH_W_PLL_NR 0x4C7100 |
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| 319 | #define mmPSOC_MME_PLL_NR 0xC71100 |
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| 320 | #define mmPSOC_TPC_PLL_NR 0xC73100 |
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| 321 | #define mmIF_W_PLL_NR 0x488100 |
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| 322 | |
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| 323 | #define mmPCIE_WRAP_RR_ELBI_RD_SEC_REG_CTRL 0xC01208 |
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| 324 | |
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| 325 | #endif /* ASIC_REG_GAUDI_REGS_H_ */ |
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| 326 | |
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