1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_MME0_QM_REGS_H_
14#define ASIC_REG_MME0_QM_REGS_H_
15
16/*
17 *****************************************
18 * MME0_QM (Prototype: QMAN)
19 *****************************************
20 */
21
22#define mmMME0_QM_GLBL_CFG0 0x68000
23
24#define mmMME0_QM_GLBL_CFG1 0x68004
25
26#define mmMME0_QM_GLBL_PROT 0x68008
27
28#define mmMME0_QM_GLBL_ERR_CFG 0x6800C
29
30#define mmMME0_QM_GLBL_SECURE_PROPS_0 0x68010
31
32#define mmMME0_QM_GLBL_SECURE_PROPS_1 0x68014
33
34#define mmMME0_QM_GLBL_SECURE_PROPS_2 0x68018
35
36#define mmMME0_QM_GLBL_SECURE_PROPS_3 0x6801C
37
38#define mmMME0_QM_GLBL_SECURE_PROPS_4 0x68020
39
40#define mmMME0_QM_GLBL_NON_SECURE_PROPS_0 0x68024
41
42#define mmMME0_QM_GLBL_NON_SECURE_PROPS_1 0x68028
43
44#define mmMME0_QM_GLBL_NON_SECURE_PROPS_2 0x6802C
45
46#define mmMME0_QM_GLBL_NON_SECURE_PROPS_3 0x68030
47
48#define mmMME0_QM_GLBL_NON_SECURE_PROPS_4 0x68034
49
50#define mmMME0_QM_GLBL_STS0 0x68038
51
52#define mmMME0_QM_GLBL_STS1_0 0x68040
53
54#define mmMME0_QM_GLBL_STS1_1 0x68044
55
56#define mmMME0_QM_GLBL_STS1_2 0x68048
57
58#define mmMME0_QM_GLBL_STS1_3 0x6804C
59
60#define mmMME0_QM_GLBL_STS1_4 0x68050
61
62#define mmMME0_QM_GLBL_MSG_EN_0 0x68054
63
64#define mmMME0_QM_GLBL_MSG_EN_1 0x68058
65
66#define mmMME0_QM_GLBL_MSG_EN_2 0x6805C
67
68#define mmMME0_QM_GLBL_MSG_EN_3 0x68060
69
70#define mmMME0_QM_GLBL_MSG_EN_4 0x68068
71
72#define mmMME0_QM_PQ_BASE_LO_0 0x68070
73
74#define mmMME0_QM_PQ_BASE_LO_1 0x68074
75
76#define mmMME0_QM_PQ_BASE_LO_2 0x68078
77
78#define mmMME0_QM_PQ_BASE_LO_3 0x6807C
79
80#define mmMME0_QM_PQ_BASE_HI_0 0x68080
81
82#define mmMME0_QM_PQ_BASE_HI_1 0x68084
83
84#define mmMME0_QM_PQ_BASE_HI_2 0x68088
85
86#define mmMME0_QM_PQ_BASE_HI_3 0x6808C
87
88#define mmMME0_QM_PQ_SIZE_0 0x68090
89
90#define mmMME0_QM_PQ_SIZE_1 0x68094
91
92#define mmMME0_QM_PQ_SIZE_2 0x68098
93
94#define mmMME0_QM_PQ_SIZE_3 0x6809C
95
96#define mmMME0_QM_PQ_PI_0 0x680A0
97
98#define mmMME0_QM_PQ_PI_1 0x680A4
99
100#define mmMME0_QM_PQ_PI_2 0x680A8
101
102#define mmMME0_QM_PQ_PI_3 0x680AC
103
104#define mmMME0_QM_PQ_CI_0 0x680B0
105
106#define mmMME0_QM_PQ_CI_1 0x680B4
107
108#define mmMME0_QM_PQ_CI_2 0x680B8
109
110#define mmMME0_QM_PQ_CI_3 0x680BC
111
112#define mmMME0_QM_PQ_CFG0_0 0x680C0
113
114#define mmMME0_QM_PQ_CFG0_1 0x680C4
115
116#define mmMME0_QM_PQ_CFG0_2 0x680C8
117
118#define mmMME0_QM_PQ_CFG0_3 0x680CC
119
120#define mmMME0_QM_PQ_CFG1_0 0x680D0
121
122#define mmMME0_QM_PQ_CFG1_1 0x680D4
123
124#define mmMME0_QM_PQ_CFG1_2 0x680D8
125
126#define mmMME0_QM_PQ_CFG1_3 0x680DC
127
128#define mmMME0_QM_PQ_ARUSER_31_11_0 0x680E0
129
130#define mmMME0_QM_PQ_ARUSER_31_11_1 0x680E4
131
132#define mmMME0_QM_PQ_ARUSER_31_11_2 0x680E8
133
134#define mmMME0_QM_PQ_ARUSER_31_11_3 0x680EC
135
136#define mmMME0_QM_PQ_STS0_0 0x680F0
137
138#define mmMME0_QM_PQ_STS0_1 0x680F4
139
140#define mmMME0_QM_PQ_STS0_2 0x680F8
141
142#define mmMME0_QM_PQ_STS0_3 0x680FC
143
144#define mmMME0_QM_PQ_STS1_0 0x68100
145
146#define mmMME0_QM_PQ_STS1_1 0x68104
147
148#define mmMME0_QM_PQ_STS1_2 0x68108
149
150#define mmMME0_QM_PQ_STS1_3 0x6810C
151
152#define mmMME0_QM_CQ_CFG0_0 0x68110
153
154#define mmMME0_QM_CQ_CFG0_1 0x68114
155
156#define mmMME0_QM_CQ_CFG0_2 0x68118
157
158#define mmMME0_QM_CQ_CFG0_3 0x6811C
159
160#define mmMME0_QM_CQ_CFG0_4 0x68120
161
162#define mmMME0_QM_CQ_CFG1_0 0x68124
163
164#define mmMME0_QM_CQ_CFG1_1 0x68128
165
166#define mmMME0_QM_CQ_CFG1_2 0x6812C
167
168#define mmMME0_QM_CQ_CFG1_3 0x68130
169
170#define mmMME0_QM_CQ_CFG1_4 0x68134
171
172#define mmMME0_QM_CQ_ARUSER_31_11_0 0x68138
173
174#define mmMME0_QM_CQ_ARUSER_31_11_1 0x6813C
175
176#define mmMME0_QM_CQ_ARUSER_31_11_2 0x68140
177
178#define mmMME0_QM_CQ_ARUSER_31_11_3 0x68144
179
180#define mmMME0_QM_CQ_ARUSER_31_11_4 0x68148
181
182#define mmMME0_QM_CQ_STS0_0 0x6814C
183
184#define mmMME0_QM_CQ_STS0_1 0x68150
185
186#define mmMME0_QM_CQ_STS0_2 0x68154
187
188#define mmMME0_QM_CQ_STS0_3 0x68158
189
190#define mmMME0_QM_CQ_STS0_4 0x6815C
191
192#define mmMME0_QM_CQ_STS1_0 0x68160
193
194#define mmMME0_QM_CQ_STS1_1 0x68164
195
196#define mmMME0_QM_CQ_STS1_2 0x68168
197
198#define mmMME0_QM_CQ_STS1_3 0x6816C
199
200#define mmMME0_QM_CQ_STS1_4 0x68170
201
202#define mmMME0_QM_CQ_PTR_LO_0 0x68174
203
204#define mmMME0_QM_CQ_PTR_HI_0 0x68178
205
206#define mmMME0_QM_CQ_TSIZE_0 0x6817C
207
208#define mmMME0_QM_CQ_CTL_0 0x68180
209
210#define mmMME0_QM_CQ_PTR_LO_1 0x68184
211
212#define mmMME0_QM_CQ_PTR_HI_1 0x68188
213
214#define mmMME0_QM_CQ_TSIZE_1 0x6818C
215
216#define mmMME0_QM_CQ_CTL_1 0x68190
217
218#define mmMME0_QM_CQ_PTR_LO_2 0x68194
219
220#define mmMME0_QM_CQ_PTR_HI_2 0x68198
221
222#define mmMME0_QM_CQ_TSIZE_2 0x6819C
223
224#define mmMME0_QM_CQ_CTL_2 0x681A0
225
226#define mmMME0_QM_CQ_PTR_LO_3 0x681A4
227
228#define mmMME0_QM_CQ_PTR_HI_3 0x681A8
229
230#define mmMME0_QM_CQ_TSIZE_3 0x681AC
231
232#define mmMME0_QM_CQ_CTL_3 0x681B0
233
234#define mmMME0_QM_CQ_PTR_LO_4 0x681B4
235
236#define mmMME0_QM_CQ_PTR_HI_4 0x681B8
237
238#define mmMME0_QM_CQ_TSIZE_4 0x681BC
239
240#define mmMME0_QM_CQ_CTL_4 0x681C0
241
242#define mmMME0_QM_CQ_PTR_LO_STS_0 0x681C4
243
244#define mmMME0_QM_CQ_PTR_LO_STS_1 0x681C8
245
246#define mmMME0_QM_CQ_PTR_LO_STS_2 0x681CC
247
248#define mmMME0_QM_CQ_PTR_LO_STS_3 0x681D0
249
250#define mmMME0_QM_CQ_PTR_LO_STS_4 0x681D4
251
252#define mmMME0_QM_CQ_PTR_HI_STS_0 0x681D8
253
254#define mmMME0_QM_CQ_PTR_HI_STS_1 0x681DC
255
256#define mmMME0_QM_CQ_PTR_HI_STS_2 0x681E0
257
258#define mmMME0_QM_CQ_PTR_HI_STS_3 0x681E4
259
260#define mmMME0_QM_CQ_PTR_HI_STS_4 0x681E8
261
262#define mmMME0_QM_CQ_TSIZE_STS_0 0x681EC
263
264#define mmMME0_QM_CQ_TSIZE_STS_1 0x681F0
265
266#define mmMME0_QM_CQ_TSIZE_STS_2 0x681F4
267
268#define mmMME0_QM_CQ_TSIZE_STS_3 0x681F8
269
270#define mmMME0_QM_CQ_TSIZE_STS_4 0x681FC
271
272#define mmMME0_QM_CQ_CTL_STS_0 0x68200
273
274#define mmMME0_QM_CQ_CTL_STS_1 0x68204
275
276#define mmMME0_QM_CQ_CTL_STS_2 0x68208
277
278#define mmMME0_QM_CQ_CTL_STS_3 0x6820C
279
280#define mmMME0_QM_CQ_CTL_STS_4 0x68210
281
282#define mmMME0_QM_CQ_IFIFO_CNT_0 0x68214
283
284#define mmMME0_QM_CQ_IFIFO_CNT_1 0x68218
285
286#define mmMME0_QM_CQ_IFIFO_CNT_2 0x6821C
287
288#define mmMME0_QM_CQ_IFIFO_CNT_3 0x68220
289
290#define mmMME0_QM_CQ_IFIFO_CNT_4 0x68224
291
292#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_0 0x68228
293
294#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_1 0x6822C
295
296#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_2 0x68230
297
298#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_3 0x68234
299
300#define mmMME0_QM_CP_MSG_BASE0_ADDR_LO_4 0x68238
301
302#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_0 0x6823C
303
304#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_1 0x68240
305
306#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_2 0x68244
307
308#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_3 0x68248
309
310#define mmMME0_QM_CP_MSG_BASE0_ADDR_HI_4 0x6824C
311
312#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_0 0x68250
313
314#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_1 0x68254
315
316#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_2 0x68258
317
318#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_3 0x6825C
319
320#define mmMME0_QM_CP_MSG_BASE1_ADDR_LO_4 0x68260
321
322#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_0 0x68264
323
324#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_1 0x68268
325
326#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_2 0x6826C
327
328#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_3 0x68270
329
330#define mmMME0_QM_CP_MSG_BASE1_ADDR_HI_4 0x68274
331
332#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_0 0x68278
333
334#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_1 0x6827C
335
336#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_2 0x68280
337
338#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_3 0x68284
339
340#define mmMME0_QM_CP_MSG_BASE2_ADDR_LO_4 0x68288
341
342#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_0 0x6828C
343
344#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_1 0x68290
345
346#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_2 0x68294
347
348#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_3 0x68298
349
350#define mmMME0_QM_CP_MSG_BASE2_ADDR_HI_4 0x6829C
351
352#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_0 0x682A0
353
354#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_1 0x682A4
355
356#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_2 0x682A8
357
358#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_3 0x682AC
359
360#define mmMME0_QM_CP_MSG_BASE3_ADDR_LO_4 0x682B0
361
362#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_0 0x682B4
363
364#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_1 0x682B8
365
366#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_2 0x682BC
367
368#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_3 0x682C0
369
370#define mmMME0_QM_CP_MSG_BASE3_ADDR_HI_4 0x682C4
371
372#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_0 0x682C8
373
374#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_1 0x682CC
375
376#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_2 0x682D0
377
378#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_3 0x682D4
379
380#define mmMME0_QM_CP_LDMA_TSIZE_OFFSET_4 0x682D8
381
382#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_0 0x682E0
383
384#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_1 0x682E4
385
386#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_2 0x682E8
387
388#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_3 0x682EC
389
390#define mmMME0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_4 0x682F0
391
392#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_0 0x682F4
393
394#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_1 0x682F8
395
396#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_2 0x682FC
397
398#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_3 0x68300
399
400#define mmMME0_QM_CP_LDMA_DST_BASE_LO_OFFSET_4 0x68304
401
402#define mmMME0_QM_CP_FENCE0_RDATA_0 0x68308
403
404#define mmMME0_QM_CP_FENCE0_RDATA_1 0x6830C
405
406#define mmMME0_QM_CP_FENCE0_RDATA_2 0x68310
407
408#define mmMME0_QM_CP_FENCE0_RDATA_3 0x68314
409
410#define mmMME0_QM_CP_FENCE0_RDATA_4 0x68318
411
412#define mmMME0_QM_CP_FENCE1_RDATA_0 0x6831C
413
414#define mmMME0_QM_CP_FENCE1_RDATA_1 0x68320
415
416#define mmMME0_QM_CP_FENCE1_RDATA_2 0x68324
417
418#define mmMME0_QM_CP_FENCE1_RDATA_3 0x68328
419
420#define mmMME0_QM_CP_FENCE1_RDATA_4 0x6832C
421
422#define mmMME0_QM_CP_FENCE2_RDATA_0 0x68330
423
424#define mmMME0_QM_CP_FENCE2_RDATA_1 0x68334
425
426#define mmMME0_QM_CP_FENCE2_RDATA_2 0x68338
427
428#define mmMME0_QM_CP_FENCE2_RDATA_3 0x6833C
429
430#define mmMME0_QM_CP_FENCE2_RDATA_4 0x68340
431
432#define mmMME0_QM_CP_FENCE3_RDATA_0 0x68344
433
434#define mmMME0_QM_CP_FENCE3_RDATA_1 0x68348
435
436#define mmMME0_QM_CP_FENCE3_RDATA_2 0x6834C
437
438#define mmMME0_QM_CP_FENCE3_RDATA_3 0x68350
439
440#define mmMME0_QM_CP_FENCE3_RDATA_4 0x68354
441
442#define mmMME0_QM_CP_FENCE0_CNT_0 0x68358
443
444#define mmMME0_QM_CP_FENCE0_CNT_1 0x6835C
445
446#define mmMME0_QM_CP_FENCE0_CNT_2 0x68360
447
448#define mmMME0_QM_CP_FENCE0_CNT_3 0x68364
449
450#define mmMME0_QM_CP_FENCE0_CNT_4 0x68368
451
452#define mmMME0_QM_CP_FENCE1_CNT_0 0x6836C
453
454#define mmMME0_QM_CP_FENCE1_CNT_1 0x68370
455
456#define mmMME0_QM_CP_FENCE1_CNT_2 0x68374
457
458#define mmMME0_QM_CP_FENCE1_CNT_3 0x68378
459
460#define mmMME0_QM_CP_FENCE1_CNT_4 0x6837C
461
462#define mmMME0_QM_CP_FENCE2_CNT_0 0x68380
463
464#define mmMME0_QM_CP_FENCE2_CNT_1 0x68384
465
466#define mmMME0_QM_CP_FENCE2_CNT_2 0x68388
467
468#define mmMME0_QM_CP_FENCE2_CNT_3 0x6838C
469
470#define mmMME0_QM_CP_FENCE2_CNT_4 0x68390
471
472#define mmMME0_QM_CP_FENCE3_CNT_0 0x68394
473
474#define mmMME0_QM_CP_FENCE3_CNT_1 0x68398
475
476#define mmMME0_QM_CP_FENCE3_CNT_2 0x6839C
477
478#define mmMME0_QM_CP_FENCE3_CNT_3 0x683A0
479
480#define mmMME0_QM_CP_FENCE3_CNT_4 0x683A4
481
482#define mmMME0_QM_CP_STS_0 0x683A8
483
484#define mmMME0_QM_CP_STS_1 0x683AC
485
486#define mmMME0_QM_CP_STS_2 0x683B0
487
488#define mmMME0_QM_CP_STS_3 0x683B4
489
490#define mmMME0_QM_CP_STS_4 0x683B8
491
492#define mmMME0_QM_CP_CURRENT_INST_LO_0 0x683BC
493
494#define mmMME0_QM_CP_CURRENT_INST_LO_1 0x683C0
495
496#define mmMME0_QM_CP_CURRENT_INST_LO_2 0x683C4
497
498#define mmMME0_QM_CP_CURRENT_INST_LO_3 0x683C8
499
500#define mmMME0_QM_CP_CURRENT_INST_LO_4 0x683CC
501
502#define mmMME0_QM_CP_CURRENT_INST_HI_0 0x683D0
503
504#define mmMME0_QM_CP_CURRENT_INST_HI_1 0x683D4
505
506#define mmMME0_QM_CP_CURRENT_INST_HI_2 0x683D8
507
508#define mmMME0_QM_CP_CURRENT_INST_HI_3 0x683DC
509
510#define mmMME0_QM_CP_CURRENT_INST_HI_4 0x683E0
511
512#define mmMME0_QM_CP_BARRIER_CFG_0 0x683F4
513
514#define mmMME0_QM_CP_BARRIER_CFG_1 0x683F8
515
516#define mmMME0_QM_CP_BARRIER_CFG_2 0x683FC
517
518#define mmMME0_QM_CP_BARRIER_CFG_3 0x68400
519
520#define mmMME0_QM_CP_BARRIER_CFG_4 0x68404
521
522#define mmMME0_QM_CP_DBG_0_0 0x68408
523
524#define mmMME0_QM_CP_DBG_0_1 0x6840C
525
526#define mmMME0_QM_CP_DBG_0_2 0x68410
527
528#define mmMME0_QM_CP_DBG_0_3 0x68414
529
530#define mmMME0_QM_CP_DBG_0_4 0x68418
531
532#define mmMME0_QM_CP_ARUSER_31_11_0 0x6841C
533
534#define mmMME0_QM_CP_ARUSER_31_11_1 0x68420
535
536#define mmMME0_QM_CP_ARUSER_31_11_2 0x68424
537
538#define mmMME0_QM_CP_ARUSER_31_11_3 0x68428
539
540#define mmMME0_QM_CP_ARUSER_31_11_4 0x6842C
541
542#define mmMME0_QM_CP_AWUSER_31_11_0 0x68430
543
544#define mmMME0_QM_CP_AWUSER_31_11_1 0x68434
545
546#define mmMME0_QM_CP_AWUSER_31_11_2 0x68438
547
548#define mmMME0_QM_CP_AWUSER_31_11_3 0x6843C
549
550#define mmMME0_QM_CP_AWUSER_31_11_4 0x68440
551
552#define mmMME0_QM_ARB_CFG_0 0x68A00
553
554#define mmMME0_QM_ARB_CHOISE_Q_PUSH 0x68A04
555
556#define mmMME0_QM_ARB_WRR_WEIGHT_0 0x68A08
557
558#define mmMME0_QM_ARB_WRR_WEIGHT_1 0x68A0C
559
560#define mmMME0_QM_ARB_WRR_WEIGHT_2 0x68A10
561
562#define mmMME0_QM_ARB_WRR_WEIGHT_3 0x68A14
563
564#define mmMME0_QM_ARB_CFG_1 0x68A18
565
566#define mmMME0_QM_ARB_MST_AVAIL_CRED_0 0x68A20
567
568#define mmMME0_QM_ARB_MST_AVAIL_CRED_1 0x68A24
569
570#define mmMME0_QM_ARB_MST_AVAIL_CRED_2 0x68A28
571
572#define mmMME0_QM_ARB_MST_AVAIL_CRED_3 0x68A2C
573
574#define mmMME0_QM_ARB_MST_AVAIL_CRED_4 0x68A30
575
576#define mmMME0_QM_ARB_MST_AVAIL_CRED_5 0x68A34
577
578#define mmMME0_QM_ARB_MST_AVAIL_CRED_6 0x68A38
579
580#define mmMME0_QM_ARB_MST_AVAIL_CRED_7 0x68A3C
581
582#define mmMME0_QM_ARB_MST_AVAIL_CRED_8 0x68A40
583
584#define mmMME0_QM_ARB_MST_AVAIL_CRED_9 0x68A44
585
586#define mmMME0_QM_ARB_MST_AVAIL_CRED_10 0x68A48
587
588#define mmMME0_QM_ARB_MST_AVAIL_CRED_11 0x68A4C
589
590#define mmMME0_QM_ARB_MST_AVAIL_CRED_12 0x68A50
591
592#define mmMME0_QM_ARB_MST_AVAIL_CRED_13 0x68A54
593
594#define mmMME0_QM_ARB_MST_AVAIL_CRED_14 0x68A58
595
596#define mmMME0_QM_ARB_MST_AVAIL_CRED_15 0x68A5C
597
598#define mmMME0_QM_ARB_MST_AVAIL_CRED_16 0x68A60
599
600#define mmMME0_QM_ARB_MST_AVAIL_CRED_17 0x68A64
601
602#define mmMME0_QM_ARB_MST_AVAIL_CRED_18 0x68A68
603
604#define mmMME0_QM_ARB_MST_AVAIL_CRED_19 0x68A6C
605
606#define mmMME0_QM_ARB_MST_AVAIL_CRED_20 0x68A70
607
608#define mmMME0_QM_ARB_MST_AVAIL_CRED_21 0x68A74
609
610#define mmMME0_QM_ARB_MST_AVAIL_CRED_22 0x68A78
611
612#define mmMME0_QM_ARB_MST_AVAIL_CRED_23 0x68A7C
613
614#define mmMME0_QM_ARB_MST_AVAIL_CRED_24 0x68A80
615
616#define mmMME0_QM_ARB_MST_AVAIL_CRED_25 0x68A84
617
618#define mmMME0_QM_ARB_MST_AVAIL_CRED_26 0x68A88
619
620#define mmMME0_QM_ARB_MST_AVAIL_CRED_27 0x68A8C
621
622#define mmMME0_QM_ARB_MST_AVAIL_CRED_28 0x68A90
623
624#define mmMME0_QM_ARB_MST_AVAIL_CRED_29 0x68A94
625
626#define mmMME0_QM_ARB_MST_AVAIL_CRED_30 0x68A98
627
628#define mmMME0_QM_ARB_MST_AVAIL_CRED_31 0x68A9C
629
630#define mmMME0_QM_ARB_MST_CRED_INC 0x68AA0
631
632#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_0 0x68AA4
633
634#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_1 0x68AA8
635
636#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_2 0x68AAC
637
638#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_3 0x68AB0
639
640#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_4 0x68AB4
641
642#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_5 0x68AB8
643
644#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_6 0x68ABC
645
646#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_7 0x68AC0
647
648#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_8 0x68AC4
649
650#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_9 0x68AC8
651
652#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_10 0x68ACC
653
654#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_11 0x68AD0
655
656#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_12 0x68AD4
657
658#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_13 0x68AD8
659
660#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_14 0x68ADC
661
662#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_15 0x68AE0
663
664#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_16 0x68AE4
665
666#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_17 0x68AE8
667
668#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_18 0x68AEC
669
670#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_19 0x68AF0
671
672#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_20 0x68AF4
673
674#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_21 0x68AF8
675
676#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_22 0x68AFC
677
678#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_23 0x68B00
679
680#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_24 0x68B04
681
682#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_25 0x68B08
683
684#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_26 0x68B0C
685
686#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_27 0x68B10
687
688#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_28 0x68B14
689
690#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_29 0x68B18
691
692#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_30 0x68B1C
693
694#define mmMME0_QM_ARB_MST_CHOISE_PUSH_OFST_31 0x68B20
695
696#define mmMME0_QM_ARB_SLV_MASTER_INC_CRED_OFST 0x68B28
697
698#define mmMME0_QM_ARB_MST_SLAVE_EN 0x68B2C
699
700#define mmMME0_QM_ARB_MST_QUIET_PER 0x68B34
701
702#define mmMME0_QM_ARB_SLV_CHOISE_WDT 0x68B38
703
704#define mmMME0_QM_ARB_SLV_ID 0x68B3C
705
706#define mmMME0_QM_ARB_MSG_MAX_INFLIGHT 0x68B44
707
708#define mmMME0_QM_ARB_MSG_AWUSER_31_11 0x68B48
709
710#define mmMME0_QM_ARB_MSG_AWUSER_SEC_PROP 0x68B4C
711
712#define mmMME0_QM_ARB_MSG_AWUSER_NON_SEC_PROP 0x68B50
713
714#define mmMME0_QM_ARB_BASE_LO 0x68B54
715
716#define mmMME0_QM_ARB_BASE_HI 0x68B58
717
718#define mmMME0_QM_ARB_STATE_STS 0x68B80
719
720#define mmMME0_QM_ARB_CHOISE_FULLNESS_STS 0x68B84
721
722#define mmMME0_QM_ARB_MSG_STS 0x68B88
723
724#define mmMME0_QM_ARB_SLV_CHOISE_Q_HEAD 0x68B8C
725
726#define mmMME0_QM_ARB_ERR_CAUSE 0x68B9C
727
728#define mmMME0_QM_ARB_ERR_MSG_EN 0x68BA0
729
730#define mmMME0_QM_ARB_ERR_STS_DRP 0x68BA8
731
732#define mmMME0_QM_ARB_MST_CRED_STS_0 0x68BB0
733
734#define mmMME0_QM_ARB_MST_CRED_STS_1 0x68BB4
735
736#define mmMME0_QM_ARB_MST_CRED_STS_2 0x68BB8
737
738#define mmMME0_QM_ARB_MST_CRED_STS_3 0x68BBC
739
740#define mmMME0_QM_ARB_MST_CRED_STS_4 0x68BC0
741
742#define mmMME0_QM_ARB_MST_CRED_STS_5 0x68BC4
743
744#define mmMME0_QM_ARB_MST_CRED_STS_6 0x68BC8
745
746#define mmMME0_QM_ARB_MST_CRED_STS_7 0x68BCC
747
748#define mmMME0_QM_ARB_MST_CRED_STS_8 0x68BD0
749
750#define mmMME0_QM_ARB_MST_CRED_STS_9 0x68BD4
751
752#define mmMME0_QM_ARB_MST_CRED_STS_10 0x68BD8
753
754#define mmMME0_QM_ARB_MST_CRED_STS_11 0x68BDC
755
756#define mmMME0_QM_ARB_MST_CRED_STS_12 0x68BE0
757
758#define mmMME0_QM_ARB_MST_CRED_STS_13 0x68BE4
759
760#define mmMME0_QM_ARB_MST_CRED_STS_14 0x68BE8
761
762#define mmMME0_QM_ARB_MST_CRED_STS_15 0x68BEC
763
764#define mmMME0_QM_ARB_MST_CRED_STS_16 0x68BF0
765
766#define mmMME0_QM_ARB_MST_CRED_STS_17 0x68BF4
767
768#define mmMME0_QM_ARB_MST_CRED_STS_18 0x68BF8
769
770#define mmMME0_QM_ARB_MST_CRED_STS_19 0x68BFC
771
772#define mmMME0_QM_ARB_MST_CRED_STS_20 0x68C00
773
774#define mmMME0_QM_ARB_MST_CRED_STS_21 0x68C04
775
776#define mmMME0_QM_ARB_MST_CRED_STS_22 0x68C08
777
778#define mmMME0_QM_ARB_MST_CRED_STS_23 0x68C0C
779
780#define mmMME0_QM_ARB_MST_CRED_STS_24 0x68C10
781
782#define mmMME0_QM_ARB_MST_CRED_STS_25 0x68C14
783
784#define mmMME0_QM_ARB_MST_CRED_STS_26 0x68C18
785
786#define mmMME0_QM_ARB_MST_CRED_STS_27 0x68C1C
787
788#define mmMME0_QM_ARB_MST_CRED_STS_28 0x68C20
789
790#define mmMME0_QM_ARB_MST_CRED_STS_29 0x68C24
791
792#define mmMME0_QM_ARB_MST_CRED_STS_30 0x68C28
793
794#define mmMME0_QM_ARB_MST_CRED_STS_31 0x68C2C
795
796#define mmMME0_QM_CGM_CFG 0x68C70
797
798#define mmMME0_QM_CGM_STS 0x68C74
799
800#define mmMME0_QM_CGM_CFG1 0x68C78
801
802#define mmMME0_QM_LOCAL_RANGE_BASE 0x68C80
803
804#define mmMME0_QM_LOCAL_RANGE_SIZE 0x68C84
805
806#define mmMME0_QM_CSMR_STRICT_PRIO_CFG 0x68C90
807
808#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_1 0x68C94
809
810#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_0 0x68C98
811
812#define mmMME0_QM_LBW_WR_RATE_LIM_CFG_1 0x68C9C
813
814#define mmMME0_QM_HBW_RD_RATE_LIM_CFG_0 0x68CA0
815
816#define mmMME0_QM_GLBL_AXCACHE 0x68CA4
817
818#define mmMME0_QM_IND_GW_APB_CFG 0x68CB0
819
820#define mmMME0_QM_IND_GW_APB_WDATA 0x68CB4
821
822#define mmMME0_QM_IND_GW_APB_RDATA 0x68CB8
823
824#define mmMME0_QM_IND_GW_APB_STATUS 0x68CBC
825
826#define mmMME0_QM_GLBL_ERR_ADDR_LO 0x68CD0
827
828#define mmMME0_QM_GLBL_ERR_ADDR_HI 0x68CD4
829
830#define mmMME0_QM_GLBL_ERR_WDATA 0x68CD8
831
832#define mmMME0_QM_GLBL_MEM_INIT_BUSY 0x68D00
833
834#endif /* ASIC_REG_MME0_QM_REGS_H_ */
835

source code of linux/drivers/accel/habanalabs/include/gaudi/asic_reg/mme0_qm_regs.h