| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_MMU_UP_REGS_H_ |
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| 14 | #define ASIC_REG_MMU_UP_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * MMU_UP (Prototype: MMU) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | #define mmMMU_UP_MMU_ENABLE 0xC1100C |
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| 23 | |
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| 24 | #define mmMMU_UP_FORCE_ORDERING 0xC11010 |
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| 25 | |
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| 26 | #define mmMMU_UP_FEATURE_ENABLE 0xC11014 |
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| 27 | |
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| 28 | #define mmMMU_UP_VA_ORDERING_MASK_31_7 0xC11018 |
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| 29 | |
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| 30 | #define mmMMU_UP_VA_ORDERING_MASK_49_32 0xC1101C |
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| 31 | |
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| 32 | #define mmMMU_UP_LOG2_DDR_SIZE 0xC11020 |
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| 33 | |
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| 34 | #define mmMMU_UP_SCRAMBLER 0xC11024 |
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| 35 | |
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| 36 | #define mmMMU_UP_MEM_INIT_BUSY 0xC11028 |
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| 37 | |
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| 38 | #define mmMMU_UP_SPI_MASK 0xC1102C |
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| 39 | |
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| 40 | #define mmMMU_UP_SPI_CAUSE 0xC11030 |
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| 41 | |
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| 42 | #define mmMMU_UP_PAGE_ERROR_CAPTURE 0xC11034 |
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| 43 | |
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| 44 | #define mmMMU_UP_PAGE_ERROR_CAPTURE_VA 0xC11038 |
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| 45 | |
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| 46 | #define mmMMU_UP_ACCESS_ERROR_CAPTURE 0xC1103C |
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| 47 | |
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| 48 | #define mmMMU_UP_ACCESS_ERROR_CAPTURE_VA 0xC11040 |
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| 49 | |
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| 50 | #define mmMMU_UP_SPI_INTERRUPT_CLR 0xC11044 |
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| 51 | |
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| 52 | #define mmMMU_UP_SPI_INTERRUPT_MASK 0xC11048 |
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| 53 | |
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| 54 | #define mmMMU_UP_DBG_MEM_WRAP_RM 0xC1104C |
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| 55 | |
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| 56 | #define mmMMU_UP_SPI_CAUSE_CLR 0xC11050 |
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| 57 | |
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| 58 | #define mmMMU_UP_SLICE_CREDIT 0xC11054 |
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| 59 | |
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| 60 | #define mmMMU_UP_PIPE_CREDIT 0xC11058 |
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| 61 | |
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| 62 | #define mmMMU_UP_RAZWI_WRITE_VLD 0xC1105C |
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| 63 | |
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| 64 | #define mmMMU_UP_RAZWI_WRITE_ID 0xC11060 |
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| 65 | |
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| 66 | #define mmMMU_UP_RAZWI_READ_VLD 0xC11064 |
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| 67 | |
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| 68 | #define mmMMU_UP_RAZWI_READ_ID 0xC11068 |
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| 69 | |
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| 70 | #define mmMMU_UP_MMU_BYPASS 0xC1106C |
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| 71 | |
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| 72 | #endif /* ASIC_REG_MMU_UP_REGS_H_ */ |
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| 73 | |
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