1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_PSOC_CPU_PLL_REGS_H_
14#define ASIC_REG_PSOC_CPU_PLL_REGS_H_
15
16/*
17 *****************************************
18 * PSOC_CPU_PLL (Prototype: PLL)
19 *****************************************
20 */
21
22#define mmPSOC_CPU_PLL_NR 0xC70100
23
24#define mmPSOC_CPU_PLL_NF 0xC70104
25
26#define mmPSOC_CPU_PLL_OD 0xC70108
27
28#define mmPSOC_CPU_PLL_NB 0xC7010C
29
30#define mmPSOC_CPU_PLL_CFG 0xC70110
31
32#define mmPSOC_CPU_PLL_LOSE_MASK 0xC70120
33
34#define mmPSOC_CPU_PLL_LOCK_INTR 0xC70128
35
36#define mmPSOC_CPU_PLL_LOCK_BYPASS 0xC7012C
37
38#define mmPSOC_CPU_PLL_DATA_CHNG 0xC70130
39
40#define mmPSOC_CPU_PLL_RST 0xC70134
41
42#define mmPSOC_CPU_PLL_SLIP_WD_CNTR 0xC70150
43
44#define mmPSOC_CPU_PLL_DIV_FACTOR_0 0xC70200
45
46#define mmPSOC_CPU_PLL_DIV_FACTOR_1 0xC70204
47
48#define mmPSOC_CPU_PLL_DIV_FACTOR_2 0xC70208
49
50#define mmPSOC_CPU_PLL_DIV_FACTOR_3 0xC7020C
51
52#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_0 0xC70220
53
54#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_1 0xC70224
55
56#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_2 0xC70228
57
58#define mmPSOC_CPU_PLL_DIV_FACTOR_CMD_3 0xC7022C
59
60#define mmPSOC_CPU_PLL_DIV_SEL_0 0xC70280
61
62#define mmPSOC_CPU_PLL_DIV_SEL_1 0xC70284
63
64#define mmPSOC_CPU_PLL_DIV_SEL_2 0xC70288
65
66#define mmPSOC_CPU_PLL_DIV_SEL_3 0xC7028C
67
68#define mmPSOC_CPU_PLL_DIV_EN_0 0xC702A0
69
70#define mmPSOC_CPU_PLL_DIV_EN_1 0xC702A4
71
72#define mmPSOC_CPU_PLL_DIV_EN_2 0xC702A8
73
74#define mmPSOC_CPU_PLL_DIV_EN_3 0xC702AC
75
76#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_0 0xC702C0
77
78#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_1 0xC702C4
79
80#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_2 0xC702C8
81
82#define mmPSOC_CPU_PLL_DIV_FACTOR_BUSY_3 0xC702CC
83
84#define mmPSOC_CPU_PLL_CLK_GATER 0xC70300
85
86#define mmPSOC_CPU_PLL_CLK_RLX_0 0xC70310
87
88#define mmPSOC_CPU_PLL_CLK_RLX_1 0xC70314
89
90#define mmPSOC_CPU_PLL_CLK_RLX_2 0xC70318
91
92#define mmPSOC_CPU_PLL_CLK_RLX_3 0xC7031C
93
94#define mmPSOC_CPU_PLL_REF_CNTR_PERIOD 0xC70400
95
96#define mmPSOC_CPU_PLL_REF_LOW_THRESHOLD 0xC70410
97
98#define mmPSOC_CPU_PLL_REF_HIGH_THRESHOLD 0xC70420
99
100#define mmPSOC_CPU_PLL_PLL_NOT_STABLE 0xC70430
101
102#define mmPSOC_CPU_PLL_FREQ_CALC_EN 0xC70440
103
104#define mmPSOC_CPU_PLL_RLX_BITMAP_CFG 0xC70500
105
106#define mmPSOC_CPU_PLL_RLX_BITMAP_0 0xC70510
107
108#define mmPSOC_CPU_PLL_RLX_BITMAP_1 0xC70514
109
110#define mmPSOC_CPU_PLL_RLX_BITMAP_2 0xC70518
111
112#define mmPSOC_CPU_PLL_RLX_BITMAP_3 0xC7051C
113
114#endif /* ASIC_REG_PSOC_CPU_PLL_REGS_H_ */
115

source code of linux/drivers/accel/habanalabs/include/gaudi/asic_reg/psoc_cpu_pll_regs.h