| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ |
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| 14 | #define ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * PSOC_GLOBAL_CONF (Prototype: GLOBAL_CONF) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | /* PSOC_GLOBAL_CONF_NON_RST_FLOPS */ |
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| 23 | #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_SHIFT 0 |
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| 24 | #define PSOC_GLOBAL_CONF_NON_RST_FLOPS_VAL_MASK 0xFFFFFFFF |
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| 25 | |
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| 26 | /* PSOC_GLOBAL_CONF_PCI_FW_FSM */ |
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| 27 | #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_SHIFT 0 |
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| 28 | #define PSOC_GLOBAL_CONF_PCI_FW_FSM_EN_MASK 0x1 |
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| 29 | |
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| 30 | /* PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START */ |
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| 31 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_SHIFT 0 |
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| 32 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_RE_START_IND_MASK 0x1 |
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| 33 | |
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| 34 | /* PSOC_GLOBAL_CONF_BTM_FSM */ |
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| 35 | #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_SHIFT 0 |
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| 36 | #define PSOC_GLOBAL_CONF_BTM_FSM_STATE_MASK 0xF |
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| 37 | |
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| 38 | /* PSOC_GLOBAL_CONF_SW_BTM_FSM */ |
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| 39 | #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_SHIFT 0 |
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| 40 | #define PSOC_GLOBAL_CONF_SW_BTM_FSM_CTRL_MASK 0xF |
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| 41 | |
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| 42 | /* PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM */ |
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| 43 | #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_SHIFT 0 |
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| 44 | #define PSOC_GLOBAL_CONF_SW_BOOT_SEQ_FSM_CTRL_MASK 0xF |
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| 45 | |
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| 46 | /* PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT */ |
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| 47 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_SHIFT 0 |
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| 48 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_TIMEOUT_VAL_MASK 0xFFFFFFFF |
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| 49 | |
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| 50 | /* PSOC_GLOBAL_CONF_SPI_MEM_EN */ |
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| 51 | #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_SHIFT 0 |
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| 52 | #define PSOC_GLOBAL_CONF_SPI_MEM_EN_IND_MASK 0x1 |
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| 53 | |
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| 54 | /* PSOC_GLOBAL_CONF_PRSTN */ |
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| 55 | #define PSOC_GLOBAL_CONF_PRSTN_VAL_SHIFT 0 |
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| 56 | #define PSOC_GLOBAL_CONF_PRSTN_VAL_MASK 0x1 |
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| 57 | |
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| 58 | /* PSOC_GLOBAL_CONF_PCIE_EN */ |
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| 59 | #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_SHIFT 0 |
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| 60 | #define PSOC_GLOBAL_CONF_PCIE_EN_MASK_MASK 0x1 |
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| 61 | |
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| 62 | /* PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR */ |
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| 63 | #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_SHIFT 0 |
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| 64 | #define PSOC_GLOBAL_CONF_PCIE_PRSTN_INTR_IND_MASK 0x1 |
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| 65 | |
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| 66 | /* PSOC_GLOBAL_CONF_SPI_IMG_STS */ |
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| 67 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_SHIFT 0 |
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| 68 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRI_MASK 0x1 |
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| 69 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_SHIFT 1 |
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| 70 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_SEC_MASK 0x2 |
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| 71 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_SHIFT 2 |
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| 72 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PRSTN_MASK 0x4 |
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| 73 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_SHIFT 3 |
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| 74 | #define PSOC_GLOBAL_CONF_SPI_IMG_STS_PCI_MASK 0x8 |
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| 75 | |
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| 76 | /* PSOC_GLOBAL_CONF_BOOT_SEQ_FSM */ |
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| 77 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_SHIFT 0 |
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| 78 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_IDLE_MASK 0x1 |
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| 79 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_SHIFT 1 |
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| 80 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_BOOT_INIT_MASK 0x2 |
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| 81 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_SHIFT 2 |
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| 82 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRI_MASK 0x4 |
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| 83 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_SHIFT 3 |
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| 84 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_SEC_MASK 0x8 |
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| 85 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_SHIFT 4 |
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| 86 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PRSTN_MASK 0x10 |
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| 87 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_SHIFT 5 |
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| 88 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_SPI_PCIE_MASK 0x20 |
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| 89 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_SHIFT 6 |
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| 90 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_ROM_MASK 0x40 |
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| 91 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_SHIFT 7 |
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| 92 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_PCLK_READY_MASK 0x80 |
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| 93 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_SHIFT 8 |
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| 94 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_FSM_LTSSM_EN_MASK 0x100 |
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| 95 | |
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| 96 | /* PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD */ |
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| 97 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_SHIFT 0 |
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| 98 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_EXT_LD_DONE_MASK 0x1 |
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| 99 | |
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| 100 | /* PSOC_GLOBAL_CONF_PHY_STABLE */ |
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| 101 | #define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_SHIFT 0 |
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| 102 | #define PSOC_GLOBAL_CONF_PHY_STABLE_PRSTN_MASK 0x1 |
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| 103 | |
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| 104 | /* PSOC_GLOBAL_CONF_PRSTN_OVR */ |
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| 105 | #define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_SHIFT 0 |
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| 106 | #define PSOC_GLOBAL_CONF_PRSTN_OVR_EN_MASK 0x1 |
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| 107 | #define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_SHIFT 4 |
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| 108 | #define PSOC_GLOBAL_CONF_PRSTN_OVR_VAL_MASK 0x10 |
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| 109 | |
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| 110 | /* PSOC_GLOBAL_CONF_ETR_FLUSH */ |
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| 111 | #define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_SHIFT 0 |
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| 112 | #define PSOC_GLOBAL_CONF_ETR_FLUSH_MASK_MASK 0x1 |
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| 113 | |
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| 114 | /* PSOC_GLOBAL_CONF_COLD_RST_FLOPS */ |
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| 115 | #define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_SHIFT 0 |
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| 116 | #define PSOC_GLOBAL_CONF_COLD_RST_FLOPS_VAL_MASK 0xFFFFFFFF |
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| 117 | |
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| 118 | /* PSOC_GLOBAL_CONF_DIS_RAZWI_ERR */ |
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| 119 | #define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_SHIFT 0 |
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| 120 | #define PSOC_GLOBAL_CONF_DIS_RAZWI_ERR_IND_MASK 0x1 |
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| 121 | |
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| 122 | /* PSOC_GLOBAL_CONF_PCIE_PHY_RST_N */ |
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| 123 | #define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_SHIFT 0 |
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| 124 | #define PSOC_GLOBAL_CONF_PCIE_PHY_RST_N_IND_MASK 0x1 |
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| 125 | |
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| 126 | /* PSOC_GLOBAL_CONF_RAZWI */ |
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| 127 | #define PSOC_GLOBAL_CONF_RAZWI_INTR_SHIFT 0 |
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| 128 | #define PSOC_GLOBAL_CONF_RAZWI_INTR_MASK 0x1 |
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| 129 | #define PSOC_GLOBAL_CONF_RAZWI_MASK_SHIFT 4 |
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| 130 | #define PSOC_GLOBAL_CONF_RAZWI_MASK_MASK 0x10 |
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| 131 | |
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| 132 | /* PSOC_GLOBAL_CONF_PROT */ |
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| 133 | #define PSOC_GLOBAL_CONF_PROT_AR_SHIFT 0 |
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| 134 | #define PSOC_GLOBAL_CONF_PROT_AR_MASK 0x7 |
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| 135 | #define PSOC_GLOBAL_CONF_PROT_AW_SHIFT 4 |
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| 136 | #define PSOC_GLOBAL_CONF_PROT_AW_MASK 0x70 |
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| 137 | |
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| 138 | /* PSOC_GLOBAL_CONF_ADC */ |
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| 139 | #define PSOC_GLOBAL_CONF_ADC_INTR_SHIFT 0 |
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| 140 | #define PSOC_GLOBAL_CONF_ADC_INTR_MASK 0x1 |
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| 141 | #define PSOC_GLOBAL_CONF_ADC_MASK_SHIFT 4 |
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| 142 | #define PSOC_GLOBAL_CONF_ADC_MASK_MASK 0x10 |
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| 143 | |
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| 144 | /* PSOC_GLOBAL_CONF_BOOT_SEQ_TO */ |
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| 145 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_SHIFT 0 |
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| 146 | #define PSOC_GLOBAL_CONF_BOOT_SEQ_TO_MASK_MASK 0x1 |
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| 147 | |
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| 148 | /* PSOC_GLOBAL_CONF_SCRATCHPAD */ |
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| 149 | #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_SHIFT 0 |
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| 150 | #define PSOC_GLOBAL_CONF_SCRATCHPAD_REG_MASK 0xFFFFFFFF |
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| 151 | |
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| 152 | /* PSOC_GLOBAL_CONF_SEMAPHORE */ |
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| 153 | #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_SHIFT 0 |
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| 154 | #define PSOC_GLOBAL_CONF_SEMAPHORE_REG_MASK 0xFFFFFFFF |
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| 155 | |
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| 156 | /* PSOC_GLOBAL_CONF_CPU_BOOT_STATUS */ |
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| 157 | #define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_SHIFT 0 |
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| 158 | #define PSOC_GLOBAL_CONF_CPU_BOOT_STATUS_CNTR_MASK 0xFFFFFFFF |
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| 159 | |
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| 160 | /* PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU */ |
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| 161 | #define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_SHIFT 0 |
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| 162 | #define PSOC_GLOBAL_CONF_KMD_MSG_TO_CPU_VAL_MASK 0xFFFFFFFF |
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| 163 | |
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| 164 | /* PSOC_GLOBAL_CONF_SPL_SOURCE */ |
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| 165 | #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_SHIFT 0 |
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| 166 | #define PSOC_GLOBAL_CONF_SPL_SOURCE_VAL_MASK 0x7 |
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| 167 | |
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| 168 | /* PSOC_GLOBAL_CONF_I2C_MSTR1_DBG */ |
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| 169 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_SHIFT 0 |
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| 170 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_S_GEN_MASK 0x1 |
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| 171 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_SHIFT 1 |
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| 172 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_P_GEN_MASK 0x2 |
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| 173 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_SHIFT 2 |
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| 174 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_DATA_MASK 0x4 |
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| 175 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_SHIFT 3 |
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| 176 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_MASK 0x8 |
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| 177 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_SHIFT 4 |
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| 178 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_RD_MASK 0x10 |
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| 179 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_SHIFT 5 |
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| 180 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_WR_MASK 0x20 |
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| 181 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_SHIFT 6 |
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| 182 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_HS_MASK 0x40 |
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| 183 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_SHIFT 7 |
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| 184 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MASTER_ACT_MASK 0x80 |
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| 185 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_SHIFT 8 |
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| 186 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLAVE_ACT_MASK 0x100 |
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| 187 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_SHIFT 9 |
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| 188 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_ADDR_10BIT_MASK 0x200 |
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| 189 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_SHIFT 10 |
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| 190 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_MST_CSTATE_MASK 0x7C00 |
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| 191 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_SHIFT 15 |
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| 192 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_SLV_CSTATE_MASK 0x78000 |
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| 193 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_SHIFT 19 |
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| 194 | #define PSOC_GLOBAL_CONF_I2C_MSTR1_DBG_IC_EN_MASK 0x80000 |
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| 195 | |
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| 196 | /* PSOC_GLOBAL_CONF_I2C_SLV */ |
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| 197 | #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_SHIFT 0 |
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| 198 | #define PSOC_GLOBAL_CONF_I2C_SLV_CPU_CTRL_MASK 0x1 |
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| 199 | |
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| 200 | /* PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK */ |
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| 201 | #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_SHIFT 0 |
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| 202 | #define PSOC_GLOBAL_CONF_I2C_SLV_INTR_MASK_FLD_INT_MASK 0x1 |
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| 203 | |
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| 204 | /* PSOC_GLOBAL_CONF_TRACE_ADDR */ |
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| 205 | #define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_SHIFT 0 |
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| 206 | #define PSOC_GLOBAL_CONF_TRACE_ADDR_MSB_MASK 0x3FF |
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| 207 | |
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| 208 | /* PSOC_GLOBAL_CONF_ARUSER */ |
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| 209 | #define PSOC_GLOBAL_CONF_ARUSER_VAL_SHIFT 0 |
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| 210 | #define PSOC_GLOBAL_CONF_ARUSER_VAL_MASK 0xFFFFFFFF |
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| 211 | |
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| 212 | /* PSOC_GLOBAL_CONF_AWUSER */ |
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| 213 | #define PSOC_GLOBAL_CONF_AWUSER_VAL_SHIFT 0 |
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| 214 | #define PSOC_GLOBAL_CONF_AWUSER_VAL_MASK 0xFFFFFFFF |
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| 215 | |
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| 216 | /* PSOC_GLOBAL_CONF_TRACE_AWUSER */ |
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| 217 | #define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_SHIFT 0 |
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| 218 | #define PSOC_GLOBAL_CONF_TRACE_AWUSER_VAL_MASK 0xFFFFFFFF |
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| 219 | |
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| 220 | /* PSOC_GLOBAL_CONF_TRACE_ARUSER */ |
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| 221 | #define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_SHIFT 0 |
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| 222 | #define PSOC_GLOBAL_CONF_TRACE_ARUSER_VAL_MASK 0xFFFFFFFF |
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| 223 | |
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| 224 | /* PSOC_GLOBAL_CONF_BTL_STS */ |
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| 225 | #define PSOC_GLOBAL_CONF_BTL_STS_DONE_SHIFT 0 |
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| 226 | #define PSOC_GLOBAL_CONF_BTL_STS_DONE_MASK 0x1 |
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| 227 | #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_SHIFT 4 |
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| 228 | #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_MASK 0x10 |
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| 229 | #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_SHIFT 8 |
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| 230 | #define PSOC_GLOBAL_CONF_BTL_STS_FAIL_CODE_MASK 0xF00 |
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| 231 | |
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| 232 | /* PSOC_GLOBAL_CONF_TIMEOUT_INTR */ |
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| 233 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_SHIFT 0 |
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| 234 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_0_MASK 0x1 |
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| 235 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_SHIFT 1 |
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| 236 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_1_MASK 0x2 |
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| 237 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_SHIFT 2 |
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| 238 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_2_MASK 0x4 |
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| 239 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_SHIFT 3 |
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| 240 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_3_MASK 0x8 |
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| 241 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_SHIFT 4 |
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| 242 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_4_MASK 0x10 |
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| 243 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_SHIFT 5 |
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| 244 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_TIMER_MASK 0x20 |
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| 245 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_SHIFT 6 |
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| 246 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_0_MASK 0x40 |
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| 247 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_SHIFT 7 |
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| 248 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_UART_1_MASK 0x80 |
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| 249 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_SHIFT 8 |
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| 250 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_5_MASK 0x100 |
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| 251 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_SHIFT 9 |
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| 252 | #define PSOC_GLOBAL_CONF_TIMEOUT_INTR_GPIO_6_MASK 0x200 |
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| 253 | |
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| 254 | /* PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR */ |
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| 255 | #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_SHIFT 0 |
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| 256 | #define PSOC_GLOBAL_CONF_COMB_TIMEOUT_INTR_IND_MASK 0x1 |
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| 257 | |
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| 258 | /* PSOC_GLOBAL_CONF_PERIPH_INTR */ |
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| 259 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_SHIFT 0 |
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| 260 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TX_MASK 0x1 |
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| 261 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_SHIFT 1 |
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| 262 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RX_MASK 0x2 |
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| 263 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_SHIFT 2 |
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| 264 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_TXOVR_MASK 0x4 |
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| 265 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_SHIFT 3 |
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| 266 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_0_RXOVR_MASK 0x8 |
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| 267 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_SHIFT 4 |
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| 268 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TX_MASK 0x10 |
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| 269 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_SHIFT 5 |
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| 270 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RX_MASK 0x20 |
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| 271 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_SHIFT 6 |
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| 272 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_TXOVR_MASK 0x40 |
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| 273 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_SHIFT 7 |
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| 274 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_UART_1_RXOVR_MASK 0x80 |
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| 275 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_SHIFT 12 |
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| 276 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_MASK 0x1000 |
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| 277 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_SHIFT 13 |
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| 278 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_EMMC_WAKEUP_MASK 0x2000 |
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| 279 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_SHIFT 16 |
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| 280 | #define PSOC_GLOBAL_CONF_PERIPH_INTR_MII_MASK 0x10000 |
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| 281 | |
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| 282 | /* PSOC_GLOBAL_CONF_COMB_PERIPH_INTR */ |
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| 283 | #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_SHIFT 0 |
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| 284 | #define PSOC_GLOBAL_CONF_COMB_PERIPH_INTR_IND_MASK 0x1 |
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| 285 | |
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| 286 | /* PSOC_GLOBAL_CONF_AXI_ERR_INTR */ |
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| 287 | #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_SHIFT 0 |
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| 288 | #define PSOC_GLOBAL_CONF_AXI_ERR_INTR_IND_MASK 0x1 |
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| 289 | |
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| 290 | /* PSOC_GLOBAL_CONF_TARGETID */ |
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| 291 | #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_SHIFT 1 |
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| 292 | #define PSOC_GLOBAL_CONF_TARGETID_TDESIGNER_MASK 0xFFE |
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| 293 | #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_SHIFT 16 |
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| 294 | #define PSOC_GLOBAL_CONF_TARGETID_TPARTNO_MASK 0xFFF0000 |
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| 295 | #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_SHIFT 28 |
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| 296 | #define PSOC_GLOBAL_CONF_TARGETID_TREVISION_MASK 0xF0000000 |
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| 297 | |
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| 298 | /* PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE */ |
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| 299 | #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_SHIFT 0 |
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| 300 | #define PSOC_GLOBAL_CONF_EMMC_INT_VOL_STABLE_IND_MASK 0x1 |
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| 301 | |
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| 302 | /* PSOC_GLOBAL_CONF_BOOT_STRAP_PINS */ |
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| 303 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_SHIFT 0 |
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| 304 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SLV_ADDR_MASK 0x1 |
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| 305 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_SHIFT 1 |
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| 306 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_PCIE_EN_MASK 0x2 |
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| 307 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_SHIFT 2 |
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| 308 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_REPAIR_CFG_MASK 0xC |
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| 309 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_SHIFT 4 |
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| 310 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPOL_MASK 0x10 |
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| 311 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_SHIFT 5 |
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| 312 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_CPHA_MASK 0x20 |
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| 313 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_SHIFT 6 |
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| 314 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_EN_MASK 0x40 |
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| 315 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_SHIFT 7 |
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| 316 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_BTL_ROM_EN_MASK 0x80 |
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| 317 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_SHIFT 8 |
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| 318 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_SEL_MASK 0x1FFF00 |
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| 319 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_SHIFT 22 |
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| 320 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_GRAD_RST_MASK 0x400000 |
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| 321 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_SHIFT 23 |
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| 322 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_DUMP_DIS_MASK 0x800000 |
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| 323 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_SHIFT 24 |
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| 324 | #define PSOC_GLOBAL_CONF_BOOT_STRAP_PINS_I2C_MASK 0x1F000000 |
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| 325 | |
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| 326 | /* PSOC_GLOBAL_CONF_MEM_REPAIR_DIV */ |
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| 327 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_SHIFT 0 |
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| 328 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_EN_MASK 0x1 |
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| 329 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_SHIFT 8 |
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| 330 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_DIV_VAL_MASK 0xFF00 |
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| 331 | |
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| 332 | /* PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL */ |
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| 333 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_SHIFT 0 |
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| 334 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_SET_MASK 0x1 |
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| 335 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_SHIFT 1 |
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| 336 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_CTRL_CLR_MASK 0x2 |
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| 337 | |
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| 338 | /* PSOC_GLOBAL_CONF_MEM_REPAIR_STS */ |
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| 339 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_SHIFT 0 |
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| 340 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_IND_MASK 0x1 |
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| 341 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_SHIFT 4 |
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| 342 | #define PSOC_GLOBAL_CONF_MEM_REPAIR_STS_FAIL_MASK 0x10 |
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| 343 | |
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| 344 | /* PSOC_GLOBAL_CONF_OUTSTANT_TRANS */ |
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| 345 | #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_SHIFT 0 |
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| 346 | #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_RD_MASK 0x1 |
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| 347 | #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_SHIFT 1 |
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| 348 | #define PSOC_GLOBAL_CONF_OUTSTANT_TRANS_WR_MASK 0x2 |
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| 349 | |
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| 350 | /* PSOC_GLOBAL_CONF_MASK_REQ */ |
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| 351 | #define PSOC_GLOBAL_CONF_MASK_REQ_IND_SHIFT 0 |
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| 352 | #define PSOC_GLOBAL_CONF_MASK_REQ_IND_MASK 0x1 |
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| 353 | |
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| 354 | /* PSOC_GLOBAL_CONF_WD_RST_CFG_L */ |
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| 355 | #define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_SHIFT 0 |
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| 356 | #define PSOC_GLOBAL_CONF_WD_RST_CFG_L_VAL_MASK 0xFFFFFFFF |
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| 357 | |
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| 358 | /* PSOC_GLOBAL_CONF_WD_RST_CFG_H */ |
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| 359 | #define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_SHIFT 0 |
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| 360 | #define PSOC_GLOBAL_CONF_WD_RST_CFG_H_VAL_MASK 0x3FFFFF |
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| 361 | |
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| 362 | /* PSOC_GLOBAL_CONF_MNL_RST_CFG_L */ |
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| 363 | #define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_SHIFT 0 |
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| 364 | #define PSOC_GLOBAL_CONF_MNL_RST_CFG_L_VAL_MASK 0xFFFFFFFF |
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| 365 | |
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| 366 | /* PSOC_GLOBAL_CONF_MNL_RST_CFG_H */ |
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| 367 | #define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_SHIFT 0 |
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| 368 | #define PSOC_GLOBAL_CONF_MNL_RST_CFG_H_VAL_MASK 0x3FFFFF |
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| 369 | |
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| 370 | /* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L */ |
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| 371 | #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_SHIFT 0 |
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| 372 | #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_L_VAL_MASK 0xFFFFFFFF |
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| 373 | |
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| 374 | /* PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H */ |
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| 375 | #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_SHIFT 0 |
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| 376 | #define PSOC_GLOBAL_CONF_PRSTN_RST_CFG_H_VAL_MASK 0xFFFFFFFF |
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| 377 | |
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| 378 | /* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L */ |
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| 379 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_SHIFT 0 |
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| 380 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_L_VAL_MASK 0xFFFFFFFF |
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| 381 | |
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| 382 | /* PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H */ |
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| 383 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_SHIFT 0 |
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| 384 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_H_VAL_MASK 0x3FFFFF |
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| 385 | |
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| 386 | /* PSOC_GLOBAL_CONF_SW_ALL_RST */ |
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| 387 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_SHIFT 0 |
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| 388 | #define PSOC_GLOBAL_CONF_SW_ALL_RST_IND_MASK 0x1 |
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| 389 | |
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| 390 | /* PSOC_GLOBAL_CONF_SOFT_RST */ |
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| 391 | #define PSOC_GLOBAL_CONF_SOFT_RST_IND_SHIFT 0 |
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| 392 | #define PSOC_GLOBAL_CONF_SOFT_RST_IND_MASK 0x1 |
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| 393 | |
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| 394 | /* PSOC_GLOBAL_CONF_SOFT_RST_CFG_L */ |
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| 395 | #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_SHIFT 0 |
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| 396 | #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_L_VAL_MASK 0xFFFFFFFF |
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| 397 | |
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| 398 | /* PSOC_GLOBAL_CONF_SOFT_RST_CFG_H */ |
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| 399 | #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_SHIFT 0 |
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| 400 | #define PSOC_GLOBAL_CONF_SOFT_RST_CFG_H_VAL_MASK 0x3FFFFF |
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| 401 | |
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| 402 | /* PSOC_GLOBAL_CONF_UNIT_RST_N */ |
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| 403 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_SHIFT 0 |
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| 404 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_IND_MASK 0x1 |
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| 405 | |
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| 406 | /* PSOC_GLOBAL_CONF_UNIT_RST_N_L */ |
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| 407 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_SHIFT 0 |
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| 408 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_L_VAL_MASK 0xFFFFFFFF |
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| 409 | |
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| 410 | /* PSOC_GLOBAL_CONF_UNIT_RST_N_H */ |
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| 411 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_SHIFT 0 |
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| 412 | #define PSOC_GLOBAL_CONF_UNIT_RST_N_H_VAL_MASK 0x3FFFFF |
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| 413 | |
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| 414 | /* PSOC_GLOBAL_CONF_BTL_IMG */ |
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| 415 | #define PSOC_GLOBAL_CONF_BTL_IMG_SEL_SHIFT 0 |
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| 416 | #define PSOC_GLOBAL_CONF_BTL_IMG_SEL_MASK 0x1 |
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| 417 | |
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| 418 | /* PSOC_GLOBAL_CONF_PRSTN_MASK */ |
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| 419 | #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_SHIFT 0 |
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| 420 | #define PSOC_GLOBAL_CONF_PRSTN_MASK_IND_MASK 0x1 |
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| 421 | |
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| 422 | /* PSOC_GLOBAL_CONF_WD_MASK */ |
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| 423 | #define PSOC_GLOBAL_CONF_WD_MASK_IND_SHIFT 0 |
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| 424 | #define PSOC_GLOBAL_CONF_WD_MASK_IND_MASK 0x1 |
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| 425 | |
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| 426 | /* PSOC_GLOBAL_CONF_RST_SRC */ |
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| 427 | #define PSOC_GLOBAL_CONF_RST_SRC_VAL_SHIFT 0 |
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| 428 | #define PSOC_GLOBAL_CONF_RST_SRC_VAL_MASK 0xF |
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| 429 | |
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| 430 | /* PSOC_GLOBAL_CONF_BOOT_STATE */ |
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| 431 | #define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_SHIFT 0 |
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| 432 | #define PSOC_GLOBAL_CONF_BOOT_STATE_VAL_MASK 0x1 |
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| 433 | |
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| 434 | /* PSOC_GLOBAL_CONF_PAD_1V8_CFG */ |
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| 435 | #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_SHIFT 0 |
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| 436 | #define PSOC_GLOBAL_CONF_PAD_1V8_CFG_VAL_MASK 0x7F |
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| 437 | |
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| 438 | /* PSOC_GLOBAL_CONF_PAD_3V3_CFG */ |
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| 439 | #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_SHIFT 0 |
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| 440 | #define PSOC_GLOBAL_CONF_PAD_3V3_CFG_VAL_MASK 0x7F |
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| 441 | |
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| 442 | /* PSOC_GLOBAL_CONF_PAD_1V8_INPUT */ |
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| 443 | #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_SHIFT 0 |
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| 444 | #define PSOC_GLOBAL_CONF_PAD_1V8_INPUT_CFG_MASK 0x7 |
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| 445 | |
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| 446 | /* PSOC_GLOBAL_CONF_BNK3V3_MS */ |
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| 447 | #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_SHIFT 0 |
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| 448 | #define PSOC_GLOBAL_CONF_BNK3V3_MS_VAL_MASK 0x3 |
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| 449 | |
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| 450 | /* PSOC_GLOBAL_CONF_ADC_CLK_FREQ */ |
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| 451 | #define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_SHIFT 0 |
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| 452 | #define PSOC_GLOBAL_CONF_ADC_CLK_FREQ_VAL_MASK 0xFF |
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| 453 | |
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| 454 | /* PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START */ |
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| 455 | #define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_SHIFT 0 |
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| 456 | #define PSOC_GLOBAL_CONF_ADC_DELAY_FROM_START_VAL_MASK 0xFF |
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| 457 | |
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| 458 | /* PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES */ |
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| 459 | #define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_SHIFT 0 |
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| 460 | #define PSOC_GLOBAL_CONF_ADC_DATA_SAMPLES_VAL_MASK 0x1F |
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| 461 | |
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| 462 | /* PSOC_GLOBAL_CONF_ADC_TPH_CS */ |
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| 463 | #define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_SHIFT 0 |
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| 464 | #define PSOC_GLOBAL_CONF_ADC_TPH_CS_VAL_MASK 0xFF |
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| 465 | |
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| 466 | /* PSOC_GLOBAL_CONF_ADC_LSB_NMSB */ |
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| 467 | #define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_SHIFT 0 |
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| 468 | #define PSOC_GLOBAL_CONF_ADC_LSB_NMSB_VAL_MASK 0x1 |
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| 469 | |
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| 470 | /* PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES */ |
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| 471 | #define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_SHIFT 0 |
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| 472 | #define PSOC_GLOBAL_CONF_ADC_ONE_NCONTIUES_VAL_MASK 0x1 |
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| 473 | |
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| 474 | /* PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE */ |
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| 475 | #define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_SHIFT 0 |
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| 476 | #define PSOC_GLOBAL_CONF_ADC_BLOCK_ENABLE_VAL_MASK 0x1 |
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| 477 | |
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| 478 | /* PSOC_GLOBAL_CONF_ADC_CFG_DATA */ |
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| 479 | #define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_SHIFT 0 |
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| 480 | #define PSOC_GLOBAL_CONF_ADC_CFG_DATA_VAL_MASK 0xFFFFFFFF |
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| 481 | |
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| 482 | /* PSOC_GLOBAL_CONF_ADC_TDV_CSDO */ |
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| 483 | #define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_SHIFT 0 |
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| 484 | #define PSOC_GLOBAL_CONF_ADC_TDV_CSDO_VAL_MASK 0xFF |
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| 485 | |
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| 486 | /* PSOC_GLOBAL_CONF_ADC_TSU_CSCK */ |
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| 487 | #define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_SHIFT 0 |
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| 488 | #define PSOC_GLOBAL_CONF_ADC_TSU_CSCK_VAL_MASK 0xFF |
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| 489 | |
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| 490 | /* PSOC_GLOBAL_CONF_PAD_DEFAULT */ |
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| 491 | #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_SHIFT 0 |
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| 492 | #define PSOC_GLOBAL_CONF_PAD_DEFAULT_VAL_MASK 0xF |
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| 493 | |
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| 494 | /* PSOC_GLOBAL_CONF_PAD_SEL */ |
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| 495 | #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_SHIFT 0 |
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| 496 | #define PSOC_GLOBAL_CONF_PAD_SEL_VAL_MASK 0x3 |
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| 497 | |
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| 498 | /* PSOC_GLOBAL_CONF_RST_CTRL */ |
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| 499 | #define PSOC_GLOBAL_CONF_RST_CTRL_SEL_SHIFT 0 |
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| 500 | #define PSOC_GLOBAL_CONF_RST_CTRL_SEL_MASK 0xFF |
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| 501 | |
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| 502 | #endif /* ASIC_REG_PSOC_GLOBAL_CONF_MASKS_H_ */ |
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| 503 | |
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