| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2018-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | #ifndef GAUDI_H |
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| 9 | #define GAUDI_H |
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| 10 | |
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| 11 | #define SRAM_BAR_ID 0 |
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| 12 | #define CFG_BAR_ID 2 |
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| 13 | #define HBM_BAR_ID 4 |
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| 14 | |
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| 15 | #define SRAM_BAR_SIZE 0x4000000ull /* 64MB */ |
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| 16 | #define CFG_BAR_SIZE 0x8000000ull /* 128MB */ |
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| 17 | |
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| 18 | #define CFG_BASE 0x7FFC000000ull |
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| 19 | #define CFG_SIZE 0x4000000 /* 32MB CFG + 32MB DBG*/ |
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| 20 | |
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| 21 | #define SRAM_BASE_ADDR 0x7FF0000000ull |
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| 22 | #define SRAM_SIZE 0x1400000 /* 20MB */ |
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| 23 | |
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| 24 | #define SPI_FLASH_BASE_ADDR 0x7FF8000000ull |
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| 25 | |
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| 26 | #define PSOC_SCRATCHPAD_ADDR 0x7FFBFE0000ull |
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| 27 | #define PSOC_SCRATCHPAD_SIZE 0x10000 /* 64KB */ |
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| 28 | |
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| 29 | #define PCIE_FW_SRAM_ADDR 0x7FFBFF0000ull |
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| 30 | #define PCIE_FW_SRAM_SIZE 0x8000 /* 32KB */ |
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| 31 | |
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| 32 | #define DRAM_PHYS_BASE 0x0ull |
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| 33 | |
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| 34 | #define HOST_PHYS_BASE 0x8000000000ull /* 0.5TB */ |
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| 35 | #define HOST_PHYS_SIZE 0x1000000000000ull /* 0.25PB (48 bits) */ |
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| 36 | |
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| 37 | #define GAUDI_MSI_ENTRIES 32 |
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| 38 | |
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| 39 | #define QMAN_PQ_ENTRY_SIZE 16 /* Bytes */ |
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| 40 | |
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| 41 | #define MAX_ASID 2 |
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| 42 | |
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| 43 | #define PROT_BITS_OFFS 0xF80 |
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| 44 | |
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| 45 | #define MME_NUMBER_OF_MASTER_ENGINES 2 |
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| 46 | |
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| 47 | #define MME_NUMBER_OF_SLAVE_ENGINES 2 |
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| 48 | |
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| 49 | #define TPC_NUMBER_OF_ENGINES 8 |
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| 50 | |
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| 51 | #define DMA_NUMBER_OF_CHANNELS 8 |
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| 52 | |
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| 53 | #define NIC_NUMBER_OF_MACROS 5 |
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| 54 | |
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| 55 | #define NIC_NUMBER_OF_ENGINES (NIC_NUMBER_OF_MACROS * 2) |
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| 56 | |
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| 57 | #define NUMBER_OF_IF 8 |
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| 58 | |
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| 59 | #define DEVICE_CACHE_LINE_SIZE 128 |
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| 60 | |
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| 61 | #endif /* GAUDI_H */ |
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| 62 | |
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