| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_EDMA0_CORE_CTX |
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| 19 | * (Prototype: DMA_CORE_CTX) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE0_EDMA0_CORE_CTX_RATE_LIM_TKN 0x41CB860 |
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| 24 | |
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| 25 | #define mmDCORE0_EDMA0_CORE_CTX_PWRLP 0x41CB864 |
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| 26 | |
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| 27 | #define mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS 0x41CB868 |
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| 28 | |
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| 29 | #define mmDCORE0_EDMA0_CORE_CTX_IDX 0x41CB86C |
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| 30 | |
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| 31 | #define mmDCORE0_EDMA0_CORE_CTX_IDX_INC 0x41CB870 |
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| 32 | |
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| 33 | #define mmDCORE0_EDMA0_CORE_CTX_CTRL 0x41CB874 |
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| 34 | |
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| 35 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0 0x41CB878 |
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| 36 | |
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| 37 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1 0x41CB87C |
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| 38 | |
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| 39 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1 0x41CB880 |
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| 40 | |
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| 41 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2 0x41CB884 |
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| 42 | |
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| 43 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2 0x41CB888 |
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| 44 | |
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| 45 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3 0x41CB88C |
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| 46 | |
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| 47 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3 0x41CB890 |
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| 48 | |
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| 49 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4 0x41CB894 |
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| 50 | |
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| 51 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4 0x41CB898 |
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| 52 | |
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| 53 | #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1 0x41CB89C |
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| 54 | |
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| 55 | #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1 0x41CB8A0 |
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| 56 | |
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| 57 | #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2 0x41CB8A4 |
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| 58 | |
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| 59 | #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2 0x41CB8A8 |
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| 60 | |
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| 61 | #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3 0x41CB8AC |
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| 62 | |
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| 63 | #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3 0x41CB8B0 |
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| 64 | |
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| 65 | #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4 0x41CB8B4 |
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| 66 | |
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| 67 | #define mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4 0x41CB8B8 |
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| 68 | |
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| 69 | #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI 0x41CB8BC |
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| 70 | |
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| 71 | #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO 0x41CB8C0 |
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| 72 | |
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| 73 | #define mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA 0x41CB8C4 |
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| 74 | |
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| 75 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO 0x41CB8C8 |
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| 76 | |
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| 77 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI 0x41CB8CC |
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| 78 | |
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| 79 | #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO 0x41CB8D0 |
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| 80 | |
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| 81 | #define mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI 0x41CB8D4 |
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| 82 | |
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| 83 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO 0x41CB8D8 |
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| 84 | |
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| 85 | #define mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI 0x41CB8DC |
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| 86 | |
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| 87 | #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO 0x41CB8E0 |
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| 88 | |
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| 89 | #define mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI 0x41CB8E4 |
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| 90 | |
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| 91 | #define mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0 0x41CB8E8 |
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| 92 | |
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| 93 | #define mmDCORE0_EDMA0_CORE_CTX_COMMIT 0x41CB8EC |
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| 94 | |
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| 95 | #endif /* ASIC_REG_DCORE0_EDMA0_CORE_CTX_REGS_H_ */ |
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| 96 | |
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