| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ |
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| 14 | #define ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_EDMA0_QM |
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| 19 | * (Prototype: QMAN) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | /* DCORE0_EDMA0_QM_GLBL_CFG0 */ |
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| 24 | #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT 0 |
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| 25 | #define DCORE0_EDMA0_QM_GLBL_CFG0_PQF_EN_MASK 0xF |
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| 26 | #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT 4 |
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| 27 | #define DCORE0_EDMA0_QM_GLBL_CFG0_CQF_EN_MASK 0x1F0 |
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| 28 | #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_SHIFT 9 |
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| 29 | #define DCORE0_EDMA0_QM_GLBL_CFG0_CP_EN_MASK 0x3E00 |
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| 30 | #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT 14 |
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| 31 | #define DCORE0_EDMA0_QM_GLBL_CFG0_ARC_CQF_EN_MASK 0x4000 |
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| 32 | |
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| 33 | /* DCORE0_EDMA0_QM_GLBL_CFG1 */ |
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| 34 | #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_SHIFT 0 |
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| 35 | #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 0xF |
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| 36 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_SHIFT 4 |
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| 37 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 0x1F0 |
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| 38 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_SHIFT 9 |
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| 39 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_STOP_MASK 0x3E00 |
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| 40 | #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_SHIFT 16 |
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| 41 | #define DCORE0_EDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 0xF0000 |
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| 42 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_SHIFT 20 |
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| 43 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 0x1F00000 |
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| 44 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_SHIFT 25 |
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| 45 | #define DCORE0_EDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 0x3E000000 |
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| 46 | |
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| 47 | /* DCORE0_EDMA0_QM_GLBL_CFG2 */ |
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| 48 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_SHIFT 0 |
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| 49 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 0x1 |
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| 50 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_SHIFT 1 |
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| 51 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 0x2 |
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| 52 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_SHIFT 4 |
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| 53 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWUSER_OVRD_MASK 0x10 |
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| 54 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_SHIFT 5 |
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| 55 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARUSER_OVRD_MASK 0x20 |
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| 56 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_SHIFT 6 |
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| 57 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWUSER_OVRD_MASK 0x40 |
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| 58 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_SHIFT 7 |
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| 59 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARUSER_OVRD_MASK 0x80 |
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| 60 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_SHIFT 8 |
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| 61 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWPROT_OVRD_MASK 0x100 |
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| 62 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_SHIFT 9 |
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| 63 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARPROT_OVRD_MASK 0x200 |
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| 64 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_SHIFT 10 |
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| 65 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWPROT_OVRD_MASK 0x400 |
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| 66 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_SHIFT 11 |
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| 67 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARPROT_OVRD_MASK 0x800 |
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| 68 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_SHIFT 12 |
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| 69 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_AWCACHE_OVRD_MASK 0x1000 |
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| 70 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_SHIFT 13 |
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| 71 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_HBW_ARCACHE_OVRD_MASK 0x2000 |
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| 72 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_SHIFT 14 |
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| 73 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_AWCACHE_OVRD_MASK 0x4000 |
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| 74 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_SHIFT 15 |
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| 75 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_ARCACHE_OVRD_MASK 0x8000 |
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| 76 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_SHIFT 16 |
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| 77 | #define DCORE0_EDMA0_QM_GLBL_CFG2_ARC_LBW_BUSER_OVRD_MASK 0x10000 |
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| 78 | |
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| 79 | /* DCORE0_EDMA0_QM_GLBL_ERR_CFG */ |
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| 80 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT 0 |
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| 81 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_MASK 0xF |
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| 82 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT 4 |
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| 83 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_MASK 0x1F0 |
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| 84 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT 9 |
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| 85 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_MASK 0x3E00 |
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| 86 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT 16 |
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| 87 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_MASK 0xF0000 |
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| 88 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT 20 |
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| 89 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_MASK 0x1F00000 |
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| 90 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT 25 |
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| 91 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_MASK 0x3E000000 |
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| 92 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT 31 |
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| 93 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_MASK 0x80000000 |
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| 94 | |
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| 95 | /* DCORE0_EDMA0_QM_GLBL_ERR_CFG1 */ |
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| 96 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT 0 |
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| 97 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_MASK 0x1 |
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| 98 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT 1 |
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| 99 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_MASK 0x2 |
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| 100 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT 2 |
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| 101 | #define DCORE0_EDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_MASK 0x4 |
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| 102 | |
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| 103 | /* DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN */ |
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| 104 | #define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_SHIFT 0 |
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| 105 | #define DCORE0_EDMA0_QM_GLBL_ERR_ARC_HALT_EN_ERR_IND_MASK 0xFFFFFF |
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| 106 | |
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| 107 | /* DCORE0_EDMA0_QM_GLBL_AXCACHE */ |
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| 108 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_SHIFT 0 |
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| 109 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AR_MASK 0xF |
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| 110 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_SHIFT 16 |
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| 111 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_HBW_AW_MASK 0xF0000 |
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| 112 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_SHIFT 20 |
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| 113 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AW_MASK 0xF00000 |
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| 114 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_SHIFT 24 |
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| 115 | #define DCORE0_EDMA0_QM_GLBL_AXCACHE_LBW_AR_MASK 0xF000000 |
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| 116 | |
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| 117 | /* DCORE0_EDMA0_QM_GLBL_STS0 */ |
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| 118 | #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_SHIFT 0 |
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| 119 | #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK 0xF |
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| 120 | #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_SHIFT 4 |
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| 121 | #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK 0x1F0 |
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| 122 | #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_SHIFT 9 |
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| 123 | #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK 0x3E00 |
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| 124 | #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_SHIFT 16 |
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| 125 | #define DCORE0_EDMA0_QM_GLBL_STS0_PQF_IS_STOP_MASK 0xF0000 |
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| 126 | #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_SHIFT 20 |
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| 127 | #define DCORE0_EDMA0_QM_GLBL_STS0_CQF_IS_STOP_MASK 0x1F00000 |
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| 128 | #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_SHIFT 25 |
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| 129 | #define DCORE0_EDMA0_QM_GLBL_STS0_CP_IS_STOP_MASK 0x3E000000 |
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| 130 | #define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_SHIFT 31 |
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| 131 | #define DCORE0_EDMA0_QM_GLBL_STS0_ARB_IS_STOP_MASK 0x80000000 |
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| 132 | |
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| 133 | /* DCORE0_EDMA0_QM_GLBL_STS1 */ |
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| 134 | #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_SHIFT 0 |
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| 135 | #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 0x1 |
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| 136 | #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_SHIFT 1 |
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| 137 | #define DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IS_STOP_MASK 0x2 |
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| 138 | |
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| 139 | /* DCORE0_EDMA0_QM_GLBL_ERR_STS */ |
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| 140 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_SHIFT 0 |
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| 141 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQF_RD_ERR_MASK 0x1 |
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| 142 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_SHIFT 1 |
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| 143 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CQF_RD_ERR_MASK 0x2 |
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| 144 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_SHIFT 2 |
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| 145 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_RD_ERR_MASK 0x4 |
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| 146 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_SHIFT 3 |
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| 147 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_UNDEF_CMD_ERR_MASK 0x8 |
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| 148 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_SHIFT 4 |
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| 149 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_STOP_OP_MASK 0x10 |
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| 150 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_SHIFT 5 |
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| 151 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_MSG_WR_ERR_MASK 0x20 |
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| 152 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_SHIFT 6 |
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| 153 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_WREG_ERR_MASK 0x40 |
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| 154 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_SHIFT 8 |
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| 155 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_OVF_ERR_MASK 0x100 |
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| 156 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_SHIFT 9 |
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| 157 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_OVF_ERR_MASK 0x200 |
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| 158 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_SHIFT 10 |
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| 159 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_OVF_ERR_MASK 0x400 |
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| 160 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_SHIFT 11 |
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| 161 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_OVF_ERR_MASK 0x800 |
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| 162 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_SHIFT 12 |
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| 163 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE0_UDF_ERR_MASK 0x1000 |
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| 164 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_SHIFT 13 |
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| 165 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE1_UDF_ERR_MASK 0x2000 |
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| 166 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_SHIFT 14 |
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| 167 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE2_UDF_ERR_MASK 0x4000 |
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| 168 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_SHIFT 15 |
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| 169 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CP_FENCE3_UDF_ERR_MASK 0x8000 |
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| 170 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_SHIFT 16 |
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| 171 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_CPDMA_UP_OVF_ERR_MASK 0x10000 |
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| 172 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_SHIFT 17 |
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| 173 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_PQC_L2H_ERR_MASK 0x20000 |
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| 174 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_SHIFT 18 |
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| 175 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_RSVD_18_24_MASK 0x1FC0000 |
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| 176 | |
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| 177 | /* DCORE0_EDMA0_QM_GLBL_ERR_STS_4 */ |
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| 178 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_SHIFT 0 |
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| 179 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD0_MASK 0x1 |
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| 180 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_SHIFT 1 |
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| 181 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQF_RD_ERR_MASK 0x2 |
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| 182 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_SHIFT 2 |
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| 183 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_RD_ERR_MASK 0x4 |
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| 184 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_SHIFT 3 |
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| 185 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_UNDEF_CMD_ERR_MASK 0x8 |
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| 186 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_SHIFT 4 |
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| 187 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_STOP_OP_MASK 0x10 |
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| 188 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_SHIFT 5 |
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| 189 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_MSG_WR_ERR_MASK 0x20 |
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| 190 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_SHIFT 6 |
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| 191 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_WREG_ERR_MASK 0x40 |
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| 192 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_SHIFT 8 |
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| 193 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_OVF_ERR_MASK 0x100 |
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| 194 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_SHIFT 9 |
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| 195 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_OVF_ERR_MASK 0x200 |
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| 196 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_SHIFT 10 |
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| 197 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_OVF_ERR_MASK 0x400 |
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| 198 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_SHIFT 11 |
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| 199 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_OVF_ERR_MASK 0x800 |
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| 200 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_SHIFT 12 |
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| 201 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE0_UDF_ERR_MASK 0x1000 |
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| 202 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_SHIFT 13 |
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| 203 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE1_UDF_ERR_MASK 0x2000 |
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| 204 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_SHIFT 14 |
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| 205 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE2_UDF_ERR_MASK 0x4000 |
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| 206 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_SHIFT 15 |
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| 207 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_FENCE3_UDF_ERR_MASK 0x8000 |
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| 208 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_SHIFT 16 |
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| 209 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CPDMA_UP_OVF_ERR_MASK 0x10000 |
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| 210 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_SHIFT 17 |
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| 211 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_RSVD17_MASK 0x20000 |
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| 212 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 |
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| 213 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 |
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| 214 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_SHIFT 19 |
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| 215 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 |
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| 216 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_SHIFT 20 |
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| 217 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQF_RD_ERR_MASK 0x100000 |
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| 218 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 |
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| 219 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 |
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| 220 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 |
|---|
| 221 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 |
|---|
| 222 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_SHIFT 23 |
|---|
| 223 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_ARC_AXI_ERR_MASK 0x800000 |
|---|
| 224 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_SHIFT 24 |
|---|
| 225 | #define DCORE0_EDMA0_QM_GLBL_ERR_STS_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 |
|---|
| 226 | |
|---|
| 227 | /* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN */ |
|---|
| 228 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_SHIFT 0 |
|---|
| 229 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQF_RD_ERR_MASK 0x1 |
|---|
| 230 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_SHIFT 1 |
|---|
| 231 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CQF_RD_ERR_MASK 0x2 |
|---|
| 232 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_SHIFT 2 |
|---|
| 233 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_RD_ERR_MASK 0x4 |
|---|
| 234 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_SHIFT 3 |
|---|
| 235 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_UNDEF_CMD_ERR_MASK 0x8 |
|---|
| 236 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_SHIFT 4 |
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| 237 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_STOP_OP_MASK 0x10 |
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| 238 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_SHIFT 5 |
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| 239 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_MSG_WR_ERR_MASK 0x20 |
|---|
| 240 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_SHIFT 6 |
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| 241 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_WREG_ERR_MASK 0x40 |
|---|
| 242 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_SHIFT 8 |
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| 243 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_OVF_ERR_MASK 0x100 |
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| 244 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_SHIFT 9 |
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| 245 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_OVF_ERR_MASK 0x200 |
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| 246 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_SHIFT 10 |
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| 247 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_OVF_ERR_MASK 0x400 |
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| 248 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_SHIFT 11 |
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| 249 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_OVF_ERR_MASK 0x800 |
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| 250 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_SHIFT 12 |
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| 251 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE0_UDF_ERR_MASK 0x1000 |
|---|
| 252 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_SHIFT 13 |
|---|
| 253 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE1_UDF_ERR_MASK 0x2000 |
|---|
| 254 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_SHIFT 14 |
|---|
| 255 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE2_UDF_ERR_MASK 0x4000 |
|---|
| 256 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_SHIFT 15 |
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| 257 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CP_FENCE3_UDF_ERR_MASK 0x8000 |
|---|
| 258 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_SHIFT 16 |
|---|
| 259 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_CPDMA_UP_OVF_ERR_MASK 0x10000 |
|---|
| 260 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_SHIFT 17 |
|---|
| 261 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_PQC_L2H_ERR_MASK 0x20000 |
|---|
| 262 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_SHIFT 18 |
|---|
| 263 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_RSVD_18_24_MASK 0x1FC0000 |
|---|
| 264 | |
|---|
| 265 | /* DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4 */ |
|---|
| 266 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_SHIFT 0 |
|---|
| 267 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD0_MASK 0x1 |
|---|
| 268 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_SHIFT 1 |
|---|
| 269 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQF_RD_ERR_MASK 0x2 |
|---|
| 270 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_SHIFT 2 |
|---|
| 271 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_RD_ERR_MASK 0x4 |
|---|
| 272 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_SHIFT 3 |
|---|
| 273 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_UNDEF_CMD_ERR_MASK 0x8 |
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| 274 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_SHIFT 4 |
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| 275 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_STOP_OP_MASK 0x10 |
|---|
| 276 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_SHIFT 5 |
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| 277 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_MSG_WR_ERR_MASK 0x20 |
|---|
| 278 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_SHIFT 6 |
|---|
| 279 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_WREG_ERR_MASK 0x40 |
|---|
| 280 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_SHIFT 8 |
|---|
| 281 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_OVF_ERR_MASK 0x100 |
|---|
| 282 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_SHIFT 9 |
|---|
| 283 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_OVF_ERR_MASK 0x200 |
|---|
| 284 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_SHIFT 10 |
|---|
| 285 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_OVF_ERR_MASK 0x400 |
|---|
| 286 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_SHIFT 11 |
|---|
| 287 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_OVF_ERR_MASK 0x800 |
|---|
| 288 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_SHIFT 12 |
|---|
| 289 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE0_UDF_ERR_MASK 0x1000 |
|---|
| 290 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_SHIFT 13 |
|---|
| 291 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE1_UDF_ERR_MASK 0x2000 |
|---|
| 292 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_SHIFT 14 |
|---|
| 293 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE2_UDF_ERR_MASK 0x4000 |
|---|
| 294 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_SHIFT 15 |
|---|
| 295 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_FENCE3_UDF_ERR_MASK 0x8000 |
|---|
| 296 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_SHIFT 16 |
|---|
| 297 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CPDMA_UP_OVF_ERR_MASK 0x10000 |
|---|
| 298 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_SHIFT 17 |
|---|
| 299 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_RSVD17_MASK 0x20000 |
|---|
| 300 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_SHIFT 18 |
|---|
| 301 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_IFIFO_CI_ERR_MASK 0x40000 |
|---|
| 302 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_SHIFT 19 |
|---|
| 303 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CQ_WR_CTL_CI_ERR_MASK 0x80000 |
|---|
| 304 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_SHIFT 20 |
|---|
| 305 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQF_RD_ERR_MASK 0x100000 |
|---|
| 306 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_SHIFT 21 |
|---|
| 307 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_IFIFO_CI_ERR_MASK 0x200000 |
|---|
| 308 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_SHIFT 22 |
|---|
| 309 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_CQ_WR_CTL_CI_ERR_MASK 0x400000 |
|---|
| 310 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_SHIFT 23 |
|---|
| 311 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_ARC_AXI_ERR_MASK 0x800000 |
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| 312 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_SHIFT 24 |
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| 313 | #define DCORE0_EDMA0_QM_GLBL_ERR_MSG_EN_4_CP_SWITCH_WDT_ERR_MASK 0x1000000 |
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| 314 | |
|---|
| 315 | /* DCORE0_EDMA0_QM_GLBL_PROT */ |
|---|
| 316 | #define DCORE0_EDMA0_QM_GLBL_PROT_PQF_SHIFT 0 |
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| 317 | #define DCORE0_EDMA0_QM_GLBL_PROT_PQF_MASK 0xF |
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| 318 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQF_SHIFT 4 |
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| 319 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQF_MASK 0x1F0 |
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| 320 | #define DCORE0_EDMA0_QM_GLBL_PROT_CP_SHIFT 9 |
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| 321 | #define DCORE0_EDMA0_QM_GLBL_PROT_CP_MASK 0x3E00 |
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| 322 | #define DCORE0_EDMA0_QM_GLBL_PROT_ERR_SHIFT 14 |
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| 323 | #define DCORE0_EDMA0_QM_GLBL_PROT_ERR_MASK 0x4000 |
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| 324 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARB_SHIFT 15 |
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| 325 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARB_MASK 0x8000 |
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| 326 | #define DCORE0_EDMA0_QM_GLBL_PROT_PQC_SHIFT 16 |
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| 327 | #define DCORE0_EDMA0_QM_GLBL_PROT_PQC_MASK 0x10000 |
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| 328 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_SHIFT 17 |
|---|
| 329 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_IFIFO_MSG_MASK 0x20000 |
|---|
| 330 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_SHIFT 18 |
|---|
| 331 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_IFIFO_MSG_MASK 0x40000 |
|---|
| 332 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_SHIFT 19 |
|---|
| 333 | #define DCORE0_EDMA0_QM_GLBL_PROT_CQ_CTL_MSG_MASK 0x80000 |
|---|
| 334 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_SHIFT 20 |
|---|
| 335 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQ_CTL_MSG_MASK 0x100000 |
|---|
| 336 | #define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_SHIFT 21 |
|---|
| 337 | #define DCORE0_EDMA0_QM_GLBL_PROT_CP_WR_ARC_MASK 0x200000 |
|---|
| 338 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_SHIFT 22 |
|---|
| 339 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CQF_MASK 0x400000 |
|---|
| 340 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_SHIFT 23 |
|---|
| 341 | #define DCORE0_EDMA0_QM_GLBL_PROT_ARC_CORE_MASK 0x800000 |
|---|
| 342 | |
|---|
| 343 | /* DCORE0_EDMA0_QM_PQ_BASE_LO */ |
|---|
| 344 | #define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_SHIFT 0 |
|---|
| 345 | #define DCORE0_EDMA0_QM_PQ_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 346 | |
|---|
| 347 | /* DCORE0_EDMA0_QM_PQ_BASE_HI */ |
|---|
| 348 | #define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_SHIFT 0 |
|---|
| 349 | #define DCORE0_EDMA0_QM_PQ_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 350 | |
|---|
| 351 | /* DCORE0_EDMA0_QM_PQ_SIZE */ |
|---|
| 352 | #define DCORE0_EDMA0_QM_PQ_SIZE_VAL_SHIFT 0 |
|---|
| 353 | #define DCORE0_EDMA0_QM_PQ_SIZE_VAL_MASK 0x1F |
|---|
| 354 | |
|---|
| 355 | /* DCORE0_EDMA0_QM_PQ_PI */ |
|---|
| 356 | #define DCORE0_EDMA0_QM_PQ_PI_VAL_SHIFT 0 |
|---|
| 357 | #define DCORE0_EDMA0_QM_PQ_PI_VAL_MASK 0xFFFFFFFF |
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| 358 | |
|---|
| 359 | /* DCORE0_EDMA0_QM_PQ_CI */ |
|---|
| 360 | #define DCORE0_EDMA0_QM_PQ_CI_VAL_SHIFT 0 |
|---|
| 361 | #define DCORE0_EDMA0_QM_PQ_CI_VAL_MASK 0xFFFFFFFF |
|---|
| 362 | |
|---|
| 363 | /* DCORE0_EDMA0_QM_PQ_CFG0 */ |
|---|
| 364 | #define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_SHIFT 0 |
|---|
| 365 | #define DCORE0_EDMA0_QM_PQ_CFG0_FORCE_STALL_MASK 0x1 |
|---|
| 366 | |
|---|
| 367 | /* DCORE0_EDMA0_QM_PQ_CFG1 */ |
|---|
| 368 | #define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_SHIFT 0 |
|---|
| 369 | #define DCORE0_EDMA0_QM_PQ_CFG1_CREDIT_LIM_MASK 0xFF |
|---|
| 370 | #define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_SHIFT 16 |
|---|
| 371 | #define DCORE0_EDMA0_QM_PQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 |
|---|
| 372 | |
|---|
| 373 | /* DCORE0_EDMA0_QM_PQ_STS0 */ |
|---|
| 374 | #define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_SHIFT 0 |
|---|
| 375 | #define DCORE0_EDMA0_QM_PQ_STS0_CREDIT_CNT_MASK 0xFF |
|---|
| 376 | #define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_SHIFT 8 |
|---|
| 377 | #define DCORE0_EDMA0_QM_PQ_STS0_FREE_CNT_MASK 0xFF00 |
|---|
| 378 | #define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_SHIFT 16 |
|---|
| 379 | #define DCORE0_EDMA0_QM_PQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 |
|---|
| 380 | |
|---|
| 381 | /* DCORE0_EDMA0_QM_PQ_STS1 */ |
|---|
| 382 | #define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_SHIFT 0 |
|---|
| 383 | #define DCORE0_EDMA0_QM_PQ_STS1_BUF_EMPTY_MASK 0x1 |
|---|
| 384 | #define DCORE0_EDMA0_QM_PQ_STS1_BUSY_SHIFT 1 |
|---|
| 385 | #define DCORE0_EDMA0_QM_PQ_STS1_BUSY_MASK 0x2 |
|---|
| 386 | |
|---|
| 387 | /* DCORE0_EDMA0_QM_CQ_CFG0 */ |
|---|
| 388 | #define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_SHIFT 0 |
|---|
| 389 | #define DCORE0_EDMA0_QM_CQ_CFG0_IF_B2B_EN_MASK 0x1 |
|---|
| 390 | #define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_SHIFT 1 |
|---|
| 391 | #define DCORE0_EDMA0_QM_CQ_CFG0_IF_MSG_EN_MASK 0x2 |
|---|
| 392 | #define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_SHIFT 2 |
|---|
| 393 | #define DCORE0_EDMA0_QM_CQ_CFG0_CTL_MSG_EN_MASK 0x4 |
|---|
| 394 | |
|---|
| 395 | /* DCORE0_EDMA0_QM_CQ_STS0 */ |
|---|
| 396 | #define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_SHIFT 0 |
|---|
| 397 | #define DCORE0_EDMA0_QM_CQ_STS0_CREDIT_CNT_MASK 0xFF |
|---|
| 398 | #define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_SHIFT 8 |
|---|
| 399 | #define DCORE0_EDMA0_QM_CQ_STS0_FREE_CNT_MASK 0xFF00 |
|---|
| 400 | #define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_SHIFT 16 |
|---|
| 401 | #define DCORE0_EDMA0_QM_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 |
|---|
| 402 | |
|---|
| 403 | /* DCORE0_EDMA0_QM_CQ_CFG1 */ |
|---|
| 404 | #define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_SHIFT 0 |
|---|
| 405 | #define DCORE0_EDMA0_QM_CQ_CFG1_CREDIT_LIM_MASK 0xFF |
|---|
| 406 | #define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 |
|---|
| 407 | #define DCORE0_EDMA0_QM_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 |
|---|
| 408 | |
|---|
| 409 | /* DCORE0_EDMA0_QM_CQ_STS1 */ |
|---|
| 410 | #define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_SHIFT 0 |
|---|
| 411 | #define DCORE0_EDMA0_QM_CQ_STS1_BUF_EMPTY_MASK 0x1 |
|---|
| 412 | #define DCORE0_EDMA0_QM_CQ_STS1_BUSY_SHIFT 1 |
|---|
| 413 | #define DCORE0_EDMA0_QM_CQ_STS1_BUSY_MASK 0x2 |
|---|
| 414 | |
|---|
| 415 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_0 */ |
|---|
| 416 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_SHIFT 0 |
|---|
| 417 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_0_VAL_MASK 0xFFFFFFFF |
|---|
| 418 | |
|---|
| 419 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_0 */ |
|---|
| 420 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_SHIFT 0 |
|---|
| 421 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_0_VAL_MASK 0xFFFFFFFF |
|---|
| 422 | |
|---|
| 423 | /* DCORE0_EDMA0_QM_CQ_TSIZE_0 */ |
|---|
| 424 | #define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_SHIFT 0 |
|---|
| 425 | #define DCORE0_EDMA0_QM_CQ_TSIZE_0_VAL_MASK 0xFFFFFFFF |
|---|
| 426 | |
|---|
| 427 | /* DCORE0_EDMA0_QM_CQ_CTL_0 */ |
|---|
| 428 | #define DCORE0_EDMA0_QM_CQ_CTL_0_UP_SHIFT 28 |
|---|
| 429 | #define DCORE0_EDMA0_QM_CQ_CTL_0_UP_MASK 0xF0000000 |
|---|
| 430 | |
|---|
| 431 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_1 */ |
|---|
| 432 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_SHIFT 0 |
|---|
| 433 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_1_VAL_MASK 0xFFFFFFFF |
|---|
| 434 | |
|---|
| 435 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_1 */ |
|---|
| 436 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_SHIFT 0 |
|---|
| 437 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_1_VAL_MASK 0xFFFFFFFF |
|---|
| 438 | |
|---|
| 439 | /* DCORE0_EDMA0_QM_CQ_TSIZE_1 */ |
|---|
| 440 | #define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_SHIFT 0 |
|---|
| 441 | #define DCORE0_EDMA0_QM_CQ_TSIZE_1_VAL_MASK 0xFFFFFFFF |
|---|
| 442 | |
|---|
| 443 | /* DCORE0_EDMA0_QM_CQ_CTL_1 */ |
|---|
| 444 | #define DCORE0_EDMA0_QM_CQ_CTL_1_UP_SHIFT 28 |
|---|
| 445 | #define DCORE0_EDMA0_QM_CQ_CTL_1_UP_MASK 0xF0000000 |
|---|
| 446 | |
|---|
| 447 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_2 */ |
|---|
| 448 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_SHIFT 0 |
|---|
| 449 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_2_VAL_MASK 0xFFFFFFFF |
|---|
| 450 | |
|---|
| 451 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_2 */ |
|---|
| 452 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_SHIFT 0 |
|---|
| 453 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_2_VAL_MASK 0xFFFFFFFF |
|---|
| 454 | |
|---|
| 455 | /* DCORE0_EDMA0_QM_CQ_TSIZE_2 */ |
|---|
| 456 | #define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_SHIFT 0 |
|---|
| 457 | #define DCORE0_EDMA0_QM_CQ_TSIZE_2_VAL_MASK 0xFFFFFFFF |
|---|
| 458 | |
|---|
| 459 | /* DCORE0_EDMA0_QM_CQ_CTL_2 */ |
|---|
| 460 | #define DCORE0_EDMA0_QM_CQ_CTL_2_UP_SHIFT 28 |
|---|
| 461 | #define DCORE0_EDMA0_QM_CQ_CTL_2_UP_MASK 0xF0000000 |
|---|
| 462 | |
|---|
| 463 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_3 */ |
|---|
| 464 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_SHIFT 0 |
|---|
| 465 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_3_VAL_MASK 0xFFFFFFFF |
|---|
| 466 | |
|---|
| 467 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_3 */ |
|---|
| 468 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_SHIFT 0 |
|---|
| 469 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_3_VAL_MASK 0xFFFFFFFF |
|---|
| 470 | |
|---|
| 471 | /* DCORE0_EDMA0_QM_CQ_TSIZE_3 */ |
|---|
| 472 | #define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_SHIFT 0 |
|---|
| 473 | #define DCORE0_EDMA0_QM_CQ_TSIZE_3_VAL_MASK 0xFFFFFFFF |
|---|
| 474 | |
|---|
| 475 | /* DCORE0_EDMA0_QM_CQ_CTL_3 */ |
|---|
| 476 | #define DCORE0_EDMA0_QM_CQ_CTL_3_UP_SHIFT 28 |
|---|
| 477 | #define DCORE0_EDMA0_QM_CQ_CTL_3_UP_MASK 0xF0000000 |
|---|
| 478 | |
|---|
| 479 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_4 */ |
|---|
| 480 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_SHIFT 0 |
|---|
| 481 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_4_VAL_MASK 0xFFFFFFFF |
|---|
| 482 | |
|---|
| 483 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_4 */ |
|---|
| 484 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_SHIFT 0 |
|---|
| 485 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_4_VAL_MASK 0xFFFFFFFF |
|---|
| 486 | |
|---|
| 487 | /* DCORE0_EDMA0_QM_CQ_TSIZE_4 */ |
|---|
| 488 | #define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_SHIFT 0 |
|---|
| 489 | #define DCORE0_EDMA0_QM_CQ_TSIZE_4_VAL_MASK 0xFFFFFFFF |
|---|
| 490 | |
|---|
| 491 | /* DCORE0_EDMA0_QM_CQ_CTL_4 */ |
|---|
| 492 | #define DCORE0_EDMA0_QM_CQ_CTL_4_UP_SHIFT 28 |
|---|
| 493 | #define DCORE0_EDMA0_QM_CQ_CTL_4_UP_MASK 0xF0000000 |
|---|
| 494 | |
|---|
| 495 | /* DCORE0_EDMA0_QM_CQ_TSIZE_STS */ |
|---|
| 496 | #define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_SHIFT 0 |
|---|
| 497 | #define DCORE0_EDMA0_QM_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 498 | |
|---|
| 499 | /* DCORE0_EDMA0_QM_CQ_PTR_LO_STS */ |
|---|
| 500 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_SHIFT 0 |
|---|
| 501 | #define DCORE0_EDMA0_QM_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 502 | |
|---|
| 503 | /* DCORE0_EDMA0_QM_CQ_PTR_HI_STS */ |
|---|
| 504 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_SHIFT 0 |
|---|
| 505 | #define DCORE0_EDMA0_QM_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 506 | |
|---|
| 507 | /* DCORE0_EDMA0_QM_CQ_IFIFO_STS */ |
|---|
| 508 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_SHIFT 0 |
|---|
| 509 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CNT_MASK 0x7 |
|---|
| 510 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_SHIFT 4 |
|---|
| 511 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_RDY_MASK 0x10 |
|---|
| 512 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 |
|---|
| 513 | #define DCORE0_EDMA0_QM_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 |
|---|
| 514 | |
|---|
| 515 | /* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO */ |
|---|
| 516 | #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_SHIFT 0 |
|---|
| 517 | #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 518 | |
|---|
| 519 | /* DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI */ |
|---|
| 520 | #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_SHIFT 0 |
|---|
| 521 | #define DCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 522 | |
|---|
| 523 | /* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO */ |
|---|
| 524 | #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_SHIFT 0 |
|---|
| 525 | #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 526 | |
|---|
| 527 | /* DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI */ |
|---|
| 528 | #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_SHIFT 0 |
|---|
| 529 | #define DCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 530 | |
|---|
| 531 | /* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO */ |
|---|
| 532 | #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_SHIFT 0 |
|---|
| 533 | #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 534 | |
|---|
| 535 | /* DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI */ |
|---|
| 536 | #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_SHIFT 0 |
|---|
| 537 | #define DCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 538 | |
|---|
| 539 | /* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO */ |
|---|
| 540 | #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_SHIFT 0 |
|---|
| 541 | #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 542 | |
|---|
| 543 | /* DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI */ |
|---|
| 544 | #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_SHIFT 0 |
|---|
| 545 | #define DCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 546 | |
|---|
| 547 | /* DCORE0_EDMA0_QM_CP_FENCE0_RDATA */ |
|---|
| 548 | #define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_SHIFT 0 |
|---|
| 549 | #define DCORE0_EDMA0_QM_CP_FENCE0_RDATA_INC_VAL_MASK 0xF |
|---|
| 550 | |
|---|
| 551 | /* DCORE0_EDMA0_QM_CP_FENCE1_RDATA */ |
|---|
| 552 | #define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_SHIFT 0 |
|---|
| 553 | #define DCORE0_EDMA0_QM_CP_FENCE1_RDATA_INC_VAL_MASK 0xF |
|---|
| 554 | |
|---|
| 555 | /* DCORE0_EDMA0_QM_CP_FENCE2_RDATA */ |
|---|
| 556 | #define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_SHIFT 0 |
|---|
| 557 | #define DCORE0_EDMA0_QM_CP_FENCE2_RDATA_INC_VAL_MASK 0xF |
|---|
| 558 | |
|---|
| 559 | /* DCORE0_EDMA0_QM_CP_FENCE3_RDATA */ |
|---|
| 560 | #define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_SHIFT 0 |
|---|
| 561 | #define DCORE0_EDMA0_QM_CP_FENCE3_RDATA_INC_VAL_MASK 0xF |
|---|
| 562 | |
|---|
| 563 | /* DCORE0_EDMA0_QM_CP_FENCE0_CNT */ |
|---|
| 564 | #define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_SHIFT 0 |
|---|
| 565 | #define DCORE0_EDMA0_QM_CP_FENCE0_CNT_VAL_MASK 0x3FFF |
|---|
| 566 | |
|---|
| 567 | /* DCORE0_EDMA0_QM_CP_FENCE1_CNT */ |
|---|
| 568 | #define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_SHIFT 0 |
|---|
| 569 | #define DCORE0_EDMA0_QM_CP_FENCE1_CNT_VAL_MASK 0x3FFF |
|---|
| 570 | |
|---|
| 571 | /* DCORE0_EDMA0_QM_CP_FENCE2_CNT */ |
|---|
| 572 | #define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_SHIFT 0 |
|---|
| 573 | #define DCORE0_EDMA0_QM_CP_FENCE2_CNT_VAL_MASK 0x3FFF |
|---|
| 574 | |
|---|
| 575 | /* DCORE0_EDMA0_QM_CP_FENCE3_CNT */ |
|---|
| 576 | #define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_SHIFT 0 |
|---|
| 577 | #define DCORE0_EDMA0_QM_CP_FENCE3_CNT_VAL_MASK 0x3FFF |
|---|
| 578 | |
|---|
| 579 | /* DCORE0_EDMA0_QM_CP_BARRIER_CFG */ |
|---|
| 580 | #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_SHIFT 0 |
|---|
| 581 | #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_EBGUARD_MASK 0xFFF |
|---|
| 582 | #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_SHIFT 16 |
|---|
| 583 | #define DCORE0_EDMA0_QM_CP_BARRIER_CFG_RBGUARD_MASK 0xF0000 |
|---|
| 584 | |
|---|
| 585 | /* DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET */ |
|---|
| 586 | #define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_SHIFT 0 |
|---|
| 587 | #define DCORE0_EDMA0_QM_CP_LDMA_SRC_BASE_LO_OFFSET_VAL_MASK 0xFFFF |
|---|
| 588 | |
|---|
| 589 | /* DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET */ |
|---|
| 590 | #define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_SHIFT 0 |
|---|
| 591 | #define DCORE0_EDMA0_QM_CP_LDMA_DST_BASE_LO_OFFSET_VAL_MASK 0xFFFF |
|---|
| 592 | |
|---|
| 593 | /* DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET */ |
|---|
| 594 | #define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_SHIFT 0 |
|---|
| 595 | #define DCORE0_EDMA0_QM_CP_LDMA_TSIZE_OFFSET_VAL_MASK 0xFFFF |
|---|
| 596 | |
|---|
| 597 | /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0 */ |
|---|
| 598 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_SHIFT 0 |
|---|
| 599 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_0_VAL_MASK 0xFFFF |
|---|
| 600 | |
|---|
| 601 | /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1 */ |
|---|
| 602 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_SHIFT 0 |
|---|
| 603 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_1_VAL_MASK 0xFFFF |
|---|
| 604 | |
|---|
| 605 | /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2 */ |
|---|
| 606 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_SHIFT 0 |
|---|
| 607 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_2_VAL_MASK 0xFFFF |
|---|
| 608 | |
|---|
| 609 | /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3 */ |
|---|
| 610 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_SHIFT 0 |
|---|
| 611 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_3_VAL_MASK 0xFFFF |
|---|
| 612 | |
|---|
| 613 | /* DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4 */ |
|---|
| 614 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_SHIFT 0 |
|---|
| 615 | #define DCORE0_EDMA0_QM_CP_CQ_PTR_LO_OFFSET_4_VAL_MASK 0xFFFF |
|---|
| 616 | |
|---|
| 617 | /* DCORE0_EDMA0_QM_CP_STS */ |
|---|
| 618 | #define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_SHIFT 0 |
|---|
| 619 | #define DCORE0_EDMA0_QM_CP_STS_MSG_INFLIGHT_CNT_MASK 0xFF |
|---|
| 620 | #define DCORE0_EDMA0_QM_CP_STS_ERDY_SHIFT 8 |
|---|
| 621 | #define DCORE0_EDMA0_QM_CP_STS_ERDY_MASK 0x100 |
|---|
| 622 | #define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_SHIFT 9 |
|---|
| 623 | #define DCORE0_EDMA0_QM_CP_STS_SWITCH_EN_MASK 0x200 |
|---|
| 624 | #define DCORE0_EDMA0_QM_CP_STS_MRDY_SHIFT 10 |
|---|
| 625 | #define DCORE0_EDMA0_QM_CP_STS_MRDY_MASK 0x400 |
|---|
| 626 | #define DCORE0_EDMA0_QM_CP_STS_SW_STOP_SHIFT 11 |
|---|
| 627 | #define DCORE0_EDMA0_QM_CP_STS_SW_STOP_MASK 0x800 |
|---|
| 628 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_SHIFT 12 |
|---|
| 629 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_ID_MASK 0x3000 |
|---|
| 630 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_SHIFT 14 |
|---|
| 631 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_IN_PROGRESS_MASK 0x4000 |
|---|
| 632 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_SHIFT 16 |
|---|
| 633 | #define DCORE0_EDMA0_QM_CP_STS_FENCE_TARGET_MASK 0x3FFF0000 |
|---|
| 634 | #define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_SHIFT 30 |
|---|
| 635 | #define DCORE0_EDMA0_QM_CP_STS_CUR_CQ_MASK 0x40000000 |
|---|
| 636 | |
|---|
| 637 | /* DCORE0_EDMA0_QM_CP_CURRENT_INST_LO */ |
|---|
| 638 | #define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_SHIFT 0 |
|---|
| 639 | #define DCORE0_EDMA0_QM_CP_CURRENT_INST_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 640 | |
|---|
| 641 | /* DCORE0_EDMA0_QM_CP_CURRENT_INST_HI */ |
|---|
| 642 | #define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_SHIFT 0 |
|---|
| 643 | #define DCORE0_EDMA0_QM_CP_CURRENT_INST_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 644 | |
|---|
| 645 | /* DCORE0_EDMA0_QM_CP_PRED */ |
|---|
| 646 | #define DCORE0_EDMA0_QM_CP_PRED_VAL_SHIFT 0 |
|---|
| 647 | #define DCORE0_EDMA0_QM_CP_PRED_VAL_MASK 0xFFFFFFFF |
|---|
| 648 | |
|---|
| 649 | /* DCORE0_EDMA0_QM_CP_PRED_UPEN */ |
|---|
| 650 | #define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_SHIFT 0 |
|---|
| 651 | #define DCORE0_EDMA0_QM_CP_PRED_UPEN_VAL_MASK 0xFFFFFFFF |
|---|
| 652 | |
|---|
| 653 | /* DCORE0_EDMA0_QM_CP_DBG_0 */ |
|---|
| 654 | #define DCORE0_EDMA0_QM_CP_DBG_0_CS_SHIFT 0 |
|---|
| 655 | #define DCORE0_EDMA0_QM_CP_DBG_0_CS_MASK 0x1F |
|---|
| 656 | #define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_SHIFT 5 |
|---|
| 657 | #define DCORE0_EDMA0_QM_CP_DBG_0_EB_CNT_NOT_ZERO_MASK 0x20 |
|---|
| 658 | #define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_SHIFT 6 |
|---|
| 659 | #define DCORE0_EDMA0_QM_CP_DBG_0_BULK_CNT_NOT_ZERO_MASK 0x40 |
|---|
| 660 | #define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_SHIFT 7 |
|---|
| 661 | #define DCORE0_EDMA0_QM_CP_DBG_0_MREB_STALL_MASK 0x80 |
|---|
| 662 | #define DCORE0_EDMA0_QM_CP_DBG_0_STALL_SHIFT 8 |
|---|
| 663 | #define DCORE0_EDMA0_QM_CP_DBG_0_STALL_MASK 0x100 |
|---|
| 664 | |
|---|
| 665 | /* DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED */ |
|---|
| 666 | #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_SHIFT 0 |
|---|
| 667 | #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_TH_MASK 0x3 |
|---|
| 668 | #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_SHIFT 8 |
|---|
| 669 | #define DCORE0_EDMA0_QM_CP_CPDMA_UP_CRED_VAL_MASK 0x300 |
|---|
| 670 | |
|---|
| 671 | /* DCORE0_EDMA0_QM_CP_IN_DATA_LO */ |
|---|
| 672 | #define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_SHIFT 0 |
|---|
| 673 | #define DCORE0_EDMA0_QM_CP_IN_DATA_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 674 | |
|---|
| 675 | /* DCORE0_EDMA0_QM_CP_IN_DATA_HI */ |
|---|
| 676 | #define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_SHIFT 0 |
|---|
| 677 | #define DCORE0_EDMA0_QM_CP_IN_DATA_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 678 | |
|---|
| 679 | /* DCORE0_EDMA0_QM_PQC_HBW_BASE_LO */ |
|---|
| 680 | #define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_SHIFT 0 |
|---|
| 681 | #define DCORE0_EDMA0_QM_PQC_HBW_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 682 | |
|---|
| 683 | /* DCORE0_EDMA0_QM_PQC_HBW_BASE_HI */ |
|---|
| 684 | #define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_SHIFT 0 |
|---|
| 685 | #define DCORE0_EDMA0_QM_PQC_HBW_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 686 | |
|---|
| 687 | /* DCORE0_EDMA0_QM_PQC_SIZE */ |
|---|
| 688 | #define DCORE0_EDMA0_QM_PQC_SIZE_VAL_SHIFT 0 |
|---|
| 689 | #define DCORE0_EDMA0_QM_PQC_SIZE_VAL_MASK 0xFFFFFFFF |
|---|
| 690 | |
|---|
| 691 | /* DCORE0_EDMA0_QM_PQC_PI */ |
|---|
| 692 | #define DCORE0_EDMA0_QM_PQC_PI_VAL_SHIFT 0 |
|---|
| 693 | #define DCORE0_EDMA0_QM_PQC_PI_VAL_MASK 0xFFFFFFFF |
|---|
| 694 | |
|---|
| 695 | /* DCORE0_EDMA0_QM_PQC_LBW_WDATA */ |
|---|
| 696 | #define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_SHIFT 0 |
|---|
| 697 | #define DCORE0_EDMA0_QM_PQC_LBW_WDATA_VAL_MASK 0xFFFFFFFF |
|---|
| 698 | |
|---|
| 699 | /* DCORE0_EDMA0_QM_PQC_LBW_BASE_LO */ |
|---|
| 700 | #define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_SHIFT 0 |
|---|
| 701 | #define DCORE0_EDMA0_QM_PQC_LBW_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 702 | |
|---|
| 703 | /* DCORE0_EDMA0_QM_PQC_LBW_BASE_HI */ |
|---|
| 704 | #define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_SHIFT 0 |
|---|
| 705 | #define DCORE0_EDMA0_QM_PQC_LBW_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 706 | |
|---|
| 707 | /* DCORE0_EDMA0_QM_PQC_CFG */ |
|---|
| 708 | #define DCORE0_EDMA0_QM_PQC_CFG_EN_SHIFT 0 |
|---|
| 709 | #define DCORE0_EDMA0_QM_PQC_CFG_EN_MASK 0x1 |
|---|
| 710 | #define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_SHIFT 4 |
|---|
| 711 | #define DCORE0_EDMA0_QM_PQC_CFG_DIRECT_MASK 0x10 |
|---|
| 712 | |
|---|
| 713 | /* DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND */ |
|---|
| 714 | #define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 |
|---|
| 715 | #define DCORE0_EDMA0_QM_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 |
|---|
| 716 | |
|---|
| 717 | /* DCORE0_EDMA0_QM_ARB_MASK */ |
|---|
| 718 | #define DCORE0_EDMA0_QM_ARB_MASK_VAL_SHIFT 0 |
|---|
| 719 | #define DCORE0_EDMA0_QM_ARB_MASK_VAL_MASK 0xF |
|---|
| 720 | |
|---|
| 721 | /* DCORE0_EDMA0_QM_ARB_CFG_0 */ |
|---|
| 722 | #define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_SHIFT 0 |
|---|
| 723 | #define DCORE0_EDMA0_QM_ARB_CFG_0_PRIO_TYPE_MASK 0x1 |
|---|
| 724 | #define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_SHIFT 4 |
|---|
| 725 | #define DCORE0_EDMA0_QM_ARB_CFG_0_IS_MASTER_MASK 0x10 |
|---|
| 726 | #define DCORE0_EDMA0_QM_ARB_CFG_0_EN_SHIFT 8 |
|---|
| 727 | #define DCORE0_EDMA0_QM_ARB_CFG_0_EN_MASK 0x100 |
|---|
| 728 | #define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_SHIFT 9 |
|---|
| 729 | #define DCORE0_EDMA0_QM_ARB_CFG_0_MST_MSG_NOSTALL_MASK 0x200 |
|---|
| 730 | |
|---|
| 731 | /* DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH */ |
|---|
| 732 | #define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_SHIFT 0 |
|---|
| 733 | #define DCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH_VAL_MASK 0x3 |
|---|
| 734 | |
|---|
| 735 | /* DCORE0_EDMA0_QM_ARB_WRR_WEIGHT */ |
|---|
| 736 | #define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_SHIFT 0 |
|---|
| 737 | #define DCORE0_EDMA0_QM_ARB_WRR_WEIGHT_VAL_MASK 0xFF |
|---|
| 738 | |
|---|
| 739 | /* DCORE0_EDMA0_QM_ARB_CFG_1 */ |
|---|
| 740 | #define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_SHIFT 0 |
|---|
| 741 | #define DCORE0_EDMA0_QM_ARB_CFG_1_CLR_MASK 0x1 |
|---|
| 742 | |
|---|
| 743 | /* DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED */ |
|---|
| 744 | #define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_SHIFT 0 |
|---|
| 745 | #define DCORE0_EDMA0_QM_ARB_MST_AVAIL_CRED_VAL_MASK 0x7F |
|---|
| 746 | |
|---|
| 747 | /* DCORE0_EDMA0_QM_ARB_MST_CRED_INC */ |
|---|
| 748 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_SHIFT 0 |
|---|
| 749 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_INC_VAL_MASK 0xFFFFFFFF |
|---|
| 750 | |
|---|
| 751 | /* DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST */ |
|---|
| 752 | #define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_SHIFT 0 |
|---|
| 753 | #define DCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_VAL_MASK 0xFFFFFFFF |
|---|
| 754 | |
|---|
| 755 | /* DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST */ |
|---|
| 756 | #define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_SHIFT 0 |
|---|
| 757 | #define DCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST_VAL_MASK 0xFFFFFFFF |
|---|
| 758 | |
|---|
| 759 | /* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN */ |
|---|
| 760 | #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_SHIFT 0 |
|---|
| 761 | #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_VAL_MASK 0xFFFFFFFF |
|---|
| 762 | |
|---|
| 763 | /* DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1 */ |
|---|
| 764 | #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_SHIFT 0 |
|---|
| 765 | #define DCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1_VAL_MASK 0xFFFFFFFF |
|---|
| 766 | |
|---|
| 767 | /* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT */ |
|---|
| 768 | #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_SHIFT 0 |
|---|
| 769 | #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_WDT_VAL_MASK 0xFFFFFFFF |
|---|
| 770 | |
|---|
| 771 | /* DCORE0_EDMA0_QM_ARB_SLV_ID */ |
|---|
| 772 | #define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_SHIFT 0 |
|---|
| 773 | #define DCORE0_EDMA0_QM_ARB_SLV_ID_VAL_MASK 0x7F |
|---|
| 774 | |
|---|
| 775 | /* DCORE0_EDMA0_QM_ARB_MST_QUIET_PER */ |
|---|
| 776 | #define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_SHIFT 0 |
|---|
| 777 | #define DCORE0_EDMA0_QM_ARB_MST_QUIET_PER_VAL_MASK 0xFFFFFFFF |
|---|
| 778 | |
|---|
| 779 | /* DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT */ |
|---|
| 780 | #define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_SHIFT 0 |
|---|
| 781 | #define DCORE0_EDMA0_QM_ARB_MSG_MAX_INFLIGHT_VAL_MASK 0x3F |
|---|
| 782 | |
|---|
| 783 | /* DCORE0_EDMA0_QM_ARB_BASE_LO */ |
|---|
| 784 | #define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_SHIFT 0 |
|---|
| 785 | #define DCORE0_EDMA0_QM_ARB_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 786 | |
|---|
| 787 | /* DCORE0_EDMA0_QM_ARB_BASE_HI */ |
|---|
| 788 | #define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_SHIFT 0 |
|---|
| 789 | #define DCORE0_EDMA0_QM_ARB_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 790 | |
|---|
| 791 | /* DCORE0_EDMA0_QM_ARB_STATE_STS */ |
|---|
| 792 | #define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_SHIFT 0 |
|---|
| 793 | #define DCORE0_EDMA0_QM_ARB_STATE_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 794 | |
|---|
| 795 | /* DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS */ |
|---|
| 796 | #define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_SHIFT 0 |
|---|
| 797 | #define DCORE0_EDMA0_QM_ARB_CHOICE_FULLNESS_STS_VAL_MASK 0x7F |
|---|
| 798 | |
|---|
| 799 | /* DCORE0_EDMA0_QM_ARB_MSG_STS */ |
|---|
| 800 | #define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_SHIFT 0 |
|---|
| 801 | #define DCORE0_EDMA0_QM_ARB_MSG_STS_FULL_MASK 0x1 |
|---|
| 802 | #define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_SHIFT 1 |
|---|
| 803 | #define DCORE0_EDMA0_QM_ARB_MSG_STS_NO_INFLIGHT_MASK 0x2 |
|---|
| 804 | |
|---|
| 805 | /* DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD */ |
|---|
| 806 | #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_SHIFT 0 |
|---|
| 807 | #define DCORE0_EDMA0_QM_ARB_SLV_CHOICE_Q_HEAD_VAL_MASK 0x3 |
|---|
| 808 | |
|---|
| 809 | /* DCORE0_EDMA0_QM_ARB_ERR_CAUSE */ |
|---|
| 810 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_SHIFT 0 |
|---|
| 811 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_OVF_MASK 0x1 |
|---|
| 812 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_SHIFT 1 |
|---|
| 813 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_CHOICE_WDT_MASK 0x2 |
|---|
| 814 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_SHIFT 2 |
|---|
| 815 | #define DCORE0_EDMA0_QM_ARB_ERR_CAUSE_AXI_LBW_ERR_MASK 0x4 |
|---|
| 816 | |
|---|
| 817 | /* DCORE0_EDMA0_QM_ARB_ERR_MSG_EN */ |
|---|
| 818 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_SHIFT 0 |
|---|
| 819 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_OVF_MASK 0x1 |
|---|
| 820 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_SHIFT 1 |
|---|
| 821 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_CHOICE_WDT_MASK 0x2 |
|---|
| 822 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_SHIFT 2 |
|---|
| 823 | #define DCORE0_EDMA0_QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 |
|---|
| 824 | |
|---|
| 825 | /* DCORE0_EDMA0_QM_ARB_ERR_STS_DRP */ |
|---|
| 826 | #define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_SHIFT 0 |
|---|
| 827 | #define DCORE0_EDMA0_QM_ARB_ERR_STS_DRP_VAL_MASK 0x3 |
|---|
| 828 | |
|---|
| 829 | /* DCORE0_EDMA0_QM_ARB_MST_CRED_STS */ |
|---|
| 830 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_SHIFT 0 |
|---|
| 831 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_VAL_MASK 0x7F |
|---|
| 832 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_SHIFT 24 |
|---|
| 833 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_IDX_MASK 0x1F000000 |
|---|
| 834 | |
|---|
| 835 | /* DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1 */ |
|---|
| 836 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_SHIFT 0 |
|---|
| 837 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_VAL_MASK 0x7F |
|---|
| 838 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_SHIFT 24 |
|---|
| 839 | #define DCORE0_EDMA0_QM_ARB_MST_CRED_STS_1_IDX_MASK 0x1F000000 |
|---|
| 840 | |
|---|
| 841 | /* DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG */ |
|---|
| 842 | #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_SHIFT 0 |
|---|
| 843 | #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_ARB_TYPE_MASK 0x1 |
|---|
| 844 | #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_SHIFT 4 |
|---|
| 845 | #define DCORE0_EDMA0_QM_CSMR_STRICT_PRIO_CFG_PER_ENTRY_MASK 0x10 |
|---|
| 846 | |
|---|
| 847 | /* DCORE0_EDMA0_QM_ARC_CQ_CFG0 */ |
|---|
| 848 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_SHIFT 0 |
|---|
| 849 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_B2B_EN_MASK 0x1 |
|---|
| 850 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_SHIFT 1 |
|---|
| 851 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_IF_MSG_EN_MASK 0x2 |
|---|
| 852 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_SHIFT 2 |
|---|
| 853 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG0_CTL_MSG_EN_MASK 0x4 |
|---|
| 854 | |
|---|
| 855 | /* DCORE0_EDMA0_QM_ARC_CQ_CFG1 */ |
|---|
| 856 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_SHIFT 0 |
|---|
| 857 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_CREDIT_LIM_MASK 0xFF |
|---|
| 858 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_SHIFT 16 |
|---|
| 859 | #define DCORE0_EDMA0_QM_ARC_CQ_CFG1_MAX_INFLIGHT_MASK 0xFF0000 |
|---|
| 860 | |
|---|
| 861 | /* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO */ |
|---|
| 862 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_SHIFT 0 |
|---|
| 863 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 864 | |
|---|
| 865 | /* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI */ |
|---|
| 866 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_SHIFT 0 |
|---|
| 867 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 868 | |
|---|
| 869 | /* DCORE0_EDMA0_QM_ARC_CQ_TSIZE */ |
|---|
| 870 | #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_SHIFT 0 |
|---|
| 871 | #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_VAL_MASK 0xFFFFFFFF |
|---|
| 872 | |
|---|
| 873 | /* DCORE0_EDMA0_QM_ARC_CQ_CTL */ |
|---|
| 874 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_SHIFT 28 |
|---|
| 875 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_UP_MASK 0xF0000000 |
|---|
| 876 | |
|---|
| 877 | /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS */ |
|---|
| 878 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_SHIFT 0 |
|---|
| 879 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CNT_MASK 0x7 |
|---|
| 880 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_SHIFT 4 |
|---|
| 881 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_RDY_MASK 0x10 |
|---|
| 882 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_SHIFT 8 |
|---|
| 883 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_STS_CTL_STALL_MASK 0x100 |
|---|
| 884 | |
|---|
| 885 | /* DCORE0_EDMA0_QM_ARC_CQ_STS0 */ |
|---|
| 886 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_SHIFT 0 |
|---|
| 887 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_CREDIT_CNT_MASK 0xFF |
|---|
| 888 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_SHIFT 8 |
|---|
| 889 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_FREE_CNT_MASK 0xFF00 |
|---|
| 890 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_SHIFT 16 |
|---|
| 891 | #define DCORE0_EDMA0_QM_ARC_CQ_STS0_INFLIGHT_CNT_MASK 0xFF0000 |
|---|
| 892 | |
|---|
| 893 | /* DCORE0_EDMA0_QM_ARC_CQ_STS1 */ |
|---|
| 894 | #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_SHIFT 0 |
|---|
| 895 | #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUF_EMPTY_MASK 0x1 |
|---|
| 896 | #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_SHIFT 1 |
|---|
| 897 | #define DCORE0_EDMA0_QM_ARC_CQ_STS1_BUSY_MASK 0x2 |
|---|
| 898 | |
|---|
| 899 | /* DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS */ |
|---|
| 900 | #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_SHIFT 0 |
|---|
| 901 | #define DCORE0_EDMA0_QM_ARC_CQ_TSIZE_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 902 | |
|---|
| 903 | /* DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS */ |
|---|
| 904 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_SHIFT 0 |
|---|
| 905 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 906 | |
|---|
| 907 | /* DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS */ |
|---|
| 908 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_SHIFT 0 |
|---|
| 909 | #define DCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS_VAL_MASK 0xFFFFFFFF |
|---|
| 910 | |
|---|
| 911 | /* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI */ |
|---|
| 912 | #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_SHIFT 0 |
|---|
| 913 | #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 914 | |
|---|
| 915 | /* DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO */ |
|---|
| 916 | #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_SHIFT 0 |
|---|
| 917 | #define DCORE0_EDMA0_QM_CP_WR_ARC_ADDR_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 918 | |
|---|
| 919 | /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI */ |
|---|
| 920 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 |
|---|
| 921 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 922 | |
|---|
| 923 | /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO */ |
|---|
| 924 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 |
|---|
| 925 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 926 | |
|---|
| 927 | /* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI */ |
|---|
| 928 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 |
|---|
| 929 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 930 | |
|---|
| 931 | /* DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO */ |
|---|
| 932 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 |
|---|
| 933 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 934 | |
|---|
| 935 | /* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI */ |
|---|
| 936 | #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_SHIFT 0 |
|---|
| 937 | #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 938 | |
|---|
| 939 | /* DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO */ |
|---|
| 940 | #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_SHIFT 0 |
|---|
| 941 | #define DCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 942 | |
|---|
| 943 | /* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI */ |
|---|
| 944 | #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_SHIFT 0 |
|---|
| 945 | #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_HI_VAL_MASK 0xFFFFFFFF |
|---|
| 946 | |
|---|
| 947 | /* DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO */ |
|---|
| 948 | #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_SHIFT 0 |
|---|
| 949 | #define DCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO_VAL_MASK 0xFFFFFFFF |
|---|
| 950 | |
|---|
| 951 | /* DCORE0_EDMA0_QM_ADDR_OVRD */ |
|---|
| 952 | #define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_SHIFT 0 |
|---|
| 953 | #define DCORE0_EDMA0_QM_ADDR_OVRD_IDX_MASK 0xFF |
|---|
| 954 | |
|---|
| 955 | /* DCORE0_EDMA0_QM_CQ_IFIFO_CI */ |
|---|
| 956 | #define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_SHIFT 0 |
|---|
| 957 | #define DCORE0_EDMA0_QM_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF |
|---|
| 958 | |
|---|
| 959 | /* DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI */ |
|---|
| 960 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_SHIFT 0 |
|---|
| 961 | #define DCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI_VAL_MASK 0xFFFFFFFF |
|---|
| 962 | |
|---|
| 963 | /* DCORE0_EDMA0_QM_CQ_CTL_CI */ |
|---|
| 964 | #define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_SHIFT 0 |
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| 965 | #define DCORE0_EDMA0_QM_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF |
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| 966 | |
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| 967 | /* DCORE0_EDMA0_QM_ARC_CQ_CTL_CI */ |
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| 968 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_SHIFT 0 |
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| 969 | #define DCORE0_EDMA0_QM_ARC_CQ_CTL_CI_VAL_MASK 0xFFFFFFFF |
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| 970 | |
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| 971 | /* DCORE0_EDMA0_QM_CP_CFG */ |
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| 972 | #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_SHIFT 0 |
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| 973 | #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_EN_MASK 0x1 |
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| 974 | #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_SHIFT 1 |
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| 975 | #define DCORE0_EDMA0_QM_CP_CFG_SWITCH_WD_EN_MASK 0x2 |
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| 976 | |
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| 977 | /* DCORE0_EDMA0_QM_CP_EXT_SWITCH */ |
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| 978 | #define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_SHIFT 0 |
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| 979 | #define DCORE0_EDMA0_QM_CP_EXT_SWITCH_VAL_MASK 0x1 |
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| 980 | |
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| 981 | /* DCORE0_EDMA0_QM_CP_SWITCH_WD_SET */ |
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| 982 | #define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_SHIFT 0 |
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| 983 | #define DCORE0_EDMA0_QM_CP_SWITCH_WD_SET_VAL_MASK 0xFFFFFFFF |
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| 984 | |
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| 985 | /* DCORE0_EDMA0_QM_CP_SWITCH_WD */ |
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| 986 | #define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_SHIFT 0 |
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| 987 | #define DCORE0_EDMA0_QM_CP_SWITCH_WD_VAL_MASK 0xFFFFFFFF |
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| 988 | |
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| 989 | /* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO */ |
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| 990 | #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_SHIFT 0 |
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| 991 | #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_LO_VAL_MASK 0xFFFFFFFF |
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| 992 | |
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| 993 | /* DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI */ |
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| 994 | #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_SHIFT 0 |
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| 995 | #define DCORE0_EDMA0_QM_ARC_LB_ADDR_BASE_HI_VAL_MASK 0xFFFFFFFF |
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| 996 | |
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| 997 | /* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI */ |
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| 998 | #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_SHIFT 0 |
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| 999 | #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 1000 | |
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| 1001 | /* DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO */ |
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| 1002 | #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_SHIFT 0 |
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| 1003 | #define DCORE0_EDMA0_QM_ENGINE_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 1004 | |
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| 1005 | /* DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE */ |
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| 1006 | #define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_SHIFT 0 |
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| 1007 | #define DCORE0_EDMA0_QM_ENGINE_ADDR_RANGE_SIZE_VAL_MASK 0xFFFFFFFF |
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| 1008 | |
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| 1009 | /* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI */ |
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| 1010 | #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_SHIFT 0 |
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| 1011 | #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 1012 | |
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| 1013 | /* DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO */ |
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| 1014 | #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_SHIFT 0 |
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| 1015 | #define DCORE0_EDMA0_QM_QM_ARC_AUX_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 1016 | |
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| 1017 | /* DCORE0_EDMA0_QM_QM_BASE_ADDR_HI */ |
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| 1018 | #define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_SHIFT 0 |
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| 1019 | #define DCORE0_EDMA0_QM_QM_BASE_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 1020 | |
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| 1021 | /* DCORE0_EDMA0_QM_QM_BASE_ADDR_LO */ |
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| 1022 | #define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_SHIFT 0 |
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| 1023 | #define DCORE0_EDMA0_QM_QM_BASE_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 1024 | |
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| 1025 | /* DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND */ |
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| 1026 | #define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_SHIFT 0 |
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| 1027 | #define DCORE0_EDMA0_QM_ARC_PQC_SECURE_PUSH_IND_CP_NUM_MASK 0x3 |
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| 1028 | |
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| 1029 | /* DCORE0_EDMA0_QM_PQC_STS_0 */ |
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| 1030 | #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_SHIFT 0 |
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| 1031 | #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_DATA_MASK 0xFFFF |
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| 1032 | #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_SHIFT 16 |
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| 1033 | #define DCORE0_EDMA0_QM_PQC_STS_0_COMP_OFST_MASK 0xFFFF0000 |
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| 1034 | |
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| 1035 | /* DCORE0_EDMA0_QM_PQC_STS_1 */ |
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| 1036 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_SHIFT 0 |
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| 1037 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_CNTR_MASK 0xF |
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| 1038 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_SHIFT 4 |
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| 1039 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_EMPTY_MASK 0x10 |
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| 1040 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_SHIFT 5 |
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| 1041 | #define DCORE0_EDMA0_QM_PQC_STS_1_COMP_FIFO_FULL_MASK 0x20 |
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| 1042 | |
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| 1043 | /* DCORE0_EDMA0_QM_SEI_STATUS */ |
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| 1044 | #define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_SHIFT 0 |
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| 1045 | #define DCORE0_EDMA0_QM_SEI_STATUS_QM_INT_MASK 0x1 |
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| 1046 | #define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_SHIFT 1 |
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| 1047 | #define DCORE0_EDMA0_QM_SEI_STATUS_ARC_INT_MASK 0x2 |
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| 1048 | |
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| 1049 | /* DCORE0_EDMA0_QM_SEI_MASK */ |
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| 1050 | #define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_SHIFT 0 |
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| 1051 | #define DCORE0_EDMA0_QM_SEI_MASK_QM_INT_MASK 0x1 |
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| 1052 | #define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_SHIFT 1 |
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| 1053 | #define DCORE0_EDMA0_QM_SEI_MASK_ARC_INT_MASK 0x2 |
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| 1054 | |
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| 1055 | /* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO */ |
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| 1056 | #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_SHIFT 0 |
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| 1057 | #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_LO_VAL_MASK 0xFFFFFFFF |
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| 1058 | |
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| 1059 | /* DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI */ |
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| 1060 | #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_SHIFT 0 |
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| 1061 | #define DCORE0_EDMA0_QM_GLBL_ERR_ADDR_HI_VAL_MASK 0xFFFFFFFF |
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| 1062 | |
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| 1063 | /* DCORE0_EDMA0_QM_GLBL_ERR_WDATA */ |
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| 1064 | #define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_SHIFT 0 |
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| 1065 | #define DCORE0_EDMA0_QM_GLBL_ERR_WDATA_VAL_MASK 0xFFFFFFFF |
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| 1066 | |
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| 1067 | /* DCORE0_EDMA0_QM_L2H_MASK_LO */ |
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| 1068 | #define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_SHIFT 20 |
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| 1069 | #define DCORE0_EDMA0_QM_L2H_MASK_LO_VAL_MASK 0xFFF00000 |
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| 1070 | |
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| 1071 | /* DCORE0_EDMA0_QM_L2H_MASK_HI */ |
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| 1072 | #define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_SHIFT 0 |
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| 1073 | #define DCORE0_EDMA0_QM_L2H_MASK_HI_VAL_MASK 0xFFFFFFFF |
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| 1074 | |
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| 1075 | /* DCORE0_EDMA0_QM_L2H_CMPR_LO */ |
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| 1076 | #define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_SHIFT 20 |
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| 1077 | #define DCORE0_EDMA0_QM_L2H_CMPR_LO_VAL_MASK 0xFFF00000 |
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| 1078 | |
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| 1079 | /* DCORE0_EDMA0_QM_L2H_CMPR_HI */ |
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| 1080 | #define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_SHIFT 0 |
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| 1081 | #define DCORE0_EDMA0_QM_L2H_CMPR_HI_VAL_MASK 0xFFFFFFFF |
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| 1082 | |
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| 1083 | /* DCORE0_EDMA0_QM_LOCAL_RANGE_BASE */ |
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| 1084 | #define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_SHIFT 0 |
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| 1085 | #define DCORE0_EDMA0_QM_LOCAL_RANGE_BASE_VAL_MASK 0xFFFF |
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| 1086 | |
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| 1087 | /* DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE */ |
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| 1088 | #define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_SHIFT 0 |
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| 1089 | #define DCORE0_EDMA0_QM_LOCAL_RANGE_SIZE_VAL_MASK 0xFFFF |
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| 1090 | |
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| 1091 | /* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1 */ |
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| 1092 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_SHIFT 0 |
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| 1093 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_TOUT_MASK 0xFF |
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| 1094 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_SHIFT 31 |
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| 1095 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_1_EN_MASK 0x80000000 |
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| 1096 | |
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| 1097 | /* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0 */ |
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| 1098 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 |
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| 1099 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF |
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| 1100 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_SHIFT 16 |
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| 1101 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 |
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| 1102 | |
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| 1103 | /* DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1 */ |
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| 1104 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_SHIFT 0 |
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| 1105 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_TOUT_MASK 0xFF |
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| 1106 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_SHIFT 31 |
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| 1107 | #define DCORE0_EDMA0_QM_LBW_WR_RATE_LIM_CFG_1_EN_MASK 0x80000000 |
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| 1108 | |
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| 1109 | /* DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0 */ |
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| 1110 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_SHIFT 0 |
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| 1111 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_RST_TOKEN_MASK 0xFF |
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| 1112 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_SHIFT 16 |
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| 1113 | #define DCORE0_EDMA0_QM_HBW_RD_RATE_LIM_CFG_0_SAT_MASK 0xFF0000 |
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| 1114 | |
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| 1115 | /* DCORE0_EDMA0_QM_IND_GW_APB_CFG */ |
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| 1116 | #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_SHIFT 0 |
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| 1117 | #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_ADDR_MASK 0x7FFFFFFF |
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| 1118 | #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_SHIFT 31 |
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| 1119 | #define DCORE0_EDMA0_QM_IND_GW_APB_CFG_CMD_MASK 0x80000000 |
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| 1120 | |
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| 1121 | /* DCORE0_EDMA0_QM_IND_GW_APB_WDATA */ |
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| 1122 | #define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_SHIFT 0 |
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| 1123 | #define DCORE0_EDMA0_QM_IND_GW_APB_WDATA_VAL_MASK 0xFFFFFFFF |
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| 1124 | |
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| 1125 | /* DCORE0_EDMA0_QM_IND_GW_APB_RDATA */ |
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| 1126 | #define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_SHIFT 0 |
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| 1127 | #define DCORE0_EDMA0_QM_IND_GW_APB_RDATA_VAL_MASK 0xFFFFFFFF |
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| 1128 | |
|---|
| 1129 | /* DCORE0_EDMA0_QM_IND_GW_APB_STATUS */ |
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| 1130 | #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_SHIFT 0 |
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| 1131 | #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_RDY_MASK 0x1 |
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| 1132 | #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_SHIFT 1 |
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| 1133 | #define DCORE0_EDMA0_QM_IND_GW_APB_STATUS_ERR_MASK 0x2 |
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| 1134 | |
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| 1135 | /* DCORE0_EDMA0_QM_PERF_CNT_FREE_LO */ |
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| 1136 | #define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_SHIFT 0 |
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| 1137 | #define DCORE0_EDMA0_QM_PERF_CNT_FREE_LO_VAL_MASK 0xFFFFFFFF |
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| 1138 | |
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| 1139 | /* DCORE0_EDMA0_QM_PERF_CNT_FREE_HI */ |
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| 1140 | #define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_SHIFT 0 |
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| 1141 | #define DCORE0_EDMA0_QM_PERF_CNT_FREE_HI_VAL_MASK 0xFFFFFFFF |
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| 1142 | |
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| 1143 | /* DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO */ |
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| 1144 | #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_SHIFT 0 |
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| 1145 | #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_LO_VAL_MASK 0xFFFFFFFF |
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| 1146 | |
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| 1147 | /* DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI */ |
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| 1148 | #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_SHIFT 0 |
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| 1149 | #define DCORE0_EDMA0_QM_PERF_CNT_IDLE_HI_VAL_MASK 0xFFFFFFFF |
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| 1150 | |
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| 1151 | /* DCORE0_EDMA0_QM_PERF_CNT_CFG */ |
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| 1152 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_SHIFT 0 |
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| 1153 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_PQ_MASK_MASK 0xF |
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| 1154 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_SHIFT 8 |
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| 1155 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CQ_MASK_MASK 0x1F00 |
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| 1156 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_SHIFT 16 |
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| 1157 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_CP_MASK_MASK 0x1F0000 |
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| 1158 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_SHIFT 24 |
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| 1159 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_AGENT_MASK_MASK 0x1000000 |
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| 1160 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_SHIFT 30 |
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| 1161 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_FREE_MASK 0x40000000 |
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| 1162 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_SHIFT 31 |
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| 1163 | #define DCORE0_EDMA0_QM_PERF_CNT_CFG_EN_IDLE_MASK 0x80000000 |
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| 1164 | |
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| 1165 | #endif /* ASIC_REG_DCORE0_EDMA0_QM_MASKS_H_ */ |
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| 1166 | |
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