| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ |
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| 14 | #define ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_HMMU0_STLB |
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| 19 | * (Prototype: STLB) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | /* DCORE0_HMMU0_STLB_BUSY */ |
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| 24 | #define DCORE0_HMMU0_STLB_BUSY_BUSY_SHIFT 0 |
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| 25 | #define DCORE0_HMMU0_STLB_BUSY_BUSY_MASK 0xFFFFFFFF |
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| 26 | |
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| 27 | /* DCORE0_HMMU0_STLB_ASID */ |
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| 28 | #define DCORE0_HMMU0_STLB_ASID_ASID_SHIFT 0 |
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| 29 | #define DCORE0_HMMU0_STLB_ASID_ASID_MASK 0x3FF |
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| 30 | |
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| 31 | /* DCORE0_HMMU0_STLB_HOP0_PA43_12 */ |
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| 32 | #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_SHIFT 0 |
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| 33 | #define DCORE0_HMMU0_STLB_HOP0_PA43_12_HOP0_PA43_12_MASK 0xFFFFFFFF |
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| 34 | |
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| 35 | /* DCORE0_HMMU0_STLB_HOP0_PA63_44 */ |
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| 36 | #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_SHIFT 0 |
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| 37 | #define DCORE0_HMMU0_STLB_HOP0_PA63_44_HOP0_PA63_44_MASK 0xFFFFF |
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| 38 | |
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| 39 | /* DCORE0_HMMU0_STLB_CACHE_INV */ |
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| 40 | #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_SHIFT 0 |
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| 41 | #define DCORE0_HMMU0_STLB_CACHE_INV_PRODUCER_INDEX_MASK 0xFF |
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| 42 | #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_SHIFT 8 |
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| 43 | #define DCORE0_HMMU0_STLB_CACHE_INV_INDEX_MASK_MASK 0xFF00 |
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| 44 | |
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| 45 | /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8 */ |
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| 46 | #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_SHIFT 0 |
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| 47 | #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_39_8_PA_MASK 0xFFFFFFFF |
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| 48 | |
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| 49 | /* DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40 */ |
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| 50 | #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_SHIFT 0 |
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| 51 | #define DCORE0_HMMU0_STLB_CACHE_INV_BASE_63_40_PA_MASK 0xFFFFFF |
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| 52 | |
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| 53 | /* DCORE0_HMMU0_STLB_STLB_FEATURE_EN */ |
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| 54 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_SHIFT 0 |
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| 55 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_STLB_CTRL_MULTI_PAGE_SIZE_EN_MASK 0x1 |
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| 56 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_SHIFT 1 |
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| 57 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_MULTI_PAGE_SIZE_EN_MASK 0x2 |
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| 58 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_SHIFT 2 |
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| 59 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_LOOKUP_EN_MASK 0x4 |
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| 60 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_SHIFT 3 |
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| 61 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BYPASS_MASK 0x8 |
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| 62 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_SHIFT 4 |
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| 63 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_BANK_STOP_MASK 0x10 |
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| 64 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_SHIFT 5 |
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| 65 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_TRACE_EN_MASK 0x20 |
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| 66 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_SHIFT 6 |
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| 67 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWER_EN_MASK 0x40 |
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| 68 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_SHIFT 7 |
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| 69 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_CACHING_EN_MASK 0x1F80 |
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| 70 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_SHIFT 13 |
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| 71 | #define DCORE0_HMMU0_STLB_STLB_FEATURE_EN_FOLLOWING_NUM_LIMIT_MASK 0xE000 |
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| 72 | |
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| 73 | /* DCORE0_HMMU0_STLB_STLB_AXI_CACHE */ |
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| 74 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_SHIFT 0 |
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| 75 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_ARCACHE_MASK 0xF |
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| 76 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_SHIFT 4 |
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| 77 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_STLB_CTRL_AWCACHE_MASK 0xF0 |
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| 78 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_SHIFT 8 |
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| 79 | #define DCORE0_HMMU0_STLB_STLB_AXI_CACHE_INV_ARCACHE_MASK 0xF00 |
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| 80 | |
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| 81 | /* DCORE0_HMMU0_STLB_HOP_CONFIGURATION */ |
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| 82 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_SHIFT 0 |
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| 83 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_HOP_MASK 0x7 |
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| 84 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_SHIFT 4 |
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| 85 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_SMALL_P_MASK 0x70 |
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| 86 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_SHIFT 8 |
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| 87 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FIRST_LOOKUP_HOP_LARGE_P_MASK 0x700 |
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| 88 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_SHIFT 12 |
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| 89 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LAST_HOP_MASK 0x7000 |
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| 90 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_SHIFT 16 |
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| 91 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_FOLLOWER_HOP_MASK 0x70000 |
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| 92 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_SHIFT 20 |
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| 93 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK 0x100000 |
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| 94 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_SHIFT 21 |
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| 95 | #define DCORE0_HMMU0_STLB_HOP_CONFIGURATION_LARGE_PAGE_INDICATION_BIT_MASK 0x7E00000 |
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| 96 | |
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| 97 | /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32 */ |
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| 98 | #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_SHIFT 0 |
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| 99 | #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_63_32_R_MASK 0xFFFFFFFF |
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| 100 | |
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| 101 | /* DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0 */ |
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| 102 | #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_SHIFT 0 |
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| 103 | #define DCORE0_HMMU0_STLB_LINK_LIST_LOOKUP_MASK_31_0_R_MASK 0xFFFFFFFF |
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| 104 | |
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| 105 | /* DCORE0_HMMU0_STLB_INV_ALL_START */ |
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| 106 | #define DCORE0_HMMU0_STLB_INV_ALL_START_R_SHIFT 0 |
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| 107 | #define DCORE0_HMMU0_STLB_INV_ALL_START_R_MASK 0x1 |
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| 108 | |
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| 109 | /* DCORE0_HMMU0_STLB_INV_ALL_SET */ |
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| 110 | #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_SHIFT 0 |
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| 111 | #define DCORE0_HMMU0_STLB_INV_ALL_SET_R_MASK 0xFF |
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| 112 | |
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| 113 | /* DCORE0_HMMU0_STLB_INV_PS */ |
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| 114 | #define DCORE0_HMMU0_STLB_INV_PS_R_SHIFT 0 |
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| 115 | #define DCORE0_HMMU0_STLB_INV_PS_R_MASK 0x3 |
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| 116 | |
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| 117 | /* DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX */ |
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| 118 | #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_SHIFT 0 |
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| 119 | #define DCORE0_HMMU0_STLB_INV_CONSUMER_INDEX_R_MASK 0xFF |
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| 120 | |
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| 121 | /* DCORE0_HMMU0_STLB_INV_HIT_COUNT */ |
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| 122 | #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_SHIFT 0 |
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| 123 | #define DCORE0_HMMU0_STLB_INV_HIT_COUNT_R_MASK 0x7FF |
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| 124 | |
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| 125 | /* DCORE0_HMMU0_STLB_INV_SET */ |
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| 126 | #define DCORE0_HMMU0_STLB_INV_SET_R_SHIFT 0 |
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| 127 | #define DCORE0_HMMU0_STLB_INV_SET_R_MASK 0xFF |
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| 128 | |
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| 129 | /* DCORE0_HMMU0_STLB_SRAM_INIT */ |
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| 130 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_SHIFT 0 |
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| 131 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_TAG_MASK 0x3 |
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| 132 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_SHIFT 2 |
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| 133 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_SLICE_MASK 0xC |
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| 134 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_SHIFT 4 |
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| 135 | #define DCORE0_HMMU0_STLB_SRAM_INIT_BUSY_DATA_MASK 0x10 |
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| 136 | |
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| 137 | /* DCORE0_HMMU0_STLB_MEM_CACHE_INVALIDATION */ |
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| 138 | |
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| 139 | /* DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS */ |
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| 140 | #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_SHIFT 0 |
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| 141 | #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_INVALIDATE_DONE_MASK 0x1 |
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| 142 | #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_SHIFT 1 |
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| 143 | #define DCORE0_HMMU0_STLB_MEM_CACHE_INV_STATUS_CACHE_IDLE_MASK 0x2 |
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| 144 | |
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| 145 | /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7 */ |
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| 146 | #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_SHIFT 0 |
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| 147 | #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_38_7_R_MASK 0xFFFFFFFF |
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| 148 | |
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| 149 | /* DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39 */ |
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| 150 | #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_SHIFT 0 |
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| 151 | #define DCORE0_HMMU0_STLB_MEM_CACHE_BASE_63_39_R_MASK 0x1FFFFFF |
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| 152 | |
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| 153 | /* DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG */ |
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| 154 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_SHIFT 0 |
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| 155 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_EN_MASK 0x3F |
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| 156 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_SHIFT 6 |
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| 157 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_CACHE_HOP_PREFETCH_EN_MASK 0xFC0 |
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| 158 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_SHIFT 12 |
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| 159 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_BYPASS_EN_MASK 0x1000 |
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| 160 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_SHIFT 13 |
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| 161 | #define DCORE0_HMMU0_STLB_MEM_CACHE_CONFIG_RELEASE_INVALIDATE_MASK 0x2000 |
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| 162 | |
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| 163 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5 */ |
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| 164 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_SHIFT 0 |
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| 165 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MIN_MASK 0x1FF |
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| 166 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_SHIFT 9 |
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| 167 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MAX_MASK 0x3FE00 |
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| 168 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_SHIFT 18 |
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| 169 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP5_MASK_MASK 0x7FC0000 |
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| 170 | |
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| 171 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4 */ |
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| 172 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_SHIFT 0 |
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| 173 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MIN_MASK 0x1FF |
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| 174 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_SHIFT 9 |
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| 175 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MAX_MASK 0x3FE00 |
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| 176 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_SHIFT 18 |
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| 177 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP4_MASK_MASK 0x7FC0000 |
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| 178 | |
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| 179 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3 */ |
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| 180 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_SHIFT 0 |
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| 181 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MIN_MASK 0x1FF |
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| 182 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_SHIFT 9 |
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| 183 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MAX_MASK 0x3FE00 |
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| 184 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_SHIFT 18 |
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| 185 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP3_MASK_MASK 0x7FC0000 |
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| 186 | |
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| 187 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2 */ |
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| 188 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_SHIFT 0 |
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| 189 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MIN_MASK 0x1FF |
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| 190 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_SHIFT 9 |
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| 191 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MAX_MASK 0x3FE00 |
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| 192 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_SHIFT 18 |
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| 193 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP2_MASK_MASK 0x7FC0000 |
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| 194 | |
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| 195 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1 */ |
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| 196 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_SHIFT 0 |
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| 197 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MIN_MASK 0x1FF |
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| 198 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_SHIFT 9 |
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| 199 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MAX_MASK 0x3FE00 |
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| 200 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_SHIFT 18 |
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| 201 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP1_MASK_MASK 0x7FC0000 |
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| 202 | |
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| 203 | /* DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0 */ |
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| 204 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_SHIFT 0 |
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| 205 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MIN_MASK 0x1FF |
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| 206 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_SHIFT 9 |
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| 207 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MAX_MASK 0x3FE00 |
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| 208 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_SHIFT 18 |
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| 209 | #define DCORE0_HMMU0_STLB_SET_THRESHOLD_HOP0_MASK_MASK 0x7FC0000 |
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| 210 | |
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| 211 | /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_CLR */ |
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| 212 | |
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| 213 | /* DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK */ |
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| 214 | #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_SHIFT 0 |
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| 215 | #define DCORE0_HMMU0_STLB_MULTI_HIT_INTERRUPT_MASK_R_MASK 0x1 |
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| 216 | |
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| 217 | /* DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG */ |
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| 218 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_SHIFT 0 |
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| 219 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_PLRU_EVICTION_MASK 0x1 |
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| 220 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_SHIFT 1 |
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| 221 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_CACHE_STOP_MASK 0x2 |
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| 222 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_SHIFT 2 |
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| 223 | #define DCORE0_HMMU0_STLB_MEM_L0_CACHE_CFG_INV_WRITEBACK_MASK 0x4 |
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| 224 | |
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| 225 | /* DCORE0_HMMU0_STLB_MEM_READ_ARPROT */ |
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| 226 | #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_SHIFT 0 |
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| 227 | #define DCORE0_HMMU0_STLB_MEM_READ_ARPROT_R_MASK 0x7 |
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| 228 | |
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| 229 | /* DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION */ |
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| 230 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_SHIFT 0 |
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| 231 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_RANGE_INVALIDATION_ENABLE_MASK 0x1 |
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| 232 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_SHIFT 1 |
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| 233 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_EN_MASK 0x2 |
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| 234 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_SHIFT 2 |
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| 235 | #define DCORE0_HMMU0_STLB_RANGE_CACHE_INVALIDATION_INVALIDATION_ASID_MASK 0xFFC |
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| 236 | |
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| 237 | /* DCORE0_HMMU0_STLB_RANGE_INV_START_LSB */ |
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| 238 | #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_SHIFT 0 |
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| 239 | #define DCORE0_HMMU0_STLB_RANGE_INV_START_LSB_INV_START_LSB_MASK 0xFFFFFFFF |
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| 240 | |
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| 241 | /* DCORE0_HMMU0_STLB_RANGE_INV_START_MSB */ |
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| 242 | #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_SHIFT 0 |
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| 243 | #define DCORE0_HMMU0_STLB_RANGE_INV_START_MSB_INV_START_MSB_MASK 0xFFFFF |
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| 244 | |
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| 245 | /* DCORE0_HMMU0_STLB_RANGE_INV_END_LSB */ |
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| 246 | #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_SHIFT 0 |
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| 247 | #define DCORE0_HMMU0_STLB_RANGE_INV_END_LSB_INV_END_LSB_MASK 0xFFFFFFFF |
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| 248 | |
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| 249 | /* DCORE0_HMMU0_STLB_RANGE_INV_END_MSB */ |
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| 250 | #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_SHIFT 0 |
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| 251 | #define DCORE0_HMMU0_STLB_RANGE_INV_END_MSB_INV_END_MSB_MASK 0xFFFFF |
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| 252 | |
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| 253 | /* DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL */ |
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| 254 | #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_SHIFT 0 |
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| 255 | #define DCORE0_HMMU0_STLB_ASID_SCRAMBLER_CTRL_SCRAMBLER_SCRAM_EN_MASK 0x1 |
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| 256 | |
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| 257 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0 */ |
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| 258 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 259 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_0_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 260 | |
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| 261 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1 */ |
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| 262 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 263 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_1_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 264 | |
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| 265 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2 */ |
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| 266 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 267 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_2_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 268 | |
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| 269 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3 */ |
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| 270 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 271 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_3_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 272 | |
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| 273 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4 */ |
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| 274 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 275 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_4_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 276 | |
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| 277 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5 */ |
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| 278 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 279 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_5_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 280 | |
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| 281 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6 */ |
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| 282 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 283 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_6_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 284 | |
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| 285 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7 */ |
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| 286 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 287 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_7_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 288 | |
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| 289 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8 */ |
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| 290 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 291 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_8_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 292 | |
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| 293 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9 */ |
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| 294 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 295 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MATRIX_H3_9_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 296 | |
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| 297 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10 */ |
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| 298 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 299 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_10_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 300 | |
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| 301 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11 */ |
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| 302 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 303 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_11_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 304 | |
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| 305 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12 */ |
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| 306 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 307 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_12_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 308 | |
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| 309 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13 */ |
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| 310 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 311 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_13_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 312 | |
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| 313 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14 */ |
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| 314 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 315 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_14_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 316 | |
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| 317 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15 */ |
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| 318 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 319 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_15_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 320 | |
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| 321 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16 */ |
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| 322 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 323 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_16_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 324 | |
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| 325 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17 */ |
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| 326 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 327 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_17_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 328 | |
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| 329 | /* DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18 */ |
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| 330 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_SHIFT 0 |
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| 331 | #define DCORE0_HMMU0_STLB_ASID_SCR_POLY_MAT_H3_18_ASID_POLY_MATRIX_H3_MASK 0x1FF |
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| 332 | |
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| 333 | #endif /* ASIC_REG_DCORE0_HMMU0_STLB_MASKS_H_ */ |
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| 334 | |
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