| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ |
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| 14 | #define ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_MME_CTRL_LO |
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| 19 | * (Prototype: MME_CTRL_LO) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | /* DCORE0_MME_CTRL_LO_ARCH_STATUS */ |
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| 24 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_SHIFT 0 |
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| 25 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_IN_MASK 0x1F |
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| 26 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_SHIFT 5 |
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| 27 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_EU_MASK 0x20 |
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| 28 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_SHIFT 6 |
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| 29 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AP_MASK 0x40 |
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| 30 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SHIFT 7 |
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| 31 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_MASK 0x180 |
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| 32 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_SHIFT 9 |
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| 33 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK 0x3E00 |
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| 34 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_SHIFT 14 |
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| 35 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK 0xC000 |
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| 36 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_SHIFT 16 |
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| 37 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK 0x30000 |
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| 38 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_SHIFT 18 |
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| 39 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK 0x7C0000 |
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| 40 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_SHIFT 23 |
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| 41 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_ACCUM_FREE_MASK 0x3800000 |
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| 42 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_SHIFT 30 |
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| 43 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK 0x40000000 |
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| 44 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_SHIFT 31 |
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| 45 | #define DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK 0x80000000 |
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| 46 | |
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| 47 | /* DCORE0_MME_CTRL_LO_CMD */ |
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| 48 | #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_SHIFT 0 |
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| 49 | #define DCORE0_MME_CTRL_LO_CMD_AGU_IN_MASK 0x1F |
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| 50 | #define DCORE0_MME_CTRL_LO_CMD_EU_SHIFT 5 |
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| 51 | #define DCORE0_MME_CTRL_LO_CMD_EU_MASK 0x20 |
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| 52 | #define DCORE0_MME_CTRL_LO_CMD_AP_SHIFT 6 |
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| 53 | #define DCORE0_MME_CTRL_LO_CMD_AP_MASK 0x40 |
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| 54 | #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_SHIFT 7 |
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| 55 | #define DCORE0_MME_CTRL_LO_CMD_AGU_COUT_MASK 0x180 |
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| 56 | #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_SHIFT 9 |
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| 57 | #define DCORE0_MME_CTRL_LO_CMD_COPY_AND_INC_MASK 0x200 |
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| 58 | #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_SHIFT 10 |
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| 59 | #define DCORE0_MME_CTRL_LO_CMD_DESC_SEL_MASK 0xC00 |
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| 60 | #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_SHIFT 12 |
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| 61 | #define DCORE0_MME_CTRL_LO_CMD_MASK_IDLE_IND_MASK 0x1000 |
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| 62 | #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_SHIFT 13 |
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| 63 | #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW0_MASK 0x2000 |
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| 64 | #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_SHIFT 14 |
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| 65 | #define DCORE0_MME_CTRL_LO_CMD_AGU_OUT1_FROM_AGU0_DW1_4_MASK 0x4000 |
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| 66 | #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_SHIFT 15 |
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| 67 | #define DCORE0_MME_CTRL_LO_CMD_NULL_DESC_MASK 0x8000 |
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| 68 | |
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| 69 | /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 */ |
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| 70 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_SHIFT 0 |
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| 71 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK0_MASK 0x3F |
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| 72 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_SHIFT 6 |
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| 73 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN0_MASK 0x40 |
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| 74 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_SHIFT 8 |
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| 75 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_MASK1_MASK 0x3F00 |
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| 76 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_SHIFT 14 |
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| 77 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SIGNAL_EN1_MASK 0x4000 |
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| 78 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_SHIFT 15 |
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| 79 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_MASTER_WAIT_SLAVE_FENCE_MASK 0x8000 |
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| 80 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_SHIFT 16 |
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| 81 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SEND_FENCE2MASTER_MASK 0x10000 |
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| 82 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_SHIFT 17 |
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| 83 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE_SIGNAL_EN_MASK 0x20000 |
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| 84 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_SHIFT 18 |
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| 85 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_SLV_ADR_MASK 0x40000 |
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| 86 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_SHIFT 19 |
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| 87 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_SLV_ADR_MASK 0x80000 |
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| 88 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_SHIFT 20 |
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| 89 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE0_USE_MSTR_ADR_PLUS4_MASK 0x100000 |
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| 90 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_SHIFT 21 |
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| 91 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0_SLAVE1_USE_MSTR_ADR_PLUS4_MASK 0x200000 |
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| 92 | |
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| 93 | /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 */ |
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| 94 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_SHIFT 0 |
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| 95 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0_V_MASK 0xFFFFFFFF |
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| 96 | |
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| 97 | /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 */ |
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| 98 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_SHIFT 0 |
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| 99 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_VALUE_MASK 0x7FFF |
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| 100 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_SHIFT 15 |
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| 101 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_RESERVED_MASK 0x3FFF8000 |
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| 102 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_SHIFT 30 |
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| 103 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_PERF_EN_MASK 0x40000000 |
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| 104 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_SHIFT 31 |
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| 105 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0_SO_OP_MASK 0x80000000 |
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| 106 | |
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| 107 | /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 */ |
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| 108 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_SHIFT 0 |
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| 109 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1_V_MASK 0xFFFFFFFF |
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| 110 | |
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| 111 | /* DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 */ |
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| 112 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_SHIFT 0 |
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| 113 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_VALUE_MASK 0x7FFF |
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| 114 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_SHIFT 15 |
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| 115 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_RESERVED_MASK 0x3FFF8000 |
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| 116 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_SHIFT 30 |
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| 117 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_PERF_EN_MASK 0x40000000 |
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| 118 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_SHIFT 31 |
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| 119 | #define DCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1_SO_OP_MASK 0x80000000 |
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| 120 | |
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| 121 | /* DCORE0_MME_CTRL_LO_ARCH_A_SS */ |
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| 122 | #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_SHIFT 0 |
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| 123 | #define DCORE0_MME_CTRL_LO_ARCH_A_SS_MINUS_1_MASK 0xFFFFFFFF |
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| 124 | |
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| 125 | /* DCORE0_MME_CTRL_LO_ARCH_B_SS */ |
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| 126 | #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_SHIFT 0 |
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| 127 | #define DCORE0_MME_CTRL_LO_ARCH_B_SS_MINUS_1_MASK 0xFFFFFFFF |
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| 128 | |
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| 129 | /* DCORE0_MME_CTRL_LO_ARCH_COUT_SS */ |
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| 130 | #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_SHIFT 0 |
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| 131 | #define DCORE0_MME_CTRL_LO_ARCH_COUT_SS_MINUS_1_MASK 0xFFFFFFFF |
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| 132 | |
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| 133 | /* DCORE0_MME_CTRL_LO_QM_STALL */ |
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| 134 | #define DCORE0_MME_CTRL_LO_QM_STALL_V_SHIFT 0 |
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| 135 | #define DCORE0_MME_CTRL_LO_QM_STALL_V_MASK 0x1 |
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| 136 | |
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| 137 | /* DCORE0_MME_CTRL_LO_LOG_SHADOW_LO */ |
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| 138 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_SHIFT 0 |
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| 139 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_0_MASK 0x1FF |
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| 140 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_SHIFT 9 |
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| 141 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_LO_MASK_1_MASK 0x3FE00 |
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| 142 | |
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| 143 | /* DCORE0_MME_CTRL_LO_LOG_SHADOW_HI */ |
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| 144 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_SHIFT 0 |
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| 145 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_2_MASK 0x1FF |
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| 146 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_SHIFT 9 |
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| 147 | #define DCORE0_MME_CTRL_LO_LOG_SHADOW_HI_MASK_3_MASK 0x3FE00 |
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| 148 | |
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| 149 | /* DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH */ |
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| 150 | #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_SHIFT 0 |
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| 151 | #define DCORE0_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH_V_MASK 0x1F |
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| 152 | |
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| 153 | /* DCORE0_MME_CTRL_LO_REDUN */ |
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| 154 | #define DCORE0_MME_CTRL_LO_REDUN_FMA_SHIFT 0 |
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| 155 | #define DCORE0_MME_CTRL_LO_REDUN_FMA_MASK 0x3F |
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| 156 | |
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| 157 | /* DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH */ |
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| 158 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_SHIFT 0 |
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| 159 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO0_MASK 0x1F |
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| 160 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_SHIFT 5 |
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| 161 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO1_MASK 0x3E0 |
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| 162 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_SHIFT 10 |
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| 163 | #define DCORE0_MME_CTRL_LO_EUS_LOCAL_FIFO_TH_FIFO2_MASK 0x7C00 |
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| 164 | |
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| 165 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 */ |
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| 166 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_SHIFT 0 |
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| 167 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_MASK 0xFF |
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| 168 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_SHIFT 8 |
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| 169 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE0_MASK 0x1F00 |
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| 170 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_SHIFT 13 |
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| 171 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE1_MASK 0x3E000 |
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| 172 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_SHIFT 18 |
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| 173 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE2_MASK 0x7C0000 |
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| 174 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_SHIFT 23 |
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| 175 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0_FP_PE3_MASK 0xF800000 |
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| 176 | |
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| 177 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 */ |
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| 178 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_SHIFT 0 |
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| 179 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE4_MASK 0x1F |
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| 180 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_SHIFT 5 |
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| 181 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1_FP_PE_HI_MASK 0x3E0 |
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| 182 | |
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| 183 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 */ |
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| 184 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_SHIFT 0 |
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| 185 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_DLY_MASK 0xFFF |
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| 186 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_SHIFT 31 |
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| 187 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16_EN_MASK 0x80000000 |
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| 188 | |
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| 189 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 */ |
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| 190 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_SHIFT 0 |
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| 191 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_DLY_MASK 0xFFF |
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| 192 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_SHIFT 31 |
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| 193 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8_EN_MASK 0x80000000 |
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| 194 | |
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| 195 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 */ |
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| 196 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_SHIFT 0 |
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| 197 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_DLY_MASK 0xFFF |
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| 198 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_SHIFT 31 |
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| 199 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32_EN_MASK 0x80000000 |
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| 200 | |
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| 201 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I */ |
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| 202 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_SHIFT 0 |
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| 203 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_DLY_MASK 0xFFF |
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| 204 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_SHIFT 31 |
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| 205 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I_EN_MASK 0x80000000 |
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| 206 | |
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| 207 | /* DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 */ |
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| 208 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_SHIFT 0 |
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| 209 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_DLY_MASK 0xFFF |
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| 210 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_SHIFT 31 |
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| 211 | #define DCORE0_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32_EN_MASK 0x80000000 |
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| 212 | |
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| 213 | /* DCORE0_MME_CTRL_LO_PCU_RL_DESC0 */ |
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| 214 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_SHIFT 0 |
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| 215 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_RST_TOKEN_MASK 0xFFFF |
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| 216 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_SHIFT 16 |
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| 217 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_TIMEOUT_MASK 0xFF0000 |
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| 218 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_SHIFT 24 |
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| 219 | #define DCORE0_MME_CTRL_LO_PCU_RL_DESC0_RL_DUMMY2REAL_PERIOD_MASK 0xFF000000 |
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| 220 | |
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| 221 | /* DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE */ |
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| 222 | #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_SHIFT 0 |
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| 223 | #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_INC_VAL_MASK 0xFFFF |
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| 224 | #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_SHIFT 16 |
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| 225 | #define DCORE0_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE_DEC_VAL_MASK 0xFFFF0000 |
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| 226 | |
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| 227 | /* DCORE0_MME_CTRL_LO_PCU_RL_TH */ |
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| 228 | #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_SHIFT 0 |
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| 229 | #define DCORE0_MME_CTRL_LO_PCU_RL_TH_POOL_TH_DEC_MASK 0xFFFF |
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| 230 | #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_SHIFT 16 |
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| 231 | #define DCORE0_MME_CTRL_LO_PCU_RL_TH_DUMMY_REAL_DIFF_TH_MASK 0xFFFF0000 |
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| 232 | |
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| 233 | /* DCORE0_MME_CTRL_LO_PCU_RL_MIN */ |
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| 234 | #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_SHIFT 0 |
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| 235 | #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_AVG_MIN_TO_FORCE_DUMMY_MASK 0xFFFF |
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| 236 | #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_SHIFT 16 |
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| 237 | #define DCORE0_MME_CTRL_LO_PCU_RL_MIN_TOKEN_MIN_VAL_MASK 0xFFFF0000 |
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| 238 | |
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| 239 | /* DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN */ |
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| 240 | #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_SHIFT 0 |
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| 241 | #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_PCU_DISABLE_MASK 0x1 |
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| 242 | #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_SHIFT 1 |
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| 243 | #define DCORE0_MME_CTRL_LO_PCU_RL_CTRL_EN_MIN_VAL_PROT_EN_MASK 0x2 |
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| 244 | |
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| 245 | /* DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE */ |
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| 246 | #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_SHIFT 0 |
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| 247 | #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_ALL_MACS_MASK 0x7 |
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| 248 | #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_SHIFT 3 |
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| 249 | #define DCORE0_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE_REAL_MACS_MASK 0x18 |
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| 250 | |
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| 251 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16 */ |
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| 252 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_SHIFT 0 |
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| 253 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_ODD_MASK 0xFFFF |
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| 254 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_SHIFT 16 |
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| 255 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_BF16_EVEN_MASK 0xFFFF0000 |
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| 256 | |
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| 257 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16 */ |
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| 258 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_SHIFT 0 |
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| 259 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_ODD_MASK 0xFFFF |
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| 260 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_SHIFT 16 |
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| 261 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_BF16_EVEN_MASK 0xFFFF0000 |
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| 262 | |
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| 263 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16 */ |
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| 264 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_SHIFT 0 |
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| 265 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_ODD_MASK 0xFFFF |
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| 266 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_SHIFT 16 |
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| 267 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP16_EVEN_MASK 0xFFFF0000 |
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| 268 | |
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| 269 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16 */ |
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| 270 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_SHIFT 0 |
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| 271 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_ODD_MASK 0xFFFF |
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| 272 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_SHIFT 16 |
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| 273 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP16_EVEN_MASK 0xFFFF0000 |
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| 274 | |
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| 275 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_F8 */ |
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| 276 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_SHIFT 0 |
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| 277 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_ODD_MASK 0xFF |
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| 278 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_SHIFT 8 |
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| 279 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_A_VAL_EVEN_MASK 0xFF00 |
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| 280 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_SHIFT 16 |
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| 281 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_ODD_MASK 0xFF0000 |
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| 282 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_SHIFT 24 |
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| 283 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_F8_B_VAL_EVEN_MASK 0xFF000000 |
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| 284 | |
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| 285 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD */ |
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| 286 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_SHIFT 0 |
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| 287 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD_V_MASK 0xFFFFFFFF |
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| 288 | |
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| 289 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN */ |
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| 290 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_SHIFT 0 |
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| 291 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN_V_MASK 0xFFFFFFFF |
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| 292 | |
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| 293 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD */ |
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| 294 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_SHIFT 0 |
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| 295 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD_V_MASK 0xFFFFFFFF |
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| 296 | |
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| 297 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN */ |
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| 298 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_SHIFT 0 |
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| 299 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN_V_MASK 0xFFFFFFFF |
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| 300 | |
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| 301 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD */ |
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| 302 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_SHIFT 0 |
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| 303 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD_V_MASK 0xFFFFFFFF |
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| 304 | |
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| 305 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN */ |
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| 306 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_SHIFT 0 |
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| 307 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN_V_MASK 0xFFFFFFFF |
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| 308 | |
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| 309 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD */ |
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| 310 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_SHIFT 0 |
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| 311 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD_V_MASK 0xFFFFFFFF |
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| 312 | |
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| 313 | /* DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN */ |
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| 314 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_SHIFT 0 |
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| 315 | #define DCORE0_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN_V_MASK 0xFFFFFFFF |
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| 316 | |
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| 317 | /* DCORE0_MME_CTRL_LO_PROT */ |
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| 318 | #define DCORE0_MME_CTRL_LO_PROT_VALUE_SHIFT 0 |
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| 319 | #define DCORE0_MME_CTRL_LO_PROT_VALUE_MASK 0x7 |
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| 320 | |
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| 321 | /* DCORE0_MME_CTRL_LO_EU */ |
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| 322 | #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_SHIFT 0 |
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| 323 | #define DCORE0_MME_CTRL_LO_EU_POWER_SAVE_DISABLE_MASK 0x1 |
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| 324 | #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_SHIFT 1 |
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| 325 | #define DCORE0_MME_CTRL_LO_EU_FP_PYR_CLOSE_CGATE_EN_MASK 0x2 |
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| 326 | #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_SHIFT 2 |
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| 327 | #define DCORE0_MME_CTRL_LO_EU_FP_CLS_CLOSE_CGATE_EN_MASK 0x4 |
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| 328 | #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_SHIFT 8 |
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| 329 | #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_DLY_MASK 0xFFF00 |
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| 330 | #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_SHIFT 20 |
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| 331 | #define DCORE0_MME_CTRL_LO_EU_FP_CLOSE_CGATE_ON_DESC_MASK 0x100000 |
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| 332 | #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_SHIFT 21 |
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| 333 | #define DCORE0_MME_CTRL_LO_EU_FP_ROLLUP_CDC_STALL_DIS_MASK 0x200000 |
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| 334 | |
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| 335 | /* DCORE0_MME_CTRL_LO_SBTE */ |
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| 336 | #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_SHIFT 0 |
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| 337 | #define DCORE0_MME_CTRL_LO_SBTE_CLOSE_CGATE_MASK 0x1F |
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| 338 | |
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| 339 | /* DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR */ |
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| 340 | #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_SHIFT 0 |
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| 341 | #define DCORE0_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR_V_MASK 0xFFFFFFFF |
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| 342 | |
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| 343 | /* DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR */ |
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| 344 | #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_SHIFT 0 |
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| 345 | #define DCORE0_MME_CTRL_LO_AGU_SM_TOTAL_CNTR_V_MASK 0xFFFFFFFF |
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| 346 | |
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| 347 | /* DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC */ |
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| 348 | #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_SHIFT 0 |
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| 349 | #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_VAL_MASK 0xFFFFF |
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| 350 | #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_SHIFT 31 |
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| 351 | #define DCORE0_MME_CTRL_LO_PCU_RL_SAT_SEC_SEL_MASK 0x80000000 |
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| 352 | |
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| 353 | /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 */ |
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| 354 | #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__SHIFT 0 |
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| 355 | #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32_V_NMB__MASK 0xFFFFFFFF |
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| 356 | |
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| 357 | /* DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 */ |
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| 358 | #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__SHIFT 0 |
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| 359 | #define DCORE0_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33_V_NMB__MASK 0x1 |
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| 360 | |
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| 361 | /* DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS */ |
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| 362 | #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_SHIFT 0 |
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| 363 | #define DCORE0_MME_CTRL_LO_EU_ISOLATION_DIS_FMA_MASK 0x1 |
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| 364 | |
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| 365 | /* DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN */ |
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| 366 | #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_SHIFT 0 |
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| 367 | #define DCORE0_MME_CTRL_LO_QM_SLV_CLK_EN_V_MASK 0x1 |
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| 368 | |
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| 369 | /* DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS */ |
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| 370 | #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_SHIFT 0 |
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| 371 | #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_AXI_MASK 0x1 |
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| 372 | #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_SHIFT 1 |
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| 373 | #define DCORE0_MME_CTRL_LO_HBW_CLK_ENABLER_DIS_APB_MASK 0x2 |
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| 374 | |
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| 375 | /* DCORE0_MME_CTRL_LO_AGU */ |
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| 376 | #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_SHIFT 0 |
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| 377 | #define DCORE0_MME_CTRL_LO_AGU_COUT_H_FROM_SPATIAL_LOOP_MASK 0x1 |
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| 378 | |
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| 379 | /* DCORE0_MME_CTRL_LO_QM */ |
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| 380 | #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_SHIFT 0 |
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| 381 | #define DCORE0_MME_CTRL_LO_QM_STOP_ON_SBTE_ERR_MASK 0x1 |
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| 382 | #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_SHIFT 1 |
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| 383 | #define DCORE0_MME_CTRL_LO_QM_EXT_ADDR_ERR_EN_MASK 0x2 |
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| 384 | |
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| 385 | /* DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS */ |
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| 386 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_SHIFT 0 |
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| 387 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT0_MASK 0xF |
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| 388 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_SHIFT 4 |
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| 389 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AGU_COUT1_MASK 0xF0 |
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| 390 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_SHIFT 8 |
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| 391 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_AP_BRAIN_MASK 0xF00 |
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| 392 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_SHIFT 12 |
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| 393 | #define DCORE0_MME_CTRL_LO_EARLY_RELEASE_STATUS_EU_BRAIN_MASK 0xF000 |
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| 394 | |
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| 395 | /* DCORE0_MME_CTRL_LO_INTR_CAUSE */ |
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| 396 | #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_SHIFT 0 |
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| 397 | #define DCORE0_MME_CTRL_LO_INTR_CAUSE_V_MASK 0xFFFF |
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| 398 | |
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| 399 | /* DCORE0_MME_CTRL_LO_INTR_MASK */ |
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| 400 | #define DCORE0_MME_CTRL_LO_INTR_MASK_V_SHIFT 0 |
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| 401 | #define DCORE0_MME_CTRL_LO_INTR_MASK_V_MASK 0x3FFFFF |
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| 402 | |
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| 403 | /* DCORE0_MME_CTRL_LO_INTR_CLEAR */ |
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| 404 | #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_SHIFT 0 |
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| 405 | #define DCORE0_MME_CTRL_LO_INTR_CLEAR_V_MASK 0xFFFF |
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| 406 | |
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| 407 | /* DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC */ |
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| 408 | #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_SHIFT 0 |
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| 409 | #define DCORE0_MME_CTRL_LO_REDUN_PSOC_SEL_SEC_V_MASK 0x1 |
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| 410 | |
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| 411 | /* DCORE0_MME_CTRL_LO_BIST */ |
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| 412 | #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_SHIFT 0 |
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| 413 | #define DCORE0_MME_CTRL_LO_BIST_FUNC_MODE_MASK 0x1 |
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| 414 | #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_SHIFT 1 |
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| 415 | #define DCORE0_MME_CTRL_LO_BIST_APB_SW_MODE_MASK 0x2 |
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| 416 | |
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| 417 | /* DCORE0_MME_CTRL_LO_EU_RL_ENABLE */ |
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| 418 | #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_SHIFT 0 |
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| 419 | #define DCORE0_MME_CTRL_LO_EU_RL_ENABLE_V_MASK 0x1 |
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| 420 | |
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| 421 | /* DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL */ |
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| 422 | #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_SHIFT 0 |
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| 423 | #define DCORE0_MME_CTRL_LO_EU_RL_TOKEN_SEL_STAT_MASK 0x1 |
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| 424 | |
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| 425 | /* DCORE0_MME_CTRL_LO_EU_RL_CFG */ |
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| 426 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_SHIFT 0 |
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| 427 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_RST_TOKEN_MASK 0xFF |
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| 428 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_SHIFT 8 |
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| 429 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_TIMEOUT_MASK 0xFF00 |
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| 430 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_SHIFT 16 |
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| 431 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_SATURATION_MASK 0xFF0000 |
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| 432 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_SHIFT 24 |
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| 433 | #define DCORE0_MME_CTRL_LO_EU_RL_CFG_DATA_SIZE_MASK 0xFF000000 |
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| 434 | |
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| 435 | /* DCORE0_MME_CTRL_LO_PCU_DBG_DW0 */ |
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| 436 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_SHIFT 0 |
|---|
| 437 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_FSM_STATE_MASK 0x1 |
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| 438 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_SHIFT 8 |
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| 439 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW0_REAL_POOL_TOKENS_MASK 0xFFFFF00 |
|---|
| 440 | |
|---|
| 441 | /* DCORE0_MME_CTRL_LO_PCU_DBG_DW1 */ |
|---|
| 442 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_SHIFT 0 |
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| 443 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW1_ALL_POOL_TOKENS_MASK 0xFFFFF |
|---|
| 444 | |
|---|
| 445 | /* DCORE0_MME_CTRL_LO_PCU_DBG_DW2 */ |
|---|
| 446 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_SHIFT 0 |
|---|
| 447 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_BUBBLE_CYC_CNTR_MASK 0xFFFF |
|---|
| 448 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_SHIFT 16 |
|---|
| 449 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW2_DUMMY_CYC_CNTR_MASK 0xFFFF0000 |
|---|
| 450 | |
|---|
| 451 | /* DCORE0_MME_CTRL_LO_PCU_DBG_DW3 */ |
|---|
| 452 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_SHIFT 0 |
|---|
| 453 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_REAL_MACS_HISTORY_MASK 0xFFFF |
|---|
| 454 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_SHIFT 16 |
|---|
| 455 | #define DCORE0_MME_CTRL_LO_PCU_DBG_DW3_ALL_MACS_HISTORY_MASK 0xFFFF0000 |
|---|
| 456 | |
|---|
| 457 | /* DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID */ |
|---|
| 458 | #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_SHIFT 0 |
|---|
| 459 | #define DCORE0_MME_CTRL_LO_PCU_DBG_WKL_ID_B_MASK 0xFFFFFFFF |
|---|
| 460 | |
|---|
| 461 | /* DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM */ |
|---|
| 462 | #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_SHIFT 0 |
|---|
| 463 | #define DCORE0_MME_CTRL_LO_ETF_MEM_WRAP_RM_V_MASK 0x3FFFFFFF |
|---|
| 464 | |
|---|
| 465 | #endif /* ASIC_REG_DCORE0_MME_CTRL_LO_MASKS_H_ */ |
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| 466 | |
|---|
