1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2020 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_
14#define ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_
15
16/*
17 *****************************************
18 * DCORE0_MME_SBTE0
19 * (Prototype: SB)
20 *****************************************
21 */
22
23/* DCORE0_MME_SBTE0_MAX_SIZE */
24#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_SHIFT 0
25#define DCORE0_MME_SBTE0_MAX_SIZE_DATA_MASK 0xFFFF
26#define DCORE0_MME_SBTE0_MAX_SIZE_MD_SHIFT 16
27#define DCORE0_MME_SBTE0_MAX_SIZE_MD_MASK 0xFFFF0000
28
29/* DCORE0_MME_SBTE0_FORCE_MISS */
30#define DCORE0_MME_SBTE0_FORCE_MISS_R_SHIFT 0
31#define DCORE0_MME_SBTE0_FORCE_MISS_R_MASK 0x1
32
33/* DCORE0_MME_SBTE0_MAX */
34#define DCORE0_MME_SBTE0_MAX_OS_SHIFT 0
35#define DCORE0_MME_SBTE0_MAX_OS_MASK 0xFFFF
36
37/* DCORE0_MME_SBTE0_RL */
38#define DCORE0_MME_SBTE0_RL_SATURATION_SHIFT 0
39#define DCORE0_MME_SBTE0_RL_SATURATION_MASK 0xFF
40#define DCORE0_MME_SBTE0_RL_TIMEOUT_SHIFT 8
41#define DCORE0_MME_SBTE0_RL_TIMEOUT_MASK 0xFF00
42#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_SHIFT 16
43#define DCORE0_MME_SBTE0_RL_RATE_LIMITER_EN_MASK 0x10000
44
45/* DCORE0_MME_SBTE0_SB_STALL */
46#define DCORE0_MME_SBTE0_SB_STALL_R_SHIFT 0
47#define DCORE0_MME_SBTE0_SB_STALL_R_MASK 0x1
48
49/* DCORE0_MME_SBTE0_INTR */
50#define DCORE0_MME_SBTE0_INTR_I0_SHIFT 0
51#define DCORE0_MME_SBTE0_INTR_I0_MASK 0x1
52
53/* DCORE0_MME_SBTE0_ARUSER */
54#define DCORE0_MME_SBTE0_ARUSER_ASID_SHIFT 0
55#define DCORE0_MME_SBTE0_ARUSER_ASID_MASK 0x3FF
56#define DCORE0_MME_SBTE0_ARUSER_MMBP_SHIFT 10
57#define DCORE0_MME_SBTE0_ARUSER_MMBP_MASK 0x400
58#define DCORE0_MME_SBTE0_ARUSER_DUMMY_SHIFT 11
59#define DCORE0_MME_SBTE0_ARUSER_DUMMY_MASK 0xFFFFF800
60
61/* DCORE0_MME_SBTE0_ARCACHE */
62#define DCORE0_MME_SBTE0_ARCACHE_N_SHIFT 0
63#define DCORE0_MME_SBTE0_ARCACHE_N_MASK 0xF
64
65/* DCORE0_MME_SBTE0_STATUS */
66#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_SHIFT 0
67#define DCORE0_MME_SBTE0_STATUS_DROP_CNT_MASK 0xFFFFFFFF
68
69/* DCORE0_MME_SBTE0_PRTN */
70#define DCORE0_MME_SBTE0_PRTN_CLK_EN_SHIFT 0
71#define DCORE0_MME_SBTE0_PRTN_CLK_EN_MASK 0x1
72
73/* DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS */
74#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_SHIFT 0
75#define DCORE0_MME_SBTE0_CFG_SB_INFLIGHTS_W_MASK 0xFFFFFFFF
76
77/* DCORE0_MME_SBTE0_PROT */
78#define DCORE0_MME_SBTE0_PROT_W_SHIFT 0
79#define DCORE0_MME_SBTE0_PROT_W_MASK 0x7
80
81/* DCORE0_MME_SBTE0_INTR_MASK */
82#define DCORE0_MME_SBTE0_INTR_MASK_W_SHIFT 0
83#define DCORE0_MME_SBTE0_INTR_MASK_W_MASK 0x1
84
85/* DCORE0_MME_SBTE0_ARUSER_MSB */
86#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_SHIFT 0
87#define DCORE0_MME_SBTE0_ARUSER_MSB_VAL_MASK 0xFFFFFFFF
88
89/* DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY */
90#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_SHIFT 0
91#define DCORE0_MME_SBTE0_CFG_SB_OCCUPIENCY_VAL_MASK 0xFFFFFFFF
92
93/* DCORE0_MME_SBTE0_ENABLE_CGATE */
94#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_SHIFT 0
95#define DCORE0_MME_SBTE0_ENABLE_CGATE_TE_EN_MASK 0x1
96#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_SHIFT 4
97#define DCORE0_MME_SBTE0_ENABLE_CGATE_SB_EN_MASK 0x10
98
99/* DCORE0_MME_SBTE0_INTF_VLD_DBG */
100#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_SHIFT 0
101#define DCORE0_MME_SBTE0_INTF_VLD_DBG_VLD_MASK 0xFFFFFFFF
102
103/* DCORE0_MME_SBTE0_INTF_RDY_DBG */
104#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_SHIFT 0
105#define DCORE0_MME_SBTE0_INTF_RDY_DBG_RDY_MASK 0xFFFFFFFF
106
107#endif /* ASIC_REG_DCORE0_MME_SBTE0_MASKS_H_ */
108

source code of linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/dcore0_mme_sbte0_masks.h