| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ |
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| 14 | #define ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_SYNC_MNGR_MSTR_IF_AXUSER |
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| 19 | * (Prototype: AXUSER) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID */ |
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| 24 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_SHIFT 0 |
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| 25 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_WR_MASK 0x3FF |
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| 26 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_SHIFT 16 |
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| 27 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_ASID_RD_MASK 0x3FF0000 |
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| 28 | |
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| 29 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP */ |
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| 30 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_SHIFT 0 |
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| 31 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_WR_MASK 0x1 |
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| 32 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_SHIFT 4 |
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| 33 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_MMU_BP_RD_MASK 0x10 |
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| 34 | |
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| 35 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER */ |
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| 36 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_SHIFT 0 |
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| 37 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_WR_MASK 0x1 |
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| 38 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_SHIFT 4 |
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| 39 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_STRONG_ORDER_RD_MASK 0x10 |
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| 40 | |
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| 41 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP */ |
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| 42 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_SHIFT 0 |
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| 43 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_WR_MASK 0x1 |
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| 44 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_SHIFT 4 |
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| 45 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_NO_SNOOP_RD_MASK 0x10 |
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| 46 | |
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| 47 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION */ |
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| 48 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_SHIFT 0 |
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| 49 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_IND_MASK 0x1 |
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| 50 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_SHIFT 4 |
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| 51 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_DTYPE_MASK 0xF0 |
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| 52 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_SHIFT 8 |
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| 53 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_OP_MASK 0x300 |
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| 54 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_SHIFT 12 |
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| 55 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_ROUND_MASK 0x3000 |
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| 56 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_SHIFT 16 |
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| 57 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_REDUCTION_MAX_MASK 0x10000 |
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| 58 | |
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| 59 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC */ |
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| 60 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_SHIFT 0 |
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| 61 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_IND_MASK 0x3 |
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| 62 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_SHIFT 4 |
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| 63 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_ADDITION_SIZE_MASK 0xFF0 |
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| 64 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_SHIFT 12 |
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| 65 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_ATOMIC_MSB_MASK_MASK 0x1F000 |
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| 66 | |
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| 67 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS */ |
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| 68 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_SHIFT 0 |
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| 69 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_WR_MASK 0xF |
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| 70 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_SHIFT 4 |
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| 71 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_QOS_RD_MASK 0x70 |
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| 72 | |
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| 73 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD */ |
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| 74 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_SHIFT 0 |
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| 75 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_27_MASK 0x1 |
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| 76 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_SHIFT 1 |
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| 77 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_28_MASK 0x2 |
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| 78 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_SHIFT 2 |
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| 79 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_30_MASK 0x4 |
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| 80 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_SHIFT 3 |
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| 81 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RSVD_WR_BIT_31_MASK 0x8 |
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| 82 | |
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| 83 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE */ |
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| 84 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_SHIFT 0 |
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| 85 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_WR_MASK 0x1 |
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| 86 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_SHIFT 4 |
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| 87 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_EMEM_CPAGE_RD_MASK 0x10 |
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| 88 | |
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| 89 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE */ |
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| 90 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_SHIFT 0 |
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| 91 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_WR_MASK 0x1 |
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| 92 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_SHIFT 4 |
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| 93 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_CORE_RD_MASK 0x10 |
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| 94 | |
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| 95 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD */ |
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| 96 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_SHIFT 0 |
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| 97 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_X_MASK 0x1F |
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| 98 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_SHIFT 8 |
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| 99 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_E2E_COORD_Y_MASK 0xF00 |
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| 100 | |
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| 101 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO */ |
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| 102 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_SHIFT 0 |
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| 103 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_LO_VAL_MASK 0xFFFFFFFF |
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| 104 | |
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| 105 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI */ |
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| 106 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_SHIFT 0 |
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| 107 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_WR_OVRD_HI_VAL_MASK 0x3FF |
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| 108 | |
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| 109 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO */ |
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| 110 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_SHIFT 0 |
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| 111 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_LO_VAL_MASK 0xFFFFFFFF |
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| 112 | |
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| 113 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI */ |
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| 114 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_SHIFT 0 |
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| 115 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_HB_RD_OVRD_HI_VAL_MASK 0x3FF |
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| 116 | |
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| 117 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD */ |
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| 118 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_SHIFT 0 |
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| 119 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_COORD_VAL_MASK 0x3FF |
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| 120 | |
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| 121 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK */ |
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| 122 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_SHIFT 0 |
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| 123 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_LOCK_VAL_MASK 0x1 |
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| 124 | |
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| 125 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD */ |
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| 126 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_SHIFT 0 |
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| 127 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_21_11_MASK 0x7FF |
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| 128 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_SHIFT 12 |
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| 129 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_RSVD_BIT_22_MASK 0x1000 |
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| 130 | |
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| 131 | /* DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD */ |
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| 132 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_SHIFT 0 |
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| 133 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_LB_OVRD_VAL_MASK 0xFFFFFFFF |
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| 134 | |
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| 135 | #endif /* ASIC_REG_DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MASKS_H_ */ |
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| 136 | |
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