| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_TPC0_CFG_SPECIAL |
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| 19 | * (Prototype: SPECIAL_REGS) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_0 0x400BE80 |
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| 24 | |
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| 25 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_1 0x400BE84 |
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| 26 | |
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| 27 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_2 0x400BE88 |
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| 28 | |
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| 29 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_3 0x400BE8C |
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| 30 | |
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| 31 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_4 0x400BE90 |
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| 32 | |
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| 33 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_5 0x400BE94 |
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| 34 | |
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| 35 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_6 0x400BE98 |
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| 36 | |
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| 37 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_7 0x400BE9C |
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| 38 | |
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| 39 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_8 0x400BEA0 |
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| 40 | |
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| 41 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_9 0x400BEA4 |
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| 42 | |
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| 43 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_10 0x400BEA8 |
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| 44 | |
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| 45 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_11 0x400BEAC |
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| 46 | |
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| 47 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_12 0x400BEB0 |
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| 48 | |
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| 49 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_13 0x400BEB4 |
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| 50 | |
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| 51 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_14 0x400BEB8 |
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| 52 | |
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| 53 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_15 0x400BEBC |
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| 54 | |
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| 55 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_16 0x400BEC0 |
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| 56 | |
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| 57 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_17 0x400BEC4 |
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| 58 | |
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| 59 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_18 0x400BEC8 |
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| 60 | |
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| 61 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_19 0x400BECC |
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| 62 | |
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| 63 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_20 0x400BED0 |
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| 64 | |
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| 65 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_21 0x400BED4 |
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| 66 | |
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| 67 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_22 0x400BED8 |
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| 68 | |
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| 69 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_23 0x400BEDC |
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| 70 | |
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| 71 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_24 0x400BEE0 |
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| 72 | |
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| 73 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_25 0x400BEE4 |
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| 74 | |
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| 75 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_26 0x400BEE8 |
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| 76 | |
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| 77 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_27 0x400BEEC |
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| 78 | |
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| 79 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_28 0x400BEF0 |
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| 80 | |
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| 81 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_29 0x400BEF4 |
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| 82 | |
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| 83 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_30 0x400BEF8 |
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| 84 | |
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| 85 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_PRIV_31 0x400BEFC |
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| 86 | |
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| 87 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_DATA 0x400BF00 |
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| 88 | |
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| 89 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_GW_REQ 0x400BF04 |
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| 90 | |
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| 91 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_NUMOF 0x400BF0C |
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| 92 | |
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| 93 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_SEL 0x400BF10 |
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| 94 | |
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| 95 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_CTL 0x400BF14 |
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| 96 | |
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| 97 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_MASK 0x400BF18 |
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| 98 | |
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| 99 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_GLBL_ERR_MASK 0x400BF1C |
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| 100 | |
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| 101 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_STS 0x400BF20 |
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| 102 | |
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| 103 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_ECC_ERR_ADDR 0x400BF24 |
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| 104 | |
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| 105 | #define mmDCORE0_TPC0_CFG_SPECIAL_MEM_RM 0x400BF28 |
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| 106 | |
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| 107 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_MASK 0x400BF40 |
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| 108 | |
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| 109 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_ADDR 0x400BF44 |
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| 110 | |
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| 111 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_ERR_CAUSE 0x400BF48 |
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| 112 | |
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| 113 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0 0x400BF60 |
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| 114 | |
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| 115 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1 0x400BF64 |
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| 116 | |
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| 117 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2 0x400BF68 |
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| 118 | |
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| 119 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 0x400BF6C |
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| 120 | |
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| 121 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_0 0x400BF80 |
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| 122 | |
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| 123 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_1 0x400BF84 |
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| 124 | |
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| 125 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_2 0x400BF88 |
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| 126 | |
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| 127 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_3 0x400BF8C |
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| 128 | |
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| 129 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_4 0x400BF90 |
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| 130 | |
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| 131 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_5 0x400BF94 |
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| 132 | |
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| 133 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_6 0x400BF98 |
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| 134 | |
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| 135 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_7 0x400BF9C |
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| 136 | |
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| 137 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_8 0x400BFA0 |
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| 138 | |
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| 139 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_9 0x400BFA4 |
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| 140 | |
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| 141 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_10 0x400BFA8 |
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| 142 | |
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| 143 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_11 0x400BFAC |
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| 144 | |
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| 145 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_12 0x400BFB0 |
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| 146 | |
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| 147 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_13 0x400BFB4 |
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| 148 | |
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| 149 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_14 0x400BFB8 |
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| 150 | |
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| 151 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_15 0x400BFBC |
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| 152 | |
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| 153 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_16 0x400BFC0 |
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| 154 | |
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| 155 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_17 0x400BFC4 |
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| 156 | |
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| 157 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_18 0x400BFC8 |
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| 158 | |
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| 159 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_19 0x400BFCC |
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| 160 | |
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| 161 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_20 0x400BFD0 |
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| 162 | |
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| 163 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_21 0x400BFD4 |
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| 164 | |
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| 165 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_22 0x400BFD8 |
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| 166 | |
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| 167 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_23 0x400BFDC |
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| 168 | |
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| 169 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_24 0x400BFE0 |
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| 170 | |
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| 171 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_25 0x400BFE4 |
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| 172 | |
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| 173 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_26 0x400BFE8 |
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| 174 | |
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| 175 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_27 0x400BFEC |
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| 176 | |
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| 177 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_28 0x400BFF0 |
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| 178 | |
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| 179 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_29 0x400BFF4 |
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| 180 | |
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| 181 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_30 0x400BFF8 |
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| 182 | |
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| 183 | #define mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SEC_31 0x400BFFC |
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| 184 | |
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| 185 | #endif /* ASIC_REG_DCORE0_TPC0_CFG_SPECIAL_REGS_H_ */ |
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| 186 | |
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