| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_TPC0_EML_SPMU |
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| 19 | * (Prototype: SPMU) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR0_EL0 0x1000 |
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| 24 | |
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| 25 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR1_EL0 0x1008 |
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| 26 | |
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| 27 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR2_EL0 0x1010 |
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| 28 | |
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| 29 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR3_EL0 0x1018 |
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| 30 | |
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| 31 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR4_EL0 0x1020 |
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| 32 | |
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| 33 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTR5_EL0 0x1028 |
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| 34 | |
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| 35 | #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_L_EL0 0x10F8 |
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| 36 | |
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| 37 | #define mmDCORE0_TPC0_EML_SPMU_PMCCNTR_H_EL0 0x10FC |
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| 38 | |
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| 39 | #define mmDCORE0_TPC0_EML_SPMU_PMTRC 0x1200 |
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| 40 | |
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| 41 | #define mmDCORE0_TPC0_EML_SPMU_TRC_CTRL_HOST 0x1204 |
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| 42 | |
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| 43 | #define mmDCORE0_TPC0_EML_SPMU_TRC_STAT_HOST 0x1208 |
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| 44 | |
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| 45 | #define mmDCORE0_TPC0_EML_SPMU_TRC_EN_HOST 0x120C |
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| 46 | |
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| 47 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER0_EL0 0x1400 |
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| 48 | |
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| 49 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER1_EL0 0x1404 |
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| 50 | |
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| 51 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER2_EL0 0x1408 |
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| 52 | |
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| 53 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER3_EL0 0x140C |
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| 54 | |
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| 55 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER4_EL0 0x1410 |
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| 56 | |
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| 57 | #define mmDCORE0_TPC0_EML_SPMU_PMEVTYPER5_EL0 0x1414 |
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| 58 | |
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| 59 | #define mmDCORE0_TPC0_EML_SPMU_PMSSR 0x1610 |
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| 60 | |
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| 61 | #define mmDCORE0_TPC0_EML_SPMU_PMOVSSR 0x1614 |
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| 62 | |
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| 63 | #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_L 0x1618 |
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| 64 | |
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| 65 | #define mmDCORE0_TPC0_EML_SPMU_PMCCNTSR_H 0x161C |
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| 66 | |
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| 67 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR0 0x1620 |
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| 68 | |
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| 69 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR1 0x1624 |
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| 70 | |
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| 71 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR2 0x1628 |
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| 72 | |
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| 73 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR3 0x162C |
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| 74 | |
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| 75 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR4 0x1630 |
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| 76 | |
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| 77 | #define mmDCORE0_TPC0_EML_SPMU_PMEVCNTSR5 0x1634 |
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| 78 | |
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| 79 | #define mmDCORE0_TPC0_EML_SPMU_PMSCR 0x16F0 |
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| 80 | |
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| 81 | #define mmDCORE0_TPC0_EML_SPMU_PMSRR 0x16F4 |
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| 82 | |
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| 83 | #define mmDCORE0_TPC0_EML_SPMU_PMCNTENSET_EL0 0x1C00 |
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| 84 | |
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| 85 | #define mmDCORE0_TPC0_EML_SPMU_PMCNTENCLR_EL0 0x1C20 |
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| 86 | |
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| 87 | #define mmDCORE0_TPC0_EML_SPMU_PMINTENSET_EL1 0x1C40 |
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| 88 | |
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| 89 | #define mmDCORE0_TPC0_EML_SPMU_PMINTENCLR_EL1 0x1C60 |
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| 90 | |
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| 91 | #define mmDCORE0_TPC0_EML_SPMU_PMOVSCLR_EL0 0x1C80 |
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| 92 | |
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| 93 | #define mmDCORE0_TPC0_EML_SPMU_PMSWINC_EL0 0x1CA0 |
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| 94 | |
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| 95 | #define mmDCORE0_TPC0_EML_SPMU_PMOVSSET_EL0 0x1CC0 |
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| 96 | |
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| 97 | #define mmDCORE0_TPC0_EML_SPMU_PMCFGR 0x1E00 |
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| 98 | |
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| 99 | #define mmDCORE0_TPC0_EML_SPMU_PMCR_EL0 0x1E04 |
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| 100 | |
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| 101 | #define mmDCORE0_TPC0_EML_SPMU_PMITCTRL 0x1F00 |
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| 102 | |
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| 103 | #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMSET 0x1FA0 |
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| 104 | |
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| 105 | #define mmDCORE0_TPC0_EML_SPMU_PMCLAIMCLR 0x1FA4 |
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| 106 | |
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| 107 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF0 0x1FA8 |
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| 108 | |
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| 109 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVAFF1 0x1FAC |
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| 110 | |
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| 111 | #define mmDCORE0_TPC0_EML_SPMU_PMLAR 0x1FB0 |
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| 112 | |
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| 113 | #define mmDCORE0_TPC0_EML_SPMU_PMLSR 0x1FB4 |
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| 114 | |
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| 115 | #define mmDCORE0_TPC0_EML_SPMU_PMAUTHSTATUS 0x1FB8 |
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| 116 | |
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| 117 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVARCH 0x1FBC |
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| 118 | |
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| 119 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVID2 0x1FC0 |
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| 120 | |
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| 121 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVID1 0x1FC4 |
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| 122 | |
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| 123 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVID 0x1FC8 |
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| 124 | |
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| 125 | #define mmDCORE0_TPC0_EML_SPMU_PMDEVTYPE 0x1FCC |
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| 126 | |
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| 127 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR4 0x1FD0 |
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| 128 | |
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| 129 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR5 0x1FD4 |
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| 130 | |
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| 131 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR6 0x1FD8 |
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| 132 | |
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| 133 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR7 0x1FDC |
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| 134 | |
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| 135 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR0 0x1FE0 |
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| 136 | |
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| 137 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR1 0x1FE4 |
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| 138 | |
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| 139 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR2 0x1FE8 |
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| 140 | |
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| 141 | #define mmDCORE0_TPC0_EML_SPMU_PMPIDR3 0x1FEC |
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| 142 | |
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| 143 | #define mmDCORE0_TPC0_EML_SPMU_PMCIDR0 0x1FF0 |
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| 144 | |
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| 145 | #define mmDCORE0_TPC0_EML_SPMU_PMCIDR1 0x1FF4 |
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| 146 | |
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| 147 | #define mmDCORE0_TPC0_EML_SPMU_PMCIDR2 0x1FF8 |
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| 148 | |
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| 149 | #define mmDCORE0_TPC0_EML_SPMU_PMCIDR3 0x1FFC |
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| 150 | |
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| 151 | #endif /* ASIC_REG_DCORE0_TPC0_EML_SPMU_REGS_H_ */ |
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| 152 | |
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