| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_TPC0_QM_ARC_AUX |
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| 19 | * (Prototype: QMAN_ARC_AUX) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ 0x4008100 |
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| 24 | |
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| 25 | #define mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK 0x4008104 |
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| 26 | |
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| 27 | #define mmDCORE0_TPC0_QM_ARC_AUX_RST_VEC_ADDR 0x4008108 |
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| 28 | |
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| 29 | #define mmDCORE0_TPC0_QM_ARC_AUX_DBG_MODE 0x400810C |
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| 30 | |
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| 31 | #define mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM 0x4008110 |
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| 32 | |
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| 33 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_NUM 0x4008114 |
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| 34 | |
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| 35 | #define mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT 0x4008118 |
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| 36 | |
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| 37 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_SYS_ADDR_BASE 0x400811C |
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| 38 | |
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| 39 | #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_AP_STS 0x4008120 |
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| 40 | |
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| 41 | #define mmDCORE0_TPC0_QM_ARC_AUX_CTI_CFG_MUX_SEL 0x4008124 |
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| 42 | |
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| 43 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST 0x4008128 |
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| 44 | |
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| 45 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ 0x400812C |
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| 46 | |
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| 47 | #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_LSB_ADDR 0x4008130 |
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| 48 | |
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| 49 | #define mmDCORE0_TPC0_QM_ARC_AUX_SRAM_MSB_ADDR 0x4008134 |
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| 50 | |
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| 51 | #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_LSB_ADDR 0x4008138 |
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| 52 | |
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| 53 | #define mmDCORE0_TPC0_QM_ARC_AUX_PCIE_MSB_ADDR 0x400813C |
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| 54 | |
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| 55 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LSB_ADDR 0x4008140 |
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| 56 | |
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| 57 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_MSB_ADDR 0x4008144 |
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| 58 | |
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| 59 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_LSB_ADDR 0x4008150 |
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| 60 | |
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| 61 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_MSB_ADDR 0x4008154 |
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| 62 | |
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| 63 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_LSB_ADDR 0x4008158 |
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| 64 | |
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| 65 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_MSB_ADDR 0x400815C |
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| 66 | |
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| 67 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_LSB_ADDR 0x4008160 |
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| 68 | |
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| 69 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_MSB_ADDR 0x4008164 |
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| 70 | |
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| 71 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_LSB_ADDR 0x4008168 |
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| 72 | |
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| 73 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_MSB_ADDR 0x400816C |
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| 74 | |
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| 75 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM0_OFFSET 0x4008170 |
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| 76 | |
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| 77 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM1_OFFSET 0x4008174 |
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| 78 | |
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| 79 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM2_OFFSET 0x4008178 |
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| 80 | |
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| 81 | #define mmDCORE0_TPC0_QM_ARC_AUX_HBM3_OFFSET 0x400817C |
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| 82 | |
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| 83 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_0 0x4008180 |
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| 84 | |
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| 85 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_1 0x4008184 |
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| 86 | |
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| 87 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_2 0x4008188 |
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| 88 | |
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| 89 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_3 0x400818C |
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| 90 | |
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| 91 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_4 0x4008190 |
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| 92 | |
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| 93 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_5 0x4008194 |
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| 94 | |
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| 95 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_LSB_ADDR_6 0x4008198 |
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| 96 | |
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| 97 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_0 0x400819C |
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| 98 | |
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| 99 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_1 0x40081A0 |
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| 100 | |
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| 101 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_2 0x40081A4 |
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| 102 | |
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| 103 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_3 0x40081A8 |
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| 104 | |
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| 105 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_4 0x40081AC |
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| 106 | |
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| 107 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_5 0x40081B0 |
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| 108 | |
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| 109 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_PURPOSE_MSB_ADDR_6 0x40081B4 |
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| 110 | |
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| 111 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_CBU_AWCACHE_OVR 0x40081B8 |
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| 112 | |
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| 113 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_LBU_AWCACHE_OVR 0x40081BC |
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| 114 | |
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| 115 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_0 0x40081C0 |
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| 116 | |
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| 117 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_1 0x40081C4 |
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| 118 | |
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| 119 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_2 0x40081C8 |
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| 120 | |
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| 121 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_3 0x40081CC |
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| 122 | |
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| 123 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_4 0x40081D0 |
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| 124 | |
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| 125 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_5 0x40081D4 |
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| 126 | |
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| 127 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_6 0x40081D8 |
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| 128 | |
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| 129 | #define mmDCORE0_TPC0_QM_ARC_AUX_CONTEXT_ID_7 0x40081DC |
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| 130 | |
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| 131 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_0 0x40081E0 |
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| 132 | |
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| 133 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_1 0x40081E4 |
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| 134 | |
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| 135 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_2 0x40081E8 |
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| 136 | |
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| 137 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_3 0x40081EC |
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| 138 | |
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| 139 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_4 0x40081F0 |
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| 140 | |
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| 141 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_5 0x40081F4 |
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| 142 | |
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| 143 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_6 0x40081F8 |
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| 144 | |
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| 145 | #define mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7 0x40081FC |
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| 146 | |
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| 147 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_0 0x4008200 |
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| 148 | |
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| 149 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_1 0x4008204 |
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| 150 | |
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| 151 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_2 0x4008208 |
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| 152 | |
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| 153 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_3 0x400820C |
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| 154 | |
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| 155 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_4 0x4008210 |
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| 156 | |
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| 157 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_5 0x4008214 |
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| 158 | |
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| 159 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_6 0x4008218 |
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| 160 | |
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| 161 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_7 0x400821C |
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| 162 | |
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| 163 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_8 0x4008220 |
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| 164 | |
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| 165 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_9 0x4008224 |
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| 166 | |
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| 167 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_10 0x4008228 |
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| 168 | |
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| 169 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_11 0x400822C |
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| 170 | |
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| 171 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_12 0x4008230 |
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| 172 | |
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| 173 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_13 0x4008234 |
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| 174 | |
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| 175 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_14 0x4008238 |
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| 176 | |
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| 177 | #define mmDCORE0_TPC0_QM_ARC_AUX_SW_INTR_15 0x400823C |
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| 178 | |
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| 179 | #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_0 0x4008280 |
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| 180 | |
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| 181 | #define mmDCORE0_TPC0_QM_ARC_AUX_IRQ_INTR_MASK_1 0x4008284 |
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| 182 | |
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| 183 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_STS 0x4008290 |
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| 184 | |
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| 185 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_CLR 0x4008294 |
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| 186 | |
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| 187 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_MASK 0x4008298 |
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| 188 | |
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| 189 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_EXCPTN_CAUSE 0x400829C |
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| 190 | |
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| 191 | #define mmDCORE0_TPC0_QM_ARC_AUX_SEI_INTR_HALT_EN 0x40082A0 |
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| 192 | |
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| 193 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_SEI_INTR_HALT_MASK 0x40082A4 |
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| 194 | |
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| 195 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_SEI_INTR_HALT_MASK 0x40082A8 |
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| 196 | |
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| 197 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_STS 0x40082B0 |
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| 198 | |
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| 199 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_CLR 0x40082B4 |
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| 200 | |
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| 201 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REI_INTR_MASK 0x40082B8 |
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| 202 | |
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| 203 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_ERR_ADDR 0x40082BC |
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| 204 | |
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| 205 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_ECC_SYNDROME 0x40082C0 |
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| 206 | |
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| 207 | #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_ERR_ADDR 0x40082C4 |
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| 208 | |
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| 209 | #define mmDCORE0_TPC0_QM_ARC_AUX_I_CACHE_ECC_SYNDROME 0x40082C8 |
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| 210 | |
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| 211 | #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_ERR_ADDR 0x40082CC |
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| 212 | |
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| 213 | #define mmDCORE0_TPC0_QM_ARC_AUX_D_CACHE_ECC_SYNDROME 0x40082D0 |
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| 214 | |
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| 215 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_AWADDR_ERR 0x40082E0 |
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| 216 | |
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| 217 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_TRMINATE_ARADDR_ERR 0x40082E4 |
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| 218 | |
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| 219 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_BRESP 0x40082E8 |
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| 220 | |
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| 221 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_RRESP 0x40082EC |
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| 222 | |
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| 223 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXLEN 0x40082F0 |
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| 224 | |
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| 225 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_LBW_TERMINATE_AXSIZE 0x40082F4 |
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| 226 | |
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| 227 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0 0x4008300 |
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| 228 | |
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| 229 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_1 0x4008304 |
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| 230 | |
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| 231 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_2 0x4008308 |
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| 232 | |
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| 233 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_3 0x400830C |
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| 234 | |
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| 235 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_4 0x4008310 |
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| 236 | |
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| 237 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_5 0x4008314 |
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| 238 | |
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| 239 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_6 0x4008318 |
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| 240 | |
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| 241 | #define mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_7 0x400831C |
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| 242 | |
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| 243 | #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_WR_CNT 0x4008320 |
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| 244 | |
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| 245 | #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_WR_CNT 0x4008324 |
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| 246 | |
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| 247 | #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_CBU_RD_CNT 0x4008328 |
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| 248 | |
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| 249 | #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_CBU_RD_CNT 0x400832C |
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| 250 | |
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| 251 | #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_WR_CNT 0x4008330 |
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| 252 | |
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| 253 | #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_WR_CNT 0x4008334 |
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| 254 | |
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| 255 | #define mmDCORE0_TPC0_QM_ARC_AUX_TOTAL_LBU_RD_CNT 0x4008338 |
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| 256 | |
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| 257 | #define mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT 0x400833C |
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| 258 | |
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| 259 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR 0x4008350 |
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| 260 | |
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| 261 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_OVR_EN 0x4008354 |
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| 262 | |
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| 263 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR 0x4008358 |
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| 264 | |
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| 265 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_OVR_EN 0x400835C |
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| 266 | |
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| 267 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR 0x4008360 |
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| 268 | |
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| 269 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_ARUSER_MSB_OVR_EN 0x4008364 |
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| 270 | |
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| 271 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR 0x4008368 |
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| 272 | |
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| 273 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AWUSER_MSB_OVR_EN 0x400836C |
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| 274 | |
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| 275 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_AXCACHE_OVR 0x4008370 |
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| 276 | |
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| 277 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_LOCK_OVR 0x4008374 |
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| 278 | |
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| 279 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_PROT_OVR 0x4008378 |
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| 280 | |
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| 281 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_MAX_OUTSTANDING 0x400837C |
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| 282 | |
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| 283 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN 0x4008380 |
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| 284 | |
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| 285 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORCE_RSP_OK 0x4008384 |
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| 286 | |
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| 287 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_NO_WR_INFLIGHT 0x400838C |
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| 288 | |
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| 289 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_SEI_INTR_ID 0x4008390 |
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| 290 | |
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| 291 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR 0x4008400 |
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| 292 | |
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| 293 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_ARUSER_OVR_EN 0x4008404 |
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| 294 | |
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| 295 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR 0x4008408 |
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| 296 | |
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| 297 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AWUSER_OVR_EN 0x400840C |
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| 298 | |
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| 299 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_AXCACHE_OVR 0x4008420 |
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| 300 | |
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| 301 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_LOCK_OVR 0x4008424 |
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| 302 | |
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| 303 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_PROT_OVR 0x4008428 |
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| 304 | |
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| 305 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_MAX_OUTSTANDING 0x400842C |
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| 306 | |
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| 307 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN 0x4008430 |
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| 308 | |
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| 309 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_FORCE_RSP_OK 0x4008434 |
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| 310 | |
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| 311 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_NO_WR_INFLIGHT 0x400843C |
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| 312 | |
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| 313 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBU_SEI_INTR_ID 0x4008440 |
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| 314 | |
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| 315 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0 0x4008500 |
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| 316 | |
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| 317 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_1 0x4008504 |
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| 318 | |
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| 319 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_2 0x4008508 |
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| 320 | |
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| 321 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_3 0x400850C |
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| 322 | |
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| 323 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_4 0x4008510 |
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| 324 | |
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| 325 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_5 0x4008514 |
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| 326 | |
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| 327 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_6 0x4008518 |
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| 328 | |
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| 329 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_7 0x400851C |
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| 330 | |
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| 331 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_0 0x4008520 |
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| 332 | |
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| 333 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_1 0x4008524 |
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| 334 | |
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| 335 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_2 0x4008528 |
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| 336 | |
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| 337 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_3 0x400852C |
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| 338 | |
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| 339 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_4 0x4008530 |
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| 340 | |
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| 341 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_5 0x4008534 |
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| 342 | |
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| 343 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_6 0x4008538 |
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| 344 | |
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| 345 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_SIZE_7 0x400853C |
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| 346 | |
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| 347 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_0 0x4008540 |
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| 348 | |
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| 349 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_1 0x4008544 |
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| 350 | |
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| 351 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_2 0x4008548 |
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| 352 | |
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| 353 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_3 0x400854C |
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| 354 | |
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| 355 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_4 0x4008550 |
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| 356 | |
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| 357 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_5 0x4008554 |
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| 358 | |
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| 359 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_6 0x4008558 |
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| 360 | |
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| 361 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PI_7 0x400855C |
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| 362 | |
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| 363 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_0 0x4008560 |
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| 364 | |
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| 365 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_1 0x4008564 |
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| 366 | |
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| 367 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_2 0x4008568 |
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| 368 | |
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| 369 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_3 0x400856C |
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| 370 | |
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| 371 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_4 0x4008570 |
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| 372 | |
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| 373 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_5 0x4008574 |
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| 374 | |
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| 375 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_6 0x4008578 |
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| 376 | |
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| 377 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_CI_7 0x400857C |
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| 378 | |
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| 379 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_0 0x4008580 |
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| 380 | |
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| 381 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_1 0x4008584 |
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| 382 | |
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| 383 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_2 0x4008588 |
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| 384 | |
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| 385 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_3 0x400858C |
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| 386 | |
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| 387 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_4 0x4008590 |
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| 388 | |
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| 389 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_5 0x4008594 |
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| 390 | |
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| 391 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_6 0x4008598 |
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| 392 | |
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| 393 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_PUSH_REG_7 0x400859C |
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| 394 | |
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| 395 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_0 0x40085A0 |
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| 396 | |
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| 397 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_1 0x40085A4 |
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| 398 | |
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| 399 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_2 0x40085A8 |
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| 400 | |
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| 401 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_3 0x40085AC |
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| 402 | |
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| 403 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_4 0x40085B0 |
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| 404 | |
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| 405 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_5 0x40085B4 |
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| 406 | |
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| 407 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_6 0x40085B8 |
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| 408 | |
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| 409 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_MAX_OCCUPANCY_7 0x40085BC |
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| 410 | |
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| 411 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_0 0x40085C0 |
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| 412 | |
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| 413 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_1 0x40085C4 |
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| 414 | |
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| 415 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_2 0x40085C8 |
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| 416 | |
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| 417 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_3 0x40085CC |
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| 418 | |
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| 419 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_4 0x40085D0 |
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| 420 | |
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| 421 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_5 0x40085D4 |
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| 422 | |
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| 423 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_6 0x40085D8 |
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| 424 | |
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| 425 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_VALID_ENTRIES_7 0x40085DC |
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| 426 | |
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| 427 | #define mmDCORE0_TPC0_QM_ARC_AUX_GENERAL_Q_VLD_ENTRY_MASK 0x40085E0 |
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| 428 | |
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| 429 | #define mmDCORE0_TPC0_QM_ARC_AUX_NIC_Q_VLD_ENTRY_MASK 0x40085E4 |
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| 430 | |
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| 431 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_DROP_EN 0x4008620 |
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| 432 | |
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| 433 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_WARN_MSG 0x4008624 |
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| 434 | |
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| 435 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG 0x4008628 |
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| 436 | |
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| 437 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWPROT 0x4008630 |
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| 438 | |
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| 439 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWUSER 0x4008634 |
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| 440 | |
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| 441 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWBURST 0x4008638 |
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| 442 | |
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| 443 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWLOCK 0x400863C |
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| 444 | |
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| 445 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_GEN_AXI_AWCACHE 0x4008640 |
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| 446 | |
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| 447 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_WRR_ARB_WEIGHT 0x4008644 |
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| 448 | |
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| 449 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_FULL_CFG 0x4008648 |
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| 450 | |
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| 451 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT 0x400864C |
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| 452 | |
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| 453 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_IFIFO_SHADOW_CI 0x4008650 |
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| 454 | |
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| 455 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_IFIFO_SHADOW_CI 0x4008654 |
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| 456 | |
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| 457 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_CQ_SHADOW_CI 0x4008658 |
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| 458 | |
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| 459 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI 0x400865C |
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| 460 | |
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| 461 | #define mmDCORE0_TPC0_QM_ARC_AUX_AUX2APB_PROT 0x4008700 |
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| 462 | |
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| 463 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_FORK_WIN_EN 0x4008704 |
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| 464 | |
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| 465 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR0 0x4008708 |
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| 466 | |
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| 467 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK0 0x400870C |
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| 468 | |
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| 469 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_BASE_ADDR1 0x4008710 |
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| 470 | |
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| 471 | #define mmDCORE0_TPC0_QM_ARC_AUX_QMAN_LBW_FORK_ADDR_MASK1 0x4008714 |
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| 472 | |
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| 473 | #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR0 0x4008718 |
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| 474 | |
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| 475 | #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK0 0x400871C |
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| 476 | |
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| 477 | #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_BASE_ADDR1 0x4008720 |
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| 478 | |
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| 479 | #define mmDCORE0_TPC0_QM_ARC_AUX_FARM_LBW_FORK_ADDR_MASK1 0x4008724 |
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| 480 | |
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| 481 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR0 0x4008728 |
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| 482 | |
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| 483 | #define mmDCORE0_TPC0_QM_ARC_AUX_LBW_APB_FORK_MAX_ADDR1 0x400872C |
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| 484 | |
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| 485 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_LBW_FORK_MASK 0x4008730 |
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| 486 | |
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| 487 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_DUP_ENG_LBW_FORK_ADDR 0x4008734 |
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| 488 | |
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| 489 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACP_ENG_LBW_FORK_ADDR 0x4008738 |
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| 490 | |
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| 491 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_VIRTUAL_ADDR 0x400873C |
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| 492 | |
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| 493 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_WIN_EN 0x4008740 |
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| 494 | |
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| 495 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_LSB 0x4008750 |
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| 496 | |
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| 497 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR0_MSB 0x4008754 |
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| 498 | |
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| 499 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_LSB 0x4008758 |
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| 500 | |
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| 501 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK0_MSB 0x400875C |
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| 502 | |
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| 503 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_LSB 0x4008760 |
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| 504 | |
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| 505 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR1_MSB 0x4008764 |
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| 506 | |
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| 507 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_LSB 0x4008768 |
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| 508 | |
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| 509 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK1_MSB 0x400876C |
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| 510 | |
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| 511 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_LSB 0x4008770 |
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| 512 | |
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| 513 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR2_MSB 0x4008774 |
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| 514 | |
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| 515 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_LSB 0x4008778 |
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| 516 | |
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| 517 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK2_MSB 0x400877C |
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| 518 | |
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| 519 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_LSB 0x4008780 |
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| 520 | |
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| 521 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_BASE_ADDR3_MSB 0x4008784 |
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| 522 | |
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| 523 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_LSB 0x4008788 |
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| 524 | |
|---|
| 525 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_FORK_ADDR_MASK3_MSB 0x400878C |
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| 526 | |
|---|
| 527 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_LSB 0x4008790 |
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| 528 | |
|---|
| 529 | #define mmDCORE0_TPC0_QM_ARC_AUX_CBU_TRMINATE_ARADDR_MSB 0x4008794 |
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| 530 | |
|---|
| 531 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_BRESP 0x4008798 |
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| 532 | |
|---|
| 533 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_CBU_TERMINATE_RRESP 0x400879C |
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| 534 | |
|---|
| 535 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_0 0x4008800 |
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| 536 | |
|---|
| 537 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_1 0x4008804 |
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| 538 | |
|---|
| 539 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_2 0x4008808 |
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| 540 | |
|---|
| 541 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_3 0x400880C |
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| 542 | |
|---|
| 543 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_4 0x4008810 |
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| 544 | |
|---|
| 545 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_5 0x4008814 |
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| 546 | |
|---|
| 547 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_6 0x4008818 |
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| 548 | |
|---|
| 549 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_7 0x400881C |
|---|
| 550 | |
|---|
| 551 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_8 0x4008820 |
|---|
| 552 | |
|---|
| 553 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_9 0x4008824 |
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| 554 | |
|---|
| 555 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_10 0x4008828 |
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| 556 | |
|---|
| 557 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_11 0x400882C |
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| 558 | |
|---|
| 559 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_12 0x4008830 |
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| 560 | |
|---|
| 561 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_13 0x4008834 |
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| 562 | |
|---|
| 563 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_14 0x4008838 |
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| 564 | |
|---|
| 565 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_REGION_CFG_15 0x400883C |
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| 566 | |
|---|
| 567 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_AWADDR_ERR 0x4008840 |
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| 568 | |
|---|
| 569 | #define mmDCORE0_TPC0_QM_ARC_AUX_DCCM_TRMINATE_ARADDR_ERR 0x4008844 |
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| 570 | |
|---|
| 571 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_BRESP 0x4008848 |
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| 572 | |
|---|
| 573 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_RRESP 0x400884C |
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| 574 | |
|---|
| 575 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_TERMINATE_EN 0x4008850 |
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| 576 | |
|---|
| 577 | #define mmDCORE0_TPC0_QM_ARC_AUX_CFG_DCCM_SECURE_REGION 0x4008854 |
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| 578 | |
|---|
| 579 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT 0x4008900 |
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| 580 | |
|---|
| 581 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_CTL 0x4008904 |
|---|
| 582 | |
|---|
| 583 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR_MSK 0x4008908 |
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| 584 | |
|---|
| 585 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_ADDR 0x400890C |
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| 586 | |
|---|
| 587 | #define mmDCORE0_TPC0_QM_ARC_AUX_ARC_ACC_ENGS_BUSER 0x4008910 |
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| 588 | |
|---|
| 589 | #define mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN 0x4008920 |
|---|
| 590 | |
|---|
| 591 | #endif /* ASIC_REG_DCORE0_TPC0_QM_ARC_AUX_REGS_H_ */ |
|---|
| 592 | |
|---|
