| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ |
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| 14 | #define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_VDEC0_BRDG_CTRL |
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| 19 | * (Prototype: VDEC_BRDG_CTRL) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | /* DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE */ |
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| 24 | #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_SHIFT 0 |
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| 25 | #define DCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE_VAL_MASK 0x1 |
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| 26 | |
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| 27 | /* DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK */ |
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| 28 | #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_SHIFT 0 |
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| 29 | #define DCORE0_VDEC0_BRDG_CTRL_IDLE_MASK_VAL_MASK 0x7 |
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| 30 | |
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| 31 | /* DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT */ |
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| 32 | #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_SHIFT 0 |
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| 33 | #define DCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT_VAL_MASK 0xFFFF |
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| 34 | |
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| 35 | /* DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT */ |
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| 36 | #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_SHIFT 0 |
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| 37 | #define DCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT_VAL_MASK 0xFFFF |
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| 38 | |
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| 39 | /* DCORE0_VDEC0_BRDG_CTRL_GRACEFUL */ |
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| 40 | #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_SHIFT 0 |
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| 41 | #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_STOP_MASK 0x1 |
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| 42 | #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_SHIFT 4 |
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| 43 | #define DCORE0_VDEC0_BRDG_CTRL_GRACEFUL_PEND_MASK 0x10 |
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| 44 | |
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| 45 | /* DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT */ |
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| 46 | #define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_SHIFT 0 |
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| 47 | #define DCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT_VAL_MASK 0xFFFF |
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| 48 | |
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| 49 | /* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR */ |
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| 50 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_SHIFT 0 |
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| 51 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_HBW_SEI_MASK 0x1 |
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| 52 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_SHIFT 1 |
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| 53 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_HBW_SEI_MASK 0x2 |
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| 54 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_SHIFT 2 |
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| 55 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_HBW_SEI_MASK 0x4 |
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| 56 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_SHIFT 3 |
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| 57 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_HBW_SEI_MASK 0x8 |
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| 58 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_SHIFT 4 |
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| 59 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_VCD_LBW_SEI_MASK 0x10 |
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| 60 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_SHIFT 5 |
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| 61 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_L2C_LBW_SEI_MASK 0x20 |
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| 62 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_SHIFT 6 |
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| 63 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_NRM_LBW_SEI_MASK 0x40 |
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| 64 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_SHIFT 7 |
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| 65 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MSIX_ABNRM_LBW_SEI_MASK 0x80 |
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| 66 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_SHIFT 8 |
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| 67 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_VCD_LBW_SEI_MASK 0x100 |
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| 68 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_SHIFT 9 |
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| 69 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_L2C_LBW_SEI_MASK 0x200 |
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| 70 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_SHIFT 10 |
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| 71 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_NRM_LBW_SEI_MASK 0x400 |
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| 72 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_SHIFT 11 |
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| 73 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_APB_ABNRM_LBW_SEI_MASK 0x800 |
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| 74 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_SHIFT 12 |
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| 75 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_SEI_MASK 0x1000 |
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| 76 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_SHIFT 13 |
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| 77 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_DEC_APB_SEI_MASK 0x2000 |
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| 78 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_SHIFT 14 |
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| 79 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_TRC_APB_SEI_MASK 0x4000 |
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| 80 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_SHIFT 15 |
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| 81 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_MSTR_IF_SEI_MASK 0x8000 |
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| 82 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_SHIFT 16 |
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| 83 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_AXI_SPLIT_BRESP_ERR_SEI_MASK 0x10000 |
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| 84 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_SHIFT 17 |
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| 85 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_WR_VIOL_SEI_MASK 0x20000 |
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| 86 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_SHIFT 18 |
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| 87 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_HBW_AXI_RD_VIOL_SEI_MASK 0x40000 |
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| 88 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_SHIFT 19 |
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| 89 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_WR_VIOL_SEI_MASK 0x80000 |
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| 90 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_SHIFT 20 |
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| 91 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_LBW_AXI_RD_VIOL_SEI_MASK 0x100000 |
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| 92 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_SHIFT 21 |
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| 93 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_VCD_SPI_MASK 0x200000 |
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| 94 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_SHIFT 22 |
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| 95 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_L2C_SPI_MASK 0x400000 |
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| 96 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_SHIFT 23 |
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| 97 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_NRM_SPI_MASK 0x800000 |
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| 98 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_SHIFT 24 |
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| 99 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_ABNRM_SPI_MASK 0x1000000 |
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| 100 | |
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| 101 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE */ |
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| 102 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_SHIFT 0 |
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| 103 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLEN_GT_31_MASK 0x1 |
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| 104 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 |
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| 105 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 |
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| 106 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_SHIFT 2 |
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| 107 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWBURST_VIOL_MASK 0x4 |
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| 108 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_SHIFT 3 |
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| 109 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWADDR_SIZE_ALIGN_VIOL_MASK 0x8 |
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| 110 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 4 |
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| 111 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x10 |
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| 112 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_SHIFT 5 |
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| 113 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLEN_GT_31_MASK 0x20 |
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| 114 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_SHIFT 6 |
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| 115 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARLOCK_VIOL_MASK 0x40 |
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| 116 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_SHIFT 7 |
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| 117 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARBURST_VIOL_MASK 0x80 |
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| 118 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_SHIFT 8 |
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| 119 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARADDR_SIZE_ALIGN_VIOL_MASK 0x100 |
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| 120 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_SHIFT 9 |
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| 121 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE_ARSIZE_VIOL_MASK 0x200 |
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| 122 | |
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| 123 | /* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE */ |
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| 124 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_SHIFT 0 |
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| 125 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_READ_ACCESS_VIOL_MASK 0x1 |
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| 126 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_SHIFT 1 |
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| 127 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLOCK_VIOL_MASK 0x2 |
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| 128 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_SHIFT 2 |
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| 129 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWADDR_ALIGN_VIOL_MASK 0x4 |
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| 130 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_SHIFT 3 |
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| 131 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWSIZE_VIOL_MASK 0x8 |
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| 132 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_SHIFT 4 |
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| 133 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_AWLEN_VIOL_MASK 0x10 |
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| 134 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_SHIFT 5 |
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| 135 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE_WSTRB_VIOL_MASK 0x20 |
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| 136 | |
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| 137 | /* DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM */ |
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| 138 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_SHIFT 0 |
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| 139 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AW_VIOL_CLR_MASK 0x1 |
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| 140 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_SHIFT 1 |
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| 141 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_HBW_AR_VIOL_CLR_MASK 0x2 |
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| 142 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_SHIFT 2 |
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| 143 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM_LBW_AW_VIOL_CLR_MASK 0x4 |
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| 144 | |
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| 145 | /* DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK */ |
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| 146 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_SHIFT 0 |
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| 147 | #define DCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK_VAL_MASK 0xFFFFFFFF |
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| 148 | |
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| 149 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK */ |
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| 150 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_SHIFT 0 |
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| 151 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF |
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| 152 | |
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| 153 | /* DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK */ |
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| 154 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_SHIFT 0 |
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| 155 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK_MASK_MASK 0xFFFFFFFF |
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| 156 | |
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| 157 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK */ |
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| 158 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_SHIFT 0 |
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| 159 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK_VAL_MASK 0x1 |
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| 160 | |
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| 161 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK */ |
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| 162 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_SHIFT 0 |
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| 163 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK_VAL_MASK 0x1 |
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| 164 | |
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| 165 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK */ |
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| 166 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_SHIFT 0 |
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| 167 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK_VAL_MASK 0x1 |
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| 168 | |
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| 169 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK */ |
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| 170 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_SHIFT 0 |
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| 171 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK_VAL_MASK 0x1 |
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| 172 | |
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| 173 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT */ |
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| 174 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_SHIFT 0 |
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| 175 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT_VAL_MASK 0x7 |
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| 176 | |
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| 177 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT */ |
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| 178 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_SHIFT 0 |
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| 179 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT_VAL_MASK 0x7 |
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| 180 | |
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| 181 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT */ |
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| 182 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_SHIFT 0 |
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| 183 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT_VAL_MASK 0x7 |
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| 184 | |
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| 185 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT */ |
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| 186 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_SHIFT 0 |
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| 187 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT_VAL_MASK 0x7 |
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| 188 | |
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| 189 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT */ |
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| 190 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_SHIFT 0 |
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| 191 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT_VAL_MASK 0x7 |
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| 192 | |
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| 193 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT */ |
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| 194 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_SHIFT 0 |
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| 195 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT_VAL_MASK 0x7 |
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| 196 | |
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| 197 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE */ |
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| 198 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_SHIFT 0 |
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| 199 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_AWSIZE_MASK 0x7 |
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| 200 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_SHIFT 3 |
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| 201 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_HBW_LEGAL_ARSIZE_MASK 0x38 |
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| 202 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_SHIFT 6 |
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| 203 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE_LBW_LEGAL_AWSIZE_MASK 0x1C0 |
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| 204 | |
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| 205 | /* DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK */ |
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| 206 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_SHIFT 0 |
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| 207 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK_VAL_MASK 0x1 |
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| 208 | |
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| 209 | /* DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA */ |
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| 210 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_SHIFT 0 |
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| 211 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA_VAL_MASK 0xFF |
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| 212 | |
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| 213 | /* DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA */ |
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| 214 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_SHIFT 0 |
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| 215 | #define DCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA_VAL_MASK 0xFF |
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| 216 | |
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| 217 | /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL */ |
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| 218 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_SHIFT 0 |
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| 219 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL_VAL_MASK 0x7 |
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| 220 | |
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| 221 | /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR */ |
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| 222 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_SHIFT 0 |
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| 223 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR_VAL_MASK 0xFFFFFFFF |
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| 224 | |
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| 225 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L */ |
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| 226 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_SHIFT 0 |
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| 227 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L_VAL_MASK 0xFFFFFFFF |
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| 228 | |
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| 229 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H */ |
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| 230 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_SHIFT 0 |
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| 231 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H_VAL_MASK 0xFFFFFFFF |
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| 232 | |
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| 233 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L */ |
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| 234 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_SHIFT 0 |
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| 235 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L_IND_MASK 0xFFFFFFFF |
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| 236 | |
|---|
| 237 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H */ |
|---|
| 238 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_SHIFT 0 |
|---|
| 239 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H_IND_MASK 0xFFFFFFFF |
|---|
| 240 | |
|---|
| 241 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L */ |
|---|
| 242 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_SHIFT 0 |
|---|
| 243 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L_VAL_MASK 0xFFFFFFFF |
|---|
| 244 | |
|---|
| 245 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H */ |
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| 246 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_SHIFT 0 |
|---|
| 247 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H_VAL_MASK 0xFFFFFFFF |
|---|
| 248 | |
|---|
| 249 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L */ |
|---|
| 250 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_SHIFT 0 |
|---|
| 251 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L_IND_MASK 0xFFFFFFFF |
|---|
| 252 | |
|---|
| 253 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H */ |
|---|
| 254 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_SHIFT 0 |
|---|
| 255 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H_IND_MASK 0xFFFFFFFF |
|---|
| 256 | |
|---|
| 257 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN */ |
|---|
| 258 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_SHIFT 0 |
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| 259 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN_VAL_MASK 0x1 |
|---|
| 260 | |
|---|
| 261 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK */ |
|---|
| 262 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_SHIFT 0 |
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| 263 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK_VAL_MASK 0x1 |
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| 264 | |
|---|
| 265 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK */ |
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| 266 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_SHIFT 0 |
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| 267 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_WR_MASK 0x1 |
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| 268 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_SHIFT 1 |
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| 269 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_APB_RD_MASK 0x2 |
|---|
| 270 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_SHIFT 2 |
|---|
| 271 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK_LBW_MASK 0x4 |
|---|
| 272 | |
|---|
| 273 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR */ |
|---|
| 274 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_SHIFT 0 |
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| 275 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF |
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| 276 | |
|---|
| 277 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR */ |
|---|
| 278 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 279 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 280 | |
|---|
| 281 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR */ |
|---|
| 282 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_SHIFT 0 |
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| 283 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 284 | |
|---|
| 285 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR */ |
|---|
| 286 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 287 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 288 | |
|---|
| 289 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR */ |
|---|
| 290 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_SHIFT 0 |
|---|
| 291 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 292 | |
|---|
| 293 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR */ |
|---|
| 294 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_SHIFT 0 |
|---|
| 295 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 296 | |
|---|
| 297 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA */ |
|---|
| 298 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_SHIFT 0 |
|---|
| 299 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA_VAL_MASK 0xFFFFFFFF |
|---|
| 300 | |
|---|
| 301 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT */ |
|---|
| 302 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_SHIFT 0 |
|---|
| 303 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT_VAL_MASK 0x7 |
|---|
| 304 | |
|---|
| 305 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L */ |
|---|
| 306 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 |
|---|
| 307 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF |
|---|
| 308 | |
|---|
| 309 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H */ |
|---|
| 310 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 |
|---|
| 311 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF |
|---|
| 312 | |
|---|
| 313 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT */ |
|---|
| 314 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_SHIFT 0 |
|---|
| 315 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT_VAL_MASK 0x7 |
|---|
| 316 | |
|---|
| 317 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR */ |
|---|
| 318 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_SHIFT 0 |
|---|
| 319 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 320 | |
|---|
| 321 | /* DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA */ |
|---|
| 322 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_SHIFT 0 |
|---|
| 323 | #define DCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF |
|---|
| 324 | |
|---|
| 325 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK */ |
|---|
| 326 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_SHIFT 0 |
|---|
| 327 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK_VAL_MASK 0x1 |
|---|
| 328 | |
|---|
| 329 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK */ |
|---|
| 330 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_SHIFT 0 |
|---|
| 331 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_WR_MASK 0x1 |
|---|
| 332 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_SHIFT 1 |
|---|
| 333 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_APB_RD_MASK 0x2 |
|---|
| 334 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_SHIFT 2 |
|---|
| 335 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK_LBW_MASK 0x4 |
|---|
| 336 | |
|---|
| 337 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR */ |
|---|
| 338 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 339 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 340 | |
|---|
| 341 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR */ |
|---|
| 342 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 343 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 344 | |
|---|
| 345 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR */ |
|---|
| 346 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 347 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 348 | |
|---|
| 349 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR */ |
|---|
| 350 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 351 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 352 | |
|---|
| 353 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR */ |
|---|
| 354 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_SHIFT 0 |
|---|
| 355 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 356 | |
|---|
| 357 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR */ |
|---|
| 358 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_SHIFT 0 |
|---|
| 359 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 360 | |
|---|
| 361 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA */ |
|---|
| 362 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_SHIFT 0 |
|---|
| 363 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA_VAL_MASK 0xFFFFFFFF |
|---|
| 364 | |
|---|
| 365 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT */ |
|---|
| 366 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_SHIFT 0 |
|---|
| 367 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT_VAL_MASK 0x7 |
|---|
| 368 | |
|---|
| 369 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L */ |
|---|
| 370 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 |
|---|
| 371 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF |
|---|
| 372 | |
|---|
| 373 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H */ |
|---|
| 374 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 |
|---|
| 375 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF |
|---|
| 376 | |
|---|
| 377 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT */ |
|---|
| 378 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_SHIFT 0 |
|---|
| 379 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT_VAL_MASK 0x7 |
|---|
| 380 | |
|---|
| 381 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR */ |
|---|
| 382 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_SHIFT 0 |
|---|
| 383 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 384 | |
|---|
| 385 | /* DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA */ |
|---|
| 386 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_SHIFT 0 |
|---|
| 387 | #define DCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF |
|---|
| 388 | |
|---|
| 389 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK */ |
|---|
| 390 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_SHIFT 0 |
|---|
| 391 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK_VAL_MASK 0x1 |
|---|
| 392 | |
|---|
| 393 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK */ |
|---|
| 394 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 |
|---|
| 395 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 |
|---|
| 396 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 |
|---|
| 397 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 |
|---|
| 398 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_SHIFT 2 |
|---|
| 399 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK_LBW_MASK 0x4 |
|---|
| 400 | |
|---|
| 401 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR */ |
|---|
| 402 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 403 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 404 | |
|---|
| 405 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR */ |
|---|
| 406 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 407 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 408 | |
|---|
| 409 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR */ |
|---|
| 410 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 411 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 412 | |
|---|
| 413 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR */ |
|---|
| 414 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 415 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 416 | |
|---|
| 417 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR */ |
|---|
| 418 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_SHIFT 0 |
|---|
| 419 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 420 | |
|---|
| 421 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR */ |
|---|
| 422 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_SHIFT 0 |
|---|
| 423 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 424 | |
|---|
| 425 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA */ |
|---|
| 426 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_SHIFT 0 |
|---|
| 427 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF |
|---|
| 428 | |
|---|
| 429 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT */ |
|---|
| 430 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 |
|---|
| 431 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 |
|---|
| 432 | |
|---|
| 433 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L */ |
|---|
| 434 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 |
|---|
| 435 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF |
|---|
| 436 | |
|---|
| 437 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H */ |
|---|
| 438 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 |
|---|
| 439 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF |
|---|
| 440 | |
|---|
| 441 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT */ |
|---|
| 442 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 |
|---|
| 443 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 |
|---|
| 444 | |
|---|
| 445 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR */ |
|---|
| 446 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 |
|---|
| 447 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF |
|---|
| 448 | |
|---|
| 449 | /* DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA */ |
|---|
| 450 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_SHIFT 0 |
|---|
| 451 | #define DCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF |
|---|
| 452 | |
|---|
| 453 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK */ |
|---|
| 454 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_SHIFT 0 |
|---|
| 455 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK_VAL_MASK 0x1 |
|---|
| 456 | |
|---|
| 457 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK */ |
|---|
| 458 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_SHIFT 0 |
|---|
| 459 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_WR_MASK 0x1 |
|---|
| 460 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_SHIFT 1 |
|---|
| 461 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_APB_RD_MASK 0x2 |
|---|
| 462 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_SHIFT 2 |
|---|
| 463 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK_LBW_MASK 0x4 |
|---|
| 464 | |
|---|
| 465 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR */ |
|---|
| 466 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 467 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 468 | |
|---|
| 469 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR */ |
|---|
| 470 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 471 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 472 | |
|---|
| 473 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR */ |
|---|
| 474 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 475 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 476 | |
|---|
| 477 | /* DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR */ |
|---|
| 478 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_SHIFT 0 |
|---|
| 479 | #define DCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR_VAL_MASK 0xFFFFFF |
|---|
| 480 | |
|---|
| 481 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR */ |
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| 482 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_SHIFT 0 |
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| 483 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR_VAL_MASK 0xFFFFFFFF |
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| 484 | |
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| 485 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR */ |
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| 486 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_SHIFT 0 |
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| 487 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR_VAL_MASK 0xFFFFFFFF |
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| 488 | |
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| 489 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA */ |
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| 490 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_SHIFT 0 |
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| 491 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA_VAL_MASK 0xFFFFFFFF |
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| 492 | |
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| 493 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT */ |
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| 494 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_SHIFT 0 |
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| 495 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT_VAL_MASK 0x7 |
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| 496 | |
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| 497 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L */ |
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| 498 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_SHIFT 0 |
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| 499 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L_VAL_MASK 0xFFFFFFFF |
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| 500 | |
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| 501 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H */ |
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| 502 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_SHIFT 0 |
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| 503 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H_VAL_MASK 0xFFFFFFFF |
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| 504 | |
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| 505 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT */ |
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| 506 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_SHIFT 0 |
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| 507 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT_VAL_MASK 0x7 |
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| 508 | |
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| 509 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR */ |
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| 510 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_SHIFT 0 |
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| 511 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR_VAL_MASK 0xFFFFFFFF |
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| 512 | |
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| 513 | /* DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA */ |
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| 514 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_SHIFT 0 |
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| 515 | #define DCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA_VAL_MASK 0xFFFFFFFF |
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| 516 | |
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| 517 | /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID */ |
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| 518 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_SHIFT 0 |
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| 519 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID_ID_MASK 0xFF |
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| 520 | |
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| 521 | /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG */ |
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| 522 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_SHIFT 0 |
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| 523 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_RESP_OK_MASK 0x1 |
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| 524 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_SHIFT 1 |
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| 525 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_FORCE_WR_BUF_MASK 0x2 |
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| 526 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_SHIFT 8 |
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| 527 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_RD_OS_MASK 0xFF00 |
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| 528 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_SHIFT 16 |
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| 529 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG_NUM_WR_OS_MASK 0xFF0000 |
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| 530 | |
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| 531 | /* DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT */ |
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| 532 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_SHIFT 0 |
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| 533 | #define DCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT_VAL_MASK 0x1 |
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| 534 | |
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| 535 | /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK */ |
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| 536 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_SHIFT 1 |
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| 537 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK_MASK_MASK 0x2 |
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| 538 | |
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| 539 | /* DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT */ |
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| 540 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_SHIFT 0 |
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| 541 | #define DCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT_VAL_MASK 0xFFFF |
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| 542 | |
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| 543 | /* DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP */ |
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| 544 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_SHIFT 0 |
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| 545 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP_ERR_RESP_MASK 0x3 |
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| 546 | |
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| 547 | /* DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP */ |
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| 548 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_SHIFT 0 |
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| 549 | #define DCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP_ERR_RESP_MASK 0x3 |
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| 550 | |
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| 551 | /* DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP */ |
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| 552 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_SHIFT 0 |
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| 553 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_WR_ERR_RESP_MASK 0x3 |
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| 554 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_SHIFT 2 |
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| 555 | #define DCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP_RD_ERR_RESP_MASK 0xC |
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| 556 | |
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| 557 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS */ |
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| 558 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_SHIFT 0 |
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| 559 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AW_STA_MASK 0x1 |
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| 560 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_SHIFT 1 |
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| 561 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS_AR_STA_MASK 0x2 |
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| 562 | |
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| 563 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L */ |
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| 564 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_SHIFT 0 |
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| 565 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L_VAL_MASK 0xFFFFFFFF |
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| 566 | |
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| 567 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H */ |
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| 568 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_SHIFT 0 |
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| 569 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H_VAL_MASK 0xFFFFFFFF |
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| 570 | |
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| 571 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L */ |
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| 572 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_SHIFT 0 |
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| 573 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L_VAL_MASK 0xFFFFFFFF |
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| 574 | |
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| 575 | /* DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H */ |
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| 576 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_SHIFT 0 |
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| 577 | #define DCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H_VAL_MASK 0xFFFFFFFF |
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| 578 | |
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| 579 | #endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_MASKS_H_ */ |
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| 580 | |
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