| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE0_VDEC0_BRDG_CTRL |
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| 19 | * (Prototype: VDEC_BRDG_CTRL) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE0_VDEC0_BRDG_CTRL_CGM_DISABLE 0x41E3100 |
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| 24 | |
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| 25 | #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_MASK 0x41E3104 |
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| 26 | |
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| 27 | #define mmDCORE0_VDEC0_BRDG_CTRL_APB_CGM_CNT 0x41E3108 |
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| 28 | |
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| 29 | #define mmDCORE0_VDEC0_BRDG_CTRL_APB_ARB_WDOG_CNT 0x41E310C |
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| 30 | |
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| 31 | #define mmDCORE0_VDEC0_BRDG_CTRL_GRACEFUL 0x41E3110 |
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| 32 | |
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| 33 | #define mmDCORE0_VDEC0_BRDG_CTRL_IDLE_CGM_CNT 0x41E3114 |
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| 34 | |
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| 35 | #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR 0x41E3120 |
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| 36 | |
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| 37 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_CAUSE 0x41E3124 |
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| 38 | |
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| 39 | #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_CAUSE 0x41E3128 |
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| 40 | |
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| 41 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_VIOL_CLR_STICKY_TERM 0x41E312C |
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| 42 | |
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| 43 | #define mmDCORE0_VDEC0_BRDG_CTRL_CAUSE_INTR_MASK 0x41E3130 |
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| 44 | |
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| 45 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_AXI_VIOL_MASK 0x41E3134 |
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| 46 | |
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| 47 | #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_AXI_VIOL_MASK 0x41E3138 |
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| 48 | |
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| 49 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_GIC_INTR_MASK 0x41E3160 |
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| 50 | |
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| 51 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_GIC_INTR_MASK 0x41E3170 |
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| 52 | |
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| 53 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_GIC_INTR_MASK 0x41E3180 |
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| 54 | |
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| 55 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_GIC_INTR_MASK 0x41E3190 |
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| 56 | |
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| 57 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_AWPROT 0x41E31A0 |
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| 58 | |
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| 59 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_ARPROT 0x41E31A4 |
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| 60 | |
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| 61 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_AWPROT 0x41E31B0 |
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| 62 | |
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| 63 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_ARPROT 0x41E31B4 |
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| 64 | |
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| 65 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_AWPROT 0x41E31C0 |
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| 66 | |
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| 67 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_LBW_SLV_ARPROT 0x41E31C4 |
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| 68 | |
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| 69 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_AXI_LEGAL_AXSIZE 0x41E31D0 |
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| 70 | |
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| 71 | #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_MSG_MASK 0x41E3200 |
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| 72 | |
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| 73 | #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_START_LBW_WDATA 0x41E3230 |
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| 74 | |
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| 75 | #define mmDCORE0_VDEC0_BRDG_CTRL_ARC_FINISH_LBW_WDATA 0x41E3260 |
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| 76 | |
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| 77 | #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_SEL 0x41E3270 |
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| 78 | |
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| 79 | #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_TRACE_ADDR 0x41E3280 |
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| 80 | |
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| 81 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_L 0x41E3290 |
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| 82 | |
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| 83 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_CNT_H 0x41E3294 |
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| 84 | |
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| 85 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_L 0x41E32A0 |
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| 86 | |
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| 87 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_FREE_RUN_SET_VALUE_H 0x41E32A4 |
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| 88 | |
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| 89 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_L 0x41E32B0 |
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| 90 | |
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| 91 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_CNT_H 0x41E32B4 |
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| 92 | |
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| 93 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_L 0x41E32C0 |
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| 94 | |
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| 95 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_BUSY_SET_VALUE_H 0x41E32C4 |
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| 96 | |
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| 97 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_CNTR_EN 0x41E32D0 |
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| 98 | |
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| 99 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_INTR_MASK 0x41E3300 |
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| 100 | |
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| 101 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_FLOW_MASK 0x41E3310 |
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| 102 | |
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| 103 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_WAIT_CNTR 0x41E3320 |
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| 104 | |
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| 105 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_WAIT_CNTR 0x41E3330 |
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| 106 | |
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| 107 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_WAIT_CNTR 0x41E3334 |
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| 108 | |
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| 109 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_VCD_MSIX_WAIT_CNTR 0x41E3338 |
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| 110 | |
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| 111 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_SWREG1_ADDR 0x41E3340 |
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| 112 | |
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| 113 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_ADDR 0x41E3350 |
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| 114 | |
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| 115 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_APB_WR_DATA 0x41E3360 |
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| 116 | |
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| 117 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWPROT 0x41E3380 |
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| 118 | |
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| 119 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_L 0x41E3390 |
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| 120 | |
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| 121 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_CPLQ_HBW_AWADDR_H 0x41E3394 |
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| 122 | |
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| 123 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWPROT 0x41E33C0 |
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| 124 | |
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| 125 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_AWADDR 0x41E33D0 |
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| 126 | |
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| 127 | #define mmDCORE0_VDEC0_BRDG_CTRL_VCD_MSIX_LBW_WDATA 0x41E33E0 |
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| 128 | |
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| 129 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_INTR_MASK 0x41E3400 |
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| 130 | |
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| 131 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_FLOW_MASK 0x41E3410 |
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| 132 | |
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| 133 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_WAIT_CNTR 0x41E3420 |
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| 134 | |
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| 135 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_WAIT_CNTR 0x41E3430 |
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| 136 | |
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| 137 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_WAIT_CNTR 0x41E3434 |
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| 138 | |
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| 139 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_L2C_MSIX_WAIT_CNTR 0x41E3438 |
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| 140 | |
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| 141 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_SWREG1_ADDR 0x41E3440 |
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| 142 | |
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| 143 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_ADDR 0x41E3450 |
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| 144 | |
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| 145 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_APB_WR_DATA 0x41E3460 |
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| 146 | |
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| 147 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWPROT 0x41E3480 |
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| 148 | |
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| 149 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_L 0x41E3490 |
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| 150 | |
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| 151 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_CPLQ_HBW_AWADDR_H 0x41E3494 |
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| 152 | |
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| 153 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWPROT 0x41E34C0 |
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| 154 | |
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| 155 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_AWADDR 0x41E34D0 |
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| 156 | |
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| 157 | #define mmDCORE0_VDEC0_BRDG_CTRL_L2C_MSIX_LBW_WDATA 0x41E34E0 |
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| 158 | |
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| 159 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_INTR_MASK 0x41E3500 |
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| 160 | |
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| 161 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_FLOW_MASK 0x41E3510 |
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| 162 | |
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| 163 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_WAIT_CNTR 0x41E3520 |
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| 164 | |
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| 165 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_WAIT_CNTR 0x41E3530 |
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| 166 | |
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| 167 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_WAIT_CNTR 0x41E3534 |
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| 168 | |
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| 169 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_NRM_MSIX_WAIT_CNTR 0x41E3538 |
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| 170 | |
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| 171 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_SWREG1_ADDR 0x41E3540 |
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| 172 | |
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| 173 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_ADDR 0x41E3550 |
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| 174 | |
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| 175 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_APB_WR_DATA 0x41E3560 |
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| 176 | |
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| 177 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWPROT 0x41E3580 |
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| 178 | |
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| 179 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_L 0x41E3590 |
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| 180 | |
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| 181 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_CPLQ_HBW_AWADDR_H 0x41E3594 |
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| 182 | |
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| 183 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWPROT 0x41E35C0 |
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| 184 | |
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| 185 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_AWADDR 0x41E35D0 |
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| 186 | |
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| 187 | #define mmDCORE0_VDEC0_BRDG_CTRL_NRM_MSIX_LBW_WDATA 0x41E35E0 |
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| 188 | |
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| 189 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_INTR_MASK 0x41E3600 |
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| 190 | |
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| 191 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_FLOW_MASK 0x41E3610 |
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| 192 | |
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| 193 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_WAIT_CNTR 0x41E3620 |
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| 194 | |
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| 195 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_WAIT_CNTR 0x41E3630 |
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| 196 | |
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| 197 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_WAIT_CNTR 0x41E3634 |
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| 198 | |
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| 199 | #define mmDCORE0_VDEC0_BRDG_CTRL_STAT_ABNRM_MSIX_WAIT_CNTR 0x41E3638 |
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| 200 | |
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| 201 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_SWREG1_ADDR 0x41E3640 |
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| 202 | |
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| 203 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_ADDR 0x41E3650 |
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| 204 | |
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| 205 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_APB_WR_DATA 0x41E3660 |
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| 206 | |
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| 207 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWPROT 0x41E3680 |
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| 208 | |
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| 209 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_L 0x41E3690 |
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| 210 | |
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| 211 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_CPLQ_HBW_AWADDR_H 0x41E3694 |
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| 212 | |
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| 213 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWPROT 0x41E36C0 |
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| 214 | |
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| 215 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_AWADDR 0x41E36D0 |
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| 216 | |
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| 217 | #define mmDCORE0_VDEC0_BRDG_CTRL_ABNRM_MSIX_LBW_WDATA 0x41E36E0 |
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| 218 | |
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| 219 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_BRESP_ERR_ID 0x41E3700 |
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| 220 | |
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| 221 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_CFG 0x41E3704 |
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| 222 | |
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| 223 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXI_SPLIT_NO_WR_INFLIGHT 0x41E3708 |
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| 224 | |
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| 225 | #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_MASK 0x41E370C |
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| 226 | |
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| 227 | #define mmDCORE0_VDEC0_BRDG_CTRL_HWEVENT_CNTXT 0x41E3714 |
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| 228 | |
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| 229 | #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_SLV_TERM_ERR_RESP 0x41E3718 |
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| 230 | |
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| 231 | #define mmDCORE0_VDEC0_BRDG_CTRL_LBW_MSTR_TERM_ERR_RESP 0x41E371C |
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| 232 | |
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| 233 | #define mmDCORE0_VDEC0_BRDG_CTRL_DEC_HBW_MSTR_ERR_RESP 0x41E3720 |
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| 234 | |
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| 235 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_VIOL_TERM_STATUS 0x41E3724 |
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| 236 | |
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| 237 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_L 0x41E3728 |
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| 238 | |
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| 239 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_AWADDR_TERM_H 0x41E372C |
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| 240 | |
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| 241 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_L 0x41E3730 |
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| 242 | |
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| 243 | #define mmDCORE0_VDEC0_BRDG_CTRL_HBW_LAST_ARADDR_TERM_H 0x41E3734 |
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| 244 | |
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| 245 | #endif /* ASIC_REG_DCORE0_VDEC0_BRDG_CTRL_REGS_H_ */ |
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| 246 | |
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