| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ |
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| 14 | #define ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DCORE3_MME_CTRL_LO |
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| 19 | * (Prototype: MME_CTRL_LO) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmDCORE3_MME_CTRL_LO_ARCH_STATUS 0x46CB000 |
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| 24 | |
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| 25 | #define mmDCORE3_MME_CTRL_LO_CMD 0x46CB004 |
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| 26 | |
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| 27 | #define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0 0x46CB148 |
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| 28 | |
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| 29 | #define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0 0x46CB14C |
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| 30 | |
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| 31 | #define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0 0x46CB150 |
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| 32 | |
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| 33 | #define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1 0x46CB154 |
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| 34 | |
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| 35 | #define mmDCORE3_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1 0x46CB158 |
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| 36 | |
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| 37 | #define mmDCORE3_MME_CTRL_LO_ARCH_A_SS 0x46CB224 |
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| 38 | |
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| 39 | #define mmDCORE3_MME_CTRL_LO_ARCH_B_SS 0x46CB228 |
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| 40 | |
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| 41 | #define mmDCORE3_MME_CTRL_LO_ARCH_COUT_SS 0x46CB27C |
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| 42 | |
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| 43 | #define mmDCORE3_MME_CTRL_LO_QM_STALL 0x46CB400 |
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| 44 | |
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| 45 | #define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_LO 0x46CB404 |
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| 46 | |
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| 47 | #define mmDCORE3_MME_CTRL_LO_LOG_SHADOW_HI 0x46CB408 |
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| 48 | |
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| 49 | #define mmDCORE3_MME_CTRL_LO_SYNC_OBJECT_FIFO_TH 0x46CB40C |
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| 50 | |
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| 51 | #define mmDCORE3_MME_CTRL_LO_REDUN 0x46CB410 |
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| 52 | |
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| 53 | #define mmDCORE3_MME_CTRL_LO_EUS_LOCAL_FIFO_TH 0x46CB414 |
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| 54 | |
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| 55 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW0 0x46CB418 |
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| 56 | |
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| 57 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_DLY_DW1 0x46CB41C |
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| 58 | |
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| 59 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F16 0x46CB420 |
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| 60 | |
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| 61 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_F8 0x46CB424 |
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| 62 | |
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| 63 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32 0x46CB428 |
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| 64 | |
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| 65 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_FP32I 0x46CB42C |
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| 66 | |
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| 67 | #define mmDCORE3_MME_CTRL_LO_EUS_ROLLUP_CD_PROT_TF32 0x46CB430 |
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| 68 | |
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| 69 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_DESC0 0x46CB434 |
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| 70 | |
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| 71 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_TOKEN_UPDATE 0x46CB438 |
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| 72 | |
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| 73 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_TH 0x46CB43C |
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| 74 | |
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| 75 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_MIN 0x46CB440 |
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| 76 | |
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| 77 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_CTRL_EN 0x46CB444 |
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| 78 | |
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| 79 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_HISTORY_LOG_SIZE 0x46CB448 |
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| 80 | |
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| 81 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_BF16 0x46CB44C |
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| 82 | |
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| 83 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_BF16 0x46CB450 |
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| 84 | |
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| 85 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP16 0x46CB454 |
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| 86 | |
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| 87 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP16 0x46CB458 |
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| 88 | |
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| 89 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_F8 0x46CB45C |
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| 90 | |
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| 91 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_ODD 0x46CB460 |
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| 92 | |
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| 93 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_FP32_EVEN 0x46CB464 |
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| 94 | |
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| 95 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_ODD 0x46CB468 |
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| 96 | |
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| 97 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_FP32_EVEN 0x46CB46C |
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| 98 | |
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| 99 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_ODD 0x46CB470 |
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| 100 | |
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| 101 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_A_TF32_EVEN 0x46CB474 |
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| 102 | |
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| 103 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_ODD 0x46CB478 |
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| 104 | |
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| 105 | #define mmDCORE3_MME_CTRL_LO_PCU_DUMMY_B_TF32_EVEN 0x46CB47C |
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| 106 | |
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| 107 | #define mmDCORE3_MME_CTRL_LO_PROT 0x46CB480 |
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| 108 | |
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| 109 | #define mmDCORE3_MME_CTRL_LO_EU 0x46CB484 |
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| 110 | |
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| 111 | #define mmDCORE3_MME_CTRL_LO_SBTE 0x46CB488 |
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| 112 | |
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| 113 | #define mmDCORE3_MME_CTRL_LO_AGU_SM_INFLIGHT_CNTR 0x46CB48C |
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| 114 | |
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| 115 | #define mmDCORE3_MME_CTRL_LO_AGU_SM_TOTAL_CNTR 0x46CB490 |
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| 116 | |
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| 117 | #define mmDCORE3_MME_CTRL_LO_PCU_RL_SAT_SEC 0x46CB494 |
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| 118 | |
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| 119 | #define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN32 0x46CB498 |
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| 120 | |
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| 121 | #define mmDCORE3_MME_CTRL_LO_FMA_FUNC_REDUN_CLK_EN33 0x46CB49C |
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| 122 | |
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| 123 | #define mmDCORE3_MME_CTRL_LO_EU_ISOLATION_DIS 0x46CB4A0 |
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| 124 | |
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| 125 | #define mmDCORE3_MME_CTRL_LO_QM_SLV_CLK_EN 0x46CB4A4 |
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| 126 | |
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| 127 | #define mmDCORE3_MME_CTRL_LO_HBW_CLK_ENABLER_DIS 0x46CB4A8 |
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| 128 | |
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| 129 | #define mmDCORE3_MME_CTRL_LO_AGU 0x46CB4AC |
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| 130 | |
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| 131 | #define mmDCORE3_MME_CTRL_LO_QM 0x46CB4B0 |
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| 132 | |
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| 133 | #define mmDCORE3_MME_CTRL_LO_EARLY_RELEASE_STATUS 0x46CB4B4 |
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| 134 | |
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| 135 | #define mmDCORE3_MME_CTRL_LO_INTR_CAUSE 0x46CB4B8 |
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| 136 | |
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| 137 | #define mmDCORE3_MME_CTRL_LO_INTR_MASK 0x46CB4BC |
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| 138 | |
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| 139 | #define mmDCORE3_MME_CTRL_LO_INTR_CLEAR 0x46CB4C0 |
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| 140 | |
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| 141 | #define mmDCORE3_MME_CTRL_LO_REDUN_PSOC_SEL_SEC 0x46CB4C4 |
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| 142 | |
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| 143 | #define mmDCORE3_MME_CTRL_LO_BIST 0x46CB4C8 |
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| 144 | |
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| 145 | #define mmDCORE3_MME_CTRL_LO_EU_RL_ENABLE 0x46CB4CC |
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| 146 | |
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| 147 | #define mmDCORE3_MME_CTRL_LO_EU_RL_TOKEN_SEL 0x46CB4D0 |
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| 148 | |
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| 149 | #define mmDCORE3_MME_CTRL_LO_EU_RL_CFG 0x46CB4D4 |
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| 150 | |
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| 151 | #define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW0 0x46CB4D8 |
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| 152 | |
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| 153 | #define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW1 0x46CB4DC |
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| 154 | |
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| 155 | #define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW2 0x46CB4E0 |
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| 156 | |
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| 157 | #define mmDCORE3_MME_CTRL_LO_PCU_DBG_DW3 0x46CB4E4 |
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| 158 | |
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| 159 | #define mmDCORE3_MME_CTRL_LO_PCU_DBG_WKL_ID 0x46CB4E8 |
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| 160 | |
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| 161 | #define mmDCORE3_MME_CTRL_LO_ETF_MEM_WRAP_RM 0x46CB4EC |
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| 162 | |
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| 163 | #endif /* ASIC_REG_DCORE3_MME_CTRL_LO_REGS_H_ */ |
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| 164 | |
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