| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef GAUDI2_BLOCKS_LINUX_DRIVER_H_ |
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| 14 | #define GAUDI2_BLOCKS_LINUX_DRIVER_H_ |
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| 15 | |
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| 16 | #define mmDCORE0_TPC0_ROM_TABLE_BASE 0x0ull |
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| 17 | #define DCORE0_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 |
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| 18 | #define DCORE0_TPC0_ROM_TABLE_SECTION 0x1000 |
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| 19 | #define mmDCORE0_TPC0_EML_SPMU_BASE 0x1000ull |
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| 20 | #define DCORE0_TPC0_EML_SPMU_MAX_OFFSET 0x1000 |
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| 21 | #define DCORE0_TPC0_EML_SPMU_SECTION 0x1000 |
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| 22 | #define mmDCORE0_TPC0_EML_ETF_BASE 0x2000ull |
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| 23 | #define DCORE0_TPC0_EML_ETF_MAX_OFFSET 0x1000 |
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| 24 | #define DCORE0_TPC0_EML_ETF_SECTION 0x1000 |
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| 25 | #define mmDCORE0_TPC0_EML_STM_BASE 0x3000ull |
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| 26 | #define DCORE0_TPC0_EML_STM_MAX_OFFSET 0x1000 |
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| 27 | #define DCORE0_TPC0_EML_STM_SECTION 0x2000 |
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| 28 | #define mmDCORE0_TPC0_EML_CTI_BASE 0x5000ull |
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| 29 | #define DCORE0_TPC0_EML_CTI_MAX_OFFSET 0x1000 |
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| 30 | #define DCORE0_TPC0_EML_CTI_SECTION 0x1000 |
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| 31 | #define mmDCORE0_TPC0_EML_FUNNEL_BASE 0x6000ull |
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| 32 | #define DCORE0_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 |
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| 33 | #define DCORE0_TPC0_EML_FUNNEL_SECTION 0x1000 |
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| 34 | #define mmDCORE0_TPC0_EML_BUSMON_0_BASE 0x7000ull |
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| 35 | #define DCORE0_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 |
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| 36 | #define DCORE0_TPC0_EML_BUSMON_0_SECTION 0x1000 |
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| 37 | #define mmDCORE0_TPC0_EML_BUSMON_1_BASE 0x8000ull |
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| 38 | #define DCORE0_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 |
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| 39 | #define DCORE0_TPC0_EML_BUSMON_1_SECTION 0x1000 |
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| 40 | #define mmDCORE0_TPC0_EML_BUSMON_2_BASE 0x9000ull |
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| 41 | #define DCORE0_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 |
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| 42 | #define DCORE0_TPC0_EML_BUSMON_2_SECTION 0x1000 |
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| 43 | #define mmDCORE0_TPC0_EML_BUSMON_3_BASE 0xA000ull |
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| 44 | #define DCORE0_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 |
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| 45 | #define DCORE0_TPC0_EML_BUSMON_3_SECTION 0x1000 |
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| 46 | #define mmDCORE0_TPC0_QM_ARC_RTT_BASE 0xB000ull |
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| 47 | #define DCORE0_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 |
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| 48 | #define DCORE0_TPC0_QM_ARC_RTT_SECTION 0x35000 |
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| 49 | #define mmDCORE0_TPC0_EML_CFG_BASE 0x40000ull |
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| 50 | #define DCORE0_TPC0_EML_CFG_MAX_OFFSET 0x1000 |
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| 51 | #define DCORE0_TPC0_EML_CFG_SECTION 0xE800 |
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| 52 | #define mmDCORE0_TPC0_EML_CFG_SPECIAL_BASE 0x40E80ull |
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| 53 | #define DCORE0_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 54 | #define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 55 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x41000ull |
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| 56 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
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| 57 | #define DCORE0_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 58 | #define mmDCORE0_TPC0_EML_TPC_CFG_BASE 0x41000ull |
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| 59 | #define DCORE0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 |
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| 60 | #define DCORE0_TPC0_EML_TPC_CFG_SECTION 0x5000 |
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| 61 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x41050ull |
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| 62 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
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| 63 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
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| 64 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x410A0ull |
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| 65 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
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| 66 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
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| 67 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x410F0ull |
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| 68 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
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| 69 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
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| 70 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x41140ull |
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| 71 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
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| 72 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
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| 73 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x41190ull |
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| 74 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
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| 75 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
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| 76 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x411E0ull |
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| 77 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
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| 78 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
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| 79 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x41230ull |
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| 80 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
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| 81 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
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| 82 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x41280ull |
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| 83 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
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| 84 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
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| 85 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x412D0ull |
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| 86 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
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| 87 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
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| 88 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x41320ull |
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| 89 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
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| 90 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
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| 91 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x41370ull |
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| 92 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
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| 93 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
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| 94 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x413C0ull |
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| 95 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
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| 96 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
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| 97 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x41410ull |
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| 98 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
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| 99 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
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| 100 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x41460ull |
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| 101 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
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| 102 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
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| 103 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x414B0ull |
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| 104 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
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| 105 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
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| 106 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x41500ull |
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| 107 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
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| 108 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
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| 109 | #define mmDCORE0_TPC0_EML_TPC_CFG_KERNEL_BASE 0x41508ull |
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| 110 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
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| 111 | #define DCORE0_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
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| 112 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x415DCull |
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| 113 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
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| 114 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
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| 115 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x4162Cull |
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| 116 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
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| 117 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
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| 118 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x4167Cull |
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| 119 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
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| 120 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
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| 121 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x416CCull |
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| 122 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
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| 123 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
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| 124 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x4171Cull |
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| 125 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
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| 126 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
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| 127 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x4176Cull |
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| 128 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
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| 129 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
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| 130 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x417BCull |
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| 131 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
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| 132 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
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| 133 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x4180Cull |
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| 134 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
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| 135 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
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| 136 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x4185Cull |
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| 137 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
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| 138 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
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| 139 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x418ACull |
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| 140 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
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| 141 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
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| 142 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x418FCull |
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| 143 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
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| 144 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
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| 145 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x4194Cull |
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| 146 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
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| 147 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
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| 148 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x4199Cull |
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| 149 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
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| 150 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
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| 151 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x419ECull |
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| 152 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
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| 153 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
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| 154 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x41A3Cull |
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| 155 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
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| 156 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
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| 157 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x41A8Cull |
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| 158 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
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| 159 | #define DCORE0_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
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| 160 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x41ADCull |
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| 161 | #define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
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| 162 | #define DCORE0_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
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| 163 | #define mmDCORE0_TPC0_EML_TPC_CFG_QM_BASE 0x41AE4ull |
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| 164 | #define DCORE0_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
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| 165 | #define DCORE0_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 |
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| 166 | #define mmDCORE0_TPC0_EML_TPC_CFG_AXUSER_BASE 0x41E00ull |
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| 167 | #define DCORE0_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
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| 168 | #define DCORE0_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
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| 169 | #define mmDCORE0_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x41E80ull |
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| 170 | #define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 171 | #define DCORE0_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
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| 172 | #define mmDCORE0_TPC0_EML_QM_DCCM_BASE 0x42000ull |
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| 173 | #define DCORE0_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 |
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| 174 | #define DCORE0_TPC0_EML_QM_DCCM_SECTION 0x8000 |
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| 175 | #define mmDCORE0_TPC0_EML_QM_ARCAUX_BASE 0x4A000ull |
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| 176 | #define DCORE0_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
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| 177 | #define DCORE0_TPC0_EML_QM_ARCAUX_SECTION 0xE800 |
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| 178 | #define mmDCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x4AE80ull |
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| 179 | #define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
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| 180 | #define DCORE0_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
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| 181 | #define mmDCORE0_TPC0_EML_TPC_QM_BASE 0x4C000ull |
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| 182 | #define DCORE0_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 |
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| 183 | #define DCORE0_TPC0_EML_TPC_QM_SECTION 0x9000 |
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| 184 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x4C900ull |
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| 185 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
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| 186 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
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| 187 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x4C908ull |
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| 188 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
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| 189 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
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| 190 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x4C910ull |
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| 191 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
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| 192 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
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| 193 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x4C918ull |
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| 194 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
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| 195 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
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| 196 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x4C920ull |
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| 197 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
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| 198 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
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| 199 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x4C928ull |
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| 200 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
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| 201 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
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| 202 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x4C930ull |
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| 203 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
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| 204 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
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| 205 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x4C938ull |
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| 206 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
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| 207 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
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| 208 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x4C940ull |
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| 209 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
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| 210 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
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| 211 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x4C948ull |
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| 212 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
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| 213 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
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| 214 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x4C950ull |
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| 215 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
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| 216 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
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| 217 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x4C958ull |
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| 218 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
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| 219 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
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| 220 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x4C960ull |
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| 221 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
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| 222 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
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| 223 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x4C968ull |
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| 224 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
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| 225 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
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| 226 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x4C970ull |
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| 227 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
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| 228 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
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| 229 | #define mmDCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x4C978ull |
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| 230 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
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| 231 | #define DCORE0_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
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| 232 | #define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x4CB00ull |
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| 233 | #define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
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| 234 | #define DCORE0_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
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| 235 | #define mmDCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x4CB80ull |
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| 236 | #define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
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| 237 | #define DCORE0_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
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| 238 | #define mmDCORE0_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x4CC00ull |
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| 239 | #define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
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| 240 | #define DCORE0_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
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| 241 | #define mmDCORE0_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x4CC80ull |
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| 242 | #define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
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| 243 | #define DCORE0_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
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| 244 | #define mmDCORE0_TPC0_EML_TPC_QM_CGM_BASE 0x4CD80ull |
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| 245 | #define DCORE0_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
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| 246 | #define DCORE0_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 |
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| 247 | #define mmDCORE0_TPC0_EML_TPC_QM_SPECIAL_BASE 0x4CE80ull |
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| 248 | #define DCORE0_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
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| 249 | #define DCORE0_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
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| 250 | #define mmDCORE0_TPC0_EML_CS_BASE 0x1FF000ull |
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| 251 | #define DCORE0_TPC0_EML_CS_MAX_OFFSET 0x1000 |
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| 252 | #define DCORE0_TPC0_EML_CS_SECTION 0x1000 |
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| 253 | #define mmDCORE0_TPC1_ROM_TABLE_BASE 0x200000ull |
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| 254 | #define DCORE0_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 |
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| 255 | #define DCORE0_TPC1_ROM_TABLE_SECTION 0x1000 |
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| 256 | #define mmDCORE0_TPC1_EML_SPMU_BASE 0x201000ull |
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| 257 | #define DCORE0_TPC1_EML_SPMU_MAX_OFFSET 0x1000 |
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| 258 | #define DCORE0_TPC1_EML_SPMU_SECTION 0x1000 |
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| 259 | #define mmDCORE0_TPC1_EML_ETF_BASE 0x202000ull |
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| 260 | #define DCORE0_TPC1_EML_ETF_MAX_OFFSET 0x1000 |
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| 261 | #define DCORE0_TPC1_EML_ETF_SECTION 0x1000 |
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| 262 | #define mmDCORE0_TPC1_EML_STM_BASE 0x203000ull |
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| 263 | #define DCORE0_TPC1_EML_STM_MAX_OFFSET 0x1000 |
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| 264 | #define DCORE0_TPC1_EML_STM_SECTION 0x2000 |
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| 265 | #define mmDCORE0_TPC1_EML_CTI_BASE 0x205000ull |
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| 266 | #define DCORE0_TPC1_EML_CTI_MAX_OFFSET 0x1000 |
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| 267 | #define DCORE0_TPC1_EML_CTI_SECTION 0x1000 |
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| 268 | #define mmDCORE0_TPC1_EML_FUNNEL_BASE 0x206000ull |
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| 269 | #define DCORE0_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 |
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| 270 | #define DCORE0_TPC1_EML_FUNNEL_SECTION 0x1000 |
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| 271 | #define mmDCORE0_TPC1_EML_BUSMON_0_BASE 0x207000ull |
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| 272 | #define DCORE0_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 |
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| 273 | #define DCORE0_TPC1_EML_BUSMON_0_SECTION 0x1000 |
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| 274 | #define mmDCORE0_TPC1_EML_BUSMON_1_BASE 0x208000ull |
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| 275 | #define DCORE0_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 |
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| 276 | #define DCORE0_TPC1_EML_BUSMON_1_SECTION 0x1000 |
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| 277 | #define mmDCORE0_TPC1_EML_BUSMON_2_BASE 0x209000ull |
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| 278 | #define DCORE0_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 |
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| 279 | #define DCORE0_TPC1_EML_BUSMON_2_SECTION 0x1000 |
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| 280 | #define mmDCORE0_TPC1_EML_BUSMON_3_BASE 0x20A000ull |
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| 281 | #define DCORE0_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 |
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| 282 | #define DCORE0_TPC1_EML_BUSMON_3_SECTION 0x1000 |
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| 283 | #define mmDCORE0_TPC1_QM_ARC_RTT_BASE 0x20B000ull |
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| 284 | #define DCORE0_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 |
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| 285 | #define DCORE0_TPC1_QM_ARC_RTT_SECTION 0x35000 |
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| 286 | #define mmDCORE0_TPC1_EML_CFG_BASE 0x240000ull |
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| 287 | #define DCORE0_TPC1_EML_CFG_MAX_OFFSET 0x1000 |
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| 288 | #define DCORE0_TPC1_EML_CFG_SECTION 0xE800 |
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| 289 | #define mmDCORE0_TPC1_EML_CFG_SPECIAL_BASE 0x240E80ull |
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| 290 | #define DCORE0_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 291 | #define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 292 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x241000ull |
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| 293 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
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| 294 | #define DCORE0_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 295 | #define mmDCORE0_TPC1_EML_TPC_CFG_BASE 0x241000ull |
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| 296 | #define DCORE0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 |
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| 297 | #define DCORE0_TPC1_EML_TPC_CFG_SECTION 0x5000 |
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| 298 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x241050ull |
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| 299 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
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| 300 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
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| 301 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2410A0ull |
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| 302 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
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| 303 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
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| 304 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2410F0ull |
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| 305 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
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| 306 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
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| 307 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x241140ull |
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| 308 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
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| 309 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
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| 310 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x241190ull |
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| 311 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
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| 312 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
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| 313 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2411E0ull |
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| 314 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
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| 315 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
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| 316 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x241230ull |
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| 317 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
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| 318 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
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| 319 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x241280ull |
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| 320 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
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| 321 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
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| 322 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2412D0ull |
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| 323 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
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| 324 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
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| 325 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x241320ull |
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| 326 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
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| 327 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
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| 328 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x241370ull |
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| 329 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
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| 330 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
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| 331 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2413C0ull |
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| 332 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
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| 333 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
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| 334 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x241410ull |
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| 335 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
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| 336 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
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| 337 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x241460ull |
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| 338 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
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| 339 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
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| 340 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2414B0ull |
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| 341 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
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| 342 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
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| 343 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x241500ull |
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| 344 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
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| 345 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
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| 346 | #define mmDCORE0_TPC1_EML_TPC_CFG_KERNEL_BASE 0x241508ull |
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| 347 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
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| 348 | #define DCORE0_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
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| 349 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2415DCull |
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| 350 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
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| 351 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
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| 352 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x24162Cull |
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| 353 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
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| 354 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
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| 355 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x24167Cull |
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| 356 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
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| 357 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
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| 358 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2416CCull |
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| 359 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
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| 360 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
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| 361 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x24171Cull |
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| 362 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
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| 363 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
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| 364 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x24176Cull |
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| 365 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
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| 366 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
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| 367 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2417BCull |
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| 368 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
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| 369 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
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| 370 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x24180Cull |
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| 371 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
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| 372 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
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| 373 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x24185Cull |
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| 374 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
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| 375 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
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| 376 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2418ACull |
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| 377 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
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| 378 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
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| 379 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2418FCull |
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| 380 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
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| 381 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
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| 382 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x24194Cull |
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| 383 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
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| 384 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
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| 385 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x24199Cull |
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| 386 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
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| 387 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
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| 388 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2419ECull |
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| 389 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
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| 390 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
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| 391 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x241A3Cull |
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| 392 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 393 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
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| 394 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x241A8Cull |
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| 395 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 396 | #define DCORE0_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
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| 397 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x241ADCull |
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| 398 | #define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
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| 399 | #define DCORE0_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
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| 400 | #define mmDCORE0_TPC1_EML_TPC_CFG_QM_BASE 0x241AE4ull |
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| 401 | #define DCORE0_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 402 | #define DCORE0_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 |
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| 403 | #define mmDCORE0_TPC1_EML_TPC_CFG_AXUSER_BASE 0x241E00ull |
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| 404 | #define DCORE0_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
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| 405 | #define DCORE0_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
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| 406 | #define mmDCORE0_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x241E80ull |
|---|
| 407 | #define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 408 | #define DCORE0_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
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| 409 | #define mmDCORE0_TPC1_EML_QM_DCCM_BASE 0x242000ull |
|---|
| 410 | #define DCORE0_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 411 | #define DCORE0_TPC1_EML_QM_DCCM_SECTION 0x8000 |
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| 412 | #define mmDCORE0_TPC1_EML_QM_ARCAUX_BASE 0x24A000ull |
|---|
| 413 | #define DCORE0_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 414 | #define DCORE0_TPC1_EML_QM_ARCAUX_SECTION 0xE800 |
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| 415 | #define mmDCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x24AE80ull |
|---|
| 416 | #define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
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| 417 | #define DCORE0_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
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| 418 | #define mmDCORE0_TPC1_EML_TPC_QM_BASE 0x24C000ull |
|---|
| 419 | #define DCORE0_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 420 | #define DCORE0_TPC1_EML_TPC_QM_SECTION 0x9000 |
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| 421 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x24C900ull |
|---|
| 422 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
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| 423 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
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| 424 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x24C908ull |
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| 425 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
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| 426 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 427 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x24C910ull |
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| 428 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
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| 429 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 430 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x24C918ull |
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| 431 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
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| 432 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
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| 433 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x24C920ull |
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| 434 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
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| 435 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
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| 436 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x24C928ull |
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| 437 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
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| 438 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
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| 439 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x24C930ull |
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| 440 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
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| 441 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
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| 442 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x24C938ull |
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| 443 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
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| 444 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
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| 445 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x24C940ull |
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| 446 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 447 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
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| 448 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x24C948ull |
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| 449 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
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| 450 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
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| 451 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x24C950ull |
|---|
| 452 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
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| 453 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 454 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x24C958ull |
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| 455 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
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| 456 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 457 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x24C960ull |
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| 458 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
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| 459 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
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| 460 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x24C968ull |
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| 461 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
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| 462 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
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| 463 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x24C970ull |
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| 464 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 465 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 466 | #define mmDCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x24C978ull |
|---|
| 467 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 468 | #define DCORE0_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
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| 469 | #define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x24CB00ull |
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| 470 | #define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 471 | #define DCORE0_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
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| 472 | #define mmDCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x24CB80ull |
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| 473 | #define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
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| 474 | #define DCORE0_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
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| 475 | #define mmDCORE0_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x24CC00ull |
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| 476 | #define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 477 | #define DCORE0_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
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| 478 | #define mmDCORE0_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x24CC80ull |
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| 479 | #define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 480 | #define DCORE0_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
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| 481 | #define mmDCORE0_TPC1_EML_TPC_QM_CGM_BASE 0x24CD80ull |
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| 482 | #define DCORE0_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
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| 483 | #define DCORE0_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 |
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| 484 | #define mmDCORE0_TPC1_EML_TPC_QM_SPECIAL_BASE 0x24CE80ull |
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| 485 | #define DCORE0_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
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| 486 | #define DCORE0_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
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| 487 | #define mmDCORE0_TPC1_EML_CS_BASE 0x3FF000ull |
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| 488 | #define DCORE0_TPC1_EML_CS_MAX_OFFSET 0x1000 |
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| 489 | #define DCORE0_TPC1_EML_CS_SECTION 0x1000 |
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| 490 | #define mmDCORE0_TPC2_ROM_TABLE_BASE 0x400000ull |
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| 491 | #define DCORE0_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 |
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| 492 | #define DCORE0_TPC2_ROM_TABLE_SECTION 0x1000 |
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| 493 | #define mmDCORE0_TPC2_EML_SPMU_BASE 0x401000ull |
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| 494 | #define DCORE0_TPC2_EML_SPMU_MAX_OFFSET 0x1000 |
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| 495 | #define DCORE0_TPC2_EML_SPMU_SECTION 0x1000 |
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| 496 | #define mmDCORE0_TPC2_EML_ETF_BASE 0x402000ull |
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| 497 | #define DCORE0_TPC2_EML_ETF_MAX_OFFSET 0x1000 |
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| 498 | #define DCORE0_TPC2_EML_ETF_SECTION 0x1000 |
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| 499 | #define mmDCORE0_TPC2_EML_STM_BASE 0x403000ull |
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| 500 | #define DCORE0_TPC2_EML_STM_MAX_OFFSET 0x1000 |
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| 501 | #define DCORE0_TPC2_EML_STM_SECTION 0x2000 |
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| 502 | #define mmDCORE0_TPC2_EML_CTI_BASE 0x405000ull |
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| 503 | #define DCORE0_TPC2_EML_CTI_MAX_OFFSET 0x1000 |
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| 504 | #define DCORE0_TPC2_EML_CTI_SECTION 0x1000 |
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| 505 | #define mmDCORE0_TPC2_EML_FUNNEL_BASE 0x406000ull |
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| 506 | #define DCORE0_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 |
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| 507 | #define DCORE0_TPC2_EML_FUNNEL_SECTION 0x1000 |
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| 508 | #define mmDCORE0_TPC2_EML_BUSMON_0_BASE 0x407000ull |
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| 509 | #define DCORE0_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 |
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| 510 | #define DCORE0_TPC2_EML_BUSMON_0_SECTION 0x1000 |
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| 511 | #define mmDCORE0_TPC2_EML_BUSMON_1_BASE 0x408000ull |
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| 512 | #define DCORE0_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 |
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| 513 | #define DCORE0_TPC2_EML_BUSMON_1_SECTION 0x1000 |
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| 514 | #define mmDCORE0_TPC2_EML_BUSMON_2_BASE 0x409000ull |
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| 515 | #define DCORE0_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 |
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| 516 | #define DCORE0_TPC2_EML_BUSMON_2_SECTION 0x1000 |
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| 517 | #define mmDCORE0_TPC2_EML_BUSMON_3_BASE 0x40A000ull |
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| 518 | #define DCORE0_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 |
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| 519 | #define DCORE0_TPC2_EML_BUSMON_3_SECTION 0x1000 |
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| 520 | #define mmDCORE0_TPC2_QM_ARC_RTT_BASE 0x40B000ull |
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| 521 | #define DCORE0_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 |
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| 522 | #define DCORE0_TPC2_QM_ARC_RTT_SECTION 0x35000 |
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| 523 | #define mmDCORE0_TPC2_EML_CFG_BASE 0x440000ull |
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| 524 | #define DCORE0_TPC2_EML_CFG_MAX_OFFSET 0x1000 |
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| 525 | #define DCORE0_TPC2_EML_CFG_SECTION 0xE800 |
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| 526 | #define mmDCORE0_TPC2_EML_CFG_SPECIAL_BASE 0x440E80ull |
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| 527 | #define DCORE0_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 528 | #define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 529 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x441000ull |
|---|
| 530 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 531 | #define DCORE0_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 532 | #define mmDCORE0_TPC2_EML_TPC_CFG_BASE 0x441000ull |
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| 533 | #define DCORE0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 |
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| 534 | #define DCORE0_TPC2_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 535 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x441050ull |
|---|
| 536 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 537 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 538 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x4410A0ull |
|---|
| 539 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 540 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 541 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x4410F0ull |
|---|
| 542 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 543 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 544 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x441140ull |
|---|
| 545 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 546 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 547 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x441190ull |
|---|
| 548 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 549 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 550 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x4411E0ull |
|---|
| 551 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 552 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 553 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x441230ull |
|---|
| 554 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 555 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 556 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x441280ull |
|---|
| 557 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 558 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 559 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x4412D0ull |
|---|
| 560 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 561 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 562 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x441320ull |
|---|
| 563 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 564 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 565 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x441370ull |
|---|
| 566 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 567 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 568 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x4413C0ull |
|---|
| 569 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 570 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 571 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x441410ull |
|---|
| 572 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 573 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 574 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x441460ull |
|---|
| 575 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 576 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 577 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x4414B0ull |
|---|
| 578 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 579 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 580 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x441500ull |
|---|
| 581 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 582 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 583 | #define mmDCORE0_TPC2_EML_TPC_CFG_KERNEL_BASE 0x441508ull |
|---|
| 584 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 585 | #define DCORE0_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 586 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x4415DCull |
|---|
| 587 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 588 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 589 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x44162Cull |
|---|
| 590 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 591 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 592 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x44167Cull |
|---|
| 593 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 594 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 595 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x4416CCull |
|---|
| 596 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 597 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 598 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x44171Cull |
|---|
| 599 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 600 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 601 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x44176Cull |
|---|
| 602 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 603 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 604 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x4417BCull |
|---|
| 605 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 606 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 607 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x44180Cull |
|---|
| 608 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 609 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 610 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x44185Cull |
|---|
| 611 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 612 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 613 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x4418ACull |
|---|
| 614 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 615 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 616 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x4418FCull |
|---|
| 617 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 618 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 619 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x44194Cull |
|---|
| 620 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 621 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 622 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x44199Cull |
|---|
| 623 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 624 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 625 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x4419ECull |
|---|
| 626 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 627 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 628 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x441A3Cull |
|---|
| 629 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 630 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 631 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x441A8Cull |
|---|
| 632 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 633 | #define DCORE0_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 634 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x441ADCull |
|---|
| 635 | #define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 636 | #define DCORE0_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 637 | #define mmDCORE0_TPC2_EML_TPC_CFG_QM_BASE 0x441AE4ull |
|---|
| 638 | #define DCORE0_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 639 | #define DCORE0_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 640 | #define mmDCORE0_TPC2_EML_TPC_CFG_AXUSER_BASE 0x441E00ull |
|---|
| 641 | #define DCORE0_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 642 | #define DCORE0_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 643 | #define mmDCORE0_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x441E80ull |
|---|
| 644 | #define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 645 | #define DCORE0_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 646 | #define mmDCORE0_TPC2_EML_QM_DCCM_BASE 0x442000ull |
|---|
| 647 | #define DCORE0_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 648 | #define DCORE0_TPC2_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 649 | #define mmDCORE0_TPC2_EML_QM_ARCAUX_BASE 0x44A000ull |
|---|
| 650 | #define DCORE0_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 651 | #define DCORE0_TPC2_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 652 | #define mmDCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x44AE80ull |
|---|
| 653 | #define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 654 | #define DCORE0_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 655 | #define mmDCORE0_TPC2_EML_TPC_QM_BASE 0x44C000ull |
|---|
| 656 | #define DCORE0_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 657 | #define DCORE0_TPC2_EML_TPC_QM_SECTION 0x9000 |
|---|
| 658 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44C900ull |
|---|
| 659 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 660 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 661 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44C908ull |
|---|
| 662 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 663 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 664 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44C910ull |
|---|
| 665 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 666 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 667 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44C918ull |
|---|
| 668 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 669 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 670 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44C920ull |
|---|
| 671 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 672 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 673 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44C928ull |
|---|
| 674 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 675 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 676 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44C930ull |
|---|
| 677 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 678 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 679 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44C938ull |
|---|
| 680 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 681 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 682 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44C940ull |
|---|
| 683 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 684 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 685 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44C948ull |
|---|
| 686 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 687 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 688 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44C950ull |
|---|
| 689 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 690 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 691 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44C958ull |
|---|
| 692 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 693 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 694 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44C960ull |
|---|
| 695 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 696 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 697 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44C968ull |
|---|
| 698 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 699 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 700 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44C970ull |
|---|
| 701 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 702 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 703 | #define mmDCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44C978ull |
|---|
| 704 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 705 | #define DCORE0_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 706 | #define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x44CB00ull |
|---|
| 707 | #define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 708 | #define DCORE0_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 709 | #define mmDCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x44CB80ull |
|---|
| 710 | #define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 711 | #define DCORE0_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 712 | #define mmDCORE0_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x44CC00ull |
|---|
| 713 | #define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 714 | #define DCORE0_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 715 | #define mmDCORE0_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x44CC80ull |
|---|
| 716 | #define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 717 | #define DCORE0_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 718 | #define mmDCORE0_TPC2_EML_TPC_QM_CGM_BASE 0x44CD80ull |
|---|
| 719 | #define DCORE0_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 720 | #define DCORE0_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 721 | #define mmDCORE0_TPC2_EML_TPC_QM_SPECIAL_BASE 0x44CE80ull |
|---|
| 722 | #define DCORE0_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 723 | #define DCORE0_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 724 | #define mmDCORE0_TPC2_EML_CS_BASE 0x5FF000ull |
|---|
| 725 | #define DCORE0_TPC2_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 726 | #define DCORE0_TPC2_EML_CS_SECTION 0x1000 |
|---|
| 727 | #define mmDCORE0_TPC3_ROM_TABLE_BASE 0x600000ull |
|---|
| 728 | #define DCORE0_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 729 | #define DCORE0_TPC3_ROM_TABLE_SECTION 0x1000 |
|---|
| 730 | #define mmDCORE0_TPC3_EML_SPMU_BASE 0x601000ull |
|---|
| 731 | #define DCORE0_TPC3_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 732 | #define DCORE0_TPC3_EML_SPMU_SECTION 0x1000 |
|---|
| 733 | #define mmDCORE0_TPC3_EML_ETF_BASE 0x602000ull |
|---|
| 734 | #define DCORE0_TPC3_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 735 | #define DCORE0_TPC3_EML_ETF_SECTION 0x1000 |
|---|
| 736 | #define mmDCORE0_TPC3_EML_STM_BASE 0x603000ull |
|---|
| 737 | #define DCORE0_TPC3_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 738 | #define DCORE0_TPC3_EML_STM_SECTION 0x2000 |
|---|
| 739 | #define mmDCORE0_TPC3_EML_CTI_BASE 0x605000ull |
|---|
| 740 | #define DCORE0_TPC3_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 741 | #define DCORE0_TPC3_EML_CTI_SECTION 0x1000 |
|---|
| 742 | #define mmDCORE0_TPC3_EML_FUNNEL_BASE 0x606000ull |
|---|
| 743 | #define DCORE0_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 744 | #define DCORE0_TPC3_EML_FUNNEL_SECTION 0x1000 |
|---|
| 745 | #define mmDCORE0_TPC3_EML_BUSMON_0_BASE 0x607000ull |
|---|
| 746 | #define DCORE0_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 747 | #define DCORE0_TPC3_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 748 | #define mmDCORE0_TPC3_EML_BUSMON_1_BASE 0x608000ull |
|---|
| 749 | #define DCORE0_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 750 | #define DCORE0_TPC3_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 751 | #define mmDCORE0_TPC3_EML_BUSMON_2_BASE 0x609000ull |
|---|
| 752 | #define DCORE0_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 753 | #define DCORE0_TPC3_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 754 | #define mmDCORE0_TPC3_EML_BUSMON_3_BASE 0x60A000ull |
|---|
| 755 | #define DCORE0_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 756 | #define DCORE0_TPC3_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 757 | #define mmDCORE0_TPC3_QM_ARC_RTT_BASE 0x60B000ull |
|---|
| 758 | #define DCORE0_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 759 | #define DCORE0_TPC3_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 760 | #define mmDCORE0_TPC3_EML_CFG_BASE 0x640000ull |
|---|
| 761 | #define DCORE0_TPC3_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 762 | #define DCORE0_TPC3_EML_CFG_SECTION 0xE800 |
|---|
| 763 | #define mmDCORE0_TPC3_EML_CFG_SPECIAL_BASE 0x640E80ull |
|---|
| 764 | #define DCORE0_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 765 | #define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 766 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x641000ull |
|---|
| 767 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 768 | #define DCORE0_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 769 | #define mmDCORE0_TPC3_EML_TPC_CFG_BASE 0x641000ull |
|---|
| 770 | #define DCORE0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 771 | #define DCORE0_TPC3_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 772 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x641050ull |
|---|
| 773 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 774 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 775 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x6410A0ull |
|---|
| 776 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 777 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 778 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x6410F0ull |
|---|
| 779 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 780 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 781 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x641140ull |
|---|
| 782 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 783 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 784 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x641190ull |
|---|
| 785 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 786 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 787 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x6411E0ull |
|---|
| 788 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 789 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 790 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x641230ull |
|---|
| 791 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 792 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 793 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x641280ull |
|---|
| 794 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 795 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 796 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x6412D0ull |
|---|
| 797 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 798 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 799 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x641320ull |
|---|
| 800 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 801 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 802 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x641370ull |
|---|
| 803 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 804 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 805 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x6413C0ull |
|---|
| 806 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 807 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 808 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x641410ull |
|---|
| 809 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 810 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 811 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x641460ull |
|---|
| 812 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 813 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 814 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x6414B0ull |
|---|
| 815 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 816 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 817 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x641500ull |
|---|
| 818 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 819 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 820 | #define mmDCORE0_TPC3_EML_TPC_CFG_KERNEL_BASE 0x641508ull |
|---|
| 821 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 822 | #define DCORE0_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 823 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x6415DCull |
|---|
| 824 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 825 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 826 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x64162Cull |
|---|
| 827 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 828 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 829 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x64167Cull |
|---|
| 830 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 831 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 832 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x6416CCull |
|---|
| 833 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 834 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 835 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x64171Cull |
|---|
| 836 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 837 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 838 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x64176Cull |
|---|
| 839 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 840 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 841 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x6417BCull |
|---|
| 842 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 843 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 844 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x64180Cull |
|---|
| 845 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 846 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 847 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x64185Cull |
|---|
| 848 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 849 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 850 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x6418ACull |
|---|
| 851 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 852 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 853 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x6418FCull |
|---|
| 854 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 855 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 856 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x64194Cull |
|---|
| 857 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 858 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 859 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x64199Cull |
|---|
| 860 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 861 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 862 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x6419ECull |
|---|
| 863 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 864 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 865 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x641A3Cull |
|---|
| 866 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 867 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 868 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x641A8Cull |
|---|
| 869 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 870 | #define DCORE0_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 871 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x641ADCull |
|---|
| 872 | #define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 873 | #define DCORE0_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 874 | #define mmDCORE0_TPC3_EML_TPC_CFG_QM_BASE 0x641AE4ull |
|---|
| 875 | #define DCORE0_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 876 | #define DCORE0_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 877 | #define mmDCORE0_TPC3_EML_TPC_CFG_AXUSER_BASE 0x641E00ull |
|---|
| 878 | #define DCORE0_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 879 | #define DCORE0_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 880 | #define mmDCORE0_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x641E80ull |
|---|
| 881 | #define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 882 | #define DCORE0_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 883 | #define mmDCORE0_TPC3_EML_QM_DCCM_BASE 0x642000ull |
|---|
| 884 | #define DCORE0_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 885 | #define DCORE0_TPC3_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 886 | #define mmDCORE0_TPC3_EML_QM_ARCAUX_BASE 0x64A000ull |
|---|
| 887 | #define DCORE0_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 888 | #define DCORE0_TPC3_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 889 | #define mmDCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x64AE80ull |
|---|
| 890 | #define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 891 | #define DCORE0_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 892 | #define mmDCORE0_TPC3_EML_TPC_QM_BASE 0x64C000ull |
|---|
| 893 | #define DCORE0_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 894 | #define DCORE0_TPC3_EML_TPC_QM_SECTION 0x9000 |
|---|
| 895 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x64C900ull |
|---|
| 896 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 897 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 898 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x64C908ull |
|---|
| 899 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 900 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 901 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x64C910ull |
|---|
| 902 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 903 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 904 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x64C918ull |
|---|
| 905 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 906 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 907 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x64C920ull |
|---|
| 908 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 909 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 910 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x64C928ull |
|---|
| 911 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 912 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 913 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x64C930ull |
|---|
| 914 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 915 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 916 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x64C938ull |
|---|
| 917 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 918 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 919 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x64C940ull |
|---|
| 920 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 921 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 922 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x64C948ull |
|---|
| 923 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 924 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 925 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x64C950ull |
|---|
| 926 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 927 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 928 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x64C958ull |
|---|
| 929 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 930 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 931 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x64C960ull |
|---|
| 932 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 933 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 934 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x64C968ull |
|---|
| 935 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 936 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 937 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x64C970ull |
|---|
| 938 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 939 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 940 | #define mmDCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x64C978ull |
|---|
| 941 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 942 | #define DCORE0_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 943 | #define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x64CB00ull |
|---|
| 944 | #define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 945 | #define DCORE0_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 946 | #define mmDCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x64CB80ull |
|---|
| 947 | #define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 948 | #define DCORE0_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 949 | #define mmDCORE0_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x64CC00ull |
|---|
| 950 | #define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 951 | #define DCORE0_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 952 | #define mmDCORE0_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x64CC80ull |
|---|
| 953 | #define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 954 | #define DCORE0_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 955 | #define mmDCORE0_TPC3_EML_TPC_QM_CGM_BASE 0x64CD80ull |
|---|
| 956 | #define DCORE0_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 957 | #define DCORE0_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 958 | #define mmDCORE0_TPC3_EML_TPC_QM_SPECIAL_BASE 0x64CE80ull |
|---|
| 959 | #define DCORE0_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 960 | #define DCORE0_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 961 | #define mmDCORE0_TPC3_EML_CS_BASE 0x7FF000ull |
|---|
| 962 | #define DCORE0_TPC3_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 963 | #define DCORE0_TPC3_EML_CS_SECTION 0x1000 |
|---|
| 964 | #define mmDCORE0_TPC4_ROM_TABLE_BASE 0x800000ull |
|---|
| 965 | #define DCORE0_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 966 | #define DCORE0_TPC4_ROM_TABLE_SECTION 0x1000 |
|---|
| 967 | #define mmDCORE0_TPC4_EML_SPMU_BASE 0x801000ull |
|---|
| 968 | #define DCORE0_TPC4_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 969 | #define DCORE0_TPC4_EML_SPMU_SECTION 0x1000 |
|---|
| 970 | #define mmDCORE0_TPC4_EML_ETF_BASE 0x802000ull |
|---|
| 971 | #define DCORE0_TPC4_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 972 | #define DCORE0_TPC4_EML_ETF_SECTION 0x1000 |
|---|
| 973 | #define mmDCORE0_TPC4_EML_STM_BASE 0x803000ull |
|---|
| 974 | #define DCORE0_TPC4_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 975 | #define DCORE0_TPC4_EML_STM_SECTION 0x2000 |
|---|
| 976 | #define mmDCORE0_TPC4_EML_CTI_BASE 0x805000ull |
|---|
| 977 | #define DCORE0_TPC4_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 978 | #define DCORE0_TPC4_EML_CTI_SECTION 0x1000 |
|---|
| 979 | #define mmDCORE0_TPC4_EML_FUNNEL_BASE 0x806000ull |
|---|
| 980 | #define DCORE0_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 981 | #define DCORE0_TPC4_EML_FUNNEL_SECTION 0x1000 |
|---|
| 982 | #define mmDCORE0_TPC4_EML_BUSMON_0_BASE 0x807000ull |
|---|
| 983 | #define DCORE0_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 984 | #define DCORE0_TPC4_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 985 | #define mmDCORE0_TPC4_EML_BUSMON_1_BASE 0x808000ull |
|---|
| 986 | #define DCORE0_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 987 | #define DCORE0_TPC4_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 988 | #define mmDCORE0_TPC4_EML_BUSMON_2_BASE 0x809000ull |
|---|
| 989 | #define DCORE0_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 990 | #define DCORE0_TPC4_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 991 | #define mmDCORE0_TPC4_EML_BUSMON_3_BASE 0x80A000ull |
|---|
| 992 | #define DCORE0_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 993 | #define DCORE0_TPC4_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 994 | #define mmDCORE0_TPC4_QM_ARC_RTT_BASE 0x80B000ull |
|---|
| 995 | #define DCORE0_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 996 | #define DCORE0_TPC4_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 997 | #define mmDCORE0_TPC4_EML_CFG_BASE 0x840000ull |
|---|
| 998 | #define DCORE0_TPC4_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 999 | #define DCORE0_TPC4_EML_CFG_SECTION 0xE800 |
|---|
| 1000 | #define mmDCORE0_TPC4_EML_CFG_SPECIAL_BASE 0x840E80ull |
|---|
| 1001 | #define DCORE0_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1002 | #define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1003 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x841000ull |
|---|
| 1004 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1005 | #define DCORE0_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1006 | #define mmDCORE0_TPC4_EML_TPC_CFG_BASE 0x841000ull |
|---|
| 1007 | #define DCORE0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 1008 | #define DCORE0_TPC4_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 1009 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x841050ull |
|---|
| 1010 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1011 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 1012 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x8410A0ull |
|---|
| 1013 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1014 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 1015 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x8410F0ull |
|---|
| 1016 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1017 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 1018 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x841140ull |
|---|
| 1019 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1020 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 1021 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x841190ull |
|---|
| 1022 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1023 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 1024 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x8411E0ull |
|---|
| 1025 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1026 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 1027 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x841230ull |
|---|
| 1028 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1029 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 1030 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x841280ull |
|---|
| 1031 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1032 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 1033 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x8412D0ull |
|---|
| 1034 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1035 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 1036 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x841320ull |
|---|
| 1037 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1038 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 1039 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x841370ull |
|---|
| 1040 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1041 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 1042 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x8413C0ull |
|---|
| 1043 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1044 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 1045 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x841410ull |
|---|
| 1046 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1047 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 1048 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x841460ull |
|---|
| 1049 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1050 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 1051 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x8414B0ull |
|---|
| 1052 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1053 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 1054 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x841500ull |
|---|
| 1055 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1056 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1057 | #define mmDCORE0_TPC4_EML_TPC_CFG_KERNEL_BASE 0x841508ull |
|---|
| 1058 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 1059 | #define DCORE0_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 1060 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x8415DCull |
|---|
| 1061 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1062 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 1063 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x84162Cull |
|---|
| 1064 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1065 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 1066 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x84167Cull |
|---|
| 1067 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1068 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 1069 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x8416CCull |
|---|
| 1070 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1071 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 1072 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x84171Cull |
|---|
| 1073 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1074 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 1075 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x84176Cull |
|---|
| 1076 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1077 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 1078 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x8417BCull |
|---|
| 1079 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1080 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 1081 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x84180Cull |
|---|
| 1082 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1083 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 1084 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x84185Cull |
|---|
| 1085 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1086 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 1087 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x8418ACull |
|---|
| 1088 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1089 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 1090 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x8418FCull |
|---|
| 1091 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1092 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 1093 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x84194Cull |
|---|
| 1094 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1095 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 1096 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x84199Cull |
|---|
| 1097 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1098 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 1099 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x8419ECull |
|---|
| 1100 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1101 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 1102 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x841A3Cull |
|---|
| 1103 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1104 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 1105 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x841A8Cull |
|---|
| 1106 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1107 | #define DCORE0_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 1108 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x841ADCull |
|---|
| 1109 | #define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1110 | #define DCORE0_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1111 | #define mmDCORE0_TPC4_EML_TPC_CFG_QM_BASE 0x841AE4ull |
|---|
| 1112 | #define DCORE0_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 1113 | #define DCORE0_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 1114 | #define mmDCORE0_TPC4_EML_TPC_CFG_AXUSER_BASE 0x841E00ull |
|---|
| 1115 | #define DCORE0_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 1116 | #define DCORE0_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 1117 | #define mmDCORE0_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x841E80ull |
|---|
| 1118 | #define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1119 | #define DCORE0_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1120 | #define mmDCORE0_TPC4_EML_QM_DCCM_BASE 0x842000ull |
|---|
| 1121 | #define DCORE0_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 1122 | #define DCORE0_TPC4_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 1123 | #define mmDCORE0_TPC4_EML_QM_ARCAUX_BASE 0x84A000ull |
|---|
| 1124 | #define DCORE0_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 1125 | #define DCORE0_TPC4_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 1126 | #define mmDCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x84AE80ull |
|---|
| 1127 | #define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1128 | #define DCORE0_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 1129 | #define mmDCORE0_TPC4_EML_TPC_QM_BASE 0x84C000ull |
|---|
| 1130 | #define DCORE0_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 1131 | #define DCORE0_TPC4_EML_TPC_QM_SECTION 0x9000 |
|---|
| 1132 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x84C900ull |
|---|
| 1133 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 1134 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 1135 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x84C908ull |
|---|
| 1136 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 1137 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 1138 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x84C910ull |
|---|
| 1139 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 1140 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 1141 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x84C918ull |
|---|
| 1142 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 1143 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 1144 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x84C920ull |
|---|
| 1145 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 1146 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 1147 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x84C928ull |
|---|
| 1148 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 1149 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 1150 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x84C930ull |
|---|
| 1151 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 1152 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 1153 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x84C938ull |
|---|
| 1154 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 1155 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 1156 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x84C940ull |
|---|
| 1157 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 1158 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 1159 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x84C948ull |
|---|
| 1160 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 1161 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 1162 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x84C950ull |
|---|
| 1163 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 1164 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 1165 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x84C958ull |
|---|
| 1166 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 1167 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 1168 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x84C960ull |
|---|
| 1169 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 1170 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 1171 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x84C968ull |
|---|
| 1172 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 1173 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 1174 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x84C970ull |
|---|
| 1175 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 1176 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 1177 | #define mmDCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x84C978ull |
|---|
| 1178 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 1179 | #define DCORE0_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 1180 | #define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x84CB00ull |
|---|
| 1181 | #define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 1182 | #define DCORE0_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 1183 | #define mmDCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x84CB80ull |
|---|
| 1184 | #define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 1185 | #define DCORE0_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 1186 | #define mmDCORE0_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x84CC00ull |
|---|
| 1187 | #define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 1188 | #define DCORE0_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 1189 | #define mmDCORE0_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x84CC80ull |
|---|
| 1190 | #define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 1191 | #define DCORE0_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 1192 | #define mmDCORE0_TPC4_EML_TPC_QM_CGM_BASE 0x84CD80ull |
|---|
| 1193 | #define DCORE0_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 1194 | #define DCORE0_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 1195 | #define mmDCORE0_TPC4_EML_TPC_QM_SPECIAL_BASE 0x84CE80ull |
|---|
| 1196 | #define DCORE0_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1197 | #define DCORE0_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 1198 | #define mmDCORE0_TPC4_EML_CS_BASE 0x9FF000ull |
|---|
| 1199 | #define DCORE0_TPC4_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 1200 | #define DCORE0_TPC4_EML_CS_SECTION 0x1000 |
|---|
| 1201 | #define mmDCORE0_TPC5_ROM_TABLE_BASE 0xA00000ull |
|---|
| 1202 | #define DCORE0_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 1203 | #define DCORE0_TPC5_ROM_TABLE_SECTION 0x1000 |
|---|
| 1204 | #define mmDCORE0_TPC5_EML_SPMU_BASE 0xA01000ull |
|---|
| 1205 | #define DCORE0_TPC5_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 1206 | #define DCORE0_TPC5_EML_SPMU_SECTION 0x1000 |
|---|
| 1207 | #define mmDCORE0_TPC5_EML_ETF_BASE 0xA02000ull |
|---|
| 1208 | #define DCORE0_TPC5_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 1209 | #define DCORE0_TPC5_EML_ETF_SECTION 0x1000 |
|---|
| 1210 | #define mmDCORE0_TPC5_EML_STM_BASE 0xA03000ull |
|---|
| 1211 | #define DCORE0_TPC5_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 1212 | #define DCORE0_TPC5_EML_STM_SECTION 0x2000 |
|---|
| 1213 | #define mmDCORE0_TPC5_EML_CTI_BASE 0xA05000ull |
|---|
| 1214 | #define DCORE0_TPC5_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 1215 | #define DCORE0_TPC5_EML_CTI_SECTION 0x1000 |
|---|
| 1216 | #define mmDCORE0_TPC5_EML_FUNNEL_BASE 0xA06000ull |
|---|
| 1217 | #define DCORE0_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 1218 | #define DCORE0_TPC5_EML_FUNNEL_SECTION 0x1000 |
|---|
| 1219 | #define mmDCORE0_TPC5_EML_BUSMON_0_BASE 0xA07000ull |
|---|
| 1220 | #define DCORE0_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 1221 | #define DCORE0_TPC5_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 1222 | #define mmDCORE0_TPC5_EML_BUSMON_1_BASE 0xA08000ull |
|---|
| 1223 | #define DCORE0_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 1224 | #define DCORE0_TPC5_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 1225 | #define mmDCORE0_TPC5_EML_BUSMON_2_BASE 0xA09000ull |
|---|
| 1226 | #define DCORE0_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 1227 | #define DCORE0_TPC5_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 1228 | #define mmDCORE0_TPC5_EML_BUSMON_3_BASE 0xA0A000ull |
|---|
| 1229 | #define DCORE0_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 1230 | #define DCORE0_TPC5_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 1231 | #define mmDCORE0_TPC5_QM_ARC_RTT_BASE 0xA0B000ull |
|---|
| 1232 | #define DCORE0_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 1233 | #define DCORE0_TPC5_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 1234 | #define mmDCORE0_TPC5_EML_CFG_BASE 0xA40000ull |
|---|
| 1235 | #define DCORE0_TPC5_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 1236 | #define DCORE0_TPC5_EML_CFG_SECTION 0xE800 |
|---|
| 1237 | #define mmDCORE0_TPC5_EML_CFG_SPECIAL_BASE 0xA40E80ull |
|---|
| 1238 | #define DCORE0_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1239 | #define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1240 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xA41000ull |
|---|
| 1241 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1242 | #define DCORE0_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1243 | #define mmDCORE0_TPC5_EML_TPC_CFG_BASE 0xA41000ull |
|---|
| 1244 | #define DCORE0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 1245 | #define DCORE0_TPC5_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 1246 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xA41050ull |
|---|
| 1247 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1248 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 1249 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xA410A0ull |
|---|
| 1250 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1251 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 1252 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xA410F0ull |
|---|
| 1253 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1254 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 1255 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xA41140ull |
|---|
| 1256 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1257 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 1258 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xA41190ull |
|---|
| 1259 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1260 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 1261 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xA411E0ull |
|---|
| 1262 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1263 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 1264 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xA41230ull |
|---|
| 1265 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1266 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 1267 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xA41280ull |
|---|
| 1268 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1269 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 1270 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xA412D0ull |
|---|
| 1271 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1272 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 1273 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xA41320ull |
|---|
| 1274 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1275 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 1276 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xA41370ull |
|---|
| 1277 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1278 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 1279 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xA413C0ull |
|---|
| 1280 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1281 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 1282 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xA41410ull |
|---|
| 1283 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1284 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 1285 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xA41460ull |
|---|
| 1286 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1287 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 1288 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xA414B0ull |
|---|
| 1289 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1290 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 1291 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xA41500ull |
|---|
| 1292 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1293 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1294 | #define mmDCORE0_TPC5_EML_TPC_CFG_KERNEL_BASE 0xA41508ull |
|---|
| 1295 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 1296 | #define DCORE0_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 1297 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0xA415DCull |
|---|
| 1298 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1299 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 1300 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0xA4162Cull |
|---|
| 1301 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1302 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 1303 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0xA4167Cull |
|---|
| 1304 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1305 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 1306 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0xA416CCull |
|---|
| 1307 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1308 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 1309 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0xA4171Cull |
|---|
| 1310 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1311 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 1312 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0xA4176Cull |
|---|
| 1313 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1314 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 1315 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0xA417BCull |
|---|
| 1316 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1317 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 1318 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0xA4180Cull |
|---|
| 1319 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1320 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 1321 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0xA4185Cull |
|---|
| 1322 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1323 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 1324 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0xA418ACull |
|---|
| 1325 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1326 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 1327 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0xA418FCull |
|---|
| 1328 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1329 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 1330 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0xA4194Cull |
|---|
| 1331 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1332 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 1333 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0xA4199Cull |
|---|
| 1334 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1335 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 1336 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0xA419ECull |
|---|
| 1337 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1338 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 1339 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0xA41A3Cull |
|---|
| 1340 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1341 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 1342 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0xA41A8Cull |
|---|
| 1343 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1344 | #define DCORE0_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 1345 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xA41ADCull |
|---|
| 1346 | #define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1347 | #define DCORE0_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1348 | #define mmDCORE0_TPC5_EML_TPC_CFG_QM_BASE 0xA41AE4ull |
|---|
| 1349 | #define DCORE0_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 1350 | #define DCORE0_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 1351 | #define mmDCORE0_TPC5_EML_TPC_CFG_AXUSER_BASE 0xA41E00ull |
|---|
| 1352 | #define DCORE0_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 1353 | #define DCORE0_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 1354 | #define mmDCORE0_TPC5_EML_TPC_CFG_SPECIAL_BASE 0xA41E80ull |
|---|
| 1355 | #define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1356 | #define DCORE0_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1357 | #define mmDCORE0_TPC5_EML_QM_DCCM_BASE 0xA42000ull |
|---|
| 1358 | #define DCORE0_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 1359 | #define DCORE0_TPC5_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 1360 | #define mmDCORE0_TPC5_EML_QM_ARCAUX_BASE 0xA4A000ull |
|---|
| 1361 | #define DCORE0_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 1362 | #define DCORE0_TPC5_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 1363 | #define mmDCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0xA4AE80ull |
|---|
| 1364 | #define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1365 | #define DCORE0_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 1366 | #define mmDCORE0_TPC5_EML_TPC_QM_BASE 0xA4C000ull |
|---|
| 1367 | #define DCORE0_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 1368 | #define DCORE0_TPC5_EML_TPC_QM_SECTION 0x9000 |
|---|
| 1369 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xA4C900ull |
|---|
| 1370 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 1371 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 1372 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xA4C908ull |
|---|
| 1373 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 1374 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 1375 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xA4C910ull |
|---|
| 1376 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 1377 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 1378 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xA4C918ull |
|---|
| 1379 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 1380 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 1381 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xA4C920ull |
|---|
| 1382 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 1383 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 1384 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xA4C928ull |
|---|
| 1385 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 1386 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 1387 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xA4C930ull |
|---|
| 1388 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 1389 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 1390 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xA4C938ull |
|---|
| 1391 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 1392 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 1393 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xA4C940ull |
|---|
| 1394 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 1395 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 1396 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xA4C948ull |
|---|
| 1397 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 1398 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 1399 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xA4C950ull |
|---|
| 1400 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 1401 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 1402 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xA4C958ull |
|---|
| 1403 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 1404 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 1405 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xA4C960ull |
|---|
| 1406 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 1407 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 1408 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xA4C968ull |
|---|
| 1409 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 1410 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 1411 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xA4C970ull |
|---|
| 1412 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 1413 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 1414 | #define mmDCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xA4C978ull |
|---|
| 1415 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 1416 | #define DCORE0_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 1417 | #define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0xA4CB00ull |
|---|
| 1418 | #define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 1419 | #define DCORE0_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 1420 | #define mmDCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xA4CB80ull |
|---|
| 1421 | #define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 1422 | #define DCORE0_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 1423 | #define mmDCORE0_TPC5_EML_TPC_QM_DBG_HBW_BASE 0xA4CC00ull |
|---|
| 1424 | #define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 1425 | #define DCORE0_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 1426 | #define mmDCORE0_TPC5_EML_TPC_QM_DBG_LBW_BASE 0xA4CC80ull |
|---|
| 1427 | #define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 1428 | #define DCORE0_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 1429 | #define mmDCORE0_TPC5_EML_TPC_QM_CGM_BASE 0xA4CD80ull |
|---|
| 1430 | #define DCORE0_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 1431 | #define DCORE0_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 1432 | #define mmDCORE0_TPC5_EML_TPC_QM_SPECIAL_BASE 0xA4CE80ull |
|---|
| 1433 | #define DCORE0_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1434 | #define DCORE0_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 1435 | #define mmDCORE0_TPC5_EML_CS_BASE 0xBFF000ull |
|---|
| 1436 | #define DCORE0_TPC5_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 1437 | #define DCORE0_TPC5_EML_CS_SECTION 0x1000 |
|---|
| 1438 | #define mmDCORE0_TPC6_ROM_TABLE_BASE 0xC00000ull |
|---|
| 1439 | #define DCORE0_TPC6_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 1440 | #define DCORE0_TPC6_ROM_TABLE_SECTION 0x1000 |
|---|
| 1441 | #define mmDCORE0_TPC6_EML_SPMU_BASE 0xC01000ull |
|---|
| 1442 | #define DCORE0_TPC6_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 1443 | #define DCORE0_TPC6_EML_SPMU_SECTION 0x1000 |
|---|
| 1444 | #define mmDCORE0_TPC6_EML_ETF_BASE 0xC02000ull |
|---|
| 1445 | #define DCORE0_TPC6_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 1446 | #define DCORE0_TPC6_EML_ETF_SECTION 0x1000 |
|---|
| 1447 | #define mmDCORE0_TPC6_EML_STM_BASE 0xC03000ull |
|---|
| 1448 | #define DCORE0_TPC6_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 1449 | #define DCORE0_TPC6_EML_STM_SECTION 0x2000 |
|---|
| 1450 | #define mmDCORE0_TPC6_EML_CTI_BASE 0xC05000ull |
|---|
| 1451 | #define DCORE0_TPC6_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 1452 | #define DCORE0_TPC6_EML_CTI_SECTION 0x1000 |
|---|
| 1453 | #define mmDCORE0_TPC6_EML_FUNNEL_BASE 0xC06000ull |
|---|
| 1454 | #define DCORE0_TPC6_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 1455 | #define DCORE0_TPC6_EML_FUNNEL_SECTION 0x1000 |
|---|
| 1456 | #define mmDCORE0_TPC6_EML_BUSMON_0_BASE 0xC07000ull |
|---|
| 1457 | #define DCORE0_TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 1458 | #define DCORE0_TPC6_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 1459 | #define mmDCORE0_TPC6_EML_BUSMON_1_BASE 0xC08000ull |
|---|
| 1460 | #define DCORE0_TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 1461 | #define DCORE0_TPC6_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 1462 | #define mmDCORE0_TPC6_EML_BUSMON_2_BASE 0xC09000ull |
|---|
| 1463 | #define DCORE0_TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 1464 | #define DCORE0_TPC6_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 1465 | #define mmDCORE0_TPC6_EML_BUSMON_3_BASE 0xC0A000ull |
|---|
| 1466 | #define DCORE0_TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 1467 | #define DCORE0_TPC6_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 1468 | #define mmDCORE0_TPC6_QM_ARC_RTT_BASE 0xC0B000ull |
|---|
| 1469 | #define DCORE0_TPC6_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 1470 | #define DCORE0_TPC6_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 1471 | #define mmDCORE0_TPC6_EML_CFG_BASE 0xC40000ull |
|---|
| 1472 | #define DCORE0_TPC6_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 1473 | #define DCORE0_TPC6_EML_CFG_SECTION 0xE800 |
|---|
| 1474 | #define mmDCORE0_TPC6_EML_CFG_SPECIAL_BASE 0xC40E80ull |
|---|
| 1475 | #define DCORE0_TPC6_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1476 | #define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1477 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0xC41000ull |
|---|
| 1478 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1479 | #define DCORE0_TPC6_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1480 | #define mmDCORE0_TPC6_EML_TPC_CFG_BASE 0xC41000ull |
|---|
| 1481 | #define DCORE0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 1482 | #define DCORE0_TPC6_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 1483 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0xC41050ull |
|---|
| 1484 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1485 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 1486 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0xC410A0ull |
|---|
| 1487 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1488 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 1489 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0xC410F0ull |
|---|
| 1490 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1491 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 1492 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0xC41140ull |
|---|
| 1493 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1494 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 1495 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0xC41190ull |
|---|
| 1496 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1497 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 1498 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0xC411E0ull |
|---|
| 1499 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1500 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 1501 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0xC41230ull |
|---|
| 1502 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1503 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 1504 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0xC41280ull |
|---|
| 1505 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1506 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 1507 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0xC412D0ull |
|---|
| 1508 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1509 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 1510 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0xC41320ull |
|---|
| 1511 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1512 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 1513 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0xC41370ull |
|---|
| 1514 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1515 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 1516 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0xC413C0ull |
|---|
| 1517 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1518 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 1519 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0xC41410ull |
|---|
| 1520 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1521 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 1522 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0xC41460ull |
|---|
| 1523 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1524 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 1525 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0xC414B0ull |
|---|
| 1526 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1527 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 1528 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0xC41500ull |
|---|
| 1529 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1530 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1531 | #define mmDCORE0_TPC6_EML_TPC_CFG_KERNEL_BASE 0xC41508ull |
|---|
| 1532 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 1533 | #define DCORE0_TPC6_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 1534 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_BASE 0xC415DCull |
|---|
| 1535 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1536 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 1537 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_BASE 0xC4162Cull |
|---|
| 1538 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1539 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 1540 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_BASE 0xC4167Cull |
|---|
| 1541 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1542 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 1543 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_BASE 0xC416CCull |
|---|
| 1544 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1545 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 1546 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_BASE 0xC4171Cull |
|---|
| 1547 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1548 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 1549 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_BASE 0xC4176Cull |
|---|
| 1550 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1551 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 1552 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_BASE 0xC417BCull |
|---|
| 1553 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1554 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 1555 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_BASE 0xC4180Cull |
|---|
| 1556 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1557 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 1558 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_BASE 0xC4185Cull |
|---|
| 1559 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1560 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 1561 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_BASE 0xC418ACull |
|---|
| 1562 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1563 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 1564 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_BASE 0xC418FCull |
|---|
| 1565 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1566 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 1567 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_BASE 0xC4194Cull |
|---|
| 1568 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1569 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 1570 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_BASE 0xC4199Cull |
|---|
| 1571 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1572 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 1573 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_BASE 0xC419ECull |
|---|
| 1574 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1575 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 1576 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_BASE 0xC41A3Cull |
|---|
| 1577 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1578 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 1579 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_BASE 0xC41A8Cull |
|---|
| 1580 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1581 | #define DCORE0_TPC6_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 1582 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0xC41ADCull |
|---|
| 1583 | #define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1584 | #define DCORE0_TPC6_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1585 | #define mmDCORE0_TPC6_EML_TPC_CFG_QM_BASE 0xC41AE4ull |
|---|
| 1586 | #define DCORE0_TPC6_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 1587 | #define DCORE0_TPC6_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 1588 | #define mmDCORE0_TPC6_EML_TPC_CFG_AXUSER_BASE 0xC41E00ull |
|---|
| 1589 | #define DCORE0_TPC6_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 1590 | #define DCORE0_TPC6_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 1591 | #define mmDCORE0_TPC6_EML_TPC_CFG_SPECIAL_BASE 0xC41E80ull |
|---|
| 1592 | #define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1593 | #define DCORE0_TPC6_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1594 | #define mmDCORE0_TPC6_EML_QM_DCCM_BASE 0xC42000ull |
|---|
| 1595 | #define DCORE0_TPC6_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 1596 | #define DCORE0_TPC6_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 1597 | #define mmDCORE0_TPC6_EML_QM_ARCAUX_BASE 0xC4A000ull |
|---|
| 1598 | #define DCORE0_TPC6_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 1599 | #define DCORE0_TPC6_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 1600 | #define mmDCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_BASE 0xC4AE80ull |
|---|
| 1601 | #define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1602 | #define DCORE0_TPC6_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 1603 | #define mmDCORE0_TPC6_EML_TPC_QM_BASE 0xC4C000ull |
|---|
| 1604 | #define DCORE0_TPC6_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 1605 | #define DCORE0_TPC6_EML_TPC_QM_SECTION 0x9000 |
|---|
| 1606 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0xC4C900ull |
|---|
| 1607 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 1608 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 1609 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0xC4C908ull |
|---|
| 1610 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 1611 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 1612 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0xC4C910ull |
|---|
| 1613 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 1614 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 1615 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0xC4C918ull |
|---|
| 1616 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 1617 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 1618 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0xC4C920ull |
|---|
| 1619 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 1620 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 1621 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0xC4C928ull |
|---|
| 1622 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 1623 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 1624 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0xC4C930ull |
|---|
| 1625 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 1626 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 1627 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0xC4C938ull |
|---|
| 1628 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 1629 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 1630 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0xC4C940ull |
|---|
| 1631 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 1632 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 1633 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0xC4C948ull |
|---|
| 1634 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 1635 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 1636 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0xC4C950ull |
|---|
| 1637 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 1638 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 1639 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0xC4C958ull |
|---|
| 1640 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 1641 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 1642 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0xC4C960ull |
|---|
| 1643 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 1644 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 1645 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0xC4C968ull |
|---|
| 1646 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 1647 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 1648 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0xC4C970ull |
|---|
| 1649 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 1650 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 1651 | #define mmDCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0xC4C978ull |
|---|
| 1652 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 1653 | #define DCORE0_TPC6_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 1654 | #define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_BASE 0xC4CB00ull |
|---|
| 1655 | #define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 1656 | #define DCORE0_TPC6_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 1657 | #define mmDCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_BASE 0xC4CB80ull |
|---|
| 1658 | #define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 1659 | #define DCORE0_TPC6_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 1660 | #define mmDCORE0_TPC6_EML_TPC_QM_DBG_HBW_BASE 0xC4CC00ull |
|---|
| 1661 | #define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 1662 | #define DCORE0_TPC6_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 1663 | #define mmDCORE0_TPC6_EML_TPC_QM_DBG_LBW_BASE 0xC4CC80ull |
|---|
| 1664 | #define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 1665 | #define DCORE0_TPC6_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 1666 | #define mmDCORE0_TPC6_EML_TPC_QM_CGM_BASE 0xC4CD80ull |
|---|
| 1667 | #define DCORE0_TPC6_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 1668 | #define DCORE0_TPC6_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 1669 | #define mmDCORE0_TPC6_EML_TPC_QM_SPECIAL_BASE 0xC4CE80ull |
|---|
| 1670 | #define DCORE0_TPC6_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1671 | #define DCORE0_TPC6_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 1672 | #define mmDCORE0_TPC6_EML_CS_BASE 0xDFF000ull |
|---|
| 1673 | #define DCORE0_TPC6_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 1674 | #define DCORE0_TPC6_EML_CS_SECTION 0x201000 |
|---|
| 1675 | #define mmDCORE1_TPC0_ROM_TABLE_BASE 0x1000000ull |
|---|
| 1676 | #define DCORE1_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 1677 | #define DCORE1_TPC0_ROM_TABLE_SECTION 0x1000 |
|---|
| 1678 | #define mmDCORE1_TPC0_EML_SPMU_BASE 0x1001000ull |
|---|
| 1679 | #define DCORE1_TPC0_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 1680 | #define DCORE1_TPC0_EML_SPMU_SECTION 0x1000 |
|---|
| 1681 | #define mmDCORE1_TPC0_EML_ETF_BASE 0x1002000ull |
|---|
| 1682 | #define DCORE1_TPC0_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 1683 | #define DCORE1_TPC0_EML_ETF_SECTION 0x1000 |
|---|
| 1684 | #define mmDCORE1_TPC0_EML_STM_BASE 0x1003000ull |
|---|
| 1685 | #define DCORE1_TPC0_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 1686 | #define DCORE1_TPC0_EML_STM_SECTION 0x2000 |
|---|
| 1687 | #define mmDCORE1_TPC0_EML_CTI_BASE 0x1005000ull |
|---|
| 1688 | #define DCORE1_TPC0_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 1689 | #define DCORE1_TPC0_EML_CTI_SECTION 0x1000 |
|---|
| 1690 | #define mmDCORE1_TPC0_EML_FUNNEL_BASE 0x1006000ull |
|---|
| 1691 | #define DCORE1_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 1692 | #define DCORE1_TPC0_EML_FUNNEL_SECTION 0x1000 |
|---|
| 1693 | #define mmDCORE1_TPC0_EML_BUSMON_0_BASE 0x1007000ull |
|---|
| 1694 | #define DCORE1_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 1695 | #define DCORE1_TPC0_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 1696 | #define mmDCORE1_TPC0_EML_BUSMON_1_BASE 0x1008000ull |
|---|
| 1697 | #define DCORE1_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 1698 | #define DCORE1_TPC0_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 1699 | #define mmDCORE1_TPC0_EML_BUSMON_2_BASE 0x1009000ull |
|---|
| 1700 | #define DCORE1_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 1701 | #define DCORE1_TPC0_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 1702 | #define mmDCORE1_TPC0_EML_BUSMON_3_BASE 0x100A000ull |
|---|
| 1703 | #define DCORE1_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 1704 | #define DCORE1_TPC0_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 1705 | #define mmDCORE1_TPC0_QM_ARC_RTT_BASE 0x100B000ull |
|---|
| 1706 | #define DCORE1_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 1707 | #define DCORE1_TPC0_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 1708 | #define mmDCORE1_TPC0_EML_CFG_BASE 0x1040000ull |
|---|
| 1709 | #define DCORE1_TPC0_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 1710 | #define DCORE1_TPC0_EML_CFG_SECTION 0xE800 |
|---|
| 1711 | #define mmDCORE1_TPC0_EML_CFG_SPECIAL_BASE 0x1040E80ull |
|---|
| 1712 | #define DCORE1_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1713 | #define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1714 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1041000ull |
|---|
| 1715 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1716 | #define DCORE1_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1717 | #define mmDCORE1_TPC0_EML_TPC_CFG_BASE 0x1041000ull |
|---|
| 1718 | #define DCORE1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 1719 | #define DCORE1_TPC0_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 1720 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1041050ull |
|---|
| 1721 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1722 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 1723 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x10410A0ull |
|---|
| 1724 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1725 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 1726 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x10410F0ull |
|---|
| 1727 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1728 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 1729 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1041140ull |
|---|
| 1730 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1731 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 1732 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1041190ull |
|---|
| 1733 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1734 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 1735 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x10411E0ull |
|---|
| 1736 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1737 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 1738 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1041230ull |
|---|
| 1739 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1740 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 1741 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1041280ull |
|---|
| 1742 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1743 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 1744 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x10412D0ull |
|---|
| 1745 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1746 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 1747 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1041320ull |
|---|
| 1748 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1749 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 1750 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1041370ull |
|---|
| 1751 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1752 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 1753 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x10413C0ull |
|---|
| 1754 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1755 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 1756 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1041410ull |
|---|
| 1757 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1758 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 1759 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1041460ull |
|---|
| 1760 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1761 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 1762 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x10414B0ull |
|---|
| 1763 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1764 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 1765 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1041500ull |
|---|
| 1766 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1767 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1768 | #define mmDCORE1_TPC0_EML_TPC_CFG_KERNEL_BASE 0x1041508ull |
|---|
| 1769 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 1770 | #define DCORE1_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 1771 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x10415DCull |
|---|
| 1772 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1773 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 1774 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x104162Cull |
|---|
| 1775 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 1776 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 1777 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x104167Cull |
|---|
| 1778 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 1779 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 1780 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x10416CCull |
|---|
| 1781 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 1782 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 1783 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x104171Cull |
|---|
| 1784 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 1785 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 1786 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x104176Cull |
|---|
| 1787 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1788 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 1789 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x10417BCull |
|---|
| 1790 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1791 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 1792 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x104180Cull |
|---|
| 1793 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1794 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 1795 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x104185Cull |
|---|
| 1796 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1797 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 1798 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x10418ACull |
|---|
| 1799 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1800 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 1801 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x10418FCull |
|---|
| 1802 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1803 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 1804 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x104194Cull |
|---|
| 1805 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1806 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 1807 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x104199Cull |
|---|
| 1808 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1809 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 1810 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x10419ECull |
|---|
| 1811 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1812 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 1813 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1041A3Cull |
|---|
| 1814 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1815 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 1816 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1041A8Cull |
|---|
| 1817 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 1818 | #define DCORE1_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 1819 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1041ADCull |
|---|
| 1820 | #define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 1821 | #define DCORE1_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 1822 | #define mmDCORE1_TPC0_EML_TPC_CFG_QM_BASE 0x1041AE4ull |
|---|
| 1823 | #define DCORE1_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 1824 | #define DCORE1_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 1825 | #define mmDCORE1_TPC0_EML_TPC_CFG_AXUSER_BASE 0x1041E00ull |
|---|
| 1826 | #define DCORE1_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 1827 | #define DCORE1_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 1828 | #define mmDCORE1_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x1041E80ull |
|---|
| 1829 | #define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1830 | #define DCORE1_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 1831 | #define mmDCORE1_TPC0_EML_QM_DCCM_BASE 0x1042000ull |
|---|
| 1832 | #define DCORE1_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 1833 | #define DCORE1_TPC0_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 1834 | #define mmDCORE1_TPC0_EML_QM_ARCAUX_BASE 0x104A000ull |
|---|
| 1835 | #define DCORE1_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 1836 | #define DCORE1_TPC0_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 1837 | #define mmDCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x104AE80ull |
|---|
| 1838 | #define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 1839 | #define DCORE1_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 1840 | #define mmDCORE1_TPC0_EML_TPC_QM_BASE 0x104C000ull |
|---|
| 1841 | #define DCORE1_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 1842 | #define DCORE1_TPC0_EML_TPC_QM_SECTION 0x9000 |
|---|
| 1843 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x104C900ull |
|---|
| 1844 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 1845 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 1846 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x104C908ull |
|---|
| 1847 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 1848 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
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| 1849 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x104C910ull |
|---|
| 1850 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 1851 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 1852 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x104C918ull |
|---|
| 1853 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
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| 1854 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
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| 1855 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x104C920ull |
|---|
| 1856 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 1857 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 1858 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x104C928ull |
|---|
| 1859 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
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| 1860 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
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| 1861 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x104C930ull |
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| 1862 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
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| 1863 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
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| 1864 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x104C938ull |
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| 1865 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
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| 1866 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
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| 1867 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x104C940ull |
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| 1868 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
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| 1869 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
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| 1870 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x104C948ull |
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| 1871 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
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| 1872 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
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| 1873 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x104C950ull |
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| 1874 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
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| 1875 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
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| 1876 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x104C958ull |
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| 1877 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
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| 1878 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
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| 1879 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x104C960ull |
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| 1880 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
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| 1881 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
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| 1882 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x104C968ull |
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| 1883 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
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| 1884 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
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| 1885 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x104C970ull |
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| 1886 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
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| 1887 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
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| 1888 | #define mmDCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x104C978ull |
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| 1889 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
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| 1890 | #define DCORE1_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
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| 1891 | #define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x104CB00ull |
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| 1892 | #define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
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| 1893 | #define DCORE1_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
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| 1894 | #define mmDCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x104CB80ull |
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| 1895 | #define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
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| 1896 | #define DCORE1_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
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| 1897 | #define mmDCORE1_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x104CC00ull |
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| 1898 | #define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
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| 1899 | #define DCORE1_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
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| 1900 | #define mmDCORE1_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x104CC80ull |
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| 1901 | #define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 1902 | #define DCORE1_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 1903 | #define mmDCORE1_TPC0_EML_TPC_QM_CGM_BASE 0x104CD80ull |
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| 1904 | #define DCORE1_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
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| 1905 | #define DCORE1_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 |
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| 1906 | #define mmDCORE1_TPC0_EML_TPC_QM_SPECIAL_BASE 0x104CE80ull |
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| 1907 | #define DCORE1_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
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| 1908 | #define DCORE1_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
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| 1909 | #define mmDCORE1_TPC0_EML_CS_BASE 0x11FF000ull |
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| 1910 | #define DCORE1_TPC0_EML_CS_MAX_OFFSET 0x1000 |
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| 1911 | #define DCORE1_TPC0_EML_CS_SECTION 0x1000 |
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| 1912 | #define mmDCORE1_TPC1_ROM_TABLE_BASE 0x1200000ull |
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| 1913 | #define DCORE1_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 |
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| 1914 | #define DCORE1_TPC1_ROM_TABLE_SECTION 0x1000 |
|---|
| 1915 | #define mmDCORE1_TPC1_EML_SPMU_BASE 0x1201000ull |
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| 1916 | #define DCORE1_TPC1_EML_SPMU_MAX_OFFSET 0x1000 |
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| 1917 | #define DCORE1_TPC1_EML_SPMU_SECTION 0x1000 |
|---|
| 1918 | #define mmDCORE1_TPC1_EML_ETF_BASE 0x1202000ull |
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| 1919 | #define DCORE1_TPC1_EML_ETF_MAX_OFFSET 0x1000 |
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| 1920 | #define DCORE1_TPC1_EML_ETF_SECTION 0x1000 |
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| 1921 | #define mmDCORE1_TPC1_EML_STM_BASE 0x1203000ull |
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| 1922 | #define DCORE1_TPC1_EML_STM_MAX_OFFSET 0x1000 |
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| 1923 | #define DCORE1_TPC1_EML_STM_SECTION 0x2000 |
|---|
| 1924 | #define mmDCORE1_TPC1_EML_CTI_BASE 0x1205000ull |
|---|
| 1925 | #define DCORE1_TPC1_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 1926 | #define DCORE1_TPC1_EML_CTI_SECTION 0x1000 |
|---|
| 1927 | #define mmDCORE1_TPC1_EML_FUNNEL_BASE 0x1206000ull |
|---|
| 1928 | #define DCORE1_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 |
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| 1929 | #define DCORE1_TPC1_EML_FUNNEL_SECTION 0x1000 |
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| 1930 | #define mmDCORE1_TPC1_EML_BUSMON_0_BASE 0x1207000ull |
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| 1931 | #define DCORE1_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 |
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| 1932 | #define DCORE1_TPC1_EML_BUSMON_0_SECTION 0x1000 |
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| 1933 | #define mmDCORE1_TPC1_EML_BUSMON_1_BASE 0x1208000ull |
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| 1934 | #define DCORE1_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 |
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| 1935 | #define DCORE1_TPC1_EML_BUSMON_1_SECTION 0x1000 |
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| 1936 | #define mmDCORE1_TPC1_EML_BUSMON_2_BASE 0x1209000ull |
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| 1937 | #define DCORE1_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 |
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| 1938 | #define DCORE1_TPC1_EML_BUSMON_2_SECTION 0x1000 |
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| 1939 | #define mmDCORE1_TPC1_EML_BUSMON_3_BASE 0x120A000ull |
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| 1940 | #define DCORE1_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 |
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| 1941 | #define DCORE1_TPC1_EML_BUSMON_3_SECTION 0x1000 |
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| 1942 | #define mmDCORE1_TPC1_QM_ARC_RTT_BASE 0x120B000ull |
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| 1943 | #define DCORE1_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 |
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| 1944 | #define DCORE1_TPC1_QM_ARC_RTT_SECTION 0x35000 |
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| 1945 | #define mmDCORE1_TPC1_EML_CFG_BASE 0x1240000ull |
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| 1946 | #define DCORE1_TPC1_EML_CFG_MAX_OFFSET 0x1000 |
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| 1947 | #define DCORE1_TPC1_EML_CFG_SECTION 0xE800 |
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| 1948 | #define mmDCORE1_TPC1_EML_CFG_SPECIAL_BASE 0x1240E80ull |
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| 1949 | #define DCORE1_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
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| 1950 | #define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 1951 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1241000ull |
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| 1952 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 1953 | #define DCORE1_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
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| 1954 | #define mmDCORE1_TPC1_EML_TPC_CFG_BASE 0x1241000ull |
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| 1955 | #define DCORE1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 |
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| 1956 | #define DCORE1_TPC1_EML_TPC_CFG_SECTION 0x5000 |
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| 1957 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1241050ull |
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| 1958 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
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| 1959 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
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| 1960 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x12410A0ull |
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| 1961 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
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| 1962 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
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| 1963 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x12410F0ull |
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| 1964 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
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| 1965 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
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| 1966 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1241140ull |
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| 1967 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
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| 1968 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
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| 1969 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1241190ull |
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| 1970 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 1971 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
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| 1972 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x12411E0ull |
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| 1973 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 1974 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 1975 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1241230ull |
|---|
| 1976 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 1977 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 1978 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1241280ull |
|---|
| 1979 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 1980 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 1981 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x12412D0ull |
|---|
| 1982 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 1983 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 1984 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1241320ull |
|---|
| 1985 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 1986 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 1987 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1241370ull |
|---|
| 1988 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 1989 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 1990 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x12413C0ull |
|---|
| 1991 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 1992 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 1993 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1241410ull |
|---|
| 1994 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 1995 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 1996 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1241460ull |
|---|
| 1997 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 1998 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 1999 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x12414B0ull |
|---|
| 2000 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2001 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 2002 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1241500ull |
|---|
| 2003 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2004 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2005 | #define mmDCORE1_TPC1_EML_TPC_CFG_KERNEL_BASE 0x1241508ull |
|---|
| 2006 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 2007 | #define DCORE1_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 2008 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x12415DCull |
|---|
| 2009 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2010 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 2011 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x124162Cull |
|---|
| 2012 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2013 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 2014 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x124167Cull |
|---|
| 2015 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2016 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 2017 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x12416CCull |
|---|
| 2018 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2019 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 2020 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x124171Cull |
|---|
| 2021 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2022 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 2023 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x124176Cull |
|---|
| 2024 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2025 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 2026 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x12417BCull |
|---|
| 2027 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2028 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 2029 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x124180Cull |
|---|
| 2030 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2031 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 2032 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x124185Cull |
|---|
| 2033 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2034 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 2035 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x12418ACull |
|---|
| 2036 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2037 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 2038 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x12418FCull |
|---|
| 2039 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2040 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 2041 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x124194Cull |
|---|
| 2042 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2043 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 2044 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x124199Cull |
|---|
| 2045 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2046 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 2047 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x12419ECull |
|---|
| 2048 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2049 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 2050 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1241A3Cull |
|---|
| 2051 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2052 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 2053 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1241A8Cull |
|---|
| 2054 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2055 | #define DCORE1_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 2056 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1241ADCull |
|---|
| 2057 | #define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2058 | #define DCORE1_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2059 | #define mmDCORE1_TPC1_EML_TPC_CFG_QM_BASE 0x1241AE4ull |
|---|
| 2060 | #define DCORE1_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 2061 | #define DCORE1_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 2062 | #define mmDCORE1_TPC1_EML_TPC_CFG_AXUSER_BASE 0x1241E00ull |
|---|
| 2063 | #define DCORE1_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 2064 | #define DCORE1_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 2065 | #define mmDCORE1_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x1241E80ull |
|---|
| 2066 | #define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2067 | #define DCORE1_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2068 | #define mmDCORE1_TPC1_EML_QM_DCCM_BASE 0x1242000ull |
|---|
| 2069 | #define DCORE1_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 2070 | #define DCORE1_TPC1_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 2071 | #define mmDCORE1_TPC1_EML_QM_ARCAUX_BASE 0x124A000ull |
|---|
| 2072 | #define DCORE1_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 2073 | #define DCORE1_TPC1_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 2074 | #define mmDCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x124AE80ull |
|---|
| 2075 | #define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2076 | #define DCORE1_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 2077 | #define mmDCORE1_TPC1_EML_TPC_QM_BASE 0x124C000ull |
|---|
| 2078 | #define DCORE1_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 2079 | #define DCORE1_TPC1_EML_TPC_QM_SECTION 0x9000 |
|---|
| 2080 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x124C900ull |
|---|
| 2081 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 2082 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 2083 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x124C908ull |
|---|
| 2084 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 2085 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 2086 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x124C910ull |
|---|
| 2087 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 2088 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 2089 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x124C918ull |
|---|
| 2090 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 2091 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 2092 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x124C920ull |
|---|
| 2093 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 2094 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 2095 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x124C928ull |
|---|
| 2096 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 2097 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 2098 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x124C930ull |
|---|
| 2099 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 2100 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 2101 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x124C938ull |
|---|
| 2102 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 2103 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 2104 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x124C940ull |
|---|
| 2105 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 2106 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 2107 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x124C948ull |
|---|
| 2108 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 2109 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 2110 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x124C950ull |
|---|
| 2111 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 2112 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 2113 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x124C958ull |
|---|
| 2114 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 2115 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 2116 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x124C960ull |
|---|
| 2117 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 2118 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 2119 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x124C968ull |
|---|
| 2120 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 2121 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 2122 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x124C970ull |
|---|
| 2123 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 2124 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 2125 | #define mmDCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x124C978ull |
|---|
| 2126 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 2127 | #define DCORE1_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 2128 | #define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x124CB00ull |
|---|
| 2129 | #define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 2130 | #define DCORE1_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 2131 | #define mmDCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x124CB80ull |
|---|
| 2132 | #define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 2133 | #define DCORE1_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 2134 | #define mmDCORE1_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x124CC00ull |
|---|
| 2135 | #define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 2136 | #define DCORE1_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 2137 | #define mmDCORE1_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x124CC80ull |
|---|
| 2138 | #define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 2139 | #define DCORE1_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 2140 | #define mmDCORE1_TPC1_EML_TPC_QM_CGM_BASE 0x124CD80ull |
|---|
| 2141 | #define DCORE1_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 2142 | #define DCORE1_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 2143 | #define mmDCORE1_TPC1_EML_TPC_QM_SPECIAL_BASE 0x124CE80ull |
|---|
| 2144 | #define DCORE1_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2145 | #define DCORE1_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 2146 | #define mmDCORE1_TPC1_EML_CS_BASE 0x13FF000ull |
|---|
| 2147 | #define DCORE1_TPC1_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 2148 | #define DCORE1_TPC1_EML_CS_SECTION 0x1000 |
|---|
| 2149 | #define mmDCORE1_TPC2_ROM_TABLE_BASE 0x1400000ull |
|---|
| 2150 | #define DCORE1_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 2151 | #define DCORE1_TPC2_ROM_TABLE_SECTION 0x1000 |
|---|
| 2152 | #define mmDCORE1_TPC2_EML_SPMU_BASE 0x1401000ull |
|---|
| 2153 | #define DCORE1_TPC2_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 2154 | #define DCORE1_TPC2_EML_SPMU_SECTION 0x1000 |
|---|
| 2155 | #define mmDCORE1_TPC2_EML_ETF_BASE 0x1402000ull |
|---|
| 2156 | #define DCORE1_TPC2_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 2157 | #define DCORE1_TPC2_EML_ETF_SECTION 0x1000 |
|---|
| 2158 | #define mmDCORE1_TPC2_EML_STM_BASE 0x1403000ull |
|---|
| 2159 | #define DCORE1_TPC2_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 2160 | #define DCORE1_TPC2_EML_STM_SECTION 0x2000 |
|---|
| 2161 | #define mmDCORE1_TPC2_EML_CTI_BASE 0x1405000ull |
|---|
| 2162 | #define DCORE1_TPC2_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 2163 | #define DCORE1_TPC2_EML_CTI_SECTION 0x1000 |
|---|
| 2164 | #define mmDCORE1_TPC2_EML_FUNNEL_BASE 0x1406000ull |
|---|
| 2165 | #define DCORE1_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 2166 | #define DCORE1_TPC2_EML_FUNNEL_SECTION 0x1000 |
|---|
| 2167 | #define mmDCORE1_TPC2_EML_BUSMON_0_BASE 0x1407000ull |
|---|
| 2168 | #define DCORE1_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 2169 | #define DCORE1_TPC2_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 2170 | #define mmDCORE1_TPC2_EML_BUSMON_1_BASE 0x1408000ull |
|---|
| 2171 | #define DCORE1_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 2172 | #define DCORE1_TPC2_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 2173 | #define mmDCORE1_TPC2_EML_BUSMON_2_BASE 0x1409000ull |
|---|
| 2174 | #define DCORE1_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 2175 | #define DCORE1_TPC2_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 2176 | #define mmDCORE1_TPC2_EML_BUSMON_3_BASE 0x140A000ull |
|---|
| 2177 | #define DCORE1_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 2178 | #define DCORE1_TPC2_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 2179 | #define mmDCORE1_TPC2_QM_ARC_RTT_BASE 0x140B000ull |
|---|
| 2180 | #define DCORE1_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 2181 | #define DCORE1_TPC2_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 2182 | #define mmDCORE1_TPC2_EML_CFG_BASE 0x1440000ull |
|---|
| 2183 | #define DCORE1_TPC2_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 2184 | #define DCORE1_TPC2_EML_CFG_SECTION 0xE800 |
|---|
| 2185 | #define mmDCORE1_TPC2_EML_CFG_SPECIAL_BASE 0x1440E80ull |
|---|
| 2186 | #define DCORE1_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2187 | #define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2188 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1441000ull |
|---|
| 2189 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2190 | #define DCORE1_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2191 | #define mmDCORE1_TPC2_EML_TPC_CFG_BASE 0x1441000ull |
|---|
| 2192 | #define DCORE1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 2193 | #define DCORE1_TPC2_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 2194 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1441050ull |
|---|
| 2195 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2196 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 2197 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x14410A0ull |
|---|
| 2198 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2199 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 2200 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x14410F0ull |
|---|
| 2201 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2202 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 2203 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1441140ull |
|---|
| 2204 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2205 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 2206 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1441190ull |
|---|
| 2207 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2208 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 2209 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x14411E0ull |
|---|
| 2210 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2211 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 2212 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1441230ull |
|---|
| 2213 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2214 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 2215 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1441280ull |
|---|
| 2216 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2217 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 2218 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x14412D0ull |
|---|
| 2219 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2220 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 2221 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1441320ull |
|---|
| 2222 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2223 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 2224 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1441370ull |
|---|
| 2225 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2226 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 2227 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x14413C0ull |
|---|
| 2228 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2229 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 2230 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1441410ull |
|---|
| 2231 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2232 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 2233 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1441460ull |
|---|
| 2234 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2235 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 2236 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x14414B0ull |
|---|
| 2237 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2238 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 2239 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1441500ull |
|---|
| 2240 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2241 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2242 | #define mmDCORE1_TPC2_EML_TPC_CFG_KERNEL_BASE 0x1441508ull |
|---|
| 2243 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 2244 | #define DCORE1_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 2245 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x14415DCull |
|---|
| 2246 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2247 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 2248 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x144162Cull |
|---|
| 2249 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2250 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 2251 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x144167Cull |
|---|
| 2252 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2253 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 2254 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x14416CCull |
|---|
| 2255 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2256 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 2257 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x144171Cull |
|---|
| 2258 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2259 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 2260 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x144176Cull |
|---|
| 2261 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2262 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 2263 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x14417BCull |
|---|
| 2264 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2265 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 2266 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x144180Cull |
|---|
| 2267 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2268 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 2269 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x144185Cull |
|---|
| 2270 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2271 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 2272 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x14418ACull |
|---|
| 2273 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2274 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 2275 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x14418FCull |
|---|
| 2276 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2277 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 2278 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x144194Cull |
|---|
| 2279 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2280 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 2281 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x144199Cull |
|---|
| 2282 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2283 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 2284 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x14419ECull |
|---|
| 2285 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2286 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 2287 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1441A3Cull |
|---|
| 2288 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2289 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 2290 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1441A8Cull |
|---|
| 2291 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2292 | #define DCORE1_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 2293 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1441ADCull |
|---|
| 2294 | #define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2295 | #define DCORE1_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2296 | #define mmDCORE1_TPC2_EML_TPC_CFG_QM_BASE 0x1441AE4ull |
|---|
| 2297 | #define DCORE1_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 2298 | #define DCORE1_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 2299 | #define mmDCORE1_TPC2_EML_TPC_CFG_AXUSER_BASE 0x1441E00ull |
|---|
| 2300 | #define DCORE1_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 2301 | #define DCORE1_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 2302 | #define mmDCORE1_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x1441E80ull |
|---|
| 2303 | #define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2304 | #define DCORE1_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2305 | #define mmDCORE1_TPC2_EML_QM_DCCM_BASE 0x1442000ull |
|---|
| 2306 | #define DCORE1_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 2307 | #define DCORE1_TPC2_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 2308 | #define mmDCORE1_TPC2_EML_QM_ARCAUX_BASE 0x144A000ull |
|---|
| 2309 | #define DCORE1_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 2310 | #define DCORE1_TPC2_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 2311 | #define mmDCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x144AE80ull |
|---|
| 2312 | #define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2313 | #define DCORE1_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 2314 | #define mmDCORE1_TPC2_EML_TPC_QM_BASE 0x144C000ull |
|---|
| 2315 | #define DCORE1_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 2316 | #define DCORE1_TPC2_EML_TPC_QM_SECTION 0x9000 |
|---|
| 2317 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x144C900ull |
|---|
| 2318 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 2319 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 2320 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x144C908ull |
|---|
| 2321 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 2322 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 2323 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x144C910ull |
|---|
| 2324 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 2325 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 2326 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x144C918ull |
|---|
| 2327 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 2328 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 2329 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x144C920ull |
|---|
| 2330 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 2331 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 2332 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x144C928ull |
|---|
| 2333 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 2334 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 2335 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x144C930ull |
|---|
| 2336 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 2337 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 2338 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x144C938ull |
|---|
| 2339 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 2340 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 2341 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x144C940ull |
|---|
| 2342 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 2343 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 2344 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x144C948ull |
|---|
| 2345 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 2346 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 2347 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x144C950ull |
|---|
| 2348 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 2349 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 2350 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x144C958ull |
|---|
| 2351 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 2352 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 2353 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x144C960ull |
|---|
| 2354 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 2355 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 2356 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x144C968ull |
|---|
| 2357 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 2358 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 2359 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x144C970ull |
|---|
| 2360 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 2361 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 2362 | #define mmDCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x144C978ull |
|---|
| 2363 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 2364 | #define DCORE1_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 2365 | #define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x144CB00ull |
|---|
| 2366 | #define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 2367 | #define DCORE1_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 2368 | #define mmDCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x144CB80ull |
|---|
| 2369 | #define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 2370 | #define DCORE1_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 2371 | #define mmDCORE1_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x144CC00ull |
|---|
| 2372 | #define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 2373 | #define DCORE1_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 2374 | #define mmDCORE1_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x144CC80ull |
|---|
| 2375 | #define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 2376 | #define DCORE1_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 2377 | #define mmDCORE1_TPC2_EML_TPC_QM_CGM_BASE 0x144CD80ull |
|---|
| 2378 | #define DCORE1_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 2379 | #define DCORE1_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 2380 | #define mmDCORE1_TPC2_EML_TPC_QM_SPECIAL_BASE 0x144CE80ull |
|---|
| 2381 | #define DCORE1_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2382 | #define DCORE1_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 2383 | #define mmDCORE1_TPC2_EML_CS_BASE 0x15FF000ull |
|---|
| 2384 | #define DCORE1_TPC2_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 2385 | #define DCORE1_TPC2_EML_CS_SECTION 0x1000 |
|---|
| 2386 | #define mmDCORE1_TPC3_ROM_TABLE_BASE 0x1600000ull |
|---|
| 2387 | #define DCORE1_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 2388 | #define DCORE1_TPC3_ROM_TABLE_SECTION 0x1000 |
|---|
| 2389 | #define mmDCORE1_TPC3_EML_SPMU_BASE 0x1601000ull |
|---|
| 2390 | #define DCORE1_TPC3_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 2391 | #define DCORE1_TPC3_EML_SPMU_SECTION 0x1000 |
|---|
| 2392 | #define mmDCORE1_TPC3_EML_ETF_BASE 0x1602000ull |
|---|
| 2393 | #define DCORE1_TPC3_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 2394 | #define DCORE1_TPC3_EML_ETF_SECTION 0x1000 |
|---|
| 2395 | #define mmDCORE1_TPC3_EML_STM_BASE 0x1603000ull |
|---|
| 2396 | #define DCORE1_TPC3_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 2397 | #define DCORE1_TPC3_EML_STM_SECTION 0x2000 |
|---|
| 2398 | #define mmDCORE1_TPC3_EML_CTI_BASE 0x1605000ull |
|---|
| 2399 | #define DCORE1_TPC3_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 2400 | #define DCORE1_TPC3_EML_CTI_SECTION 0x1000 |
|---|
| 2401 | #define mmDCORE1_TPC3_EML_FUNNEL_BASE 0x1606000ull |
|---|
| 2402 | #define DCORE1_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 2403 | #define DCORE1_TPC3_EML_FUNNEL_SECTION 0x1000 |
|---|
| 2404 | #define mmDCORE1_TPC3_EML_BUSMON_0_BASE 0x1607000ull |
|---|
| 2405 | #define DCORE1_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 2406 | #define DCORE1_TPC3_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 2407 | #define mmDCORE1_TPC3_EML_BUSMON_1_BASE 0x1608000ull |
|---|
| 2408 | #define DCORE1_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 2409 | #define DCORE1_TPC3_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 2410 | #define mmDCORE1_TPC3_EML_BUSMON_2_BASE 0x1609000ull |
|---|
| 2411 | #define DCORE1_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 2412 | #define DCORE1_TPC3_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 2413 | #define mmDCORE1_TPC3_EML_BUSMON_3_BASE 0x160A000ull |
|---|
| 2414 | #define DCORE1_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 2415 | #define DCORE1_TPC3_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 2416 | #define mmDCORE1_TPC3_QM_ARC_RTT_BASE 0x160B000ull |
|---|
| 2417 | #define DCORE1_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 2418 | #define DCORE1_TPC3_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 2419 | #define mmDCORE1_TPC3_EML_CFG_BASE 0x1640000ull |
|---|
| 2420 | #define DCORE1_TPC3_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 2421 | #define DCORE1_TPC3_EML_CFG_SECTION 0xE800 |
|---|
| 2422 | #define mmDCORE1_TPC3_EML_CFG_SPECIAL_BASE 0x1640E80ull |
|---|
| 2423 | #define DCORE1_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2424 | #define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2425 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1641000ull |
|---|
| 2426 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2427 | #define DCORE1_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2428 | #define mmDCORE1_TPC3_EML_TPC_CFG_BASE 0x1641000ull |
|---|
| 2429 | #define DCORE1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 2430 | #define DCORE1_TPC3_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 2431 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1641050ull |
|---|
| 2432 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2433 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 2434 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x16410A0ull |
|---|
| 2435 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2436 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 2437 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x16410F0ull |
|---|
| 2438 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2439 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 2440 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1641140ull |
|---|
| 2441 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2442 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 2443 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1641190ull |
|---|
| 2444 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2445 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 2446 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x16411E0ull |
|---|
| 2447 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2448 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 2449 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1641230ull |
|---|
| 2450 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2451 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 2452 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1641280ull |
|---|
| 2453 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2454 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 2455 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x16412D0ull |
|---|
| 2456 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2457 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 2458 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1641320ull |
|---|
| 2459 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2460 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 2461 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1641370ull |
|---|
| 2462 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2463 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 2464 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x16413C0ull |
|---|
| 2465 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2466 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 2467 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1641410ull |
|---|
| 2468 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2469 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 2470 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1641460ull |
|---|
| 2471 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2472 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 2473 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x16414B0ull |
|---|
| 2474 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2475 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 2476 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1641500ull |
|---|
| 2477 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2478 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2479 | #define mmDCORE1_TPC3_EML_TPC_CFG_KERNEL_BASE 0x1641508ull |
|---|
| 2480 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 2481 | #define DCORE1_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 2482 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x16415DCull |
|---|
| 2483 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2484 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 2485 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x164162Cull |
|---|
| 2486 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2487 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 2488 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x164167Cull |
|---|
| 2489 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2490 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 2491 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x16416CCull |
|---|
| 2492 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2493 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 2494 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x164171Cull |
|---|
| 2495 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2496 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 2497 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x164176Cull |
|---|
| 2498 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2499 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 2500 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x16417BCull |
|---|
| 2501 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2502 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 2503 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x164180Cull |
|---|
| 2504 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2505 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 2506 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x164185Cull |
|---|
| 2507 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2508 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 2509 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x16418ACull |
|---|
| 2510 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2511 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 2512 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x16418FCull |
|---|
| 2513 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2514 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 2515 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x164194Cull |
|---|
| 2516 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2517 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 2518 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x164199Cull |
|---|
| 2519 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2520 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 2521 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x16419ECull |
|---|
| 2522 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2523 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 2524 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1641A3Cull |
|---|
| 2525 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2526 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 2527 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1641A8Cull |
|---|
| 2528 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2529 | #define DCORE1_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 2530 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1641ADCull |
|---|
| 2531 | #define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2532 | #define DCORE1_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2533 | #define mmDCORE1_TPC3_EML_TPC_CFG_QM_BASE 0x1641AE4ull |
|---|
| 2534 | #define DCORE1_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 2535 | #define DCORE1_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 2536 | #define mmDCORE1_TPC3_EML_TPC_CFG_AXUSER_BASE 0x1641E00ull |
|---|
| 2537 | #define DCORE1_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 2538 | #define DCORE1_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 2539 | #define mmDCORE1_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x1641E80ull |
|---|
| 2540 | #define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2541 | #define DCORE1_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2542 | #define mmDCORE1_TPC3_EML_QM_DCCM_BASE 0x1642000ull |
|---|
| 2543 | #define DCORE1_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 2544 | #define DCORE1_TPC3_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 2545 | #define mmDCORE1_TPC3_EML_QM_ARCAUX_BASE 0x164A000ull |
|---|
| 2546 | #define DCORE1_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 2547 | #define DCORE1_TPC3_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 2548 | #define mmDCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x164AE80ull |
|---|
| 2549 | #define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2550 | #define DCORE1_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 2551 | #define mmDCORE1_TPC3_EML_TPC_QM_BASE 0x164C000ull |
|---|
| 2552 | #define DCORE1_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 2553 | #define DCORE1_TPC3_EML_TPC_QM_SECTION 0x9000 |
|---|
| 2554 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x164C900ull |
|---|
| 2555 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 2556 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 2557 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x164C908ull |
|---|
| 2558 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 2559 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 2560 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x164C910ull |
|---|
| 2561 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 2562 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 2563 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x164C918ull |
|---|
| 2564 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 2565 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 2566 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x164C920ull |
|---|
| 2567 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 2568 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 2569 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x164C928ull |
|---|
| 2570 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 2571 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 2572 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x164C930ull |
|---|
| 2573 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 2574 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 2575 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x164C938ull |
|---|
| 2576 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 2577 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 2578 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x164C940ull |
|---|
| 2579 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 2580 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 2581 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x164C948ull |
|---|
| 2582 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 2583 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 2584 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x164C950ull |
|---|
| 2585 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 2586 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 2587 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x164C958ull |
|---|
| 2588 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 2589 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 2590 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x164C960ull |
|---|
| 2591 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 2592 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 2593 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x164C968ull |
|---|
| 2594 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 2595 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 2596 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x164C970ull |
|---|
| 2597 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 2598 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 2599 | #define mmDCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x164C978ull |
|---|
| 2600 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 2601 | #define DCORE1_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 2602 | #define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x164CB00ull |
|---|
| 2603 | #define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 2604 | #define DCORE1_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 2605 | #define mmDCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x164CB80ull |
|---|
| 2606 | #define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 2607 | #define DCORE1_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 2608 | #define mmDCORE1_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x164CC00ull |
|---|
| 2609 | #define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 2610 | #define DCORE1_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 2611 | #define mmDCORE1_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x164CC80ull |
|---|
| 2612 | #define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 2613 | #define DCORE1_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 2614 | #define mmDCORE1_TPC3_EML_TPC_QM_CGM_BASE 0x164CD80ull |
|---|
| 2615 | #define DCORE1_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 2616 | #define DCORE1_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 2617 | #define mmDCORE1_TPC3_EML_TPC_QM_SPECIAL_BASE 0x164CE80ull |
|---|
| 2618 | #define DCORE1_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2619 | #define DCORE1_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 2620 | #define mmDCORE1_TPC3_EML_CS_BASE 0x17FF000ull |
|---|
| 2621 | #define DCORE1_TPC3_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 2622 | #define DCORE1_TPC3_EML_CS_SECTION 0x1000 |
|---|
| 2623 | #define mmDCORE1_TPC4_ROM_TABLE_BASE 0x1800000ull |
|---|
| 2624 | #define DCORE1_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 2625 | #define DCORE1_TPC4_ROM_TABLE_SECTION 0x1000 |
|---|
| 2626 | #define mmDCORE1_TPC4_EML_SPMU_BASE 0x1801000ull |
|---|
| 2627 | #define DCORE1_TPC4_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 2628 | #define DCORE1_TPC4_EML_SPMU_SECTION 0x1000 |
|---|
| 2629 | #define mmDCORE1_TPC4_EML_ETF_BASE 0x1802000ull |
|---|
| 2630 | #define DCORE1_TPC4_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 2631 | #define DCORE1_TPC4_EML_ETF_SECTION 0x1000 |
|---|
| 2632 | #define mmDCORE1_TPC4_EML_STM_BASE 0x1803000ull |
|---|
| 2633 | #define DCORE1_TPC4_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 2634 | #define DCORE1_TPC4_EML_STM_SECTION 0x2000 |
|---|
| 2635 | #define mmDCORE1_TPC4_EML_CTI_BASE 0x1805000ull |
|---|
| 2636 | #define DCORE1_TPC4_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 2637 | #define DCORE1_TPC4_EML_CTI_SECTION 0x1000 |
|---|
| 2638 | #define mmDCORE1_TPC4_EML_FUNNEL_BASE 0x1806000ull |
|---|
| 2639 | #define DCORE1_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 2640 | #define DCORE1_TPC4_EML_FUNNEL_SECTION 0x1000 |
|---|
| 2641 | #define mmDCORE1_TPC4_EML_BUSMON_0_BASE 0x1807000ull |
|---|
| 2642 | #define DCORE1_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 2643 | #define DCORE1_TPC4_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 2644 | #define mmDCORE1_TPC4_EML_BUSMON_1_BASE 0x1808000ull |
|---|
| 2645 | #define DCORE1_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 2646 | #define DCORE1_TPC4_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 2647 | #define mmDCORE1_TPC4_EML_BUSMON_2_BASE 0x1809000ull |
|---|
| 2648 | #define DCORE1_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 2649 | #define DCORE1_TPC4_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 2650 | #define mmDCORE1_TPC4_EML_BUSMON_3_BASE 0x180A000ull |
|---|
| 2651 | #define DCORE1_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 2652 | #define DCORE1_TPC4_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 2653 | #define mmDCORE1_TPC4_QM_ARC_RTT_BASE 0x180B000ull |
|---|
| 2654 | #define DCORE1_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 2655 | #define DCORE1_TPC4_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 2656 | #define mmDCORE1_TPC4_EML_CFG_BASE 0x1840000ull |
|---|
| 2657 | #define DCORE1_TPC4_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 2658 | #define DCORE1_TPC4_EML_CFG_SECTION 0xE800 |
|---|
| 2659 | #define mmDCORE1_TPC4_EML_CFG_SPECIAL_BASE 0x1840E80ull |
|---|
| 2660 | #define DCORE1_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2661 | #define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2662 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1841000ull |
|---|
| 2663 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2664 | #define DCORE1_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2665 | #define mmDCORE1_TPC4_EML_TPC_CFG_BASE 0x1841000ull |
|---|
| 2666 | #define DCORE1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 2667 | #define DCORE1_TPC4_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 2668 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1841050ull |
|---|
| 2669 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2670 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 2671 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x18410A0ull |
|---|
| 2672 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2673 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 2674 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x18410F0ull |
|---|
| 2675 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2676 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 2677 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1841140ull |
|---|
| 2678 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2679 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 2680 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1841190ull |
|---|
| 2681 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2682 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 2683 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x18411E0ull |
|---|
| 2684 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2685 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 2686 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1841230ull |
|---|
| 2687 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2688 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 2689 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1841280ull |
|---|
| 2690 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2691 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 2692 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x18412D0ull |
|---|
| 2693 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2694 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 2695 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1841320ull |
|---|
| 2696 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2697 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 2698 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1841370ull |
|---|
| 2699 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2700 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 2701 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x18413C0ull |
|---|
| 2702 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2703 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 2704 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1841410ull |
|---|
| 2705 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2706 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 2707 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1841460ull |
|---|
| 2708 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2709 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 2710 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x18414B0ull |
|---|
| 2711 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2712 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 2713 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1841500ull |
|---|
| 2714 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2715 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2716 | #define mmDCORE1_TPC4_EML_TPC_CFG_KERNEL_BASE 0x1841508ull |
|---|
| 2717 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 2718 | #define DCORE1_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 2719 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x18415DCull |
|---|
| 2720 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2721 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 2722 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x184162Cull |
|---|
| 2723 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2724 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 2725 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x184167Cull |
|---|
| 2726 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2727 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 2728 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x18416CCull |
|---|
| 2729 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2730 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 2731 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x184171Cull |
|---|
| 2732 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2733 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 2734 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x184176Cull |
|---|
| 2735 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2736 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 2737 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x18417BCull |
|---|
| 2738 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2739 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 2740 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x184180Cull |
|---|
| 2741 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2742 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 2743 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x184185Cull |
|---|
| 2744 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2745 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 2746 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x18418ACull |
|---|
| 2747 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2748 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 2749 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x18418FCull |
|---|
| 2750 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2751 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 2752 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x184194Cull |
|---|
| 2753 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2754 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 2755 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x184199Cull |
|---|
| 2756 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2757 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 2758 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x18419ECull |
|---|
| 2759 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2760 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 2761 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1841A3Cull |
|---|
| 2762 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2763 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 2764 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1841A8Cull |
|---|
| 2765 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2766 | #define DCORE1_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 2767 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1841ADCull |
|---|
| 2768 | #define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2769 | #define DCORE1_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2770 | #define mmDCORE1_TPC4_EML_TPC_CFG_QM_BASE 0x1841AE4ull |
|---|
| 2771 | #define DCORE1_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 2772 | #define DCORE1_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 2773 | #define mmDCORE1_TPC4_EML_TPC_CFG_AXUSER_BASE 0x1841E00ull |
|---|
| 2774 | #define DCORE1_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 2775 | #define DCORE1_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 2776 | #define mmDCORE1_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x1841E80ull |
|---|
| 2777 | #define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2778 | #define DCORE1_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2779 | #define mmDCORE1_TPC4_EML_QM_DCCM_BASE 0x1842000ull |
|---|
| 2780 | #define DCORE1_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 2781 | #define DCORE1_TPC4_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 2782 | #define mmDCORE1_TPC4_EML_QM_ARCAUX_BASE 0x184A000ull |
|---|
| 2783 | #define DCORE1_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 2784 | #define DCORE1_TPC4_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 2785 | #define mmDCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x184AE80ull |
|---|
| 2786 | #define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2787 | #define DCORE1_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 2788 | #define mmDCORE1_TPC4_EML_TPC_QM_BASE 0x184C000ull |
|---|
| 2789 | #define DCORE1_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 2790 | #define DCORE1_TPC4_EML_TPC_QM_SECTION 0x9000 |
|---|
| 2791 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x184C900ull |
|---|
| 2792 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 2793 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 2794 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x184C908ull |
|---|
| 2795 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 2796 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 2797 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x184C910ull |
|---|
| 2798 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 2799 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 2800 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x184C918ull |
|---|
| 2801 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 2802 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 2803 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x184C920ull |
|---|
| 2804 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 2805 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 2806 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x184C928ull |
|---|
| 2807 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 2808 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 2809 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x184C930ull |
|---|
| 2810 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 2811 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 2812 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x184C938ull |
|---|
| 2813 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 2814 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 2815 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x184C940ull |
|---|
| 2816 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 2817 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 2818 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x184C948ull |
|---|
| 2819 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 2820 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 2821 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x184C950ull |
|---|
| 2822 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 2823 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 2824 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x184C958ull |
|---|
| 2825 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 2826 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 2827 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x184C960ull |
|---|
| 2828 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 2829 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 2830 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x184C968ull |
|---|
| 2831 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 2832 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 2833 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x184C970ull |
|---|
| 2834 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 2835 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 2836 | #define mmDCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x184C978ull |
|---|
| 2837 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 2838 | #define DCORE1_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 2839 | #define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x184CB00ull |
|---|
| 2840 | #define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 2841 | #define DCORE1_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 2842 | #define mmDCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x184CB80ull |
|---|
| 2843 | #define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 2844 | #define DCORE1_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 2845 | #define mmDCORE1_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x184CC00ull |
|---|
| 2846 | #define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 2847 | #define DCORE1_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 2848 | #define mmDCORE1_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x184CC80ull |
|---|
| 2849 | #define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 2850 | #define DCORE1_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 2851 | #define mmDCORE1_TPC4_EML_TPC_QM_CGM_BASE 0x184CD80ull |
|---|
| 2852 | #define DCORE1_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 2853 | #define DCORE1_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 2854 | #define mmDCORE1_TPC4_EML_TPC_QM_SPECIAL_BASE 0x184CE80ull |
|---|
| 2855 | #define DCORE1_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2856 | #define DCORE1_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 2857 | #define mmDCORE1_TPC4_EML_CS_BASE 0x19FF000ull |
|---|
| 2858 | #define DCORE1_TPC4_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 2859 | #define DCORE1_TPC4_EML_CS_SECTION 0x1000 |
|---|
| 2860 | #define mmDCORE1_TPC5_ROM_TABLE_BASE 0x1A00000ull |
|---|
| 2861 | #define DCORE1_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 2862 | #define DCORE1_TPC5_ROM_TABLE_SECTION 0x1000 |
|---|
| 2863 | #define mmDCORE1_TPC5_EML_SPMU_BASE 0x1A01000ull |
|---|
| 2864 | #define DCORE1_TPC5_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 2865 | #define DCORE1_TPC5_EML_SPMU_SECTION 0x1000 |
|---|
| 2866 | #define mmDCORE1_TPC5_EML_ETF_BASE 0x1A02000ull |
|---|
| 2867 | #define DCORE1_TPC5_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 2868 | #define DCORE1_TPC5_EML_ETF_SECTION 0x1000 |
|---|
| 2869 | #define mmDCORE1_TPC5_EML_STM_BASE 0x1A03000ull |
|---|
| 2870 | #define DCORE1_TPC5_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 2871 | #define DCORE1_TPC5_EML_STM_SECTION 0x2000 |
|---|
| 2872 | #define mmDCORE1_TPC5_EML_CTI_BASE 0x1A05000ull |
|---|
| 2873 | #define DCORE1_TPC5_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 2874 | #define DCORE1_TPC5_EML_CTI_SECTION 0x1000 |
|---|
| 2875 | #define mmDCORE1_TPC5_EML_FUNNEL_BASE 0x1A06000ull |
|---|
| 2876 | #define DCORE1_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 2877 | #define DCORE1_TPC5_EML_FUNNEL_SECTION 0x1000 |
|---|
| 2878 | #define mmDCORE1_TPC5_EML_BUSMON_0_BASE 0x1A07000ull |
|---|
| 2879 | #define DCORE1_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 2880 | #define DCORE1_TPC5_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 2881 | #define mmDCORE1_TPC5_EML_BUSMON_1_BASE 0x1A08000ull |
|---|
| 2882 | #define DCORE1_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 2883 | #define DCORE1_TPC5_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 2884 | #define mmDCORE1_TPC5_EML_BUSMON_2_BASE 0x1A09000ull |
|---|
| 2885 | #define DCORE1_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 2886 | #define DCORE1_TPC5_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 2887 | #define mmDCORE1_TPC5_EML_BUSMON_3_BASE 0x1A0A000ull |
|---|
| 2888 | #define DCORE1_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 2889 | #define DCORE1_TPC5_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 2890 | #define mmDCORE1_TPC5_QM_ARC_RTT_BASE 0x1A0B000ull |
|---|
| 2891 | #define DCORE1_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 2892 | #define DCORE1_TPC5_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 2893 | #define mmDCORE1_TPC5_EML_CFG_BASE 0x1A40000ull |
|---|
| 2894 | #define DCORE1_TPC5_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 2895 | #define DCORE1_TPC5_EML_CFG_SECTION 0xE800 |
|---|
| 2896 | #define mmDCORE1_TPC5_EML_CFG_SPECIAL_BASE 0x1A40E80ull |
|---|
| 2897 | #define DCORE1_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 2898 | #define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2899 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x1A41000ull |
|---|
| 2900 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2901 | #define DCORE1_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 2902 | #define mmDCORE1_TPC5_EML_TPC_CFG_BASE 0x1A41000ull |
|---|
| 2903 | #define DCORE1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 2904 | #define DCORE1_TPC5_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 2905 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x1A41050ull |
|---|
| 2906 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2907 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 2908 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x1A410A0ull |
|---|
| 2909 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2910 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 2911 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x1A410F0ull |
|---|
| 2912 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2913 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 2914 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x1A41140ull |
|---|
| 2915 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2916 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 2917 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x1A41190ull |
|---|
| 2918 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2919 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 2920 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x1A411E0ull |
|---|
| 2921 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2922 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 2923 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x1A41230ull |
|---|
| 2924 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2925 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 2926 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x1A41280ull |
|---|
| 2927 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2928 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 2929 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x1A412D0ull |
|---|
| 2930 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2931 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 2932 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x1A41320ull |
|---|
| 2933 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2934 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 2935 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x1A41370ull |
|---|
| 2936 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2937 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 2938 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x1A413C0ull |
|---|
| 2939 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2940 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 2941 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x1A41410ull |
|---|
| 2942 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2943 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 2944 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x1A41460ull |
|---|
| 2945 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 2946 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 2947 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x1A414B0ull |
|---|
| 2948 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 2949 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 2950 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x1A41500ull |
|---|
| 2951 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 2952 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 2953 | #define mmDCORE1_TPC5_EML_TPC_CFG_KERNEL_BASE 0x1A41508ull |
|---|
| 2954 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 2955 | #define DCORE1_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 2956 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x1A415DCull |
|---|
| 2957 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 2958 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 2959 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x1A4162Cull |
|---|
| 2960 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 2961 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 2962 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x1A4167Cull |
|---|
| 2963 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 2964 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 2965 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x1A416CCull |
|---|
| 2966 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 2967 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 2968 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x1A4171Cull |
|---|
| 2969 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 2970 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 2971 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x1A4176Cull |
|---|
| 2972 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 2973 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 2974 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x1A417BCull |
|---|
| 2975 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 2976 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 2977 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x1A4180Cull |
|---|
| 2978 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 2979 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 2980 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x1A4185Cull |
|---|
| 2981 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 2982 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 2983 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x1A418ACull |
|---|
| 2984 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 2985 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 2986 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x1A418FCull |
|---|
| 2987 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 2988 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 2989 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x1A4194Cull |
|---|
| 2990 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 2991 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 2992 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x1A4199Cull |
|---|
| 2993 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 2994 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 2995 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x1A419ECull |
|---|
| 2996 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 2997 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 2998 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x1A41A3Cull |
|---|
| 2999 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3000 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 3001 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x1A41A8Cull |
|---|
| 3002 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3003 | #define DCORE1_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 3004 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x1A41ADCull |
|---|
| 3005 | #define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3006 | #define DCORE1_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3007 | #define mmDCORE1_TPC5_EML_TPC_CFG_QM_BASE 0x1A41AE4ull |
|---|
| 3008 | #define DCORE1_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 3009 | #define DCORE1_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 3010 | #define mmDCORE1_TPC5_EML_TPC_CFG_AXUSER_BASE 0x1A41E00ull |
|---|
| 3011 | #define DCORE1_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 3012 | #define DCORE1_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 3013 | #define mmDCORE1_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x1A41E80ull |
|---|
| 3014 | #define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3015 | #define DCORE1_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3016 | #define mmDCORE1_TPC5_EML_QM_DCCM_BASE 0x1A42000ull |
|---|
| 3017 | #define DCORE1_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 3018 | #define DCORE1_TPC5_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 3019 | #define mmDCORE1_TPC5_EML_QM_ARCAUX_BASE 0x1A4A000ull |
|---|
| 3020 | #define DCORE1_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 3021 | #define DCORE1_TPC5_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 3022 | #define mmDCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x1A4AE80ull |
|---|
| 3023 | #define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3024 | #define DCORE1_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 3025 | #define mmDCORE1_TPC5_EML_TPC_QM_BASE 0x1A4C000ull |
|---|
| 3026 | #define DCORE1_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 3027 | #define DCORE1_TPC5_EML_TPC_QM_SECTION 0x9000 |
|---|
| 3028 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x1A4C900ull |
|---|
| 3029 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 3030 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 3031 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x1A4C908ull |
|---|
| 3032 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 3033 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 3034 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x1A4C910ull |
|---|
| 3035 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 3036 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 3037 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x1A4C918ull |
|---|
| 3038 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 3039 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 3040 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x1A4C920ull |
|---|
| 3041 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 3042 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 3043 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x1A4C928ull |
|---|
| 3044 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 3045 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 3046 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x1A4C930ull |
|---|
| 3047 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 3048 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 3049 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x1A4C938ull |
|---|
| 3050 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 3051 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 3052 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x1A4C940ull |
|---|
| 3053 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 3054 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 3055 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x1A4C948ull |
|---|
| 3056 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 3057 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 3058 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x1A4C950ull |
|---|
| 3059 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 3060 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 3061 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x1A4C958ull |
|---|
| 3062 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 3063 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 3064 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x1A4C960ull |
|---|
| 3065 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 3066 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 3067 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x1A4C968ull |
|---|
| 3068 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 3069 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 3070 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x1A4C970ull |
|---|
| 3071 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 3072 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 3073 | #define mmDCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x1A4C978ull |
|---|
| 3074 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 3075 | #define DCORE1_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 3076 | #define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x1A4CB00ull |
|---|
| 3077 | #define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 3078 | #define DCORE1_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 3079 | #define mmDCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x1A4CB80ull |
|---|
| 3080 | #define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 3081 | #define DCORE1_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 3082 | #define mmDCORE1_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x1A4CC00ull |
|---|
| 3083 | #define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 3084 | #define DCORE1_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 3085 | #define mmDCORE1_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x1A4CC80ull |
|---|
| 3086 | #define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 3087 | #define DCORE1_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 3088 | #define mmDCORE1_TPC5_EML_TPC_QM_CGM_BASE 0x1A4CD80ull |
|---|
| 3089 | #define DCORE1_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 3090 | #define DCORE1_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 3091 | #define mmDCORE1_TPC5_EML_TPC_QM_SPECIAL_BASE 0x1A4CE80ull |
|---|
| 3092 | #define DCORE1_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3093 | #define DCORE1_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 3094 | #define mmDCORE1_TPC5_EML_CS_BASE 0x1BFF000ull |
|---|
| 3095 | #define DCORE1_TPC5_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 3096 | #define DCORE1_TPC5_EML_CS_SECTION 0x401000 |
|---|
| 3097 | #define mmDCORE2_TPC0_ROM_TABLE_BASE 0x2000000ull |
|---|
| 3098 | #define DCORE2_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 3099 | #define DCORE2_TPC0_ROM_TABLE_SECTION 0x1000 |
|---|
| 3100 | #define mmDCORE2_TPC0_EML_SPMU_BASE 0x2001000ull |
|---|
| 3101 | #define DCORE2_TPC0_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 3102 | #define DCORE2_TPC0_EML_SPMU_SECTION 0x1000 |
|---|
| 3103 | #define mmDCORE2_TPC0_EML_ETF_BASE 0x2002000ull |
|---|
| 3104 | #define DCORE2_TPC0_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 3105 | #define DCORE2_TPC0_EML_ETF_SECTION 0x1000 |
|---|
| 3106 | #define mmDCORE2_TPC0_EML_STM_BASE 0x2003000ull |
|---|
| 3107 | #define DCORE2_TPC0_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 3108 | #define DCORE2_TPC0_EML_STM_SECTION 0x2000 |
|---|
| 3109 | #define mmDCORE2_TPC0_EML_CTI_BASE 0x2005000ull |
|---|
| 3110 | #define DCORE2_TPC0_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 3111 | #define DCORE2_TPC0_EML_CTI_SECTION 0x1000 |
|---|
| 3112 | #define mmDCORE2_TPC0_EML_FUNNEL_BASE 0x2006000ull |
|---|
| 3113 | #define DCORE2_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 3114 | #define DCORE2_TPC0_EML_FUNNEL_SECTION 0x1000 |
|---|
| 3115 | #define mmDCORE2_TPC0_EML_BUSMON_0_BASE 0x2007000ull |
|---|
| 3116 | #define DCORE2_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 3117 | #define DCORE2_TPC0_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 3118 | #define mmDCORE2_TPC0_EML_BUSMON_1_BASE 0x2008000ull |
|---|
| 3119 | #define DCORE2_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 3120 | #define DCORE2_TPC0_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 3121 | #define mmDCORE2_TPC0_EML_BUSMON_2_BASE 0x2009000ull |
|---|
| 3122 | #define DCORE2_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 3123 | #define DCORE2_TPC0_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 3124 | #define mmDCORE2_TPC0_EML_BUSMON_3_BASE 0x200A000ull |
|---|
| 3125 | #define DCORE2_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 3126 | #define DCORE2_TPC0_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 3127 | #define mmDCORE2_TPC0_QM_ARC_RTT_BASE 0x200B000ull |
|---|
| 3128 | #define DCORE2_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 3129 | #define DCORE2_TPC0_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 3130 | #define mmDCORE2_TPC0_EML_CFG_BASE 0x2040000ull |
|---|
| 3131 | #define DCORE2_TPC0_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 3132 | #define DCORE2_TPC0_EML_CFG_SECTION 0xE800 |
|---|
| 3133 | #define mmDCORE2_TPC0_EML_CFG_SPECIAL_BASE 0x2040E80ull |
|---|
| 3134 | #define DCORE2_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3135 | #define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3136 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2041000ull |
|---|
| 3137 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3138 | #define DCORE2_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3139 | #define mmDCORE2_TPC0_EML_TPC_CFG_BASE 0x2041000ull |
|---|
| 3140 | #define DCORE2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 3141 | #define DCORE2_TPC0_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 3142 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2041050ull |
|---|
| 3143 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3144 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 3145 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x20410A0ull |
|---|
| 3146 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3147 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 3148 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x20410F0ull |
|---|
| 3149 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3150 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 3151 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2041140ull |
|---|
| 3152 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3153 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 3154 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2041190ull |
|---|
| 3155 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3156 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 3157 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x20411E0ull |
|---|
| 3158 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3159 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 3160 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2041230ull |
|---|
| 3161 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3162 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 3163 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2041280ull |
|---|
| 3164 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3165 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 3166 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x20412D0ull |
|---|
| 3167 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3168 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 3169 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2041320ull |
|---|
| 3170 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3171 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 3172 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2041370ull |
|---|
| 3173 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3174 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 3175 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x20413C0ull |
|---|
| 3176 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3177 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 3178 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2041410ull |
|---|
| 3179 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3180 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 3181 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2041460ull |
|---|
| 3182 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3183 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 3184 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x20414B0ull |
|---|
| 3185 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3186 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 3187 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2041500ull |
|---|
| 3188 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3189 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3190 | #define mmDCORE2_TPC0_EML_TPC_CFG_KERNEL_BASE 0x2041508ull |
|---|
| 3191 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 3192 | #define DCORE2_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 3193 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x20415DCull |
|---|
| 3194 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3195 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 3196 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x204162Cull |
|---|
| 3197 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3198 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 3199 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x204167Cull |
|---|
| 3200 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3201 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 3202 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x20416CCull |
|---|
| 3203 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3204 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 3205 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x204171Cull |
|---|
| 3206 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3207 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 3208 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x204176Cull |
|---|
| 3209 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3210 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 3211 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x20417BCull |
|---|
| 3212 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3213 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 3214 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x204180Cull |
|---|
| 3215 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3216 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 3217 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x204185Cull |
|---|
| 3218 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3219 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 3220 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x20418ACull |
|---|
| 3221 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3222 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 3223 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x20418FCull |
|---|
| 3224 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3225 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 3226 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x204194Cull |
|---|
| 3227 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3228 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 3229 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x204199Cull |
|---|
| 3230 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3231 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 3232 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x20419ECull |
|---|
| 3233 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3234 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 3235 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2041A3Cull |
|---|
| 3236 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3237 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 3238 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2041A8Cull |
|---|
| 3239 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3240 | #define DCORE2_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 3241 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2041ADCull |
|---|
| 3242 | #define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3243 | #define DCORE2_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3244 | #define mmDCORE2_TPC0_EML_TPC_CFG_QM_BASE 0x2041AE4ull |
|---|
| 3245 | #define DCORE2_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 3246 | #define DCORE2_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 3247 | #define mmDCORE2_TPC0_EML_TPC_CFG_AXUSER_BASE 0x2041E00ull |
|---|
| 3248 | #define DCORE2_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 3249 | #define DCORE2_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 3250 | #define mmDCORE2_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x2041E80ull |
|---|
| 3251 | #define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3252 | #define DCORE2_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3253 | #define mmDCORE2_TPC0_EML_QM_DCCM_BASE 0x2042000ull |
|---|
| 3254 | #define DCORE2_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 3255 | #define DCORE2_TPC0_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 3256 | #define mmDCORE2_TPC0_EML_QM_ARCAUX_BASE 0x204A000ull |
|---|
| 3257 | #define DCORE2_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 3258 | #define DCORE2_TPC0_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 3259 | #define mmDCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x204AE80ull |
|---|
| 3260 | #define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3261 | #define DCORE2_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 3262 | #define mmDCORE2_TPC0_EML_TPC_QM_BASE 0x204C000ull |
|---|
| 3263 | #define DCORE2_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 3264 | #define DCORE2_TPC0_EML_TPC_QM_SECTION 0x9000 |
|---|
| 3265 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x204C900ull |
|---|
| 3266 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 3267 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 3268 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x204C908ull |
|---|
| 3269 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 3270 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 3271 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x204C910ull |
|---|
| 3272 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 3273 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 3274 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x204C918ull |
|---|
| 3275 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 3276 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 3277 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x204C920ull |
|---|
| 3278 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 3279 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 3280 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x204C928ull |
|---|
| 3281 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 3282 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 3283 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x204C930ull |
|---|
| 3284 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 3285 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 3286 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x204C938ull |
|---|
| 3287 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 3288 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 3289 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x204C940ull |
|---|
| 3290 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 3291 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 3292 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x204C948ull |
|---|
| 3293 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 3294 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 3295 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x204C950ull |
|---|
| 3296 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 3297 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 3298 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x204C958ull |
|---|
| 3299 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 3300 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 3301 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x204C960ull |
|---|
| 3302 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 3303 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 3304 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x204C968ull |
|---|
| 3305 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 3306 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 3307 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x204C970ull |
|---|
| 3308 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 3309 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 3310 | #define mmDCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x204C978ull |
|---|
| 3311 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 3312 | #define DCORE2_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 3313 | #define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x204CB00ull |
|---|
| 3314 | #define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 3315 | #define DCORE2_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 3316 | #define mmDCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x204CB80ull |
|---|
| 3317 | #define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 3318 | #define DCORE2_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 3319 | #define mmDCORE2_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x204CC00ull |
|---|
| 3320 | #define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 3321 | #define DCORE2_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 3322 | #define mmDCORE2_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x204CC80ull |
|---|
| 3323 | #define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 3324 | #define DCORE2_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 3325 | #define mmDCORE2_TPC0_EML_TPC_QM_CGM_BASE 0x204CD80ull |
|---|
| 3326 | #define DCORE2_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 3327 | #define DCORE2_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 3328 | #define mmDCORE2_TPC0_EML_TPC_QM_SPECIAL_BASE 0x204CE80ull |
|---|
| 3329 | #define DCORE2_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3330 | #define DCORE2_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 3331 | #define mmDCORE2_TPC0_EML_CS_BASE 0x21FF000ull |
|---|
| 3332 | #define DCORE2_TPC0_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 3333 | #define DCORE2_TPC0_EML_CS_SECTION 0x1000 |
|---|
| 3334 | #define mmDCORE2_TPC1_ROM_TABLE_BASE 0x2200000ull |
|---|
| 3335 | #define DCORE2_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 3336 | #define DCORE2_TPC1_ROM_TABLE_SECTION 0x1000 |
|---|
| 3337 | #define mmDCORE2_TPC1_EML_SPMU_BASE 0x2201000ull |
|---|
| 3338 | #define DCORE2_TPC1_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 3339 | #define DCORE2_TPC1_EML_SPMU_SECTION 0x1000 |
|---|
| 3340 | #define mmDCORE2_TPC1_EML_ETF_BASE 0x2202000ull |
|---|
| 3341 | #define DCORE2_TPC1_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 3342 | #define DCORE2_TPC1_EML_ETF_SECTION 0x1000 |
|---|
| 3343 | #define mmDCORE2_TPC1_EML_STM_BASE 0x2203000ull |
|---|
| 3344 | #define DCORE2_TPC1_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 3345 | #define DCORE2_TPC1_EML_STM_SECTION 0x2000 |
|---|
| 3346 | #define mmDCORE2_TPC1_EML_CTI_BASE 0x2205000ull |
|---|
| 3347 | #define DCORE2_TPC1_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 3348 | #define DCORE2_TPC1_EML_CTI_SECTION 0x1000 |
|---|
| 3349 | #define mmDCORE2_TPC1_EML_FUNNEL_BASE 0x2206000ull |
|---|
| 3350 | #define DCORE2_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 3351 | #define DCORE2_TPC1_EML_FUNNEL_SECTION 0x1000 |
|---|
| 3352 | #define mmDCORE2_TPC1_EML_BUSMON_0_BASE 0x2207000ull |
|---|
| 3353 | #define DCORE2_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 3354 | #define DCORE2_TPC1_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 3355 | #define mmDCORE2_TPC1_EML_BUSMON_1_BASE 0x2208000ull |
|---|
| 3356 | #define DCORE2_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 3357 | #define DCORE2_TPC1_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 3358 | #define mmDCORE2_TPC1_EML_BUSMON_2_BASE 0x2209000ull |
|---|
| 3359 | #define DCORE2_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 3360 | #define DCORE2_TPC1_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 3361 | #define mmDCORE2_TPC1_EML_BUSMON_3_BASE 0x220A000ull |
|---|
| 3362 | #define DCORE2_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 3363 | #define DCORE2_TPC1_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 3364 | #define mmDCORE2_TPC1_QM_ARC_RTT_BASE 0x220B000ull |
|---|
| 3365 | #define DCORE2_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 3366 | #define DCORE2_TPC1_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 3367 | #define mmDCORE2_TPC1_EML_CFG_BASE 0x2240000ull |
|---|
| 3368 | #define DCORE2_TPC1_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 3369 | #define DCORE2_TPC1_EML_CFG_SECTION 0xE800 |
|---|
| 3370 | #define mmDCORE2_TPC1_EML_CFG_SPECIAL_BASE 0x2240E80ull |
|---|
| 3371 | #define DCORE2_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3372 | #define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3373 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2241000ull |
|---|
| 3374 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3375 | #define DCORE2_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3376 | #define mmDCORE2_TPC1_EML_TPC_CFG_BASE 0x2241000ull |
|---|
| 3377 | #define DCORE2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 3378 | #define DCORE2_TPC1_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 3379 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2241050ull |
|---|
| 3380 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3381 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 3382 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x22410A0ull |
|---|
| 3383 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3384 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 3385 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x22410F0ull |
|---|
| 3386 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3387 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 3388 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2241140ull |
|---|
| 3389 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3390 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 3391 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2241190ull |
|---|
| 3392 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3393 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 3394 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x22411E0ull |
|---|
| 3395 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3396 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 3397 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2241230ull |
|---|
| 3398 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3399 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 3400 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2241280ull |
|---|
| 3401 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3402 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 3403 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x22412D0ull |
|---|
| 3404 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3405 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 3406 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2241320ull |
|---|
| 3407 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3408 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 3409 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2241370ull |
|---|
| 3410 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3411 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 3412 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x22413C0ull |
|---|
| 3413 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3414 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 3415 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2241410ull |
|---|
| 3416 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3417 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 3418 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2241460ull |
|---|
| 3419 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3420 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 3421 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x22414B0ull |
|---|
| 3422 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3423 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 3424 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2241500ull |
|---|
| 3425 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3426 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3427 | #define mmDCORE2_TPC1_EML_TPC_CFG_KERNEL_BASE 0x2241508ull |
|---|
| 3428 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 3429 | #define DCORE2_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 3430 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x22415DCull |
|---|
| 3431 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3432 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 3433 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x224162Cull |
|---|
| 3434 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3435 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 3436 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x224167Cull |
|---|
| 3437 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3438 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 3439 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x22416CCull |
|---|
| 3440 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3441 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 3442 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x224171Cull |
|---|
| 3443 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3444 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 3445 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x224176Cull |
|---|
| 3446 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3447 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 3448 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x22417BCull |
|---|
| 3449 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3450 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 3451 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x224180Cull |
|---|
| 3452 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3453 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 3454 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x224185Cull |
|---|
| 3455 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3456 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 3457 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x22418ACull |
|---|
| 3458 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3459 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 3460 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x22418FCull |
|---|
| 3461 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3462 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 3463 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x224194Cull |
|---|
| 3464 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3465 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 3466 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x224199Cull |
|---|
| 3467 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3468 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 3469 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x22419ECull |
|---|
| 3470 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3471 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 3472 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2241A3Cull |
|---|
| 3473 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3474 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 3475 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2241A8Cull |
|---|
| 3476 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3477 | #define DCORE2_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 3478 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2241ADCull |
|---|
| 3479 | #define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3480 | #define DCORE2_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3481 | #define mmDCORE2_TPC1_EML_TPC_CFG_QM_BASE 0x2241AE4ull |
|---|
| 3482 | #define DCORE2_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 3483 | #define DCORE2_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 3484 | #define mmDCORE2_TPC1_EML_TPC_CFG_AXUSER_BASE 0x2241E00ull |
|---|
| 3485 | #define DCORE2_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 3486 | #define DCORE2_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 3487 | #define mmDCORE2_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x2241E80ull |
|---|
| 3488 | #define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3489 | #define DCORE2_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3490 | #define mmDCORE2_TPC1_EML_QM_DCCM_BASE 0x2242000ull |
|---|
| 3491 | #define DCORE2_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 3492 | #define DCORE2_TPC1_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 3493 | #define mmDCORE2_TPC1_EML_QM_ARCAUX_BASE 0x224A000ull |
|---|
| 3494 | #define DCORE2_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 3495 | #define DCORE2_TPC1_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 3496 | #define mmDCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x224AE80ull |
|---|
| 3497 | #define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3498 | #define DCORE2_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 3499 | #define mmDCORE2_TPC1_EML_TPC_QM_BASE 0x224C000ull |
|---|
| 3500 | #define DCORE2_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 3501 | #define DCORE2_TPC1_EML_TPC_QM_SECTION 0x9000 |
|---|
| 3502 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x224C900ull |
|---|
| 3503 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 3504 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 3505 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x224C908ull |
|---|
| 3506 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 3507 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 3508 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x224C910ull |
|---|
| 3509 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 3510 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 3511 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x224C918ull |
|---|
| 3512 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 3513 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 3514 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x224C920ull |
|---|
| 3515 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 3516 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 3517 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x224C928ull |
|---|
| 3518 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 3519 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 3520 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x224C930ull |
|---|
| 3521 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 3522 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 3523 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x224C938ull |
|---|
| 3524 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 3525 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 3526 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x224C940ull |
|---|
| 3527 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 3528 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 3529 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x224C948ull |
|---|
| 3530 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 3531 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 3532 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x224C950ull |
|---|
| 3533 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 3534 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 3535 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x224C958ull |
|---|
| 3536 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 3537 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 3538 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x224C960ull |
|---|
| 3539 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 3540 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 3541 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x224C968ull |
|---|
| 3542 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 3543 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 3544 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x224C970ull |
|---|
| 3545 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 3546 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 3547 | #define mmDCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x224C978ull |
|---|
| 3548 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 3549 | #define DCORE2_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 3550 | #define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x224CB00ull |
|---|
| 3551 | #define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 3552 | #define DCORE2_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 3553 | #define mmDCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x224CB80ull |
|---|
| 3554 | #define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 3555 | #define DCORE2_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 3556 | #define mmDCORE2_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x224CC00ull |
|---|
| 3557 | #define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 3558 | #define DCORE2_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 3559 | #define mmDCORE2_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x224CC80ull |
|---|
| 3560 | #define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 3561 | #define DCORE2_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 3562 | #define mmDCORE2_TPC1_EML_TPC_QM_CGM_BASE 0x224CD80ull |
|---|
| 3563 | #define DCORE2_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 3564 | #define DCORE2_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 3565 | #define mmDCORE2_TPC1_EML_TPC_QM_SPECIAL_BASE 0x224CE80ull |
|---|
| 3566 | #define DCORE2_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3567 | #define DCORE2_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 3568 | #define mmDCORE2_TPC1_EML_CS_BASE 0x23FF000ull |
|---|
| 3569 | #define DCORE2_TPC1_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 3570 | #define DCORE2_TPC1_EML_CS_SECTION 0x1000 |
|---|
| 3571 | #define mmDCORE2_TPC2_ROM_TABLE_BASE 0x2400000ull |
|---|
| 3572 | #define DCORE2_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 3573 | #define DCORE2_TPC2_ROM_TABLE_SECTION 0x1000 |
|---|
| 3574 | #define mmDCORE2_TPC2_EML_SPMU_BASE 0x2401000ull |
|---|
| 3575 | #define DCORE2_TPC2_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 3576 | #define DCORE2_TPC2_EML_SPMU_SECTION 0x1000 |
|---|
| 3577 | #define mmDCORE2_TPC2_EML_ETF_BASE 0x2402000ull |
|---|
| 3578 | #define DCORE2_TPC2_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 3579 | #define DCORE2_TPC2_EML_ETF_SECTION 0x1000 |
|---|
| 3580 | #define mmDCORE2_TPC2_EML_STM_BASE 0x2403000ull |
|---|
| 3581 | #define DCORE2_TPC2_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 3582 | #define DCORE2_TPC2_EML_STM_SECTION 0x2000 |
|---|
| 3583 | #define mmDCORE2_TPC2_EML_CTI_BASE 0x2405000ull |
|---|
| 3584 | #define DCORE2_TPC2_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 3585 | #define DCORE2_TPC2_EML_CTI_SECTION 0x1000 |
|---|
| 3586 | #define mmDCORE2_TPC2_EML_FUNNEL_BASE 0x2406000ull |
|---|
| 3587 | #define DCORE2_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 3588 | #define DCORE2_TPC2_EML_FUNNEL_SECTION 0x1000 |
|---|
| 3589 | #define mmDCORE2_TPC2_EML_BUSMON_0_BASE 0x2407000ull |
|---|
| 3590 | #define DCORE2_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 3591 | #define DCORE2_TPC2_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 3592 | #define mmDCORE2_TPC2_EML_BUSMON_1_BASE 0x2408000ull |
|---|
| 3593 | #define DCORE2_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 3594 | #define DCORE2_TPC2_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 3595 | #define mmDCORE2_TPC2_EML_BUSMON_2_BASE 0x2409000ull |
|---|
| 3596 | #define DCORE2_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 3597 | #define DCORE2_TPC2_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 3598 | #define mmDCORE2_TPC2_EML_BUSMON_3_BASE 0x240A000ull |
|---|
| 3599 | #define DCORE2_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 3600 | #define DCORE2_TPC2_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 3601 | #define mmDCORE2_TPC2_QM_ARC_RTT_BASE 0x240B000ull |
|---|
| 3602 | #define DCORE2_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 3603 | #define DCORE2_TPC2_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 3604 | #define mmDCORE2_TPC2_EML_CFG_BASE 0x2440000ull |
|---|
| 3605 | #define DCORE2_TPC2_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 3606 | #define DCORE2_TPC2_EML_CFG_SECTION 0xE800 |
|---|
| 3607 | #define mmDCORE2_TPC2_EML_CFG_SPECIAL_BASE 0x2440E80ull |
|---|
| 3608 | #define DCORE2_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3609 | #define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3610 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2441000ull |
|---|
| 3611 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3612 | #define DCORE2_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3613 | #define mmDCORE2_TPC2_EML_TPC_CFG_BASE 0x2441000ull |
|---|
| 3614 | #define DCORE2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 3615 | #define DCORE2_TPC2_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 3616 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2441050ull |
|---|
| 3617 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3618 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 3619 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x24410A0ull |
|---|
| 3620 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3621 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 3622 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x24410F0ull |
|---|
| 3623 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3624 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 3625 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2441140ull |
|---|
| 3626 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3627 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 3628 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2441190ull |
|---|
| 3629 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3630 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 3631 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x24411E0ull |
|---|
| 3632 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3633 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 3634 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2441230ull |
|---|
| 3635 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3636 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 3637 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2441280ull |
|---|
| 3638 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3639 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 3640 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x24412D0ull |
|---|
| 3641 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3642 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 3643 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2441320ull |
|---|
| 3644 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3645 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 3646 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2441370ull |
|---|
| 3647 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3648 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 3649 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x24413C0ull |
|---|
| 3650 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3651 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 3652 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2441410ull |
|---|
| 3653 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3654 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 3655 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2441460ull |
|---|
| 3656 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3657 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 3658 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x24414B0ull |
|---|
| 3659 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3660 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 3661 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2441500ull |
|---|
| 3662 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3663 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3664 | #define mmDCORE2_TPC2_EML_TPC_CFG_KERNEL_BASE 0x2441508ull |
|---|
| 3665 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 3666 | #define DCORE2_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 3667 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x24415DCull |
|---|
| 3668 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3669 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 3670 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x244162Cull |
|---|
| 3671 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3672 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 3673 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x244167Cull |
|---|
| 3674 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3675 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 3676 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x24416CCull |
|---|
| 3677 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3678 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 3679 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x244171Cull |
|---|
| 3680 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3681 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 3682 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x244176Cull |
|---|
| 3683 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3684 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 3685 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x24417BCull |
|---|
| 3686 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3687 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 3688 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x244180Cull |
|---|
| 3689 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3690 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 3691 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x244185Cull |
|---|
| 3692 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3693 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 3694 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x24418ACull |
|---|
| 3695 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3696 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 3697 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x24418FCull |
|---|
| 3698 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3699 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 3700 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x244194Cull |
|---|
| 3701 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3702 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 3703 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x244199Cull |
|---|
| 3704 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3705 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 3706 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x24419ECull |
|---|
| 3707 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3708 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 3709 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2441A3Cull |
|---|
| 3710 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3711 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 3712 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2441A8Cull |
|---|
| 3713 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3714 | #define DCORE2_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 3715 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2441ADCull |
|---|
| 3716 | #define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3717 | #define DCORE2_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3718 | #define mmDCORE2_TPC2_EML_TPC_CFG_QM_BASE 0x2441AE4ull |
|---|
| 3719 | #define DCORE2_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 3720 | #define DCORE2_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 3721 | #define mmDCORE2_TPC2_EML_TPC_CFG_AXUSER_BASE 0x2441E00ull |
|---|
| 3722 | #define DCORE2_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 3723 | #define DCORE2_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 3724 | #define mmDCORE2_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x2441E80ull |
|---|
| 3725 | #define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3726 | #define DCORE2_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3727 | #define mmDCORE2_TPC2_EML_QM_DCCM_BASE 0x2442000ull |
|---|
| 3728 | #define DCORE2_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 3729 | #define DCORE2_TPC2_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 3730 | #define mmDCORE2_TPC2_EML_QM_ARCAUX_BASE 0x244A000ull |
|---|
| 3731 | #define DCORE2_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 3732 | #define DCORE2_TPC2_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 3733 | #define mmDCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x244AE80ull |
|---|
| 3734 | #define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3735 | #define DCORE2_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 3736 | #define mmDCORE2_TPC2_EML_TPC_QM_BASE 0x244C000ull |
|---|
| 3737 | #define DCORE2_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 3738 | #define DCORE2_TPC2_EML_TPC_QM_SECTION 0x9000 |
|---|
| 3739 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x244C900ull |
|---|
| 3740 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 3741 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 3742 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x244C908ull |
|---|
| 3743 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 3744 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 3745 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x244C910ull |
|---|
| 3746 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 3747 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 3748 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x244C918ull |
|---|
| 3749 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 3750 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 3751 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x244C920ull |
|---|
| 3752 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 3753 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 3754 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x244C928ull |
|---|
| 3755 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 3756 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 3757 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x244C930ull |
|---|
| 3758 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 3759 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 3760 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x244C938ull |
|---|
| 3761 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 3762 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 3763 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x244C940ull |
|---|
| 3764 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 3765 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 3766 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x244C948ull |
|---|
| 3767 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 3768 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 3769 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x244C950ull |
|---|
| 3770 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 3771 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 3772 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x244C958ull |
|---|
| 3773 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 3774 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 3775 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x244C960ull |
|---|
| 3776 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 3777 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 3778 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x244C968ull |
|---|
| 3779 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 3780 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 3781 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x244C970ull |
|---|
| 3782 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 3783 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 3784 | #define mmDCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x244C978ull |
|---|
| 3785 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 3786 | #define DCORE2_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 3787 | #define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x244CB00ull |
|---|
| 3788 | #define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 3789 | #define DCORE2_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 3790 | #define mmDCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x244CB80ull |
|---|
| 3791 | #define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 3792 | #define DCORE2_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 3793 | #define mmDCORE2_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x244CC00ull |
|---|
| 3794 | #define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 3795 | #define DCORE2_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 3796 | #define mmDCORE2_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x244CC80ull |
|---|
| 3797 | #define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 3798 | #define DCORE2_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 3799 | #define mmDCORE2_TPC2_EML_TPC_QM_CGM_BASE 0x244CD80ull |
|---|
| 3800 | #define DCORE2_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 3801 | #define DCORE2_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 3802 | #define mmDCORE2_TPC2_EML_TPC_QM_SPECIAL_BASE 0x244CE80ull |
|---|
| 3803 | #define DCORE2_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3804 | #define DCORE2_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 3805 | #define mmDCORE2_TPC2_EML_CS_BASE 0x25FF000ull |
|---|
| 3806 | #define DCORE2_TPC2_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 3807 | #define DCORE2_TPC2_EML_CS_SECTION 0x1000 |
|---|
| 3808 | #define mmDCORE2_TPC3_ROM_TABLE_BASE 0x2600000ull |
|---|
| 3809 | #define DCORE2_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 3810 | #define DCORE2_TPC3_ROM_TABLE_SECTION 0x1000 |
|---|
| 3811 | #define mmDCORE2_TPC3_EML_SPMU_BASE 0x2601000ull |
|---|
| 3812 | #define DCORE2_TPC3_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 3813 | #define DCORE2_TPC3_EML_SPMU_SECTION 0x1000 |
|---|
| 3814 | #define mmDCORE2_TPC3_EML_ETF_BASE 0x2602000ull |
|---|
| 3815 | #define DCORE2_TPC3_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 3816 | #define DCORE2_TPC3_EML_ETF_SECTION 0x1000 |
|---|
| 3817 | #define mmDCORE2_TPC3_EML_STM_BASE 0x2603000ull |
|---|
| 3818 | #define DCORE2_TPC3_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 3819 | #define DCORE2_TPC3_EML_STM_SECTION 0x2000 |
|---|
| 3820 | #define mmDCORE2_TPC3_EML_CTI_BASE 0x2605000ull |
|---|
| 3821 | #define DCORE2_TPC3_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 3822 | #define DCORE2_TPC3_EML_CTI_SECTION 0x1000 |
|---|
| 3823 | #define mmDCORE2_TPC3_EML_FUNNEL_BASE 0x2606000ull |
|---|
| 3824 | #define DCORE2_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 3825 | #define DCORE2_TPC3_EML_FUNNEL_SECTION 0x1000 |
|---|
| 3826 | #define mmDCORE2_TPC3_EML_BUSMON_0_BASE 0x2607000ull |
|---|
| 3827 | #define DCORE2_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 3828 | #define DCORE2_TPC3_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 3829 | #define mmDCORE2_TPC3_EML_BUSMON_1_BASE 0x2608000ull |
|---|
| 3830 | #define DCORE2_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 3831 | #define DCORE2_TPC3_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 3832 | #define mmDCORE2_TPC3_EML_BUSMON_2_BASE 0x2609000ull |
|---|
| 3833 | #define DCORE2_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 3834 | #define DCORE2_TPC3_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 3835 | #define mmDCORE2_TPC3_EML_BUSMON_3_BASE 0x260A000ull |
|---|
| 3836 | #define DCORE2_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 3837 | #define DCORE2_TPC3_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 3838 | #define mmDCORE2_TPC3_QM_ARC_RTT_BASE 0x260B000ull |
|---|
| 3839 | #define DCORE2_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 3840 | #define DCORE2_TPC3_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 3841 | #define mmDCORE2_TPC3_EML_CFG_BASE 0x2640000ull |
|---|
| 3842 | #define DCORE2_TPC3_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 3843 | #define DCORE2_TPC3_EML_CFG_SECTION 0xE800 |
|---|
| 3844 | #define mmDCORE2_TPC3_EML_CFG_SPECIAL_BASE 0x2640E80ull |
|---|
| 3845 | #define DCORE2_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3846 | #define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3847 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2641000ull |
|---|
| 3848 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3849 | #define DCORE2_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3850 | #define mmDCORE2_TPC3_EML_TPC_CFG_BASE 0x2641000ull |
|---|
| 3851 | #define DCORE2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 3852 | #define DCORE2_TPC3_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 3853 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2641050ull |
|---|
| 3854 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3855 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 3856 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x26410A0ull |
|---|
| 3857 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3858 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 3859 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x26410F0ull |
|---|
| 3860 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3861 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 3862 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2641140ull |
|---|
| 3863 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3864 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 3865 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2641190ull |
|---|
| 3866 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3867 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 3868 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x26411E0ull |
|---|
| 3869 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3870 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 3871 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2641230ull |
|---|
| 3872 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3873 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 3874 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2641280ull |
|---|
| 3875 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3876 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 3877 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x26412D0ull |
|---|
| 3878 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3879 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 3880 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2641320ull |
|---|
| 3881 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3882 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 3883 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2641370ull |
|---|
| 3884 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3885 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 3886 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x26413C0ull |
|---|
| 3887 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3888 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 3889 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2641410ull |
|---|
| 3890 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3891 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 3892 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2641460ull |
|---|
| 3893 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3894 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 3895 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x26414B0ull |
|---|
| 3896 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3897 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 3898 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2641500ull |
|---|
| 3899 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3900 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3901 | #define mmDCORE2_TPC3_EML_TPC_CFG_KERNEL_BASE 0x2641508ull |
|---|
| 3902 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 3903 | #define DCORE2_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 3904 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x26415DCull |
|---|
| 3905 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 3906 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 3907 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x264162Cull |
|---|
| 3908 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 3909 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 3910 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x264167Cull |
|---|
| 3911 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 3912 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 3913 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x26416CCull |
|---|
| 3914 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 3915 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 3916 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x264171Cull |
|---|
| 3917 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 3918 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 3919 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x264176Cull |
|---|
| 3920 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 3921 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 3922 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x26417BCull |
|---|
| 3923 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 3924 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 3925 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x264180Cull |
|---|
| 3926 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 3927 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 3928 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x264185Cull |
|---|
| 3929 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 3930 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 3931 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x26418ACull |
|---|
| 3932 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 3933 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 3934 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x26418FCull |
|---|
| 3935 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 3936 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 3937 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x264194Cull |
|---|
| 3938 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 3939 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 3940 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x264199Cull |
|---|
| 3941 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 3942 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 3943 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x26419ECull |
|---|
| 3944 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 3945 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 3946 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2641A3Cull |
|---|
| 3947 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 3948 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 3949 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2641A8Cull |
|---|
| 3950 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 3951 | #define DCORE2_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 3952 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2641ADCull |
|---|
| 3953 | #define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 3954 | #define DCORE2_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 3955 | #define mmDCORE2_TPC3_EML_TPC_CFG_QM_BASE 0x2641AE4ull |
|---|
| 3956 | #define DCORE2_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 3957 | #define DCORE2_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 3958 | #define mmDCORE2_TPC3_EML_TPC_CFG_AXUSER_BASE 0x2641E00ull |
|---|
| 3959 | #define DCORE2_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 3960 | #define DCORE2_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 3961 | #define mmDCORE2_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x2641E80ull |
|---|
| 3962 | #define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3963 | #define DCORE2_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 3964 | #define mmDCORE2_TPC3_EML_QM_DCCM_BASE 0x2642000ull |
|---|
| 3965 | #define DCORE2_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 3966 | #define DCORE2_TPC3_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 3967 | #define mmDCORE2_TPC3_EML_QM_ARCAUX_BASE 0x264A000ull |
|---|
| 3968 | #define DCORE2_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 3969 | #define DCORE2_TPC3_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 3970 | #define mmDCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x264AE80ull |
|---|
| 3971 | #define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 3972 | #define DCORE2_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 3973 | #define mmDCORE2_TPC3_EML_TPC_QM_BASE 0x264C000ull |
|---|
| 3974 | #define DCORE2_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 3975 | #define DCORE2_TPC3_EML_TPC_QM_SECTION 0x9000 |
|---|
| 3976 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x264C900ull |
|---|
| 3977 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 3978 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 3979 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x264C908ull |
|---|
| 3980 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 3981 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 3982 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x264C910ull |
|---|
| 3983 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 3984 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 3985 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x264C918ull |
|---|
| 3986 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 3987 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 3988 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x264C920ull |
|---|
| 3989 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 3990 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 3991 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x264C928ull |
|---|
| 3992 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 3993 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 3994 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x264C930ull |
|---|
| 3995 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 3996 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 3997 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x264C938ull |
|---|
| 3998 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 3999 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 4000 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x264C940ull |
|---|
| 4001 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 4002 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 4003 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x264C948ull |
|---|
| 4004 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 4005 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 4006 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x264C950ull |
|---|
| 4007 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 4008 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 4009 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x264C958ull |
|---|
| 4010 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 4011 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 4012 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x264C960ull |
|---|
| 4013 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 4014 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 4015 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x264C968ull |
|---|
| 4016 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 4017 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 4018 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x264C970ull |
|---|
| 4019 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 4020 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 4021 | #define mmDCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x264C978ull |
|---|
| 4022 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 4023 | #define DCORE2_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 4024 | #define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x264CB00ull |
|---|
| 4025 | #define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 4026 | #define DCORE2_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 4027 | #define mmDCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x264CB80ull |
|---|
| 4028 | #define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 4029 | #define DCORE2_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 4030 | #define mmDCORE2_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x264CC00ull |
|---|
| 4031 | #define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 4032 | #define DCORE2_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 4033 | #define mmDCORE2_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x264CC80ull |
|---|
| 4034 | #define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 4035 | #define DCORE2_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 4036 | #define mmDCORE2_TPC3_EML_TPC_QM_CGM_BASE 0x264CD80ull |
|---|
| 4037 | #define DCORE2_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 4038 | #define DCORE2_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 4039 | #define mmDCORE2_TPC3_EML_TPC_QM_SPECIAL_BASE 0x264CE80ull |
|---|
| 4040 | #define DCORE2_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4041 | #define DCORE2_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 4042 | #define mmDCORE2_TPC3_EML_CS_BASE 0x27FF000ull |
|---|
| 4043 | #define DCORE2_TPC3_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 4044 | #define DCORE2_TPC3_EML_CS_SECTION 0x1000 |
|---|
| 4045 | #define mmDCORE2_TPC4_ROM_TABLE_BASE 0x2800000ull |
|---|
| 4046 | #define DCORE2_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 4047 | #define DCORE2_TPC4_ROM_TABLE_SECTION 0x1000 |
|---|
| 4048 | #define mmDCORE2_TPC4_EML_SPMU_BASE 0x2801000ull |
|---|
| 4049 | #define DCORE2_TPC4_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 4050 | #define DCORE2_TPC4_EML_SPMU_SECTION 0x1000 |
|---|
| 4051 | #define mmDCORE2_TPC4_EML_ETF_BASE 0x2802000ull |
|---|
| 4052 | #define DCORE2_TPC4_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 4053 | #define DCORE2_TPC4_EML_ETF_SECTION 0x1000 |
|---|
| 4054 | #define mmDCORE2_TPC4_EML_STM_BASE 0x2803000ull |
|---|
| 4055 | #define DCORE2_TPC4_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 4056 | #define DCORE2_TPC4_EML_STM_SECTION 0x2000 |
|---|
| 4057 | #define mmDCORE2_TPC4_EML_CTI_BASE 0x2805000ull |
|---|
| 4058 | #define DCORE2_TPC4_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 4059 | #define DCORE2_TPC4_EML_CTI_SECTION 0x1000 |
|---|
| 4060 | #define mmDCORE2_TPC4_EML_FUNNEL_BASE 0x2806000ull |
|---|
| 4061 | #define DCORE2_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 4062 | #define DCORE2_TPC4_EML_FUNNEL_SECTION 0x1000 |
|---|
| 4063 | #define mmDCORE2_TPC4_EML_BUSMON_0_BASE 0x2807000ull |
|---|
| 4064 | #define DCORE2_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 4065 | #define DCORE2_TPC4_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 4066 | #define mmDCORE2_TPC4_EML_BUSMON_1_BASE 0x2808000ull |
|---|
| 4067 | #define DCORE2_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 4068 | #define DCORE2_TPC4_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 4069 | #define mmDCORE2_TPC4_EML_BUSMON_2_BASE 0x2809000ull |
|---|
| 4070 | #define DCORE2_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 4071 | #define DCORE2_TPC4_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 4072 | #define mmDCORE2_TPC4_EML_BUSMON_3_BASE 0x280A000ull |
|---|
| 4073 | #define DCORE2_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 4074 | #define DCORE2_TPC4_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 4075 | #define mmDCORE2_TPC4_QM_ARC_RTT_BASE 0x280B000ull |
|---|
| 4076 | #define DCORE2_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 4077 | #define DCORE2_TPC4_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 4078 | #define mmDCORE2_TPC4_EML_CFG_BASE 0x2840000ull |
|---|
| 4079 | #define DCORE2_TPC4_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 4080 | #define DCORE2_TPC4_EML_CFG_SECTION 0xE800 |
|---|
| 4081 | #define mmDCORE2_TPC4_EML_CFG_SPECIAL_BASE 0x2840E80ull |
|---|
| 4082 | #define DCORE2_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4083 | #define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4084 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2841000ull |
|---|
| 4085 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4086 | #define DCORE2_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4087 | #define mmDCORE2_TPC4_EML_TPC_CFG_BASE 0x2841000ull |
|---|
| 4088 | #define DCORE2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 4089 | #define DCORE2_TPC4_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 4090 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2841050ull |
|---|
| 4091 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4092 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 4093 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x28410A0ull |
|---|
| 4094 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4095 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 4096 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x28410F0ull |
|---|
| 4097 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4098 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 4099 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2841140ull |
|---|
| 4100 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4101 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 4102 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2841190ull |
|---|
| 4103 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4104 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 4105 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x28411E0ull |
|---|
| 4106 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4107 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 4108 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2841230ull |
|---|
| 4109 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4110 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 4111 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2841280ull |
|---|
| 4112 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4113 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 4114 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x28412D0ull |
|---|
| 4115 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4116 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 4117 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2841320ull |
|---|
| 4118 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4119 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 4120 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2841370ull |
|---|
| 4121 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4122 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 4123 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x28413C0ull |
|---|
| 4124 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4125 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 4126 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2841410ull |
|---|
| 4127 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4128 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 4129 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2841460ull |
|---|
| 4130 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4131 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 4132 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x28414B0ull |
|---|
| 4133 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4134 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 4135 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2841500ull |
|---|
| 4136 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4137 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4138 | #define mmDCORE2_TPC4_EML_TPC_CFG_KERNEL_BASE 0x2841508ull |
|---|
| 4139 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 4140 | #define DCORE2_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 4141 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x28415DCull |
|---|
| 4142 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4143 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 4144 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x284162Cull |
|---|
| 4145 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4146 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 4147 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x284167Cull |
|---|
| 4148 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4149 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 4150 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x28416CCull |
|---|
| 4151 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4152 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 4153 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x284171Cull |
|---|
| 4154 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4155 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 4156 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x284176Cull |
|---|
| 4157 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4158 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 4159 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x28417BCull |
|---|
| 4160 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4161 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 4162 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x284180Cull |
|---|
| 4163 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4164 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 4165 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x284185Cull |
|---|
| 4166 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4167 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 4168 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x28418ACull |
|---|
| 4169 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4170 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 4171 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x28418FCull |
|---|
| 4172 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4173 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 4174 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x284194Cull |
|---|
| 4175 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4176 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 4177 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x284199Cull |
|---|
| 4178 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4179 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 4180 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x28419ECull |
|---|
| 4181 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4182 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 4183 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2841A3Cull |
|---|
| 4184 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4185 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 4186 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2841A8Cull |
|---|
| 4187 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4188 | #define DCORE2_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 4189 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2841ADCull |
|---|
| 4190 | #define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4191 | #define DCORE2_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4192 | #define mmDCORE2_TPC4_EML_TPC_CFG_QM_BASE 0x2841AE4ull |
|---|
| 4193 | #define DCORE2_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 4194 | #define DCORE2_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 4195 | #define mmDCORE2_TPC4_EML_TPC_CFG_AXUSER_BASE 0x2841E00ull |
|---|
| 4196 | #define DCORE2_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 4197 | #define DCORE2_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 4198 | #define mmDCORE2_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x2841E80ull |
|---|
| 4199 | #define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4200 | #define DCORE2_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4201 | #define mmDCORE2_TPC4_EML_QM_DCCM_BASE 0x2842000ull |
|---|
| 4202 | #define DCORE2_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 4203 | #define DCORE2_TPC4_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 4204 | #define mmDCORE2_TPC4_EML_QM_ARCAUX_BASE 0x284A000ull |
|---|
| 4205 | #define DCORE2_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 4206 | #define DCORE2_TPC4_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 4207 | #define mmDCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x284AE80ull |
|---|
| 4208 | #define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4209 | #define DCORE2_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 4210 | #define mmDCORE2_TPC4_EML_TPC_QM_BASE 0x284C000ull |
|---|
| 4211 | #define DCORE2_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 4212 | #define DCORE2_TPC4_EML_TPC_QM_SECTION 0x9000 |
|---|
| 4213 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x284C900ull |
|---|
| 4214 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 4215 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 4216 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x284C908ull |
|---|
| 4217 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 4218 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 4219 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x284C910ull |
|---|
| 4220 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 4221 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 4222 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x284C918ull |
|---|
| 4223 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 4224 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 4225 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x284C920ull |
|---|
| 4226 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 4227 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 4228 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x284C928ull |
|---|
| 4229 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 4230 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 4231 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x284C930ull |
|---|
| 4232 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 4233 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 4234 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x284C938ull |
|---|
| 4235 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 4236 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 4237 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x284C940ull |
|---|
| 4238 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 4239 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 4240 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x284C948ull |
|---|
| 4241 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 4242 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 4243 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x284C950ull |
|---|
| 4244 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 4245 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 4246 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x284C958ull |
|---|
| 4247 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 4248 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 4249 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x284C960ull |
|---|
| 4250 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 4251 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 4252 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x284C968ull |
|---|
| 4253 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 4254 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 4255 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x284C970ull |
|---|
| 4256 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 4257 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 4258 | #define mmDCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x284C978ull |
|---|
| 4259 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 4260 | #define DCORE2_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 4261 | #define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x284CB00ull |
|---|
| 4262 | #define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 4263 | #define DCORE2_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 4264 | #define mmDCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x284CB80ull |
|---|
| 4265 | #define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 4266 | #define DCORE2_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 4267 | #define mmDCORE2_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x284CC00ull |
|---|
| 4268 | #define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 4269 | #define DCORE2_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 4270 | #define mmDCORE2_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x284CC80ull |
|---|
| 4271 | #define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 4272 | #define DCORE2_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 4273 | #define mmDCORE2_TPC4_EML_TPC_QM_CGM_BASE 0x284CD80ull |
|---|
| 4274 | #define DCORE2_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 4275 | #define DCORE2_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 4276 | #define mmDCORE2_TPC4_EML_TPC_QM_SPECIAL_BASE 0x284CE80ull |
|---|
| 4277 | #define DCORE2_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4278 | #define DCORE2_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 4279 | #define mmDCORE2_TPC4_EML_CS_BASE 0x29FF000ull |
|---|
| 4280 | #define DCORE2_TPC4_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 4281 | #define DCORE2_TPC4_EML_CS_SECTION 0x1000 |
|---|
| 4282 | #define mmDCORE2_TPC5_ROM_TABLE_BASE 0x2A00000ull |
|---|
| 4283 | #define DCORE2_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 4284 | #define DCORE2_TPC5_ROM_TABLE_SECTION 0x1000 |
|---|
| 4285 | #define mmDCORE2_TPC5_EML_SPMU_BASE 0x2A01000ull |
|---|
| 4286 | #define DCORE2_TPC5_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 4287 | #define DCORE2_TPC5_EML_SPMU_SECTION 0x1000 |
|---|
| 4288 | #define mmDCORE2_TPC5_EML_ETF_BASE 0x2A02000ull |
|---|
| 4289 | #define DCORE2_TPC5_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 4290 | #define DCORE2_TPC5_EML_ETF_SECTION 0x1000 |
|---|
| 4291 | #define mmDCORE2_TPC5_EML_STM_BASE 0x2A03000ull |
|---|
| 4292 | #define DCORE2_TPC5_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 4293 | #define DCORE2_TPC5_EML_STM_SECTION 0x2000 |
|---|
| 4294 | #define mmDCORE2_TPC5_EML_CTI_BASE 0x2A05000ull |
|---|
| 4295 | #define DCORE2_TPC5_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 4296 | #define DCORE2_TPC5_EML_CTI_SECTION 0x1000 |
|---|
| 4297 | #define mmDCORE2_TPC5_EML_FUNNEL_BASE 0x2A06000ull |
|---|
| 4298 | #define DCORE2_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 4299 | #define DCORE2_TPC5_EML_FUNNEL_SECTION 0x1000 |
|---|
| 4300 | #define mmDCORE2_TPC5_EML_BUSMON_0_BASE 0x2A07000ull |
|---|
| 4301 | #define DCORE2_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 4302 | #define DCORE2_TPC5_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 4303 | #define mmDCORE2_TPC5_EML_BUSMON_1_BASE 0x2A08000ull |
|---|
| 4304 | #define DCORE2_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 4305 | #define DCORE2_TPC5_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 4306 | #define mmDCORE2_TPC5_EML_BUSMON_2_BASE 0x2A09000ull |
|---|
| 4307 | #define DCORE2_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 4308 | #define DCORE2_TPC5_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 4309 | #define mmDCORE2_TPC5_EML_BUSMON_3_BASE 0x2A0A000ull |
|---|
| 4310 | #define DCORE2_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 4311 | #define DCORE2_TPC5_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 4312 | #define mmDCORE2_TPC5_QM_ARC_RTT_BASE 0x2A0B000ull |
|---|
| 4313 | #define DCORE2_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 4314 | #define DCORE2_TPC5_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 4315 | #define mmDCORE2_TPC5_EML_CFG_BASE 0x2A40000ull |
|---|
| 4316 | #define DCORE2_TPC5_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 4317 | #define DCORE2_TPC5_EML_CFG_SECTION 0xE800 |
|---|
| 4318 | #define mmDCORE2_TPC5_EML_CFG_SPECIAL_BASE 0x2A40E80ull |
|---|
| 4319 | #define DCORE2_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4320 | #define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4321 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x2A41000ull |
|---|
| 4322 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4323 | #define DCORE2_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4324 | #define mmDCORE2_TPC5_EML_TPC_CFG_BASE 0x2A41000ull |
|---|
| 4325 | #define DCORE2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 4326 | #define DCORE2_TPC5_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 4327 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x2A41050ull |
|---|
| 4328 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4329 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 4330 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x2A410A0ull |
|---|
| 4331 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4332 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 4333 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x2A410F0ull |
|---|
| 4334 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4335 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 4336 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x2A41140ull |
|---|
| 4337 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4338 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 4339 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x2A41190ull |
|---|
| 4340 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4341 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 4342 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x2A411E0ull |
|---|
| 4343 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4344 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 4345 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x2A41230ull |
|---|
| 4346 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4347 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 4348 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x2A41280ull |
|---|
| 4349 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4350 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 4351 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x2A412D0ull |
|---|
| 4352 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4353 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 4354 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x2A41320ull |
|---|
| 4355 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4356 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 4357 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x2A41370ull |
|---|
| 4358 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4359 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 4360 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x2A413C0ull |
|---|
| 4361 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4362 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 4363 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x2A41410ull |
|---|
| 4364 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4365 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 4366 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x2A41460ull |
|---|
| 4367 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4368 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 4369 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x2A414B0ull |
|---|
| 4370 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4371 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 4372 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x2A41500ull |
|---|
| 4373 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4374 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4375 | #define mmDCORE2_TPC5_EML_TPC_CFG_KERNEL_BASE 0x2A41508ull |
|---|
| 4376 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 4377 | #define DCORE2_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 4378 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x2A415DCull |
|---|
| 4379 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4380 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 4381 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x2A4162Cull |
|---|
| 4382 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4383 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 4384 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x2A4167Cull |
|---|
| 4385 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4386 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 4387 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x2A416CCull |
|---|
| 4388 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4389 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 4390 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x2A4171Cull |
|---|
| 4391 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4392 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 4393 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x2A4176Cull |
|---|
| 4394 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4395 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 4396 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x2A417BCull |
|---|
| 4397 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4398 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 4399 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x2A4180Cull |
|---|
| 4400 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4401 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 4402 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x2A4185Cull |
|---|
| 4403 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4404 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 4405 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x2A418ACull |
|---|
| 4406 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4407 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 4408 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x2A418FCull |
|---|
| 4409 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4410 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 4411 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x2A4194Cull |
|---|
| 4412 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4413 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 4414 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x2A4199Cull |
|---|
| 4415 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4416 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 4417 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x2A419ECull |
|---|
| 4418 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4419 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 4420 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x2A41A3Cull |
|---|
| 4421 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4422 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 4423 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x2A41A8Cull |
|---|
| 4424 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4425 | #define DCORE2_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 4426 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x2A41ADCull |
|---|
| 4427 | #define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4428 | #define DCORE2_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4429 | #define mmDCORE2_TPC5_EML_TPC_CFG_QM_BASE 0x2A41AE4ull |
|---|
| 4430 | #define DCORE2_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 4431 | #define DCORE2_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 4432 | #define mmDCORE2_TPC5_EML_TPC_CFG_AXUSER_BASE 0x2A41E00ull |
|---|
| 4433 | #define DCORE2_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 4434 | #define DCORE2_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 4435 | #define mmDCORE2_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x2A41E80ull |
|---|
| 4436 | #define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4437 | #define DCORE2_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4438 | #define mmDCORE2_TPC5_EML_QM_DCCM_BASE 0x2A42000ull |
|---|
| 4439 | #define DCORE2_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 4440 | #define DCORE2_TPC5_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 4441 | #define mmDCORE2_TPC5_EML_QM_ARCAUX_BASE 0x2A4A000ull |
|---|
| 4442 | #define DCORE2_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 4443 | #define DCORE2_TPC5_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 4444 | #define mmDCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x2A4AE80ull |
|---|
| 4445 | #define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4446 | #define DCORE2_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 4447 | #define mmDCORE2_TPC5_EML_TPC_QM_BASE 0x2A4C000ull |
|---|
| 4448 | #define DCORE2_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 4449 | #define DCORE2_TPC5_EML_TPC_QM_SECTION 0x9000 |
|---|
| 4450 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x2A4C900ull |
|---|
| 4451 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 4452 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 4453 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x2A4C908ull |
|---|
| 4454 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 4455 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 4456 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x2A4C910ull |
|---|
| 4457 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 4458 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 4459 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x2A4C918ull |
|---|
| 4460 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 4461 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 4462 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x2A4C920ull |
|---|
| 4463 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 4464 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 4465 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x2A4C928ull |
|---|
| 4466 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 4467 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 4468 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x2A4C930ull |
|---|
| 4469 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 4470 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 4471 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x2A4C938ull |
|---|
| 4472 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 4473 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 4474 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x2A4C940ull |
|---|
| 4475 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 4476 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 4477 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x2A4C948ull |
|---|
| 4478 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 4479 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 4480 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x2A4C950ull |
|---|
| 4481 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 4482 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 4483 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x2A4C958ull |
|---|
| 4484 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 4485 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 4486 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x2A4C960ull |
|---|
| 4487 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 4488 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 4489 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x2A4C968ull |
|---|
| 4490 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 4491 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 4492 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x2A4C970ull |
|---|
| 4493 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 4494 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 4495 | #define mmDCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x2A4C978ull |
|---|
| 4496 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 4497 | #define DCORE2_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 4498 | #define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x2A4CB00ull |
|---|
| 4499 | #define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 4500 | #define DCORE2_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 4501 | #define mmDCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x2A4CB80ull |
|---|
| 4502 | #define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 4503 | #define DCORE2_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 4504 | #define mmDCORE2_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x2A4CC00ull |
|---|
| 4505 | #define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 4506 | #define DCORE2_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 4507 | #define mmDCORE2_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x2A4CC80ull |
|---|
| 4508 | #define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 4509 | #define DCORE2_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 4510 | #define mmDCORE2_TPC5_EML_TPC_QM_CGM_BASE 0x2A4CD80ull |
|---|
| 4511 | #define DCORE2_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 4512 | #define DCORE2_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 4513 | #define mmDCORE2_TPC5_EML_TPC_QM_SPECIAL_BASE 0x2A4CE80ull |
|---|
| 4514 | #define DCORE2_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4515 | #define DCORE2_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 4516 | #define mmDCORE2_TPC5_EML_CS_BASE 0x2BFF000ull |
|---|
| 4517 | #define DCORE2_TPC5_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 4518 | #define DCORE2_TPC5_EML_CS_SECTION 0x401000 |
|---|
| 4519 | #define mmDCORE3_TPC0_ROM_TABLE_BASE 0x3000000ull |
|---|
| 4520 | #define DCORE3_TPC0_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 4521 | #define DCORE3_TPC0_ROM_TABLE_SECTION 0x1000 |
|---|
| 4522 | #define mmDCORE3_TPC0_EML_SPMU_BASE 0x3001000ull |
|---|
| 4523 | #define DCORE3_TPC0_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 4524 | #define DCORE3_TPC0_EML_SPMU_SECTION 0x1000 |
|---|
| 4525 | #define mmDCORE3_TPC0_EML_ETF_BASE 0x3002000ull |
|---|
| 4526 | #define DCORE3_TPC0_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 4527 | #define DCORE3_TPC0_EML_ETF_SECTION 0x1000 |
|---|
| 4528 | #define mmDCORE3_TPC0_EML_STM_BASE 0x3003000ull |
|---|
| 4529 | #define DCORE3_TPC0_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 4530 | #define DCORE3_TPC0_EML_STM_SECTION 0x2000 |
|---|
| 4531 | #define mmDCORE3_TPC0_EML_CTI_BASE 0x3005000ull |
|---|
| 4532 | #define DCORE3_TPC0_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 4533 | #define DCORE3_TPC0_EML_CTI_SECTION 0x1000 |
|---|
| 4534 | #define mmDCORE3_TPC0_EML_FUNNEL_BASE 0x3006000ull |
|---|
| 4535 | #define DCORE3_TPC0_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 4536 | #define DCORE3_TPC0_EML_FUNNEL_SECTION 0x1000 |
|---|
| 4537 | #define mmDCORE3_TPC0_EML_BUSMON_0_BASE 0x3007000ull |
|---|
| 4538 | #define DCORE3_TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 4539 | #define DCORE3_TPC0_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 4540 | #define mmDCORE3_TPC0_EML_BUSMON_1_BASE 0x3008000ull |
|---|
| 4541 | #define DCORE3_TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 4542 | #define DCORE3_TPC0_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 4543 | #define mmDCORE3_TPC0_EML_BUSMON_2_BASE 0x3009000ull |
|---|
| 4544 | #define DCORE3_TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 4545 | #define DCORE3_TPC0_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 4546 | #define mmDCORE3_TPC0_EML_BUSMON_3_BASE 0x300A000ull |
|---|
| 4547 | #define DCORE3_TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 4548 | #define DCORE3_TPC0_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 4549 | #define mmDCORE3_TPC0_QM_ARC_RTT_BASE 0x300B000ull |
|---|
| 4550 | #define DCORE3_TPC0_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 4551 | #define DCORE3_TPC0_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 4552 | #define mmDCORE3_TPC0_EML_CFG_BASE 0x3040000ull |
|---|
| 4553 | #define DCORE3_TPC0_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 4554 | #define DCORE3_TPC0_EML_CFG_SECTION 0xE800 |
|---|
| 4555 | #define mmDCORE3_TPC0_EML_CFG_SPECIAL_BASE 0x3040E80ull |
|---|
| 4556 | #define DCORE3_TPC0_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4557 | #define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4558 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3041000ull |
|---|
| 4559 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4560 | #define DCORE3_TPC0_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4561 | #define mmDCORE3_TPC0_EML_TPC_CFG_BASE 0x3041000ull |
|---|
| 4562 | #define DCORE3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 4563 | #define DCORE3_TPC0_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 4564 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3041050ull |
|---|
| 4565 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4566 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 4567 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x30410A0ull |
|---|
| 4568 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4569 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 4570 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x30410F0ull |
|---|
| 4571 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4572 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 4573 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3041140ull |
|---|
| 4574 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4575 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 4576 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3041190ull |
|---|
| 4577 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4578 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 4579 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x30411E0ull |
|---|
| 4580 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4581 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 4582 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3041230ull |
|---|
| 4583 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4584 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 4585 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3041280ull |
|---|
| 4586 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4587 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 4588 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x30412D0ull |
|---|
| 4589 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4590 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 4591 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3041320ull |
|---|
| 4592 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4593 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 4594 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3041370ull |
|---|
| 4595 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4596 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 4597 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x30413C0ull |
|---|
| 4598 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4599 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 4600 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3041410ull |
|---|
| 4601 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4602 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 4603 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3041460ull |
|---|
| 4604 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4605 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 4606 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x30414B0ull |
|---|
| 4607 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4608 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 4609 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3041500ull |
|---|
| 4610 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4611 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4612 | #define mmDCORE3_TPC0_EML_TPC_CFG_KERNEL_BASE 0x3041508ull |
|---|
| 4613 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 4614 | #define DCORE3_TPC0_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 4615 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_BASE 0x30415DCull |
|---|
| 4616 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4617 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 4618 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_BASE 0x304162Cull |
|---|
| 4619 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4620 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 4621 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_BASE 0x304167Cull |
|---|
| 4622 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4623 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 4624 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_BASE 0x30416CCull |
|---|
| 4625 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4626 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 4627 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_BASE 0x304171Cull |
|---|
| 4628 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4629 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 4630 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_BASE 0x304176Cull |
|---|
| 4631 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4632 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 4633 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_BASE 0x30417BCull |
|---|
| 4634 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4635 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 4636 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_BASE 0x304180Cull |
|---|
| 4637 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4638 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 4639 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_BASE 0x304185Cull |
|---|
| 4640 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4641 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 4642 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_BASE 0x30418ACull |
|---|
| 4643 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4644 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 4645 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_BASE 0x30418FCull |
|---|
| 4646 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4647 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 4648 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_BASE 0x304194Cull |
|---|
| 4649 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4650 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 4651 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_BASE 0x304199Cull |
|---|
| 4652 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4653 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 4654 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_BASE 0x30419ECull |
|---|
| 4655 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4656 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 4657 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3041A3Cull |
|---|
| 4658 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4659 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 4660 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3041A8Cull |
|---|
| 4661 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4662 | #define DCORE3_TPC0_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 4663 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3041ADCull |
|---|
| 4664 | #define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4665 | #define DCORE3_TPC0_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4666 | #define mmDCORE3_TPC0_EML_TPC_CFG_QM_BASE 0x3041AE4ull |
|---|
| 4667 | #define DCORE3_TPC0_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 4668 | #define DCORE3_TPC0_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 4669 | #define mmDCORE3_TPC0_EML_TPC_CFG_AXUSER_BASE 0x3041E00ull |
|---|
| 4670 | #define DCORE3_TPC0_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 4671 | #define DCORE3_TPC0_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 4672 | #define mmDCORE3_TPC0_EML_TPC_CFG_SPECIAL_BASE 0x3041E80ull |
|---|
| 4673 | #define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4674 | #define DCORE3_TPC0_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4675 | #define mmDCORE3_TPC0_EML_QM_DCCM_BASE 0x3042000ull |
|---|
| 4676 | #define DCORE3_TPC0_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 4677 | #define DCORE3_TPC0_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 4678 | #define mmDCORE3_TPC0_EML_QM_ARCAUX_BASE 0x304A000ull |
|---|
| 4679 | #define DCORE3_TPC0_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 4680 | #define DCORE3_TPC0_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 4681 | #define mmDCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_BASE 0x304AE80ull |
|---|
| 4682 | #define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4683 | #define DCORE3_TPC0_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 4684 | #define mmDCORE3_TPC0_EML_TPC_QM_BASE 0x304C000ull |
|---|
| 4685 | #define DCORE3_TPC0_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 4686 | #define DCORE3_TPC0_EML_TPC_QM_SECTION 0x9000 |
|---|
| 4687 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x304C900ull |
|---|
| 4688 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 4689 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 4690 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x304C908ull |
|---|
| 4691 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 4692 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 4693 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x304C910ull |
|---|
| 4694 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 4695 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 4696 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x304C918ull |
|---|
| 4697 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 4698 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 4699 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x304C920ull |
|---|
| 4700 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 4701 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 4702 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x304C928ull |
|---|
| 4703 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 4704 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 4705 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x304C930ull |
|---|
| 4706 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 4707 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 4708 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x304C938ull |
|---|
| 4709 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 4710 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 4711 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x304C940ull |
|---|
| 4712 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 4713 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 4714 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x304C948ull |
|---|
| 4715 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 4716 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 4717 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x304C950ull |
|---|
| 4718 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 4719 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 4720 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x304C958ull |
|---|
| 4721 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 4722 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 4723 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x304C960ull |
|---|
| 4724 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 4725 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 4726 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x304C968ull |
|---|
| 4727 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 4728 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 4729 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x304C970ull |
|---|
| 4730 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 4731 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 4732 | #define mmDCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x304C978ull |
|---|
| 4733 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 4734 | #define DCORE3_TPC0_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 4735 | #define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_BASE 0x304CB00ull |
|---|
| 4736 | #define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 4737 | #define DCORE3_TPC0_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 4738 | #define mmDCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x304CB80ull |
|---|
| 4739 | #define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 4740 | #define DCORE3_TPC0_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 4741 | #define mmDCORE3_TPC0_EML_TPC_QM_DBG_HBW_BASE 0x304CC00ull |
|---|
| 4742 | #define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 4743 | #define DCORE3_TPC0_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 4744 | #define mmDCORE3_TPC0_EML_TPC_QM_DBG_LBW_BASE 0x304CC80ull |
|---|
| 4745 | #define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 4746 | #define DCORE3_TPC0_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 4747 | #define mmDCORE3_TPC0_EML_TPC_QM_CGM_BASE 0x304CD80ull |
|---|
| 4748 | #define DCORE3_TPC0_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 4749 | #define DCORE3_TPC0_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 4750 | #define mmDCORE3_TPC0_EML_TPC_QM_SPECIAL_BASE 0x304CE80ull |
|---|
| 4751 | #define DCORE3_TPC0_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4752 | #define DCORE3_TPC0_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 4753 | #define mmDCORE3_TPC0_EML_CS_BASE 0x31FF000ull |
|---|
| 4754 | #define DCORE3_TPC0_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 4755 | #define DCORE3_TPC0_EML_CS_SECTION 0x1000 |
|---|
| 4756 | #define mmDCORE3_TPC1_ROM_TABLE_BASE 0x3200000ull |
|---|
| 4757 | #define DCORE3_TPC1_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 4758 | #define DCORE3_TPC1_ROM_TABLE_SECTION 0x1000 |
|---|
| 4759 | #define mmDCORE3_TPC1_EML_SPMU_BASE 0x3201000ull |
|---|
| 4760 | #define DCORE3_TPC1_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 4761 | #define DCORE3_TPC1_EML_SPMU_SECTION 0x1000 |
|---|
| 4762 | #define mmDCORE3_TPC1_EML_ETF_BASE 0x3202000ull |
|---|
| 4763 | #define DCORE3_TPC1_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 4764 | #define DCORE3_TPC1_EML_ETF_SECTION 0x1000 |
|---|
| 4765 | #define mmDCORE3_TPC1_EML_STM_BASE 0x3203000ull |
|---|
| 4766 | #define DCORE3_TPC1_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 4767 | #define DCORE3_TPC1_EML_STM_SECTION 0x2000 |
|---|
| 4768 | #define mmDCORE3_TPC1_EML_CTI_BASE 0x3205000ull |
|---|
| 4769 | #define DCORE3_TPC1_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 4770 | #define DCORE3_TPC1_EML_CTI_SECTION 0x1000 |
|---|
| 4771 | #define mmDCORE3_TPC1_EML_FUNNEL_BASE 0x3206000ull |
|---|
| 4772 | #define DCORE3_TPC1_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 4773 | #define DCORE3_TPC1_EML_FUNNEL_SECTION 0x1000 |
|---|
| 4774 | #define mmDCORE3_TPC1_EML_BUSMON_0_BASE 0x3207000ull |
|---|
| 4775 | #define DCORE3_TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 4776 | #define DCORE3_TPC1_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 4777 | #define mmDCORE3_TPC1_EML_BUSMON_1_BASE 0x3208000ull |
|---|
| 4778 | #define DCORE3_TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 4779 | #define DCORE3_TPC1_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 4780 | #define mmDCORE3_TPC1_EML_BUSMON_2_BASE 0x3209000ull |
|---|
| 4781 | #define DCORE3_TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 4782 | #define DCORE3_TPC1_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 4783 | #define mmDCORE3_TPC1_EML_BUSMON_3_BASE 0x320A000ull |
|---|
| 4784 | #define DCORE3_TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 4785 | #define DCORE3_TPC1_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 4786 | #define mmDCORE3_TPC1_QM_ARC_RTT_BASE 0x320B000ull |
|---|
| 4787 | #define DCORE3_TPC1_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 4788 | #define DCORE3_TPC1_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 4789 | #define mmDCORE3_TPC1_EML_CFG_BASE 0x3240000ull |
|---|
| 4790 | #define DCORE3_TPC1_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 4791 | #define DCORE3_TPC1_EML_CFG_SECTION 0xE800 |
|---|
| 4792 | #define mmDCORE3_TPC1_EML_CFG_SPECIAL_BASE 0x3240E80ull |
|---|
| 4793 | #define DCORE3_TPC1_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4794 | #define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4795 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3241000ull |
|---|
| 4796 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4797 | #define DCORE3_TPC1_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4798 | #define mmDCORE3_TPC1_EML_TPC_CFG_BASE 0x3241000ull |
|---|
| 4799 | #define DCORE3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 4800 | #define DCORE3_TPC1_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 4801 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3241050ull |
|---|
| 4802 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4803 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 4804 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x32410A0ull |
|---|
| 4805 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4806 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 4807 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x32410F0ull |
|---|
| 4808 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4809 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 4810 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3241140ull |
|---|
| 4811 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4812 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 4813 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3241190ull |
|---|
| 4814 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4815 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 4816 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x32411E0ull |
|---|
| 4817 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4818 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 4819 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3241230ull |
|---|
| 4820 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4821 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 4822 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3241280ull |
|---|
| 4823 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4824 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 4825 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x32412D0ull |
|---|
| 4826 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4827 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 4828 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3241320ull |
|---|
| 4829 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4830 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 4831 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3241370ull |
|---|
| 4832 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4833 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 4834 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x32413C0ull |
|---|
| 4835 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4836 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 4837 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3241410ull |
|---|
| 4838 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4839 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 4840 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3241460ull |
|---|
| 4841 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4842 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 4843 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x32414B0ull |
|---|
| 4844 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4845 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 4846 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3241500ull |
|---|
| 4847 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4848 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4849 | #define mmDCORE3_TPC1_EML_TPC_CFG_KERNEL_BASE 0x3241508ull |
|---|
| 4850 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 4851 | #define DCORE3_TPC1_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 4852 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_BASE 0x32415DCull |
|---|
| 4853 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 4854 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 4855 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_BASE 0x324162Cull |
|---|
| 4856 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 4857 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 4858 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_BASE 0x324167Cull |
|---|
| 4859 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 4860 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 4861 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_BASE 0x32416CCull |
|---|
| 4862 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 4863 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 4864 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_BASE 0x324171Cull |
|---|
| 4865 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 4866 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 4867 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_BASE 0x324176Cull |
|---|
| 4868 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 4869 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 4870 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_BASE 0x32417BCull |
|---|
| 4871 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 4872 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 4873 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_BASE 0x324180Cull |
|---|
| 4874 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 4875 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 4876 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_BASE 0x324185Cull |
|---|
| 4877 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 4878 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 4879 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_BASE 0x32418ACull |
|---|
| 4880 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 4881 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 4882 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_BASE 0x32418FCull |
|---|
| 4883 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 4884 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 4885 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_BASE 0x324194Cull |
|---|
| 4886 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 4887 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 4888 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_BASE 0x324199Cull |
|---|
| 4889 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 4890 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 4891 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_BASE 0x32419ECull |
|---|
| 4892 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 4893 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 4894 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3241A3Cull |
|---|
| 4895 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 4896 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 4897 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3241A8Cull |
|---|
| 4898 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 4899 | #define DCORE3_TPC1_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 4900 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3241ADCull |
|---|
| 4901 | #define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 4902 | #define DCORE3_TPC1_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 4903 | #define mmDCORE3_TPC1_EML_TPC_CFG_QM_BASE 0x3241AE4ull |
|---|
| 4904 | #define DCORE3_TPC1_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 4905 | #define DCORE3_TPC1_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 4906 | #define mmDCORE3_TPC1_EML_TPC_CFG_AXUSER_BASE 0x3241E00ull |
|---|
| 4907 | #define DCORE3_TPC1_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 4908 | #define DCORE3_TPC1_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 4909 | #define mmDCORE3_TPC1_EML_TPC_CFG_SPECIAL_BASE 0x3241E80ull |
|---|
| 4910 | #define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4911 | #define DCORE3_TPC1_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 4912 | #define mmDCORE3_TPC1_EML_QM_DCCM_BASE 0x3242000ull |
|---|
| 4913 | #define DCORE3_TPC1_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 4914 | #define DCORE3_TPC1_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 4915 | #define mmDCORE3_TPC1_EML_QM_ARCAUX_BASE 0x324A000ull |
|---|
| 4916 | #define DCORE3_TPC1_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 4917 | #define DCORE3_TPC1_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 4918 | #define mmDCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_BASE 0x324AE80ull |
|---|
| 4919 | #define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4920 | #define DCORE3_TPC1_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 4921 | #define mmDCORE3_TPC1_EML_TPC_QM_BASE 0x324C000ull |
|---|
| 4922 | #define DCORE3_TPC1_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 4923 | #define DCORE3_TPC1_EML_TPC_QM_SECTION 0x9000 |
|---|
| 4924 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x324C900ull |
|---|
| 4925 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 4926 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 4927 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x324C908ull |
|---|
| 4928 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 4929 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 4930 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x324C910ull |
|---|
| 4931 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 4932 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 4933 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x324C918ull |
|---|
| 4934 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 4935 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 4936 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x324C920ull |
|---|
| 4937 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 4938 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 4939 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x324C928ull |
|---|
| 4940 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 4941 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 4942 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x324C930ull |
|---|
| 4943 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 4944 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 4945 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x324C938ull |
|---|
| 4946 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 4947 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 4948 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x324C940ull |
|---|
| 4949 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 4950 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 4951 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x324C948ull |
|---|
| 4952 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 4953 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 4954 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x324C950ull |
|---|
| 4955 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 4956 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 4957 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x324C958ull |
|---|
| 4958 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 4959 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 4960 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x324C960ull |
|---|
| 4961 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 4962 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 4963 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x324C968ull |
|---|
| 4964 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 4965 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 4966 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x324C970ull |
|---|
| 4967 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 4968 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 4969 | #define mmDCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x324C978ull |
|---|
| 4970 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 4971 | #define DCORE3_TPC1_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 4972 | #define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_BASE 0x324CB00ull |
|---|
| 4973 | #define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 4974 | #define DCORE3_TPC1_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 4975 | #define mmDCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x324CB80ull |
|---|
| 4976 | #define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 4977 | #define DCORE3_TPC1_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 4978 | #define mmDCORE3_TPC1_EML_TPC_QM_DBG_HBW_BASE 0x324CC00ull |
|---|
| 4979 | #define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 4980 | #define DCORE3_TPC1_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 4981 | #define mmDCORE3_TPC1_EML_TPC_QM_DBG_LBW_BASE 0x324CC80ull |
|---|
| 4982 | #define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 4983 | #define DCORE3_TPC1_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 4984 | #define mmDCORE3_TPC1_EML_TPC_QM_CGM_BASE 0x324CD80ull |
|---|
| 4985 | #define DCORE3_TPC1_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 4986 | #define DCORE3_TPC1_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 4987 | #define mmDCORE3_TPC1_EML_TPC_QM_SPECIAL_BASE 0x324CE80ull |
|---|
| 4988 | #define DCORE3_TPC1_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 4989 | #define DCORE3_TPC1_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 4990 | #define mmDCORE3_TPC1_EML_CS_BASE 0x33FF000ull |
|---|
| 4991 | #define DCORE3_TPC1_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 4992 | #define DCORE3_TPC1_EML_CS_SECTION 0x1000 |
|---|
| 4993 | #define mmDCORE3_TPC2_ROM_TABLE_BASE 0x3400000ull |
|---|
| 4994 | #define DCORE3_TPC2_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 4995 | #define DCORE3_TPC2_ROM_TABLE_SECTION 0x1000 |
|---|
| 4996 | #define mmDCORE3_TPC2_EML_SPMU_BASE 0x3401000ull |
|---|
| 4997 | #define DCORE3_TPC2_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 4998 | #define DCORE3_TPC2_EML_SPMU_SECTION 0x1000 |
|---|
| 4999 | #define mmDCORE3_TPC2_EML_ETF_BASE 0x3402000ull |
|---|
| 5000 | #define DCORE3_TPC2_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 5001 | #define DCORE3_TPC2_EML_ETF_SECTION 0x1000 |
|---|
| 5002 | #define mmDCORE3_TPC2_EML_STM_BASE 0x3403000ull |
|---|
| 5003 | #define DCORE3_TPC2_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 5004 | #define DCORE3_TPC2_EML_STM_SECTION 0x2000 |
|---|
| 5005 | #define mmDCORE3_TPC2_EML_CTI_BASE 0x3405000ull |
|---|
| 5006 | #define DCORE3_TPC2_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 5007 | #define DCORE3_TPC2_EML_CTI_SECTION 0x1000 |
|---|
| 5008 | #define mmDCORE3_TPC2_EML_FUNNEL_BASE 0x3406000ull |
|---|
| 5009 | #define DCORE3_TPC2_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 5010 | #define DCORE3_TPC2_EML_FUNNEL_SECTION 0x1000 |
|---|
| 5011 | #define mmDCORE3_TPC2_EML_BUSMON_0_BASE 0x3407000ull |
|---|
| 5012 | #define DCORE3_TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 5013 | #define DCORE3_TPC2_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 5014 | #define mmDCORE3_TPC2_EML_BUSMON_1_BASE 0x3408000ull |
|---|
| 5015 | #define DCORE3_TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 5016 | #define DCORE3_TPC2_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 5017 | #define mmDCORE3_TPC2_EML_BUSMON_2_BASE 0x3409000ull |
|---|
| 5018 | #define DCORE3_TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 5019 | #define DCORE3_TPC2_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 5020 | #define mmDCORE3_TPC2_EML_BUSMON_3_BASE 0x340A000ull |
|---|
| 5021 | #define DCORE3_TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 5022 | #define DCORE3_TPC2_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 5023 | #define mmDCORE3_TPC2_QM_ARC_RTT_BASE 0x340B000ull |
|---|
| 5024 | #define DCORE3_TPC2_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 5025 | #define DCORE3_TPC2_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 5026 | #define mmDCORE3_TPC2_EML_CFG_BASE 0x3440000ull |
|---|
| 5027 | #define DCORE3_TPC2_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 5028 | #define DCORE3_TPC2_EML_CFG_SECTION 0xE800 |
|---|
| 5029 | #define mmDCORE3_TPC2_EML_CFG_SPECIAL_BASE 0x3440E80ull |
|---|
| 5030 | #define DCORE3_TPC2_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5031 | #define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5032 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3441000ull |
|---|
| 5033 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5034 | #define DCORE3_TPC2_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5035 | #define mmDCORE3_TPC2_EML_TPC_CFG_BASE 0x3441000ull |
|---|
| 5036 | #define DCORE3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 5037 | #define DCORE3_TPC2_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 5038 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3441050ull |
|---|
| 5039 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5040 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 5041 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x34410A0ull |
|---|
| 5042 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5043 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 5044 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x34410F0ull |
|---|
| 5045 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5046 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 5047 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3441140ull |
|---|
| 5048 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5049 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 5050 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3441190ull |
|---|
| 5051 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5052 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 5053 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x34411E0ull |
|---|
| 5054 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5055 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 5056 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3441230ull |
|---|
| 5057 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5058 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 5059 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3441280ull |
|---|
| 5060 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5061 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 5062 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x34412D0ull |
|---|
| 5063 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5064 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 5065 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3441320ull |
|---|
| 5066 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5067 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 5068 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3441370ull |
|---|
| 5069 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5070 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 5071 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x34413C0ull |
|---|
| 5072 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5073 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 5074 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3441410ull |
|---|
| 5075 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5076 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 5077 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3441460ull |
|---|
| 5078 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5079 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 5080 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x34414B0ull |
|---|
| 5081 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5082 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 5083 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3441500ull |
|---|
| 5084 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5085 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5086 | #define mmDCORE3_TPC2_EML_TPC_CFG_KERNEL_BASE 0x3441508ull |
|---|
| 5087 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 5088 | #define DCORE3_TPC2_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 5089 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_BASE 0x34415DCull |
|---|
| 5090 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5091 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 5092 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_BASE 0x344162Cull |
|---|
| 5093 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5094 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 5095 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_BASE 0x344167Cull |
|---|
| 5096 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5097 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 5098 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_BASE 0x34416CCull |
|---|
| 5099 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5100 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 5101 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_BASE 0x344171Cull |
|---|
| 5102 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5103 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 5104 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_BASE 0x344176Cull |
|---|
| 5105 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5106 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 5107 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_BASE 0x34417BCull |
|---|
| 5108 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5109 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 5110 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_BASE 0x344180Cull |
|---|
| 5111 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5112 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 5113 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_BASE 0x344185Cull |
|---|
| 5114 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5115 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 5116 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_BASE 0x34418ACull |
|---|
| 5117 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5118 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 5119 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_BASE 0x34418FCull |
|---|
| 5120 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5121 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 5122 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_BASE 0x344194Cull |
|---|
| 5123 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5124 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 5125 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_BASE 0x344199Cull |
|---|
| 5126 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5127 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 5128 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_BASE 0x34419ECull |
|---|
| 5129 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5130 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 5131 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3441A3Cull |
|---|
| 5132 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5133 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 5134 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3441A8Cull |
|---|
| 5135 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5136 | #define DCORE3_TPC2_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 5137 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3441ADCull |
|---|
| 5138 | #define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5139 | #define DCORE3_TPC2_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5140 | #define mmDCORE3_TPC2_EML_TPC_CFG_QM_BASE 0x3441AE4ull |
|---|
| 5141 | #define DCORE3_TPC2_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 5142 | #define DCORE3_TPC2_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 5143 | #define mmDCORE3_TPC2_EML_TPC_CFG_AXUSER_BASE 0x3441E00ull |
|---|
| 5144 | #define DCORE3_TPC2_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 5145 | #define DCORE3_TPC2_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 5146 | #define mmDCORE3_TPC2_EML_TPC_CFG_SPECIAL_BASE 0x3441E80ull |
|---|
| 5147 | #define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5148 | #define DCORE3_TPC2_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5149 | #define mmDCORE3_TPC2_EML_QM_DCCM_BASE 0x3442000ull |
|---|
| 5150 | #define DCORE3_TPC2_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 5151 | #define DCORE3_TPC2_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 5152 | #define mmDCORE3_TPC2_EML_QM_ARCAUX_BASE 0x344A000ull |
|---|
| 5153 | #define DCORE3_TPC2_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 5154 | #define DCORE3_TPC2_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 5155 | #define mmDCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_BASE 0x344AE80ull |
|---|
| 5156 | #define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5157 | #define DCORE3_TPC2_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 5158 | #define mmDCORE3_TPC2_EML_TPC_QM_BASE 0x344C000ull |
|---|
| 5159 | #define DCORE3_TPC2_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 5160 | #define DCORE3_TPC2_EML_TPC_QM_SECTION 0x9000 |
|---|
| 5161 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x344C900ull |
|---|
| 5162 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 5163 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 5164 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x344C908ull |
|---|
| 5165 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 5166 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 5167 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x344C910ull |
|---|
| 5168 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 5169 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 5170 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x344C918ull |
|---|
| 5171 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 5172 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 5173 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x344C920ull |
|---|
| 5174 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 5175 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 5176 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x344C928ull |
|---|
| 5177 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 5178 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 5179 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x344C930ull |
|---|
| 5180 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 5181 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 5182 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x344C938ull |
|---|
| 5183 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 5184 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 5185 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x344C940ull |
|---|
| 5186 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 5187 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 5188 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x344C948ull |
|---|
| 5189 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 5190 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 5191 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x344C950ull |
|---|
| 5192 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 5193 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 5194 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x344C958ull |
|---|
| 5195 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 5196 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 5197 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x344C960ull |
|---|
| 5198 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 5199 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 5200 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x344C968ull |
|---|
| 5201 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 5202 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 5203 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x344C970ull |
|---|
| 5204 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 5205 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 5206 | #define mmDCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x344C978ull |
|---|
| 5207 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 5208 | #define DCORE3_TPC2_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 5209 | #define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_BASE 0x344CB00ull |
|---|
| 5210 | #define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 5211 | #define DCORE3_TPC2_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 5212 | #define mmDCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x344CB80ull |
|---|
| 5213 | #define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 5214 | #define DCORE3_TPC2_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 5215 | #define mmDCORE3_TPC2_EML_TPC_QM_DBG_HBW_BASE 0x344CC00ull |
|---|
| 5216 | #define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 5217 | #define DCORE3_TPC2_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 5218 | #define mmDCORE3_TPC2_EML_TPC_QM_DBG_LBW_BASE 0x344CC80ull |
|---|
| 5219 | #define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 5220 | #define DCORE3_TPC2_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 5221 | #define mmDCORE3_TPC2_EML_TPC_QM_CGM_BASE 0x344CD80ull |
|---|
| 5222 | #define DCORE3_TPC2_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 5223 | #define DCORE3_TPC2_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 5224 | #define mmDCORE3_TPC2_EML_TPC_QM_SPECIAL_BASE 0x344CE80ull |
|---|
| 5225 | #define DCORE3_TPC2_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5226 | #define DCORE3_TPC2_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 5227 | #define mmDCORE3_TPC2_EML_CS_BASE 0x35FF000ull |
|---|
| 5228 | #define DCORE3_TPC2_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 5229 | #define DCORE3_TPC2_EML_CS_SECTION 0x1000 |
|---|
| 5230 | #define mmDCORE3_TPC3_ROM_TABLE_BASE 0x3600000ull |
|---|
| 5231 | #define DCORE3_TPC3_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 5232 | #define DCORE3_TPC3_ROM_TABLE_SECTION 0x1000 |
|---|
| 5233 | #define mmDCORE3_TPC3_EML_SPMU_BASE 0x3601000ull |
|---|
| 5234 | #define DCORE3_TPC3_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 5235 | #define DCORE3_TPC3_EML_SPMU_SECTION 0x1000 |
|---|
| 5236 | #define mmDCORE3_TPC3_EML_ETF_BASE 0x3602000ull |
|---|
| 5237 | #define DCORE3_TPC3_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 5238 | #define DCORE3_TPC3_EML_ETF_SECTION 0x1000 |
|---|
| 5239 | #define mmDCORE3_TPC3_EML_STM_BASE 0x3603000ull |
|---|
| 5240 | #define DCORE3_TPC3_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 5241 | #define DCORE3_TPC3_EML_STM_SECTION 0x2000 |
|---|
| 5242 | #define mmDCORE3_TPC3_EML_CTI_BASE 0x3605000ull |
|---|
| 5243 | #define DCORE3_TPC3_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 5244 | #define DCORE3_TPC3_EML_CTI_SECTION 0x1000 |
|---|
| 5245 | #define mmDCORE3_TPC3_EML_FUNNEL_BASE 0x3606000ull |
|---|
| 5246 | #define DCORE3_TPC3_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 5247 | #define DCORE3_TPC3_EML_FUNNEL_SECTION 0x1000 |
|---|
| 5248 | #define mmDCORE3_TPC3_EML_BUSMON_0_BASE 0x3607000ull |
|---|
| 5249 | #define DCORE3_TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 5250 | #define DCORE3_TPC3_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 5251 | #define mmDCORE3_TPC3_EML_BUSMON_1_BASE 0x3608000ull |
|---|
| 5252 | #define DCORE3_TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 5253 | #define DCORE3_TPC3_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 5254 | #define mmDCORE3_TPC3_EML_BUSMON_2_BASE 0x3609000ull |
|---|
| 5255 | #define DCORE3_TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 5256 | #define DCORE3_TPC3_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 5257 | #define mmDCORE3_TPC3_EML_BUSMON_3_BASE 0x360A000ull |
|---|
| 5258 | #define DCORE3_TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 5259 | #define DCORE3_TPC3_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 5260 | #define mmDCORE3_TPC3_QM_ARC_RTT_BASE 0x360B000ull |
|---|
| 5261 | #define DCORE3_TPC3_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 5262 | #define DCORE3_TPC3_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 5263 | #define mmDCORE3_TPC3_EML_CFG_BASE 0x3640000ull |
|---|
| 5264 | #define DCORE3_TPC3_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 5265 | #define DCORE3_TPC3_EML_CFG_SECTION 0xE800 |
|---|
| 5266 | #define mmDCORE3_TPC3_EML_CFG_SPECIAL_BASE 0x3640E80ull |
|---|
| 5267 | #define DCORE3_TPC3_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5268 | #define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5269 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3641000ull |
|---|
| 5270 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5271 | #define DCORE3_TPC3_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5272 | #define mmDCORE3_TPC3_EML_TPC_CFG_BASE 0x3641000ull |
|---|
| 5273 | #define DCORE3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 5274 | #define DCORE3_TPC3_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 5275 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3641050ull |
|---|
| 5276 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5277 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 5278 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x36410A0ull |
|---|
| 5279 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5280 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 5281 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x36410F0ull |
|---|
| 5282 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5283 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 5284 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3641140ull |
|---|
| 5285 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5286 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 5287 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3641190ull |
|---|
| 5288 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5289 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 5290 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x36411E0ull |
|---|
| 5291 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5292 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 5293 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3641230ull |
|---|
| 5294 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5295 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 5296 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3641280ull |
|---|
| 5297 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5298 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 5299 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x36412D0ull |
|---|
| 5300 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5301 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 5302 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3641320ull |
|---|
| 5303 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5304 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 5305 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3641370ull |
|---|
| 5306 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5307 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 5308 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x36413C0ull |
|---|
| 5309 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5310 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 5311 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3641410ull |
|---|
| 5312 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5313 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 5314 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3641460ull |
|---|
| 5315 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5316 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 5317 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x36414B0ull |
|---|
| 5318 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5319 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 5320 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3641500ull |
|---|
| 5321 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5322 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5323 | #define mmDCORE3_TPC3_EML_TPC_CFG_KERNEL_BASE 0x3641508ull |
|---|
| 5324 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 5325 | #define DCORE3_TPC3_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 5326 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_BASE 0x36415DCull |
|---|
| 5327 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5328 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 5329 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_BASE 0x364162Cull |
|---|
| 5330 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5331 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 5332 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_BASE 0x364167Cull |
|---|
| 5333 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5334 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 5335 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_BASE 0x36416CCull |
|---|
| 5336 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5337 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 5338 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_BASE 0x364171Cull |
|---|
| 5339 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5340 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 5341 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_BASE 0x364176Cull |
|---|
| 5342 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5343 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 5344 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_BASE 0x36417BCull |
|---|
| 5345 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5346 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 5347 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_BASE 0x364180Cull |
|---|
| 5348 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5349 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 5350 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_BASE 0x364185Cull |
|---|
| 5351 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5352 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 5353 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_BASE 0x36418ACull |
|---|
| 5354 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5355 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 5356 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_BASE 0x36418FCull |
|---|
| 5357 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5358 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 5359 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_BASE 0x364194Cull |
|---|
| 5360 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5361 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 5362 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_BASE 0x364199Cull |
|---|
| 5363 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5364 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 5365 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_BASE 0x36419ECull |
|---|
| 5366 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5367 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 5368 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3641A3Cull |
|---|
| 5369 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5370 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 5371 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3641A8Cull |
|---|
| 5372 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5373 | #define DCORE3_TPC3_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 5374 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3641ADCull |
|---|
| 5375 | #define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5376 | #define DCORE3_TPC3_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5377 | #define mmDCORE3_TPC3_EML_TPC_CFG_QM_BASE 0x3641AE4ull |
|---|
| 5378 | #define DCORE3_TPC3_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 5379 | #define DCORE3_TPC3_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 5380 | #define mmDCORE3_TPC3_EML_TPC_CFG_AXUSER_BASE 0x3641E00ull |
|---|
| 5381 | #define DCORE3_TPC3_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 5382 | #define DCORE3_TPC3_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 5383 | #define mmDCORE3_TPC3_EML_TPC_CFG_SPECIAL_BASE 0x3641E80ull |
|---|
| 5384 | #define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5385 | #define DCORE3_TPC3_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5386 | #define mmDCORE3_TPC3_EML_QM_DCCM_BASE 0x3642000ull |
|---|
| 5387 | #define DCORE3_TPC3_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 5388 | #define DCORE3_TPC3_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 5389 | #define mmDCORE3_TPC3_EML_QM_ARCAUX_BASE 0x364A000ull |
|---|
| 5390 | #define DCORE3_TPC3_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 5391 | #define DCORE3_TPC3_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 5392 | #define mmDCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_BASE 0x364AE80ull |
|---|
| 5393 | #define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5394 | #define DCORE3_TPC3_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 5395 | #define mmDCORE3_TPC3_EML_TPC_QM_BASE 0x364C000ull |
|---|
| 5396 | #define DCORE3_TPC3_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 5397 | #define DCORE3_TPC3_EML_TPC_QM_SECTION 0x9000 |
|---|
| 5398 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x364C900ull |
|---|
| 5399 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 5400 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 5401 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x364C908ull |
|---|
| 5402 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 5403 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 5404 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x364C910ull |
|---|
| 5405 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 5406 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 5407 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x364C918ull |
|---|
| 5408 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 5409 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 5410 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x364C920ull |
|---|
| 5411 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 5412 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 5413 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x364C928ull |
|---|
| 5414 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 5415 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 5416 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x364C930ull |
|---|
| 5417 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 5418 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 5419 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x364C938ull |
|---|
| 5420 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 5421 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 5422 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x364C940ull |
|---|
| 5423 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 5424 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 5425 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x364C948ull |
|---|
| 5426 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 5427 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 5428 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x364C950ull |
|---|
| 5429 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 5430 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 5431 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x364C958ull |
|---|
| 5432 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 5433 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 5434 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x364C960ull |
|---|
| 5435 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 5436 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 5437 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x364C968ull |
|---|
| 5438 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 5439 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 5440 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x364C970ull |
|---|
| 5441 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 5442 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 5443 | #define mmDCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x364C978ull |
|---|
| 5444 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 5445 | #define DCORE3_TPC3_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 5446 | #define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_BASE 0x364CB00ull |
|---|
| 5447 | #define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 5448 | #define DCORE3_TPC3_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 5449 | #define mmDCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x364CB80ull |
|---|
| 5450 | #define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 5451 | #define DCORE3_TPC3_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 5452 | #define mmDCORE3_TPC3_EML_TPC_QM_DBG_HBW_BASE 0x364CC00ull |
|---|
| 5453 | #define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 5454 | #define DCORE3_TPC3_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 5455 | #define mmDCORE3_TPC3_EML_TPC_QM_DBG_LBW_BASE 0x364CC80ull |
|---|
| 5456 | #define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 5457 | #define DCORE3_TPC3_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 5458 | #define mmDCORE3_TPC3_EML_TPC_QM_CGM_BASE 0x364CD80ull |
|---|
| 5459 | #define DCORE3_TPC3_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 5460 | #define DCORE3_TPC3_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 5461 | #define mmDCORE3_TPC3_EML_TPC_QM_SPECIAL_BASE 0x364CE80ull |
|---|
| 5462 | #define DCORE3_TPC3_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5463 | #define DCORE3_TPC3_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 5464 | #define mmDCORE3_TPC3_EML_CS_BASE 0x37FF000ull |
|---|
| 5465 | #define DCORE3_TPC3_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 5466 | #define DCORE3_TPC3_EML_CS_SECTION 0x1000 |
|---|
| 5467 | #define mmDCORE3_TPC4_ROM_TABLE_BASE 0x3800000ull |
|---|
| 5468 | #define DCORE3_TPC4_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 5469 | #define DCORE3_TPC4_ROM_TABLE_SECTION 0x1000 |
|---|
| 5470 | #define mmDCORE3_TPC4_EML_SPMU_BASE 0x3801000ull |
|---|
| 5471 | #define DCORE3_TPC4_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 5472 | #define DCORE3_TPC4_EML_SPMU_SECTION 0x1000 |
|---|
| 5473 | #define mmDCORE3_TPC4_EML_ETF_BASE 0x3802000ull |
|---|
| 5474 | #define DCORE3_TPC4_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 5475 | #define DCORE3_TPC4_EML_ETF_SECTION 0x1000 |
|---|
| 5476 | #define mmDCORE3_TPC4_EML_STM_BASE 0x3803000ull |
|---|
| 5477 | #define DCORE3_TPC4_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 5478 | #define DCORE3_TPC4_EML_STM_SECTION 0x2000 |
|---|
| 5479 | #define mmDCORE3_TPC4_EML_CTI_BASE 0x3805000ull |
|---|
| 5480 | #define DCORE3_TPC4_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 5481 | #define DCORE3_TPC4_EML_CTI_SECTION 0x1000 |
|---|
| 5482 | #define mmDCORE3_TPC4_EML_FUNNEL_BASE 0x3806000ull |
|---|
| 5483 | #define DCORE3_TPC4_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 5484 | #define DCORE3_TPC4_EML_FUNNEL_SECTION 0x1000 |
|---|
| 5485 | #define mmDCORE3_TPC4_EML_BUSMON_0_BASE 0x3807000ull |
|---|
| 5486 | #define DCORE3_TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 5487 | #define DCORE3_TPC4_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 5488 | #define mmDCORE3_TPC4_EML_BUSMON_1_BASE 0x3808000ull |
|---|
| 5489 | #define DCORE3_TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 5490 | #define DCORE3_TPC4_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 5491 | #define mmDCORE3_TPC4_EML_BUSMON_2_BASE 0x3809000ull |
|---|
| 5492 | #define DCORE3_TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 5493 | #define DCORE3_TPC4_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 5494 | #define mmDCORE3_TPC4_EML_BUSMON_3_BASE 0x380A000ull |
|---|
| 5495 | #define DCORE3_TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 5496 | #define DCORE3_TPC4_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 5497 | #define mmDCORE3_TPC4_QM_ARC_RTT_BASE 0x380B000ull |
|---|
| 5498 | #define DCORE3_TPC4_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 5499 | #define DCORE3_TPC4_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 5500 | #define mmDCORE3_TPC4_EML_CFG_BASE 0x3840000ull |
|---|
| 5501 | #define DCORE3_TPC4_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 5502 | #define DCORE3_TPC4_EML_CFG_SECTION 0xE800 |
|---|
| 5503 | #define mmDCORE3_TPC4_EML_CFG_SPECIAL_BASE 0x3840E80ull |
|---|
| 5504 | #define DCORE3_TPC4_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5505 | #define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5506 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3841000ull |
|---|
| 5507 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5508 | #define DCORE3_TPC4_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5509 | #define mmDCORE3_TPC4_EML_TPC_CFG_BASE 0x3841000ull |
|---|
| 5510 | #define DCORE3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 5511 | #define DCORE3_TPC4_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 5512 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3841050ull |
|---|
| 5513 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5514 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 5515 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x38410A0ull |
|---|
| 5516 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5517 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 5518 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x38410F0ull |
|---|
| 5519 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5520 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 5521 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3841140ull |
|---|
| 5522 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5523 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 5524 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3841190ull |
|---|
| 5525 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5526 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 5527 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x38411E0ull |
|---|
| 5528 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5529 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 5530 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3841230ull |
|---|
| 5531 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5532 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 5533 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3841280ull |
|---|
| 5534 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5535 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 5536 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x38412D0ull |
|---|
| 5537 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5538 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 5539 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3841320ull |
|---|
| 5540 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5541 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 5542 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3841370ull |
|---|
| 5543 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5544 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 5545 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x38413C0ull |
|---|
| 5546 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5547 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 5548 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3841410ull |
|---|
| 5549 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5550 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 5551 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3841460ull |
|---|
| 5552 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5553 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 5554 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x38414B0ull |
|---|
| 5555 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5556 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 5557 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3841500ull |
|---|
| 5558 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5559 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5560 | #define mmDCORE3_TPC4_EML_TPC_CFG_KERNEL_BASE 0x3841508ull |
|---|
| 5561 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 5562 | #define DCORE3_TPC4_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 5563 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_BASE 0x38415DCull |
|---|
| 5564 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5565 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 5566 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_BASE 0x384162Cull |
|---|
| 5567 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5568 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 5569 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_BASE 0x384167Cull |
|---|
| 5570 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5571 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 5572 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_BASE 0x38416CCull |
|---|
| 5573 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5574 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 5575 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_BASE 0x384171Cull |
|---|
| 5576 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5577 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 5578 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_BASE 0x384176Cull |
|---|
| 5579 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5580 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 5581 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_BASE 0x38417BCull |
|---|
| 5582 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5583 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 5584 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_BASE 0x384180Cull |
|---|
| 5585 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5586 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 5587 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_BASE 0x384185Cull |
|---|
| 5588 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5589 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 5590 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_BASE 0x38418ACull |
|---|
| 5591 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5592 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 5593 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_BASE 0x38418FCull |
|---|
| 5594 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5595 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 5596 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_BASE 0x384194Cull |
|---|
| 5597 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5598 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 5599 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_BASE 0x384199Cull |
|---|
| 5600 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5601 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 5602 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_BASE 0x38419ECull |
|---|
| 5603 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5604 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 5605 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3841A3Cull |
|---|
| 5606 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5607 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 5608 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3841A8Cull |
|---|
| 5609 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5610 | #define DCORE3_TPC4_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 5611 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3841ADCull |
|---|
| 5612 | #define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5613 | #define DCORE3_TPC4_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5614 | #define mmDCORE3_TPC4_EML_TPC_CFG_QM_BASE 0x3841AE4ull |
|---|
| 5615 | #define DCORE3_TPC4_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 5616 | #define DCORE3_TPC4_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 5617 | #define mmDCORE3_TPC4_EML_TPC_CFG_AXUSER_BASE 0x3841E00ull |
|---|
| 5618 | #define DCORE3_TPC4_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 5619 | #define DCORE3_TPC4_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 5620 | #define mmDCORE3_TPC4_EML_TPC_CFG_SPECIAL_BASE 0x3841E80ull |
|---|
| 5621 | #define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5622 | #define DCORE3_TPC4_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5623 | #define mmDCORE3_TPC4_EML_QM_DCCM_BASE 0x3842000ull |
|---|
| 5624 | #define DCORE3_TPC4_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 5625 | #define DCORE3_TPC4_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 5626 | #define mmDCORE3_TPC4_EML_QM_ARCAUX_BASE 0x384A000ull |
|---|
| 5627 | #define DCORE3_TPC4_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 5628 | #define DCORE3_TPC4_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 5629 | #define mmDCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_BASE 0x384AE80ull |
|---|
| 5630 | #define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5631 | #define DCORE3_TPC4_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 5632 | #define mmDCORE3_TPC4_EML_TPC_QM_BASE 0x384C000ull |
|---|
| 5633 | #define DCORE3_TPC4_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 5634 | #define DCORE3_TPC4_EML_TPC_QM_SECTION 0x9000 |
|---|
| 5635 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x384C900ull |
|---|
| 5636 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 5637 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 5638 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x384C908ull |
|---|
| 5639 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 5640 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 5641 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x384C910ull |
|---|
| 5642 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 5643 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 5644 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x384C918ull |
|---|
| 5645 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 5646 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 5647 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x384C920ull |
|---|
| 5648 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 5649 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 5650 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x384C928ull |
|---|
| 5651 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 5652 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 5653 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x384C930ull |
|---|
| 5654 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 5655 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 5656 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x384C938ull |
|---|
| 5657 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 5658 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 5659 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x384C940ull |
|---|
| 5660 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 5661 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 5662 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x384C948ull |
|---|
| 5663 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 5664 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 5665 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x384C950ull |
|---|
| 5666 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 5667 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 5668 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x384C958ull |
|---|
| 5669 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 5670 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 5671 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x384C960ull |
|---|
| 5672 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 5673 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 5674 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x384C968ull |
|---|
| 5675 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 5676 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 5677 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x384C970ull |
|---|
| 5678 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 5679 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 5680 | #define mmDCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x384C978ull |
|---|
| 5681 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 5682 | #define DCORE3_TPC4_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 5683 | #define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_BASE 0x384CB00ull |
|---|
| 5684 | #define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 5685 | #define DCORE3_TPC4_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 5686 | #define mmDCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x384CB80ull |
|---|
| 5687 | #define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 5688 | #define DCORE3_TPC4_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 5689 | #define mmDCORE3_TPC4_EML_TPC_QM_DBG_HBW_BASE 0x384CC00ull |
|---|
| 5690 | #define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 5691 | #define DCORE3_TPC4_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 5692 | #define mmDCORE3_TPC4_EML_TPC_QM_DBG_LBW_BASE 0x384CC80ull |
|---|
| 5693 | #define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 5694 | #define DCORE3_TPC4_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 5695 | #define mmDCORE3_TPC4_EML_TPC_QM_CGM_BASE 0x384CD80ull |
|---|
| 5696 | #define DCORE3_TPC4_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 5697 | #define DCORE3_TPC4_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 5698 | #define mmDCORE3_TPC4_EML_TPC_QM_SPECIAL_BASE 0x384CE80ull |
|---|
| 5699 | #define DCORE3_TPC4_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5700 | #define DCORE3_TPC4_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 5701 | #define mmDCORE3_TPC4_EML_CS_BASE 0x39FF000ull |
|---|
| 5702 | #define DCORE3_TPC4_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 5703 | #define DCORE3_TPC4_EML_CS_SECTION 0x1000 |
|---|
| 5704 | #define mmDCORE3_TPC5_ROM_TABLE_BASE 0x3A00000ull |
|---|
| 5705 | #define DCORE3_TPC5_ROM_TABLE_MAX_OFFSET 0x1000 |
|---|
| 5706 | #define DCORE3_TPC5_ROM_TABLE_SECTION 0x1000 |
|---|
| 5707 | #define mmDCORE3_TPC5_EML_SPMU_BASE 0x3A01000ull |
|---|
| 5708 | #define DCORE3_TPC5_EML_SPMU_MAX_OFFSET 0x1000 |
|---|
| 5709 | #define DCORE3_TPC5_EML_SPMU_SECTION 0x1000 |
|---|
| 5710 | #define mmDCORE3_TPC5_EML_ETF_BASE 0x3A02000ull |
|---|
| 5711 | #define DCORE3_TPC5_EML_ETF_MAX_OFFSET 0x1000 |
|---|
| 5712 | #define DCORE3_TPC5_EML_ETF_SECTION 0x1000 |
|---|
| 5713 | #define mmDCORE3_TPC5_EML_STM_BASE 0x3A03000ull |
|---|
| 5714 | #define DCORE3_TPC5_EML_STM_MAX_OFFSET 0x1000 |
|---|
| 5715 | #define DCORE3_TPC5_EML_STM_SECTION 0x2000 |
|---|
| 5716 | #define mmDCORE3_TPC5_EML_CTI_BASE 0x3A05000ull |
|---|
| 5717 | #define DCORE3_TPC5_EML_CTI_MAX_OFFSET 0x1000 |
|---|
| 5718 | #define DCORE3_TPC5_EML_CTI_SECTION 0x1000 |
|---|
| 5719 | #define mmDCORE3_TPC5_EML_FUNNEL_BASE 0x3A06000ull |
|---|
| 5720 | #define DCORE3_TPC5_EML_FUNNEL_MAX_OFFSET 0x1000 |
|---|
| 5721 | #define DCORE3_TPC5_EML_FUNNEL_SECTION 0x1000 |
|---|
| 5722 | #define mmDCORE3_TPC5_EML_BUSMON_0_BASE 0x3A07000ull |
|---|
| 5723 | #define DCORE3_TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000 |
|---|
| 5724 | #define DCORE3_TPC5_EML_BUSMON_0_SECTION 0x1000 |
|---|
| 5725 | #define mmDCORE3_TPC5_EML_BUSMON_1_BASE 0x3A08000ull |
|---|
| 5726 | #define DCORE3_TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000 |
|---|
| 5727 | #define DCORE3_TPC5_EML_BUSMON_1_SECTION 0x1000 |
|---|
| 5728 | #define mmDCORE3_TPC5_EML_BUSMON_2_BASE 0x3A09000ull |
|---|
| 5729 | #define DCORE3_TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000 |
|---|
| 5730 | #define DCORE3_TPC5_EML_BUSMON_2_SECTION 0x1000 |
|---|
| 5731 | #define mmDCORE3_TPC5_EML_BUSMON_3_BASE 0x3A0A000ull |
|---|
| 5732 | #define DCORE3_TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000 |
|---|
| 5733 | #define DCORE3_TPC5_EML_BUSMON_3_SECTION 0x1000 |
|---|
| 5734 | #define mmDCORE3_TPC5_QM_ARC_RTT_BASE 0x3A0B000ull |
|---|
| 5735 | #define DCORE3_TPC5_QM_ARC_RTT_MAX_OFFSET 0x1400 |
|---|
| 5736 | #define DCORE3_TPC5_QM_ARC_RTT_SECTION 0x35000 |
|---|
| 5737 | #define mmDCORE3_TPC5_EML_CFG_BASE 0x3A40000ull |
|---|
| 5738 | #define DCORE3_TPC5_EML_CFG_MAX_OFFSET 0x1000 |
|---|
| 5739 | #define DCORE3_TPC5_EML_CFG_SECTION 0xE800 |
|---|
| 5740 | #define mmDCORE3_TPC5_EML_CFG_SPECIAL_BASE 0x3A40E80ull |
|---|
| 5741 | #define DCORE3_TPC5_EML_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5742 | #define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5743 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_BASE 0x3A41000ull |
|---|
| 5744 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5745 | #define DCORE3_TPC5_EML_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5746 | #define mmDCORE3_TPC5_EML_TPC_CFG_BASE 0x3A41000ull |
|---|
| 5747 | #define DCORE3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x1000 |
|---|
| 5748 | #define DCORE3_TPC5_EML_TPC_CFG_SECTION 0x5000 |
|---|
| 5749 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_BASE 0x3A41050ull |
|---|
| 5750 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5751 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 5752 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_BASE 0x3A410A0ull |
|---|
| 5753 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5754 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 5755 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_BASE 0x3A410F0ull |
|---|
| 5756 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5757 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 5758 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_BASE 0x3A41140ull |
|---|
| 5759 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5760 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 5761 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_BASE 0x3A41190ull |
|---|
| 5762 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5763 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 5764 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_BASE 0x3A411E0ull |
|---|
| 5765 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5766 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 5767 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_BASE 0x3A41230ull |
|---|
| 5768 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5769 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 5770 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_BASE 0x3A41280ull |
|---|
| 5771 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5772 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 5773 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_BASE 0x3A412D0ull |
|---|
| 5774 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5775 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 5776 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_BASE 0x3A41320ull |
|---|
| 5777 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5778 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 5779 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_BASE 0x3A41370ull |
|---|
| 5780 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5781 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 5782 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_BASE 0x3A413C0ull |
|---|
| 5783 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5784 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 5785 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_BASE 0x3A41410ull |
|---|
| 5786 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5787 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 5788 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_BASE 0x3A41460ull |
|---|
| 5789 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5790 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 5791 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_BASE 0x3A414B0ull |
|---|
| 5792 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5793 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 5794 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_BASE 0x3A41500ull |
|---|
| 5795 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5796 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5797 | #define mmDCORE3_TPC5_EML_TPC_CFG_KERNEL_BASE 0x3A41508ull |
|---|
| 5798 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 5799 | #define DCORE3_TPC5_EML_TPC_CFG_KERNEL_SECTION 0xD400 |
|---|
| 5800 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_BASE 0x3A415DCull |
|---|
| 5801 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 5802 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 5803 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_BASE 0x3A4162Cull |
|---|
| 5804 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 5805 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 5806 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_BASE 0x3A4167Cull |
|---|
| 5807 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 5808 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 5809 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_BASE 0x3A416CCull |
|---|
| 5810 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 5811 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 5812 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_BASE 0x3A4171Cull |
|---|
| 5813 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 5814 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 5815 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_BASE 0x3A4176Cull |
|---|
| 5816 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 5817 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 5818 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_BASE 0x3A417BCull |
|---|
| 5819 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 5820 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 5821 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_BASE 0x3A4180Cull |
|---|
| 5822 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 5823 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 5824 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_BASE 0x3A4185Cull |
|---|
| 5825 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 5826 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 5827 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_BASE 0x3A418ACull |
|---|
| 5828 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 5829 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 5830 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_BASE 0x3A418FCull |
|---|
| 5831 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 5832 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 5833 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_BASE 0x3A4194Cull |
|---|
| 5834 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 5835 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 5836 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_BASE 0x3A4199Cull |
|---|
| 5837 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 5838 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 5839 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_BASE 0x3A419ECull |
|---|
| 5840 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 5841 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 5842 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_BASE 0x3A41A3Cull |
|---|
| 5843 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 5844 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 5845 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_BASE 0x3A41A8Cull |
|---|
| 5846 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 5847 | #define DCORE3_TPC5_EML_TPC_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 5848 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_BASE 0x3A41ADCull |
|---|
| 5849 | #define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 5850 | #define DCORE3_TPC5_EML_TPC_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 5851 | #define mmDCORE3_TPC5_EML_TPC_CFG_QM_BASE 0x3A41AE4ull |
|---|
| 5852 | #define DCORE3_TPC5_EML_TPC_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 5853 | #define DCORE3_TPC5_EML_TPC_CFG_QM_SECTION 0x31C0 |
|---|
| 5854 | #define mmDCORE3_TPC5_EML_TPC_CFG_AXUSER_BASE 0x3A41E00ull |
|---|
| 5855 | #define DCORE3_TPC5_EML_TPC_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 5856 | #define DCORE3_TPC5_EML_TPC_CFG_AXUSER_SECTION 0x8000 |
|---|
| 5857 | #define mmDCORE3_TPC5_EML_TPC_CFG_SPECIAL_BASE 0x3A41E80ull |
|---|
| 5858 | #define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5859 | #define DCORE3_TPC5_EML_TPC_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 5860 | #define mmDCORE3_TPC5_EML_QM_DCCM_BASE 0x3A42000ull |
|---|
| 5861 | #define DCORE3_TPC5_EML_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 5862 | #define DCORE3_TPC5_EML_QM_DCCM_SECTION 0x8000 |
|---|
| 5863 | #define mmDCORE3_TPC5_EML_QM_ARCAUX_BASE 0x3A4A000ull |
|---|
| 5864 | #define DCORE3_TPC5_EML_QM_ARCAUX_MAX_OFFSET 0x1000 |
|---|
| 5865 | #define DCORE3_TPC5_EML_QM_ARCAUX_SECTION 0xE800 |
|---|
| 5866 | #define mmDCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_BASE 0x3A4AE80ull |
|---|
| 5867 | #define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5868 | #define DCORE3_TPC5_EML_QM_ARCAUX_SPECIAL_SECTION 0x1180 |
|---|
| 5869 | #define mmDCORE3_TPC5_EML_TPC_QM_BASE 0x3A4C000ull |
|---|
| 5870 | #define DCORE3_TPC5_EML_TPC_QM_MAX_OFFSET 0x1000 |
|---|
| 5871 | #define DCORE3_TPC5_EML_TPC_QM_SECTION 0x9000 |
|---|
| 5872 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_BASE 0x3A4C900ull |
|---|
| 5873 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 5874 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 5875 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_BASE 0x3A4C908ull |
|---|
| 5876 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 5877 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 5878 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_BASE 0x3A4C910ull |
|---|
| 5879 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 5880 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 5881 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_BASE 0x3A4C918ull |
|---|
| 5882 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 5883 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 5884 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_BASE 0x3A4C920ull |
|---|
| 5885 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 5886 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 5887 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_BASE 0x3A4C928ull |
|---|
| 5888 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 5889 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 5890 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_BASE 0x3A4C930ull |
|---|
| 5891 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 5892 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 5893 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_BASE 0x3A4C938ull |
|---|
| 5894 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 5895 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 5896 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_BASE 0x3A4C940ull |
|---|
| 5897 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 5898 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 5899 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_BASE 0x3A4C948ull |
|---|
| 5900 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 5901 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 5902 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_BASE 0x3A4C950ull |
|---|
| 5903 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 5904 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 5905 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_BASE 0x3A4C958ull |
|---|
| 5906 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 5907 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 5908 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_BASE 0x3A4C960ull |
|---|
| 5909 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 5910 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 5911 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_BASE 0x3A4C968ull |
|---|
| 5912 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 5913 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 5914 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_BASE 0x3A4C970ull |
|---|
| 5915 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 5916 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 5917 | #define mmDCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_BASE 0x3A4C978ull |
|---|
| 5918 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 5919 | #define DCORE3_TPC5_EML_TPC_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 5920 | #define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_BASE 0x3A4CB00ull |
|---|
| 5921 | #define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 5922 | #define DCORE3_TPC5_EML_TPC_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 5923 | #define mmDCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_BASE 0x3A4CB80ull |
|---|
| 5924 | #define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 5925 | #define DCORE3_TPC5_EML_TPC_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 5926 | #define mmDCORE3_TPC5_EML_TPC_QM_DBG_HBW_BASE 0x3A4CC00ull |
|---|
| 5927 | #define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 5928 | #define DCORE3_TPC5_EML_TPC_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 5929 | #define mmDCORE3_TPC5_EML_TPC_QM_DBG_LBW_BASE 0x3A4CC80ull |
|---|
| 5930 | #define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 5931 | #define DCORE3_TPC5_EML_TPC_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 5932 | #define mmDCORE3_TPC5_EML_TPC_QM_CGM_BASE 0x3A4CD80ull |
|---|
| 5933 | #define DCORE3_TPC5_EML_TPC_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 5934 | #define DCORE3_TPC5_EML_TPC_QM_CGM_SECTION 0x1000 |
|---|
| 5935 | #define mmDCORE3_TPC5_EML_TPC_QM_SPECIAL_BASE 0x3A4CE80ull |
|---|
| 5936 | #define DCORE3_TPC5_EML_TPC_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5937 | #define DCORE3_TPC5_EML_TPC_QM_SPECIAL_SECTION 0x1B2180 |
|---|
| 5938 | #define mmDCORE3_TPC5_EML_CS_BASE 0x3BFF000ull |
|---|
| 5939 | #define DCORE3_TPC5_EML_CS_MAX_OFFSET 0x1000 |
|---|
| 5940 | #define DCORE3_TPC5_EML_CS_SECTION 0x401000 |
|---|
| 5941 | #define mmDCORE0_TPC0_QM_DCCM_BASE 0x4000000ull |
|---|
| 5942 | #define DCORE0_TPC0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 5943 | #define DCORE0_TPC0_QM_DCCM_SECTION 0x8000 |
|---|
| 5944 | #define mmDCORE0_TPC0_QM_ARC_AUX_BASE 0x4008000ull |
|---|
| 5945 | #define DCORE0_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 5946 | #define DCORE0_TPC0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 5947 | #define mmDCORE0_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4008E80ull |
|---|
| 5948 | #define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 5949 | #define DCORE0_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 5950 | #define mmDCORE0_TPC0_QM_BASE 0x400A000ull |
|---|
| 5951 | #define DCORE0_TPC0_QM_MAX_OFFSET 0x1000 |
|---|
| 5952 | #define DCORE0_TPC0_QM_SECTION 0x9000 |
|---|
| 5953 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x400A900ull |
|---|
| 5954 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 5955 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 5956 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x400A908ull |
|---|
| 5957 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 5958 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 5959 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x400A910ull |
|---|
| 5960 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 5961 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 5962 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x400A918ull |
|---|
| 5963 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 5964 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 5965 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x400A920ull |
|---|
| 5966 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 5967 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 5968 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x400A928ull |
|---|
| 5969 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 5970 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 5971 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x400A930ull |
|---|
| 5972 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 5973 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 5974 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x400A938ull |
|---|
| 5975 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 5976 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 5977 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x400A940ull |
|---|
| 5978 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 5979 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 5980 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x400A948ull |
|---|
| 5981 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 5982 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 5983 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x400A950ull |
|---|
| 5984 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 5985 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 5986 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x400A958ull |
|---|
| 5987 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 5988 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 5989 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x400A960ull |
|---|
| 5990 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 5991 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 5992 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x400A968ull |
|---|
| 5993 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 5994 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 5995 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x400A970ull |
|---|
| 5996 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 5997 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 5998 | #define mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x400A978ull |
|---|
| 5999 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 6000 | #define DCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 6001 | #define mmDCORE0_TPC0_QM_AXUSER_SECURED_BASE 0x400AB00ull |
|---|
| 6002 | #define DCORE0_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 6003 | #define DCORE0_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 6004 | #define mmDCORE0_TPC0_QM_AXUSER_NONSECURED_BASE 0x400AB80ull |
|---|
| 6005 | #define DCORE0_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 6006 | #define DCORE0_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 6007 | #define mmDCORE0_TPC0_QM_DBG_HBW_BASE 0x400AC00ull |
|---|
| 6008 | #define DCORE0_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6009 | #define DCORE0_TPC0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 6010 | #define mmDCORE0_TPC0_QM_DBG_LBW_BASE 0x400AC80ull |
|---|
| 6011 | #define DCORE0_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6012 | #define DCORE0_TPC0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 6013 | #define mmDCORE0_TPC0_QM_CGM_BASE 0x400AD80ull |
|---|
| 6014 | #define DCORE0_TPC0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 6015 | #define DCORE0_TPC0_QM_CGM_SECTION 0x1000 |
|---|
| 6016 | #define mmDCORE0_TPC0_QM_SPECIAL_BASE 0x400AE80ull |
|---|
| 6017 | #define DCORE0_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6018 | #define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6019 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x400B000ull |
|---|
| 6020 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6021 | #define DCORE0_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6022 | #define mmDCORE0_TPC0_CFG_BASE 0x400B000ull |
|---|
| 6023 | #define DCORE0_TPC0_CFG_MAX_OFFSET 0x1000 |
|---|
| 6024 | #define DCORE0_TPC0_CFG_SECTION 0x5000 |
|---|
| 6025 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x400B050ull |
|---|
| 6026 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6027 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 6028 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x400B0A0ull |
|---|
| 6029 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6030 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 6031 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x400B0F0ull |
|---|
| 6032 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6033 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 6034 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x400B140ull |
|---|
| 6035 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6036 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 6037 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x400B190ull |
|---|
| 6038 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6039 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 6040 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x400B1E0ull |
|---|
| 6041 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6042 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 6043 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x400B230ull |
|---|
| 6044 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6045 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 6046 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x400B280ull |
|---|
| 6047 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6048 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 6049 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x400B2D0ull |
|---|
| 6050 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6051 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 6052 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x400B320ull |
|---|
| 6053 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6054 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 6055 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x400B370ull |
|---|
| 6056 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6057 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 6058 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x400B3C0ull |
|---|
| 6059 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6060 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 6061 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x400B410ull |
|---|
| 6062 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6063 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 6064 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x400B460ull |
|---|
| 6065 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6066 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 6067 | #define mmDCORE0_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x400B4B0ull |
|---|
| 6068 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6069 | #define DCORE0_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 6070 | #define mmDCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x400B500ull |
|---|
| 6071 | #define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6072 | #define DCORE0_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6073 | #define mmDCORE0_TPC0_CFG_KERNEL_BASE 0x400B508ull |
|---|
| 6074 | #define DCORE0_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 6075 | #define DCORE0_TPC0_CFG_KERNEL_SECTION 0xD400 |
|---|
| 6076 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE 0x400B5DCull |
|---|
| 6077 | #define DCORE0_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6078 | #define DCORE0_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 6079 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE 0x400B62Cull |
|---|
| 6080 | #define DCORE0_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6081 | #define DCORE0_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 6082 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_2_BASE 0x400B67Cull |
|---|
| 6083 | #define DCORE0_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6084 | #define DCORE0_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 6085 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_3_BASE 0x400B6CCull |
|---|
| 6086 | #define DCORE0_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6087 | #define DCORE0_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 6088 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_4_BASE 0x400B71Cull |
|---|
| 6089 | #define DCORE0_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6090 | #define DCORE0_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 6091 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_5_BASE 0x400B76Cull |
|---|
| 6092 | #define DCORE0_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6093 | #define DCORE0_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 6094 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_6_BASE 0x400B7BCull |
|---|
| 6095 | #define DCORE0_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6096 | #define DCORE0_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 6097 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_7_BASE 0x400B80Cull |
|---|
| 6098 | #define DCORE0_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6099 | #define DCORE0_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 6100 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_8_BASE 0x400B85Cull |
|---|
| 6101 | #define DCORE0_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6102 | #define DCORE0_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 6103 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_9_BASE 0x400B8ACull |
|---|
| 6104 | #define DCORE0_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6105 | #define DCORE0_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 6106 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_10_BASE 0x400B8FCull |
|---|
| 6107 | #define DCORE0_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6108 | #define DCORE0_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 6109 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_11_BASE 0x400B94Cull |
|---|
| 6110 | #define DCORE0_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6111 | #define DCORE0_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 6112 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_12_BASE 0x400B99Cull |
|---|
| 6113 | #define DCORE0_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6114 | #define DCORE0_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 6115 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_13_BASE 0x400B9ECull |
|---|
| 6116 | #define DCORE0_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6117 | #define DCORE0_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 6118 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_14_BASE 0x400BA3Cull |
|---|
| 6119 | #define DCORE0_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6120 | #define DCORE0_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 6121 | #define mmDCORE0_TPC0_CFG_QM_TENSOR_15_BASE 0x400BA8Cull |
|---|
| 6122 | #define DCORE0_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6123 | #define DCORE0_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 6124 | #define mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x400BADCull |
|---|
| 6125 | #define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6126 | #define DCORE0_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6127 | #define mmDCORE0_TPC0_CFG_QM_BASE 0x400BAE4ull |
|---|
| 6128 | #define DCORE0_TPC0_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 6129 | #define DCORE0_TPC0_CFG_QM_SECTION 0x31C0 |
|---|
| 6130 | #define mmDCORE0_TPC0_CFG_AXUSER_BASE 0x400BE00ull |
|---|
| 6131 | #define DCORE0_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6132 | #define DCORE0_TPC0_CFG_AXUSER_SECTION 0x8000 |
|---|
| 6133 | #define mmDCORE0_TPC0_CFG_SPECIAL_BASE 0x400BE80ull |
|---|
| 6134 | #define DCORE0_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6135 | #define DCORE0_TPC0_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 6136 | #define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x400C000ull |
|---|
| 6137 | #define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6138 | #define DCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 6139 | #define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x400C200ull |
|---|
| 6140 | #define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6141 | #define DCORE0_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 6142 | #define mmDCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x400C400ull |
|---|
| 6143 | #define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6144 | #define DCORE0_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 6145 | #define mmDCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x400C600ull |
|---|
| 6146 | #define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6147 | #define DCORE0_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 6148 | #define mmDCORE0_TPC0_MSTR_IF_E2E_CRDT_BASE 0x400C800ull |
|---|
| 6149 | #define DCORE0_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 6150 | #define DCORE0_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 6151 | #define mmDCORE0_TPC0_MSTR_IF_AXUSER_BASE 0x400CA80ull |
|---|
| 6152 | #define DCORE0_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6153 | #define DCORE0_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 6154 | #define mmDCORE0_TPC0_MSTR_IF_DBG_HBW_BASE 0x400CB00ull |
|---|
| 6155 | #define DCORE0_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6156 | #define DCORE0_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 6157 | #define mmDCORE0_TPC0_MSTR_IF_DBG_LBW_BASE 0x400CB80ull |
|---|
| 6158 | #define DCORE0_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6159 | #define DCORE0_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 6160 | #define mmDCORE0_TPC0_MSTR_IF_CORE_HBW_BASE 0x400CC00ull |
|---|
| 6161 | #define DCORE0_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 6162 | #define DCORE0_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 6163 | #define mmDCORE0_TPC0_MSTR_IF_CORE_LBW_BASE 0x400CD80ull |
|---|
| 6164 | #define DCORE0_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 6165 | #define DCORE0_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 6166 | #define mmDCORE0_TPC0_MSTR_IF_SPECIAL_BASE 0x400CE80ull |
|---|
| 6167 | #define DCORE0_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6168 | #define DCORE0_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 6169 | #define mmDCORE0_TPC1_QM_DCCM_BASE 0x4010000ull |
|---|
| 6170 | #define DCORE0_TPC1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 6171 | #define DCORE0_TPC1_QM_DCCM_SECTION 0x8000 |
|---|
| 6172 | #define mmDCORE0_TPC1_QM_ARC_AUX_BASE 0x4018000ull |
|---|
| 6173 | #define DCORE0_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 6174 | #define DCORE0_TPC1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 6175 | #define mmDCORE0_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4018E80ull |
|---|
| 6176 | #define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6177 | #define DCORE0_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 6178 | #define mmDCORE0_TPC1_QM_BASE 0x401A000ull |
|---|
| 6179 | #define DCORE0_TPC1_QM_MAX_OFFSET 0x1000 |
|---|
| 6180 | #define DCORE0_TPC1_QM_SECTION 0x9000 |
|---|
| 6181 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x401A900ull |
|---|
| 6182 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 6183 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 6184 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x401A908ull |
|---|
| 6185 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 6186 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 6187 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x401A910ull |
|---|
| 6188 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 6189 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 6190 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x401A918ull |
|---|
| 6191 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 6192 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 6193 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x401A920ull |
|---|
| 6194 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 6195 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 6196 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x401A928ull |
|---|
| 6197 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 6198 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 6199 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x401A930ull |
|---|
| 6200 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 6201 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 6202 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x401A938ull |
|---|
| 6203 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 6204 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 6205 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x401A940ull |
|---|
| 6206 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 6207 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 6208 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x401A948ull |
|---|
| 6209 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 6210 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 6211 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x401A950ull |
|---|
| 6212 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 6213 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 6214 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x401A958ull |
|---|
| 6215 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 6216 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 6217 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x401A960ull |
|---|
| 6218 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 6219 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 6220 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x401A968ull |
|---|
| 6221 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 6222 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 6223 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x401A970ull |
|---|
| 6224 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 6225 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 6226 | #define mmDCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x401A978ull |
|---|
| 6227 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 6228 | #define DCORE0_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 6229 | #define mmDCORE0_TPC1_QM_AXUSER_SECURED_BASE 0x401AB00ull |
|---|
| 6230 | #define DCORE0_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 6231 | #define DCORE0_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 6232 | #define mmDCORE0_TPC1_QM_AXUSER_NONSECURED_BASE 0x401AB80ull |
|---|
| 6233 | #define DCORE0_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 6234 | #define DCORE0_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 6235 | #define mmDCORE0_TPC1_QM_DBG_HBW_BASE 0x401AC00ull |
|---|
| 6236 | #define DCORE0_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6237 | #define DCORE0_TPC1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 6238 | #define mmDCORE0_TPC1_QM_DBG_LBW_BASE 0x401AC80ull |
|---|
| 6239 | #define DCORE0_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6240 | #define DCORE0_TPC1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 6241 | #define mmDCORE0_TPC1_QM_CGM_BASE 0x401AD80ull |
|---|
| 6242 | #define DCORE0_TPC1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 6243 | #define DCORE0_TPC1_QM_CGM_SECTION 0x1000 |
|---|
| 6244 | #define mmDCORE0_TPC1_QM_SPECIAL_BASE 0x401AE80ull |
|---|
| 6245 | #define DCORE0_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6246 | #define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6247 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x401B000ull |
|---|
| 6248 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6249 | #define DCORE0_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6250 | #define mmDCORE0_TPC1_CFG_BASE 0x401B000ull |
|---|
| 6251 | #define DCORE0_TPC1_CFG_MAX_OFFSET 0x1000 |
|---|
| 6252 | #define DCORE0_TPC1_CFG_SECTION 0x5000 |
|---|
| 6253 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x401B050ull |
|---|
| 6254 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6255 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 6256 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x401B0A0ull |
|---|
| 6257 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6258 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 6259 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x401B0F0ull |
|---|
| 6260 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6261 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 6262 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x401B140ull |
|---|
| 6263 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6264 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 6265 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x401B190ull |
|---|
| 6266 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6267 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 6268 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x401B1E0ull |
|---|
| 6269 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6270 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 6271 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x401B230ull |
|---|
| 6272 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6273 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 6274 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x401B280ull |
|---|
| 6275 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6276 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 6277 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x401B2D0ull |
|---|
| 6278 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6279 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 6280 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x401B320ull |
|---|
| 6281 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6282 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 6283 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x401B370ull |
|---|
| 6284 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6285 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 6286 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x401B3C0ull |
|---|
| 6287 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6288 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 6289 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x401B410ull |
|---|
| 6290 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6291 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 6292 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x401B460ull |
|---|
| 6293 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6294 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 6295 | #define mmDCORE0_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x401B4B0ull |
|---|
| 6296 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6297 | #define DCORE0_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 6298 | #define mmDCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x401B500ull |
|---|
| 6299 | #define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6300 | #define DCORE0_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6301 | #define mmDCORE0_TPC1_CFG_KERNEL_BASE 0x401B508ull |
|---|
| 6302 | #define DCORE0_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 6303 | #define DCORE0_TPC1_CFG_KERNEL_SECTION 0xD400 |
|---|
| 6304 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_0_BASE 0x401B5DCull |
|---|
| 6305 | #define DCORE0_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6306 | #define DCORE0_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 6307 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_1_BASE 0x401B62Cull |
|---|
| 6308 | #define DCORE0_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6309 | #define DCORE0_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 6310 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_2_BASE 0x401B67Cull |
|---|
| 6311 | #define DCORE0_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6312 | #define DCORE0_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 6313 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_3_BASE 0x401B6CCull |
|---|
| 6314 | #define DCORE0_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6315 | #define DCORE0_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 6316 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_4_BASE 0x401B71Cull |
|---|
| 6317 | #define DCORE0_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6318 | #define DCORE0_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 6319 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_5_BASE 0x401B76Cull |
|---|
| 6320 | #define DCORE0_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6321 | #define DCORE0_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 6322 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_6_BASE 0x401B7BCull |
|---|
| 6323 | #define DCORE0_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6324 | #define DCORE0_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 6325 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_7_BASE 0x401B80Cull |
|---|
| 6326 | #define DCORE0_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6327 | #define DCORE0_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 6328 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_8_BASE 0x401B85Cull |
|---|
| 6329 | #define DCORE0_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6330 | #define DCORE0_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 6331 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_9_BASE 0x401B8ACull |
|---|
| 6332 | #define DCORE0_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6333 | #define DCORE0_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 6334 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_10_BASE 0x401B8FCull |
|---|
| 6335 | #define DCORE0_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6336 | #define DCORE0_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 6337 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_11_BASE 0x401B94Cull |
|---|
| 6338 | #define DCORE0_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6339 | #define DCORE0_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 6340 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_12_BASE 0x401B99Cull |
|---|
| 6341 | #define DCORE0_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6342 | #define DCORE0_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 6343 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_13_BASE 0x401B9ECull |
|---|
| 6344 | #define DCORE0_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6345 | #define DCORE0_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 6346 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_14_BASE 0x401BA3Cull |
|---|
| 6347 | #define DCORE0_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6348 | #define DCORE0_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 6349 | #define mmDCORE0_TPC1_CFG_QM_TENSOR_15_BASE 0x401BA8Cull |
|---|
| 6350 | #define DCORE0_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6351 | #define DCORE0_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 6352 | #define mmDCORE0_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x401BADCull |
|---|
| 6353 | #define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6354 | #define DCORE0_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6355 | #define mmDCORE0_TPC1_CFG_QM_BASE 0x401BAE4ull |
|---|
| 6356 | #define DCORE0_TPC1_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 6357 | #define DCORE0_TPC1_CFG_QM_SECTION 0x31C0 |
|---|
| 6358 | #define mmDCORE0_TPC1_CFG_AXUSER_BASE 0x401BE00ull |
|---|
| 6359 | #define DCORE0_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6360 | #define DCORE0_TPC1_CFG_AXUSER_SECTION 0x8000 |
|---|
| 6361 | #define mmDCORE0_TPC1_CFG_SPECIAL_BASE 0x401BE80ull |
|---|
| 6362 | #define DCORE0_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6363 | #define DCORE0_TPC1_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 6364 | #define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x401C000ull |
|---|
| 6365 | #define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6366 | #define DCORE0_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 6367 | #define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x401C200ull |
|---|
| 6368 | #define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6369 | #define DCORE0_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 6370 | #define mmDCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x401C400ull |
|---|
| 6371 | #define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6372 | #define DCORE0_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 6373 | #define mmDCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x401C600ull |
|---|
| 6374 | #define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6375 | #define DCORE0_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 6376 | #define mmDCORE0_TPC1_MSTR_IF_E2E_CRDT_BASE 0x401C800ull |
|---|
| 6377 | #define DCORE0_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 6378 | #define DCORE0_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 6379 | #define mmDCORE0_TPC1_MSTR_IF_AXUSER_BASE 0x401CA80ull |
|---|
| 6380 | #define DCORE0_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6381 | #define DCORE0_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 6382 | #define mmDCORE0_TPC1_MSTR_IF_DBG_HBW_BASE 0x401CB00ull |
|---|
| 6383 | #define DCORE0_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6384 | #define DCORE0_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 6385 | #define mmDCORE0_TPC1_MSTR_IF_DBG_LBW_BASE 0x401CB80ull |
|---|
| 6386 | #define DCORE0_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6387 | #define DCORE0_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 6388 | #define mmDCORE0_TPC1_MSTR_IF_CORE_HBW_BASE 0x401CC00ull |
|---|
| 6389 | #define DCORE0_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 6390 | #define DCORE0_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 6391 | #define mmDCORE0_TPC1_MSTR_IF_CORE_LBW_BASE 0x401CD80ull |
|---|
| 6392 | #define DCORE0_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 6393 | #define DCORE0_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 6394 | #define mmDCORE0_TPC1_MSTR_IF_SPECIAL_BASE 0x401CE80ull |
|---|
| 6395 | #define DCORE0_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6396 | #define DCORE0_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 6397 | #define mmDCORE0_TPC2_QM_DCCM_BASE 0x4020000ull |
|---|
| 6398 | #define DCORE0_TPC2_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 6399 | #define DCORE0_TPC2_QM_DCCM_SECTION 0x8000 |
|---|
| 6400 | #define mmDCORE0_TPC2_QM_ARC_AUX_BASE 0x4028000ull |
|---|
| 6401 | #define DCORE0_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 6402 | #define DCORE0_TPC2_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 6403 | #define mmDCORE0_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4028E80ull |
|---|
| 6404 | #define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6405 | #define DCORE0_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 6406 | #define mmDCORE0_TPC2_QM_BASE 0x402A000ull |
|---|
| 6407 | #define DCORE0_TPC2_QM_MAX_OFFSET 0x1000 |
|---|
| 6408 | #define DCORE0_TPC2_QM_SECTION 0x9000 |
|---|
| 6409 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x402A900ull |
|---|
| 6410 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 6411 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 6412 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x402A908ull |
|---|
| 6413 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 6414 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 6415 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x402A910ull |
|---|
| 6416 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 6417 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 6418 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x402A918ull |
|---|
| 6419 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 6420 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 6421 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x402A920ull |
|---|
| 6422 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 6423 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 6424 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x402A928ull |
|---|
| 6425 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 6426 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 6427 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x402A930ull |
|---|
| 6428 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 6429 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 6430 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x402A938ull |
|---|
| 6431 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 6432 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 6433 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x402A940ull |
|---|
| 6434 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 6435 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 6436 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x402A948ull |
|---|
| 6437 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 6438 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 6439 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x402A950ull |
|---|
| 6440 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 6441 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 6442 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x402A958ull |
|---|
| 6443 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 6444 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 6445 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x402A960ull |
|---|
| 6446 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 6447 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 6448 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x402A968ull |
|---|
| 6449 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 6450 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 6451 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x402A970ull |
|---|
| 6452 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 6453 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 6454 | #define mmDCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x402A978ull |
|---|
| 6455 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 6456 | #define DCORE0_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 6457 | #define mmDCORE0_TPC2_QM_AXUSER_SECURED_BASE 0x402AB00ull |
|---|
| 6458 | #define DCORE0_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 6459 | #define DCORE0_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 6460 | #define mmDCORE0_TPC2_QM_AXUSER_NONSECURED_BASE 0x402AB80ull |
|---|
| 6461 | #define DCORE0_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 6462 | #define DCORE0_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 6463 | #define mmDCORE0_TPC2_QM_DBG_HBW_BASE 0x402AC00ull |
|---|
| 6464 | #define DCORE0_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6465 | #define DCORE0_TPC2_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 6466 | #define mmDCORE0_TPC2_QM_DBG_LBW_BASE 0x402AC80ull |
|---|
| 6467 | #define DCORE0_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6468 | #define DCORE0_TPC2_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 6469 | #define mmDCORE0_TPC2_QM_CGM_BASE 0x402AD80ull |
|---|
| 6470 | #define DCORE0_TPC2_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 6471 | #define DCORE0_TPC2_QM_CGM_SECTION 0x1000 |
|---|
| 6472 | #define mmDCORE0_TPC2_QM_SPECIAL_BASE 0x402AE80ull |
|---|
| 6473 | #define DCORE0_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6474 | #define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6475 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x402B000ull |
|---|
| 6476 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6477 | #define DCORE0_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6478 | #define mmDCORE0_TPC2_CFG_BASE 0x402B000ull |
|---|
| 6479 | #define DCORE0_TPC2_CFG_MAX_OFFSET 0x1000 |
|---|
| 6480 | #define DCORE0_TPC2_CFG_SECTION 0x5000 |
|---|
| 6481 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x402B050ull |
|---|
| 6482 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6483 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 6484 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x402B0A0ull |
|---|
| 6485 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6486 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 6487 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x402B0F0ull |
|---|
| 6488 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6489 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 6490 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x402B140ull |
|---|
| 6491 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6492 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 6493 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x402B190ull |
|---|
| 6494 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6495 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 6496 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x402B1E0ull |
|---|
| 6497 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6498 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 6499 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x402B230ull |
|---|
| 6500 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6501 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 6502 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x402B280ull |
|---|
| 6503 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6504 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 6505 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x402B2D0ull |
|---|
| 6506 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6507 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 6508 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x402B320ull |
|---|
| 6509 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6510 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 6511 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x402B370ull |
|---|
| 6512 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6513 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 6514 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x402B3C0ull |
|---|
| 6515 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6516 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 6517 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x402B410ull |
|---|
| 6518 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6519 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 6520 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x402B460ull |
|---|
| 6521 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6522 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 6523 | #define mmDCORE0_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x402B4B0ull |
|---|
| 6524 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6525 | #define DCORE0_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 6526 | #define mmDCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x402B500ull |
|---|
| 6527 | #define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6528 | #define DCORE0_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6529 | #define mmDCORE0_TPC2_CFG_KERNEL_BASE 0x402B508ull |
|---|
| 6530 | #define DCORE0_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 6531 | #define DCORE0_TPC2_CFG_KERNEL_SECTION 0xD400 |
|---|
| 6532 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_0_BASE 0x402B5DCull |
|---|
| 6533 | #define DCORE0_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6534 | #define DCORE0_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 6535 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_1_BASE 0x402B62Cull |
|---|
| 6536 | #define DCORE0_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6537 | #define DCORE0_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 6538 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_2_BASE 0x402B67Cull |
|---|
| 6539 | #define DCORE0_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6540 | #define DCORE0_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 6541 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_3_BASE 0x402B6CCull |
|---|
| 6542 | #define DCORE0_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6543 | #define DCORE0_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 6544 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_4_BASE 0x402B71Cull |
|---|
| 6545 | #define DCORE0_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6546 | #define DCORE0_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 6547 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_5_BASE 0x402B76Cull |
|---|
| 6548 | #define DCORE0_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6549 | #define DCORE0_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 6550 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_6_BASE 0x402B7BCull |
|---|
| 6551 | #define DCORE0_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6552 | #define DCORE0_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 6553 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_7_BASE 0x402B80Cull |
|---|
| 6554 | #define DCORE0_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6555 | #define DCORE0_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 6556 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_8_BASE 0x402B85Cull |
|---|
| 6557 | #define DCORE0_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6558 | #define DCORE0_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 6559 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_9_BASE 0x402B8ACull |
|---|
| 6560 | #define DCORE0_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6561 | #define DCORE0_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 6562 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_10_BASE 0x402B8FCull |
|---|
| 6563 | #define DCORE0_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6564 | #define DCORE0_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 6565 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_11_BASE 0x402B94Cull |
|---|
| 6566 | #define DCORE0_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6567 | #define DCORE0_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 6568 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_12_BASE 0x402B99Cull |
|---|
| 6569 | #define DCORE0_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6570 | #define DCORE0_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 6571 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_13_BASE 0x402B9ECull |
|---|
| 6572 | #define DCORE0_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6573 | #define DCORE0_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 6574 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_14_BASE 0x402BA3Cull |
|---|
| 6575 | #define DCORE0_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6576 | #define DCORE0_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 6577 | #define mmDCORE0_TPC2_CFG_QM_TENSOR_15_BASE 0x402BA8Cull |
|---|
| 6578 | #define DCORE0_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6579 | #define DCORE0_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 6580 | #define mmDCORE0_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x402BADCull |
|---|
| 6581 | #define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6582 | #define DCORE0_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6583 | #define mmDCORE0_TPC2_CFG_QM_BASE 0x402BAE4ull |
|---|
| 6584 | #define DCORE0_TPC2_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 6585 | #define DCORE0_TPC2_CFG_QM_SECTION 0x31C0 |
|---|
| 6586 | #define mmDCORE0_TPC2_CFG_AXUSER_BASE 0x402BE00ull |
|---|
| 6587 | #define DCORE0_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6588 | #define DCORE0_TPC2_CFG_AXUSER_SECTION 0x8000 |
|---|
| 6589 | #define mmDCORE0_TPC2_CFG_SPECIAL_BASE 0x402BE80ull |
|---|
| 6590 | #define DCORE0_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6591 | #define DCORE0_TPC2_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 6592 | #define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x402C000ull |
|---|
| 6593 | #define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6594 | #define DCORE0_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 6595 | #define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x402C200ull |
|---|
| 6596 | #define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6597 | #define DCORE0_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 6598 | #define mmDCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x402C400ull |
|---|
| 6599 | #define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6600 | #define DCORE0_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 6601 | #define mmDCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x402C600ull |
|---|
| 6602 | #define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6603 | #define DCORE0_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 6604 | #define mmDCORE0_TPC2_MSTR_IF_E2E_CRDT_BASE 0x402C800ull |
|---|
| 6605 | #define DCORE0_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 6606 | #define DCORE0_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 6607 | #define mmDCORE0_TPC2_MSTR_IF_AXUSER_BASE 0x402CA80ull |
|---|
| 6608 | #define DCORE0_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6609 | #define DCORE0_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 6610 | #define mmDCORE0_TPC2_MSTR_IF_DBG_HBW_BASE 0x402CB00ull |
|---|
| 6611 | #define DCORE0_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6612 | #define DCORE0_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 6613 | #define mmDCORE0_TPC2_MSTR_IF_DBG_LBW_BASE 0x402CB80ull |
|---|
| 6614 | #define DCORE0_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6615 | #define DCORE0_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 6616 | #define mmDCORE0_TPC2_MSTR_IF_CORE_HBW_BASE 0x402CC00ull |
|---|
| 6617 | #define DCORE0_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 6618 | #define DCORE0_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 6619 | #define mmDCORE0_TPC2_MSTR_IF_CORE_LBW_BASE 0x402CD80ull |
|---|
| 6620 | #define DCORE0_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 6621 | #define DCORE0_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 6622 | #define mmDCORE0_TPC2_MSTR_IF_SPECIAL_BASE 0x402CE80ull |
|---|
| 6623 | #define DCORE0_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6624 | #define DCORE0_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 6625 | #define mmDCORE0_TPC3_QM_DCCM_BASE 0x4030000ull |
|---|
| 6626 | #define DCORE0_TPC3_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 6627 | #define DCORE0_TPC3_QM_DCCM_SECTION 0x8000 |
|---|
| 6628 | #define mmDCORE0_TPC3_QM_ARC_AUX_BASE 0x4038000ull |
|---|
| 6629 | #define DCORE0_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 6630 | #define DCORE0_TPC3_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 6631 | #define mmDCORE0_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4038E80ull |
|---|
| 6632 | #define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6633 | #define DCORE0_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 6634 | #define mmDCORE0_TPC3_QM_BASE 0x403A000ull |
|---|
| 6635 | #define DCORE0_TPC3_QM_MAX_OFFSET 0x1000 |
|---|
| 6636 | #define DCORE0_TPC3_QM_SECTION 0x9000 |
|---|
| 6637 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x403A900ull |
|---|
| 6638 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 6639 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 6640 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x403A908ull |
|---|
| 6641 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 6642 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 6643 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x403A910ull |
|---|
| 6644 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 6645 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 6646 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x403A918ull |
|---|
| 6647 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 6648 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 6649 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x403A920ull |
|---|
| 6650 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 6651 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 6652 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x403A928ull |
|---|
| 6653 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 6654 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 6655 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x403A930ull |
|---|
| 6656 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 6657 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 6658 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x403A938ull |
|---|
| 6659 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 6660 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 6661 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x403A940ull |
|---|
| 6662 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 6663 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 6664 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x403A948ull |
|---|
| 6665 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 6666 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 6667 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x403A950ull |
|---|
| 6668 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 6669 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 6670 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x403A958ull |
|---|
| 6671 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 6672 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 6673 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x403A960ull |
|---|
| 6674 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 6675 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 6676 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x403A968ull |
|---|
| 6677 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 6678 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 6679 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x403A970ull |
|---|
| 6680 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 6681 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 6682 | #define mmDCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x403A978ull |
|---|
| 6683 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 6684 | #define DCORE0_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 6685 | #define mmDCORE0_TPC3_QM_AXUSER_SECURED_BASE 0x403AB00ull |
|---|
| 6686 | #define DCORE0_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 6687 | #define DCORE0_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 6688 | #define mmDCORE0_TPC3_QM_AXUSER_NONSECURED_BASE 0x403AB80ull |
|---|
| 6689 | #define DCORE0_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 6690 | #define DCORE0_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 6691 | #define mmDCORE0_TPC3_QM_DBG_HBW_BASE 0x403AC00ull |
|---|
| 6692 | #define DCORE0_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6693 | #define DCORE0_TPC3_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 6694 | #define mmDCORE0_TPC3_QM_DBG_LBW_BASE 0x403AC80ull |
|---|
| 6695 | #define DCORE0_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6696 | #define DCORE0_TPC3_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 6697 | #define mmDCORE0_TPC3_QM_CGM_BASE 0x403AD80ull |
|---|
| 6698 | #define DCORE0_TPC3_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 6699 | #define DCORE0_TPC3_QM_CGM_SECTION 0x1000 |
|---|
| 6700 | #define mmDCORE0_TPC3_QM_SPECIAL_BASE 0x403AE80ull |
|---|
| 6701 | #define DCORE0_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6702 | #define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6703 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x403B000ull |
|---|
| 6704 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6705 | #define DCORE0_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6706 | #define mmDCORE0_TPC3_CFG_BASE 0x403B000ull |
|---|
| 6707 | #define DCORE0_TPC3_CFG_MAX_OFFSET 0x1000 |
|---|
| 6708 | #define DCORE0_TPC3_CFG_SECTION 0x5000 |
|---|
| 6709 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x403B050ull |
|---|
| 6710 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6711 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 6712 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x403B0A0ull |
|---|
| 6713 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6714 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 6715 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x403B0F0ull |
|---|
| 6716 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6717 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 6718 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x403B140ull |
|---|
| 6719 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6720 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 6721 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x403B190ull |
|---|
| 6722 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6723 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 6724 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x403B1E0ull |
|---|
| 6725 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6726 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 6727 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x403B230ull |
|---|
| 6728 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6729 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 6730 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x403B280ull |
|---|
| 6731 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6732 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 6733 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x403B2D0ull |
|---|
| 6734 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6735 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 6736 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x403B320ull |
|---|
| 6737 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6738 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 6739 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x403B370ull |
|---|
| 6740 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6741 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 6742 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x403B3C0ull |
|---|
| 6743 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6744 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 6745 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x403B410ull |
|---|
| 6746 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6747 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 6748 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x403B460ull |
|---|
| 6749 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6750 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 6751 | #define mmDCORE0_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x403B4B0ull |
|---|
| 6752 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6753 | #define DCORE0_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 6754 | #define mmDCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x403B500ull |
|---|
| 6755 | #define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6756 | #define DCORE0_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6757 | #define mmDCORE0_TPC3_CFG_KERNEL_BASE 0x403B508ull |
|---|
| 6758 | #define DCORE0_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 6759 | #define DCORE0_TPC3_CFG_KERNEL_SECTION 0xD400 |
|---|
| 6760 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_0_BASE 0x403B5DCull |
|---|
| 6761 | #define DCORE0_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6762 | #define DCORE0_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 6763 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_1_BASE 0x403B62Cull |
|---|
| 6764 | #define DCORE0_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6765 | #define DCORE0_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 6766 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_2_BASE 0x403B67Cull |
|---|
| 6767 | #define DCORE0_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6768 | #define DCORE0_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 6769 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_3_BASE 0x403B6CCull |
|---|
| 6770 | #define DCORE0_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6771 | #define DCORE0_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 6772 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_4_BASE 0x403B71Cull |
|---|
| 6773 | #define DCORE0_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6774 | #define DCORE0_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 6775 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_5_BASE 0x403B76Cull |
|---|
| 6776 | #define DCORE0_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6777 | #define DCORE0_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 6778 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_6_BASE 0x403B7BCull |
|---|
| 6779 | #define DCORE0_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6780 | #define DCORE0_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 6781 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_7_BASE 0x403B80Cull |
|---|
| 6782 | #define DCORE0_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6783 | #define DCORE0_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 6784 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_8_BASE 0x403B85Cull |
|---|
| 6785 | #define DCORE0_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6786 | #define DCORE0_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 6787 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_9_BASE 0x403B8ACull |
|---|
| 6788 | #define DCORE0_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6789 | #define DCORE0_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 6790 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_10_BASE 0x403B8FCull |
|---|
| 6791 | #define DCORE0_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6792 | #define DCORE0_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 6793 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_11_BASE 0x403B94Cull |
|---|
| 6794 | #define DCORE0_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6795 | #define DCORE0_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 6796 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_12_BASE 0x403B99Cull |
|---|
| 6797 | #define DCORE0_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6798 | #define DCORE0_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 6799 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_13_BASE 0x403B9ECull |
|---|
| 6800 | #define DCORE0_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6801 | #define DCORE0_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 6802 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_14_BASE 0x403BA3Cull |
|---|
| 6803 | #define DCORE0_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6804 | #define DCORE0_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 6805 | #define mmDCORE0_TPC3_CFG_QM_TENSOR_15_BASE 0x403BA8Cull |
|---|
| 6806 | #define DCORE0_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6807 | #define DCORE0_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 6808 | #define mmDCORE0_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x403BADCull |
|---|
| 6809 | #define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6810 | #define DCORE0_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6811 | #define mmDCORE0_TPC3_CFG_QM_BASE 0x403BAE4ull |
|---|
| 6812 | #define DCORE0_TPC3_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 6813 | #define DCORE0_TPC3_CFG_QM_SECTION 0x31C0 |
|---|
| 6814 | #define mmDCORE0_TPC3_CFG_AXUSER_BASE 0x403BE00ull |
|---|
| 6815 | #define DCORE0_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6816 | #define DCORE0_TPC3_CFG_AXUSER_SECTION 0x8000 |
|---|
| 6817 | #define mmDCORE0_TPC3_CFG_SPECIAL_BASE 0x403BE80ull |
|---|
| 6818 | #define DCORE0_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6819 | #define DCORE0_TPC3_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 6820 | #define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x403C000ull |
|---|
| 6821 | #define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6822 | #define DCORE0_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 6823 | #define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x403C200ull |
|---|
| 6824 | #define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 6825 | #define DCORE0_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 6826 | #define mmDCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x403C400ull |
|---|
| 6827 | #define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6828 | #define DCORE0_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 6829 | #define mmDCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x403C600ull |
|---|
| 6830 | #define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 6831 | #define DCORE0_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 6832 | #define mmDCORE0_TPC3_MSTR_IF_E2E_CRDT_BASE 0x403C800ull |
|---|
| 6833 | #define DCORE0_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 6834 | #define DCORE0_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 6835 | #define mmDCORE0_TPC3_MSTR_IF_AXUSER_BASE 0x403CA80ull |
|---|
| 6836 | #define DCORE0_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 6837 | #define DCORE0_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 6838 | #define mmDCORE0_TPC3_MSTR_IF_DBG_HBW_BASE 0x403CB00ull |
|---|
| 6839 | #define DCORE0_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6840 | #define DCORE0_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 6841 | #define mmDCORE0_TPC3_MSTR_IF_DBG_LBW_BASE 0x403CB80ull |
|---|
| 6842 | #define DCORE0_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6843 | #define DCORE0_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 6844 | #define mmDCORE0_TPC3_MSTR_IF_CORE_HBW_BASE 0x403CC00ull |
|---|
| 6845 | #define DCORE0_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 6846 | #define DCORE0_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 6847 | #define mmDCORE0_TPC3_MSTR_IF_CORE_LBW_BASE 0x403CD80ull |
|---|
| 6848 | #define DCORE0_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 6849 | #define DCORE0_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 6850 | #define mmDCORE0_TPC3_MSTR_IF_SPECIAL_BASE 0x403CE80ull |
|---|
| 6851 | #define DCORE0_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6852 | #define DCORE0_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 6853 | #define mmDCORE0_TPC4_QM_DCCM_BASE 0x4040000ull |
|---|
| 6854 | #define DCORE0_TPC4_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 6855 | #define DCORE0_TPC4_QM_DCCM_SECTION 0x8000 |
|---|
| 6856 | #define mmDCORE0_TPC4_QM_ARC_AUX_BASE 0x4048000ull |
|---|
| 6857 | #define DCORE0_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 6858 | #define DCORE0_TPC4_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 6859 | #define mmDCORE0_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4048E80ull |
|---|
| 6860 | #define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6861 | #define DCORE0_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 6862 | #define mmDCORE0_TPC4_QM_BASE 0x404A000ull |
|---|
| 6863 | #define DCORE0_TPC4_QM_MAX_OFFSET 0x1000 |
|---|
| 6864 | #define DCORE0_TPC4_QM_SECTION 0x9000 |
|---|
| 6865 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x404A900ull |
|---|
| 6866 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 6867 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 6868 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x404A908ull |
|---|
| 6869 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 6870 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 6871 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x404A910ull |
|---|
| 6872 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 6873 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 6874 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x404A918ull |
|---|
| 6875 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 6876 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 6877 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x404A920ull |
|---|
| 6878 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 6879 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 6880 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x404A928ull |
|---|
| 6881 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 6882 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 6883 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x404A930ull |
|---|
| 6884 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 6885 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 6886 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x404A938ull |
|---|
| 6887 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 6888 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 6889 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x404A940ull |
|---|
| 6890 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 6891 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 6892 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x404A948ull |
|---|
| 6893 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 6894 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 6895 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x404A950ull |
|---|
| 6896 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 6897 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 6898 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x404A958ull |
|---|
| 6899 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 6900 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 6901 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x404A960ull |
|---|
| 6902 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 6903 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 6904 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x404A968ull |
|---|
| 6905 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 6906 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 6907 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x404A970ull |
|---|
| 6908 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 6909 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 6910 | #define mmDCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x404A978ull |
|---|
| 6911 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 6912 | #define DCORE0_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 6913 | #define mmDCORE0_TPC4_QM_AXUSER_SECURED_BASE 0x404AB00ull |
|---|
| 6914 | #define DCORE0_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 6915 | #define DCORE0_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 6916 | #define mmDCORE0_TPC4_QM_AXUSER_NONSECURED_BASE 0x404AB80ull |
|---|
| 6917 | #define DCORE0_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 6918 | #define DCORE0_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 6919 | #define mmDCORE0_TPC4_QM_DBG_HBW_BASE 0x404AC00ull |
|---|
| 6920 | #define DCORE0_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 6921 | #define DCORE0_TPC4_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 6922 | #define mmDCORE0_TPC4_QM_DBG_LBW_BASE 0x404AC80ull |
|---|
| 6923 | #define DCORE0_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 6924 | #define DCORE0_TPC4_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 6925 | #define mmDCORE0_TPC4_QM_CGM_BASE 0x404AD80ull |
|---|
| 6926 | #define DCORE0_TPC4_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 6927 | #define DCORE0_TPC4_QM_CGM_SECTION 0x1000 |
|---|
| 6928 | #define mmDCORE0_TPC4_QM_SPECIAL_BASE 0x404AE80ull |
|---|
| 6929 | #define DCORE0_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 6930 | #define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6931 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x404B000ull |
|---|
| 6932 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6933 | #define DCORE0_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 6934 | #define mmDCORE0_TPC4_CFG_BASE 0x404B000ull |
|---|
| 6935 | #define DCORE0_TPC4_CFG_MAX_OFFSET 0x1000 |
|---|
| 6936 | #define DCORE0_TPC4_CFG_SECTION 0x5000 |
|---|
| 6937 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x404B050ull |
|---|
| 6938 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6939 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 6940 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x404B0A0ull |
|---|
| 6941 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6942 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 6943 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x404B0F0ull |
|---|
| 6944 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6945 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 6946 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x404B140ull |
|---|
| 6947 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 6948 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 6949 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x404B190ull |
|---|
| 6950 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 6951 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 6952 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x404B1E0ull |
|---|
| 6953 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 6954 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 6955 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x404B230ull |
|---|
| 6956 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 6957 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 6958 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x404B280ull |
|---|
| 6959 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 6960 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 6961 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x404B2D0ull |
|---|
| 6962 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 6963 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 6964 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x404B320ull |
|---|
| 6965 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 6966 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 6967 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x404B370ull |
|---|
| 6968 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 6969 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 6970 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x404B3C0ull |
|---|
| 6971 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 6972 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 6973 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x404B410ull |
|---|
| 6974 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 6975 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 6976 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x404B460ull |
|---|
| 6977 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 6978 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 6979 | #define mmDCORE0_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x404B4B0ull |
|---|
| 6980 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 6981 | #define DCORE0_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 6982 | #define mmDCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x404B500ull |
|---|
| 6983 | #define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 6984 | #define DCORE0_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 6985 | #define mmDCORE0_TPC4_CFG_KERNEL_BASE 0x404B508ull |
|---|
| 6986 | #define DCORE0_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 6987 | #define DCORE0_TPC4_CFG_KERNEL_SECTION 0xD400 |
|---|
| 6988 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_0_BASE 0x404B5DCull |
|---|
| 6989 | #define DCORE0_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 6990 | #define DCORE0_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 6991 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_1_BASE 0x404B62Cull |
|---|
| 6992 | #define DCORE0_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 6993 | #define DCORE0_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 6994 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_2_BASE 0x404B67Cull |
|---|
| 6995 | #define DCORE0_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 6996 | #define DCORE0_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 6997 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_3_BASE 0x404B6CCull |
|---|
| 6998 | #define DCORE0_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 6999 | #define DCORE0_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 7000 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_4_BASE 0x404B71Cull |
|---|
| 7001 | #define DCORE0_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 7002 | #define DCORE0_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 7003 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_5_BASE 0x404B76Cull |
|---|
| 7004 | #define DCORE0_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 7005 | #define DCORE0_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 7006 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_6_BASE 0x404B7BCull |
|---|
| 7007 | #define DCORE0_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 7008 | #define DCORE0_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 7009 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_7_BASE 0x404B80Cull |
|---|
| 7010 | #define DCORE0_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 7011 | #define DCORE0_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 7012 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_8_BASE 0x404B85Cull |
|---|
| 7013 | #define DCORE0_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 7014 | #define DCORE0_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 7015 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_9_BASE 0x404B8ACull |
|---|
| 7016 | #define DCORE0_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 7017 | #define DCORE0_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 7018 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_10_BASE 0x404B8FCull |
|---|
| 7019 | #define DCORE0_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 7020 | #define DCORE0_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 7021 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_11_BASE 0x404B94Cull |
|---|
| 7022 | #define DCORE0_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 7023 | #define DCORE0_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 7024 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_12_BASE 0x404B99Cull |
|---|
| 7025 | #define DCORE0_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 7026 | #define DCORE0_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 7027 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_13_BASE 0x404B9ECull |
|---|
| 7028 | #define DCORE0_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 7029 | #define DCORE0_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 7030 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_14_BASE 0x404BA3Cull |
|---|
| 7031 | #define DCORE0_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 7032 | #define DCORE0_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 7033 | #define mmDCORE0_TPC4_CFG_QM_TENSOR_15_BASE 0x404BA8Cull |
|---|
| 7034 | #define DCORE0_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 7035 | #define DCORE0_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 7036 | #define mmDCORE0_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x404BADCull |
|---|
| 7037 | #define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 7038 | #define DCORE0_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 7039 | #define mmDCORE0_TPC4_CFG_QM_BASE 0x404BAE4ull |
|---|
| 7040 | #define DCORE0_TPC4_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 7041 | #define DCORE0_TPC4_CFG_QM_SECTION 0x31C0 |
|---|
| 7042 | #define mmDCORE0_TPC4_CFG_AXUSER_BASE 0x404BE00ull |
|---|
| 7043 | #define DCORE0_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7044 | #define DCORE0_TPC4_CFG_AXUSER_SECTION 0x8000 |
|---|
| 7045 | #define mmDCORE0_TPC4_CFG_SPECIAL_BASE 0x404BE80ull |
|---|
| 7046 | #define DCORE0_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7047 | #define DCORE0_TPC4_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 7048 | #define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x404C000ull |
|---|
| 7049 | #define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7050 | #define DCORE0_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7051 | #define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x404C200ull |
|---|
| 7052 | #define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7053 | #define DCORE0_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7054 | #define mmDCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x404C400ull |
|---|
| 7055 | #define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7056 | #define DCORE0_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7057 | #define mmDCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x404C600ull |
|---|
| 7058 | #define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7059 | #define DCORE0_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7060 | #define mmDCORE0_TPC4_MSTR_IF_E2E_CRDT_BASE 0x404C800ull |
|---|
| 7061 | #define DCORE0_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7062 | #define DCORE0_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7063 | #define mmDCORE0_TPC4_MSTR_IF_AXUSER_BASE 0x404CA80ull |
|---|
| 7064 | #define DCORE0_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7065 | #define DCORE0_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7066 | #define mmDCORE0_TPC4_MSTR_IF_DBG_HBW_BASE 0x404CB00ull |
|---|
| 7067 | #define DCORE0_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7068 | #define DCORE0_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7069 | #define mmDCORE0_TPC4_MSTR_IF_DBG_LBW_BASE 0x404CB80ull |
|---|
| 7070 | #define DCORE0_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7071 | #define DCORE0_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7072 | #define mmDCORE0_TPC4_MSTR_IF_CORE_HBW_BASE 0x404CC00ull |
|---|
| 7073 | #define DCORE0_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7074 | #define DCORE0_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7075 | #define mmDCORE0_TPC4_MSTR_IF_CORE_LBW_BASE 0x404CD80ull |
|---|
| 7076 | #define DCORE0_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7077 | #define DCORE0_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7078 | #define mmDCORE0_TPC4_MSTR_IF_SPECIAL_BASE 0x404CE80ull |
|---|
| 7079 | #define DCORE0_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7080 | #define DCORE0_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 7081 | #define mmDCORE0_TPC5_QM_DCCM_BASE 0x4050000ull |
|---|
| 7082 | #define DCORE0_TPC5_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 7083 | #define DCORE0_TPC5_QM_DCCM_SECTION 0x8000 |
|---|
| 7084 | #define mmDCORE0_TPC5_QM_ARC_AUX_BASE 0x4058000ull |
|---|
| 7085 | #define DCORE0_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 7086 | #define DCORE0_TPC5_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 7087 | #define mmDCORE0_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4058E80ull |
|---|
| 7088 | #define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7089 | #define DCORE0_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 7090 | #define mmDCORE0_TPC5_QM_BASE 0x405A000ull |
|---|
| 7091 | #define DCORE0_TPC5_QM_MAX_OFFSET 0x1000 |
|---|
| 7092 | #define DCORE0_TPC5_QM_SECTION 0x9000 |
|---|
| 7093 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x405A900ull |
|---|
| 7094 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 7095 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 7096 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x405A908ull |
|---|
| 7097 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 7098 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 7099 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x405A910ull |
|---|
| 7100 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 7101 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 7102 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x405A918ull |
|---|
| 7103 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 7104 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 7105 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x405A920ull |
|---|
| 7106 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 7107 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 7108 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x405A928ull |
|---|
| 7109 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 7110 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 7111 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x405A930ull |
|---|
| 7112 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 7113 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 7114 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x405A938ull |
|---|
| 7115 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 7116 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 7117 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x405A940ull |
|---|
| 7118 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 7119 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 7120 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x405A948ull |
|---|
| 7121 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 7122 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 7123 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x405A950ull |
|---|
| 7124 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 7125 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 7126 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x405A958ull |
|---|
| 7127 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 7128 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 7129 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x405A960ull |
|---|
| 7130 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 7131 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 7132 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x405A968ull |
|---|
| 7133 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 7134 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 7135 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x405A970ull |
|---|
| 7136 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 7137 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 7138 | #define mmDCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x405A978ull |
|---|
| 7139 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 7140 | #define DCORE0_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 7141 | #define mmDCORE0_TPC5_QM_AXUSER_SECURED_BASE 0x405AB00ull |
|---|
| 7142 | #define DCORE0_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 7143 | #define DCORE0_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 7144 | #define mmDCORE0_TPC5_QM_AXUSER_NONSECURED_BASE 0x405AB80ull |
|---|
| 7145 | #define DCORE0_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 7146 | #define DCORE0_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 7147 | #define mmDCORE0_TPC5_QM_DBG_HBW_BASE 0x405AC00ull |
|---|
| 7148 | #define DCORE0_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7149 | #define DCORE0_TPC5_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 7150 | #define mmDCORE0_TPC5_QM_DBG_LBW_BASE 0x405AC80ull |
|---|
| 7151 | #define DCORE0_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7152 | #define DCORE0_TPC5_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 7153 | #define mmDCORE0_TPC5_QM_CGM_BASE 0x405AD80ull |
|---|
| 7154 | #define DCORE0_TPC5_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 7155 | #define DCORE0_TPC5_QM_CGM_SECTION 0x1000 |
|---|
| 7156 | #define mmDCORE0_TPC5_QM_SPECIAL_BASE 0x405AE80ull |
|---|
| 7157 | #define DCORE0_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7158 | #define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 7159 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x405B000ull |
|---|
| 7160 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 7161 | #define DCORE0_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 7162 | #define mmDCORE0_TPC5_CFG_BASE 0x405B000ull |
|---|
| 7163 | #define DCORE0_TPC5_CFG_MAX_OFFSET 0x1000 |
|---|
| 7164 | #define DCORE0_TPC5_CFG_SECTION 0x5000 |
|---|
| 7165 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x405B050ull |
|---|
| 7166 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 7167 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 7168 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x405B0A0ull |
|---|
| 7169 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 7170 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 7171 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x405B0F0ull |
|---|
| 7172 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 7173 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 7174 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x405B140ull |
|---|
| 7175 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 7176 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 7177 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x405B190ull |
|---|
| 7178 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 7179 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 7180 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x405B1E0ull |
|---|
| 7181 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 7182 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 7183 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x405B230ull |
|---|
| 7184 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 7185 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 7186 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x405B280ull |
|---|
| 7187 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 7188 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 7189 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x405B2D0ull |
|---|
| 7190 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 7191 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 7192 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x405B320ull |
|---|
| 7193 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 7194 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 7195 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x405B370ull |
|---|
| 7196 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 7197 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 7198 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x405B3C0ull |
|---|
| 7199 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 7200 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 7201 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x405B410ull |
|---|
| 7202 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 7203 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 7204 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x405B460ull |
|---|
| 7205 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 7206 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 7207 | #define mmDCORE0_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x405B4B0ull |
|---|
| 7208 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 7209 | #define DCORE0_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 7210 | #define mmDCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x405B500ull |
|---|
| 7211 | #define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 7212 | #define DCORE0_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 7213 | #define mmDCORE0_TPC5_CFG_KERNEL_BASE 0x405B508ull |
|---|
| 7214 | #define DCORE0_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 7215 | #define DCORE0_TPC5_CFG_KERNEL_SECTION 0xD400 |
|---|
| 7216 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_0_BASE 0x405B5DCull |
|---|
| 7217 | #define DCORE0_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 7218 | #define DCORE0_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 7219 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_1_BASE 0x405B62Cull |
|---|
| 7220 | #define DCORE0_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 7221 | #define DCORE0_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 7222 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_2_BASE 0x405B67Cull |
|---|
| 7223 | #define DCORE0_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 7224 | #define DCORE0_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 7225 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_3_BASE 0x405B6CCull |
|---|
| 7226 | #define DCORE0_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 7227 | #define DCORE0_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 7228 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_4_BASE 0x405B71Cull |
|---|
| 7229 | #define DCORE0_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 7230 | #define DCORE0_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 7231 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_5_BASE 0x405B76Cull |
|---|
| 7232 | #define DCORE0_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 7233 | #define DCORE0_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 7234 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_6_BASE 0x405B7BCull |
|---|
| 7235 | #define DCORE0_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 7236 | #define DCORE0_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 7237 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_7_BASE 0x405B80Cull |
|---|
| 7238 | #define DCORE0_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 7239 | #define DCORE0_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 7240 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_8_BASE 0x405B85Cull |
|---|
| 7241 | #define DCORE0_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 7242 | #define DCORE0_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 7243 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_9_BASE 0x405B8ACull |
|---|
| 7244 | #define DCORE0_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 7245 | #define DCORE0_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 7246 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_10_BASE 0x405B8FCull |
|---|
| 7247 | #define DCORE0_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 7248 | #define DCORE0_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 7249 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_11_BASE 0x405B94Cull |
|---|
| 7250 | #define DCORE0_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 7251 | #define DCORE0_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 7252 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_12_BASE 0x405B99Cull |
|---|
| 7253 | #define DCORE0_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 7254 | #define DCORE0_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 7255 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_13_BASE 0x405B9ECull |
|---|
| 7256 | #define DCORE0_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 7257 | #define DCORE0_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 7258 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_14_BASE 0x405BA3Cull |
|---|
| 7259 | #define DCORE0_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 7260 | #define DCORE0_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 7261 | #define mmDCORE0_TPC5_CFG_QM_TENSOR_15_BASE 0x405BA8Cull |
|---|
| 7262 | #define DCORE0_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 7263 | #define DCORE0_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 7264 | #define mmDCORE0_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x405BADCull |
|---|
| 7265 | #define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 7266 | #define DCORE0_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 7267 | #define mmDCORE0_TPC5_CFG_QM_BASE 0x405BAE4ull |
|---|
| 7268 | #define DCORE0_TPC5_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 7269 | #define DCORE0_TPC5_CFG_QM_SECTION 0x31C0 |
|---|
| 7270 | #define mmDCORE0_TPC5_CFG_AXUSER_BASE 0x405BE00ull |
|---|
| 7271 | #define DCORE0_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7272 | #define DCORE0_TPC5_CFG_AXUSER_SECTION 0x8000 |
|---|
| 7273 | #define mmDCORE0_TPC5_CFG_SPECIAL_BASE 0x405BE80ull |
|---|
| 7274 | #define DCORE0_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7275 | #define DCORE0_TPC5_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 7276 | #define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x405C000ull |
|---|
| 7277 | #define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7278 | #define DCORE0_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7279 | #define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x405C200ull |
|---|
| 7280 | #define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7281 | #define DCORE0_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7282 | #define mmDCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x405C400ull |
|---|
| 7283 | #define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7284 | #define DCORE0_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7285 | #define mmDCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x405C600ull |
|---|
| 7286 | #define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7287 | #define DCORE0_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7288 | #define mmDCORE0_TPC5_MSTR_IF_E2E_CRDT_BASE 0x405C800ull |
|---|
| 7289 | #define DCORE0_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7290 | #define DCORE0_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7291 | #define mmDCORE0_TPC5_MSTR_IF_AXUSER_BASE 0x405CA80ull |
|---|
| 7292 | #define DCORE0_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7293 | #define DCORE0_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7294 | #define mmDCORE0_TPC5_MSTR_IF_DBG_HBW_BASE 0x405CB00ull |
|---|
| 7295 | #define DCORE0_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7296 | #define DCORE0_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7297 | #define mmDCORE0_TPC5_MSTR_IF_DBG_LBW_BASE 0x405CB80ull |
|---|
| 7298 | #define DCORE0_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7299 | #define DCORE0_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7300 | #define mmDCORE0_TPC5_MSTR_IF_CORE_HBW_BASE 0x405CC00ull |
|---|
| 7301 | #define DCORE0_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7302 | #define DCORE0_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7303 | #define mmDCORE0_TPC5_MSTR_IF_CORE_LBW_BASE 0x405CD80ull |
|---|
| 7304 | #define DCORE0_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7305 | #define DCORE0_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7306 | #define mmDCORE0_TPC5_MSTR_IF_SPECIAL_BASE 0x405CE80ull |
|---|
| 7307 | #define DCORE0_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7308 | #define DCORE0_TPC5_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 7309 | #define mmDCORE0_TPC6_QM_DCCM_BASE 0x4060000ull |
|---|
| 7310 | #define DCORE0_TPC6_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 7311 | #define DCORE0_TPC6_QM_DCCM_SECTION 0x8000 |
|---|
| 7312 | #define mmDCORE0_TPC6_QM_ARC_AUX_BASE 0x4068000ull |
|---|
| 7313 | #define DCORE0_TPC6_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 7314 | #define DCORE0_TPC6_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 7315 | #define mmDCORE0_TPC6_QM_ARC_AUX_SPECIAL_BASE 0x4068E80ull |
|---|
| 7316 | #define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7317 | #define DCORE0_TPC6_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 7318 | #define mmDCORE0_TPC6_QM_BASE 0x406A000ull |
|---|
| 7319 | #define DCORE0_TPC6_QM_MAX_OFFSET 0x1000 |
|---|
| 7320 | #define DCORE0_TPC6_QM_SECTION 0x9000 |
|---|
| 7321 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_BASE 0x406A900ull |
|---|
| 7322 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 7323 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 7324 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_BASE 0x406A908ull |
|---|
| 7325 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 7326 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 7327 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_BASE 0x406A910ull |
|---|
| 7328 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 7329 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 7330 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_BASE 0x406A918ull |
|---|
| 7331 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 7332 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 7333 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_BASE 0x406A920ull |
|---|
| 7334 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 7335 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 7336 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_BASE 0x406A928ull |
|---|
| 7337 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 7338 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 7339 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_BASE 0x406A930ull |
|---|
| 7340 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 7341 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 7342 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_BASE 0x406A938ull |
|---|
| 7343 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 7344 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 7345 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_BASE 0x406A940ull |
|---|
| 7346 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 7347 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 7348 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_BASE 0x406A948ull |
|---|
| 7349 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 7350 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 7351 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_BASE 0x406A950ull |
|---|
| 7352 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 7353 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 7354 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_BASE 0x406A958ull |
|---|
| 7355 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 7356 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 7357 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_BASE 0x406A960ull |
|---|
| 7358 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 7359 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 7360 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_BASE 0x406A968ull |
|---|
| 7361 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 7362 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 7363 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_BASE 0x406A970ull |
|---|
| 7364 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 7365 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 7366 | #define mmDCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_BASE 0x406A978ull |
|---|
| 7367 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 7368 | #define DCORE0_TPC6_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 7369 | #define mmDCORE0_TPC6_QM_AXUSER_SECURED_BASE 0x406AB00ull |
|---|
| 7370 | #define DCORE0_TPC6_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 7371 | #define DCORE0_TPC6_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 7372 | #define mmDCORE0_TPC6_QM_AXUSER_NONSECURED_BASE 0x406AB80ull |
|---|
| 7373 | #define DCORE0_TPC6_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 7374 | #define DCORE0_TPC6_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 7375 | #define mmDCORE0_TPC6_QM_DBG_HBW_BASE 0x406AC00ull |
|---|
| 7376 | #define DCORE0_TPC6_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7377 | #define DCORE0_TPC6_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 7378 | #define mmDCORE0_TPC6_QM_DBG_LBW_BASE 0x406AC80ull |
|---|
| 7379 | #define DCORE0_TPC6_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7380 | #define DCORE0_TPC6_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 7381 | #define mmDCORE0_TPC6_QM_CGM_BASE 0x406AD80ull |
|---|
| 7382 | #define DCORE0_TPC6_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 7383 | #define DCORE0_TPC6_QM_CGM_SECTION 0x1000 |
|---|
| 7384 | #define mmDCORE0_TPC6_QM_SPECIAL_BASE 0x406AE80ull |
|---|
| 7385 | #define DCORE0_TPC6_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7386 | #define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 |
|---|
| 7387 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_0_BASE 0x406B000ull |
|---|
| 7388 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 7389 | #define DCORE0_TPC6_QM_SPECIAL_SECTION 0x1800 |
|---|
| 7390 | #define mmDCORE0_TPC6_CFG_BASE 0x406B000ull |
|---|
| 7391 | #define DCORE0_TPC6_CFG_MAX_OFFSET 0x1000 |
|---|
| 7392 | #define DCORE0_TPC6_CFG_SECTION 0x5000 |
|---|
| 7393 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_1_BASE 0x406B050ull |
|---|
| 7394 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 7395 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 7396 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_2_BASE 0x406B0A0ull |
|---|
| 7397 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 7398 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 7399 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_3_BASE 0x406B0F0ull |
|---|
| 7400 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 7401 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 7402 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_4_BASE 0x406B140ull |
|---|
| 7403 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 7404 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 7405 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_5_BASE 0x406B190ull |
|---|
| 7406 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 7407 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 7408 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_6_BASE 0x406B1E0ull |
|---|
| 7409 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 7410 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 7411 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_7_BASE 0x406B230ull |
|---|
| 7412 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 7413 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 7414 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_8_BASE 0x406B280ull |
|---|
| 7415 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 7416 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 7417 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_9_BASE 0x406B2D0ull |
|---|
| 7418 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 7419 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 7420 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_10_BASE 0x406B320ull |
|---|
| 7421 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 7422 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 7423 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_11_BASE 0x406B370ull |
|---|
| 7424 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 7425 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 7426 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_12_BASE 0x406B3C0ull |
|---|
| 7427 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 7428 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 7429 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_13_BASE 0x406B410ull |
|---|
| 7430 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 7431 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 7432 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_14_BASE 0x406B460ull |
|---|
| 7433 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 7434 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 7435 | #define mmDCORE0_TPC6_CFG_KERNEL_TENSOR_15_BASE 0x406B4B0ull |
|---|
| 7436 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 7437 | #define DCORE0_TPC6_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 7438 | #define mmDCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_BASE 0x406B500ull |
|---|
| 7439 | #define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 7440 | #define DCORE0_TPC6_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 7441 | #define mmDCORE0_TPC6_CFG_KERNEL_BASE 0x406B508ull |
|---|
| 7442 | #define DCORE0_TPC6_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 7443 | #define DCORE0_TPC6_CFG_KERNEL_SECTION 0xD400 |
|---|
| 7444 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_0_BASE 0x406B5DCull |
|---|
| 7445 | #define DCORE0_TPC6_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 7446 | #define DCORE0_TPC6_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 7447 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_1_BASE 0x406B62Cull |
|---|
| 7448 | #define DCORE0_TPC6_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 7449 | #define DCORE0_TPC6_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 7450 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_2_BASE 0x406B67Cull |
|---|
| 7451 | #define DCORE0_TPC6_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 7452 | #define DCORE0_TPC6_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 7453 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_3_BASE 0x406B6CCull |
|---|
| 7454 | #define DCORE0_TPC6_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 7455 | #define DCORE0_TPC6_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 7456 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_4_BASE 0x406B71Cull |
|---|
| 7457 | #define DCORE0_TPC6_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 7458 | #define DCORE0_TPC6_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 7459 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_5_BASE 0x406B76Cull |
|---|
| 7460 | #define DCORE0_TPC6_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 7461 | #define DCORE0_TPC6_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 7462 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_6_BASE 0x406B7BCull |
|---|
| 7463 | #define DCORE0_TPC6_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 7464 | #define DCORE0_TPC6_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 7465 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_7_BASE 0x406B80Cull |
|---|
| 7466 | #define DCORE0_TPC6_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 7467 | #define DCORE0_TPC6_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 7468 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_8_BASE 0x406B85Cull |
|---|
| 7469 | #define DCORE0_TPC6_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 7470 | #define DCORE0_TPC6_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 7471 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_9_BASE 0x406B8ACull |
|---|
| 7472 | #define DCORE0_TPC6_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 7473 | #define DCORE0_TPC6_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 7474 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_10_BASE 0x406B8FCull |
|---|
| 7475 | #define DCORE0_TPC6_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 7476 | #define DCORE0_TPC6_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 7477 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_11_BASE 0x406B94Cull |
|---|
| 7478 | #define DCORE0_TPC6_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 7479 | #define DCORE0_TPC6_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 7480 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_12_BASE 0x406B99Cull |
|---|
| 7481 | #define DCORE0_TPC6_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 7482 | #define DCORE0_TPC6_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 7483 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_13_BASE 0x406B9ECull |
|---|
| 7484 | #define DCORE0_TPC6_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 7485 | #define DCORE0_TPC6_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 7486 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_14_BASE 0x406BA3Cull |
|---|
| 7487 | #define DCORE0_TPC6_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 7488 | #define DCORE0_TPC6_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 7489 | #define mmDCORE0_TPC6_CFG_QM_TENSOR_15_BASE 0x406BA8Cull |
|---|
| 7490 | #define DCORE0_TPC6_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 7491 | #define DCORE0_TPC6_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 7492 | #define mmDCORE0_TPC6_CFG_QM_SYNC_OBJECT_BASE 0x406BADCull |
|---|
| 7493 | #define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 7494 | #define DCORE0_TPC6_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 7495 | #define mmDCORE0_TPC6_CFG_QM_BASE 0x406BAE4ull |
|---|
| 7496 | #define DCORE0_TPC6_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 7497 | #define DCORE0_TPC6_CFG_QM_SECTION 0x31C0 |
|---|
| 7498 | #define mmDCORE0_TPC6_CFG_AXUSER_BASE 0x406BE00ull |
|---|
| 7499 | #define DCORE0_TPC6_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7500 | #define DCORE0_TPC6_CFG_AXUSER_SECTION 0x8000 |
|---|
| 7501 | #define mmDCORE0_TPC6_CFG_SPECIAL_BASE 0x406BE80ull |
|---|
| 7502 | #define DCORE0_TPC6_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7503 | #define DCORE0_TPC6_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 7504 | #define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_BASE 0x406C000ull |
|---|
| 7505 | #define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7506 | #define DCORE0_TPC6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7507 | #define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_BASE 0x406C200ull |
|---|
| 7508 | #define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7509 | #define DCORE0_TPC6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7510 | #define mmDCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_BASE 0x406C400ull |
|---|
| 7511 | #define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7512 | #define DCORE0_TPC6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7513 | #define mmDCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_BASE 0x406C600ull |
|---|
| 7514 | #define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7515 | #define DCORE0_TPC6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7516 | #define mmDCORE0_TPC6_MSTR_IF_E2E_CRDT_BASE 0x406C800ull |
|---|
| 7517 | #define DCORE0_TPC6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7518 | #define DCORE0_TPC6_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7519 | #define mmDCORE0_TPC6_MSTR_IF_AXUSER_BASE 0x406CA80ull |
|---|
| 7520 | #define DCORE0_TPC6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7521 | #define DCORE0_TPC6_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7522 | #define mmDCORE0_TPC6_MSTR_IF_DBG_HBW_BASE 0x406CB00ull |
|---|
| 7523 | #define DCORE0_TPC6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7524 | #define DCORE0_TPC6_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7525 | #define mmDCORE0_TPC6_MSTR_IF_DBG_LBW_BASE 0x406CB80ull |
|---|
| 7526 | #define DCORE0_TPC6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7527 | #define DCORE0_TPC6_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7528 | #define mmDCORE0_TPC6_MSTR_IF_CORE_HBW_BASE 0x406CC00ull |
|---|
| 7529 | #define DCORE0_TPC6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7530 | #define DCORE0_TPC6_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7531 | #define mmDCORE0_TPC6_MSTR_IF_CORE_LBW_BASE 0x406CD80ull |
|---|
| 7532 | #define DCORE0_TPC6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7533 | #define DCORE0_TPC6_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7534 | #define mmDCORE0_TPC6_MSTR_IF_SPECIAL_BASE 0x406CE80ull |
|---|
| 7535 | #define DCORE0_TPC6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7536 | #define DCORE0_TPC6_MSTR_IF_SPECIAL_SECTION 0x13180 |
|---|
| 7537 | #define mmDCORE0_HMMU0_MMU_BASE 0x4080000ull |
|---|
| 7538 | #define DCORE0_HMMU0_MMU_MAX_OFFSET 0x1000 |
|---|
| 7539 | #define DCORE0_HMMU0_MMU_SECTION 0xE800 |
|---|
| 7540 | #define mmDCORE0_HMMU0_MMU_SPECIAL_BASE 0x4080E80ull |
|---|
| 7541 | #define DCORE0_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7542 | #define DCORE0_HMMU0_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 7543 | #define mmDCORE0_HMMU0_STLB_BASE 0x4081000ull |
|---|
| 7544 | #define DCORE0_HMMU0_STLB_MAX_OFFSET 0x1000 |
|---|
| 7545 | #define DCORE0_HMMU0_STLB_SECTION 0xE800 |
|---|
| 7546 | #define mmDCORE0_HMMU0_STLB_SPECIAL_BASE 0x4081E80ull |
|---|
| 7547 | #define DCORE0_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7548 | #define DCORE0_HMMU0_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 7549 | #define mmDCORE0_HMMU0_SCRAMB_OUT_BASE 0x4083000ull |
|---|
| 7550 | #define DCORE0_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 7551 | #define DCORE0_HMMU0_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 7552 | #define mmDCORE0_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4083E80ull |
|---|
| 7553 | #define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7554 | #define DCORE0_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 7555 | #define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4084000ull |
|---|
| 7556 | #define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7557 | #define DCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7558 | #define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4084200ull |
|---|
| 7559 | #define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7560 | #define DCORE0_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7561 | #define mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4084400ull |
|---|
| 7562 | #define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7563 | #define DCORE0_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7564 | #define mmDCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4084600ull |
|---|
| 7565 | #define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7566 | #define DCORE0_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7567 | #define mmDCORE0_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4084800ull |
|---|
| 7568 | #define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7569 | #define DCORE0_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7570 | #define mmDCORE0_HMMU0_MSTR_IF_AXUSER_BASE 0x4084A80ull |
|---|
| 7571 | #define DCORE0_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7572 | #define DCORE0_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7573 | #define mmDCORE0_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4084B00ull |
|---|
| 7574 | #define DCORE0_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7575 | #define DCORE0_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7576 | #define mmDCORE0_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4084B80ull |
|---|
| 7577 | #define DCORE0_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7578 | #define DCORE0_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7579 | #define mmDCORE0_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4084C00ull |
|---|
| 7580 | #define DCORE0_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7581 | #define DCORE0_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7582 | #define mmDCORE0_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4084D80ull |
|---|
| 7583 | #define DCORE0_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7584 | #define DCORE0_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7585 | #define mmDCORE0_HMMU0_MSTR_IF_SPECIAL_BASE 0x4084E80ull |
|---|
| 7586 | #define DCORE0_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7587 | #define DCORE0_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 7588 | #define mmDCORE0_HMMU1_MMU_BASE 0x4090000ull |
|---|
| 7589 | #define DCORE0_HMMU1_MMU_MAX_OFFSET 0x1000 |
|---|
| 7590 | #define DCORE0_HMMU1_MMU_SECTION 0xE800 |
|---|
| 7591 | #define mmDCORE0_HMMU1_MMU_SPECIAL_BASE 0x4090E80ull |
|---|
| 7592 | #define DCORE0_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7593 | #define DCORE0_HMMU1_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 7594 | #define mmDCORE0_HMMU1_STLB_BASE 0x4091000ull |
|---|
| 7595 | #define DCORE0_HMMU1_STLB_MAX_OFFSET 0x1000 |
|---|
| 7596 | #define DCORE0_HMMU1_STLB_SECTION 0xE800 |
|---|
| 7597 | #define mmDCORE0_HMMU1_STLB_SPECIAL_BASE 0x4091E80ull |
|---|
| 7598 | #define DCORE0_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7599 | #define DCORE0_HMMU1_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 7600 | #define mmDCORE0_HMMU1_SCRAMB_OUT_BASE 0x4093000ull |
|---|
| 7601 | #define DCORE0_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 7602 | #define DCORE0_HMMU1_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 7603 | #define mmDCORE0_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4093E80ull |
|---|
| 7604 | #define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7605 | #define DCORE0_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 7606 | #define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4094000ull |
|---|
| 7607 | #define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7608 | #define DCORE0_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7609 | #define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4094200ull |
|---|
| 7610 | #define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7611 | #define DCORE0_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7612 | #define mmDCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4094400ull |
|---|
| 7613 | #define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7614 | #define DCORE0_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7615 | #define mmDCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4094600ull |
|---|
| 7616 | #define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7617 | #define DCORE0_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7618 | #define mmDCORE0_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4094800ull |
|---|
| 7619 | #define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7620 | #define DCORE0_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7621 | #define mmDCORE0_HMMU1_MSTR_IF_AXUSER_BASE 0x4094A80ull |
|---|
| 7622 | #define DCORE0_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7623 | #define DCORE0_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7624 | #define mmDCORE0_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4094B00ull |
|---|
| 7625 | #define DCORE0_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7626 | #define DCORE0_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7627 | #define mmDCORE0_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4094B80ull |
|---|
| 7628 | #define DCORE0_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7629 | #define DCORE0_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7630 | #define mmDCORE0_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4094C00ull |
|---|
| 7631 | #define DCORE0_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7632 | #define DCORE0_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7633 | #define mmDCORE0_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4094D80ull |
|---|
| 7634 | #define DCORE0_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7635 | #define DCORE0_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7636 | #define mmDCORE0_HMMU1_MSTR_IF_SPECIAL_BASE 0x4094E80ull |
|---|
| 7637 | #define DCORE0_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7638 | #define DCORE0_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 7639 | #define mmDCORE0_HMMU2_MMU_BASE 0x40A0000ull |
|---|
| 7640 | #define DCORE0_HMMU2_MMU_MAX_OFFSET 0x1000 |
|---|
| 7641 | #define DCORE0_HMMU2_MMU_SECTION 0xE800 |
|---|
| 7642 | #define mmDCORE0_HMMU2_MMU_SPECIAL_BASE 0x40A0E80ull |
|---|
| 7643 | #define DCORE0_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7644 | #define DCORE0_HMMU2_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 7645 | #define mmDCORE0_HMMU2_STLB_BASE 0x40A1000ull |
|---|
| 7646 | #define DCORE0_HMMU2_STLB_MAX_OFFSET 0x1000 |
|---|
| 7647 | #define DCORE0_HMMU2_STLB_SECTION 0xE800 |
|---|
| 7648 | #define mmDCORE0_HMMU2_STLB_SPECIAL_BASE 0x40A1E80ull |
|---|
| 7649 | #define DCORE0_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7650 | #define DCORE0_HMMU2_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 7651 | #define mmDCORE0_HMMU2_SCRAMB_OUT_BASE 0x40A3000ull |
|---|
| 7652 | #define DCORE0_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 7653 | #define DCORE0_HMMU2_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 7654 | #define mmDCORE0_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x40A3E80ull |
|---|
| 7655 | #define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7656 | #define DCORE0_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 7657 | #define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x40A4000ull |
|---|
| 7658 | #define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7659 | #define DCORE0_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7660 | #define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x40A4200ull |
|---|
| 7661 | #define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7662 | #define DCORE0_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7663 | #define mmDCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x40A4400ull |
|---|
| 7664 | #define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7665 | #define DCORE0_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7666 | #define mmDCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x40A4600ull |
|---|
| 7667 | #define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7668 | #define DCORE0_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7669 | #define mmDCORE0_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x40A4800ull |
|---|
| 7670 | #define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7671 | #define DCORE0_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7672 | #define mmDCORE0_HMMU2_MSTR_IF_AXUSER_BASE 0x40A4A80ull |
|---|
| 7673 | #define DCORE0_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7674 | #define DCORE0_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7675 | #define mmDCORE0_HMMU2_MSTR_IF_DBG_HBW_BASE 0x40A4B00ull |
|---|
| 7676 | #define DCORE0_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7677 | #define DCORE0_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7678 | #define mmDCORE0_HMMU2_MSTR_IF_DBG_LBW_BASE 0x40A4B80ull |
|---|
| 7679 | #define DCORE0_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7680 | #define DCORE0_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7681 | #define mmDCORE0_HMMU2_MSTR_IF_CORE_HBW_BASE 0x40A4C00ull |
|---|
| 7682 | #define DCORE0_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7683 | #define DCORE0_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7684 | #define mmDCORE0_HMMU2_MSTR_IF_CORE_LBW_BASE 0x40A4D80ull |
|---|
| 7685 | #define DCORE0_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7686 | #define DCORE0_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7687 | #define mmDCORE0_HMMU2_MSTR_IF_SPECIAL_BASE 0x40A4E80ull |
|---|
| 7688 | #define DCORE0_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7689 | #define DCORE0_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 7690 | #define mmDCORE0_HMMU3_MMU_BASE 0x40B0000ull |
|---|
| 7691 | #define DCORE0_HMMU3_MMU_MAX_OFFSET 0x1000 |
|---|
| 7692 | #define DCORE0_HMMU3_MMU_SECTION 0xE800 |
|---|
| 7693 | #define mmDCORE0_HMMU3_MMU_SPECIAL_BASE 0x40B0E80ull |
|---|
| 7694 | #define DCORE0_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7695 | #define DCORE0_HMMU3_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 7696 | #define mmDCORE0_HMMU3_STLB_BASE 0x40B1000ull |
|---|
| 7697 | #define DCORE0_HMMU3_STLB_MAX_OFFSET 0x1000 |
|---|
| 7698 | #define DCORE0_HMMU3_STLB_SECTION 0xE800 |
|---|
| 7699 | #define mmDCORE0_HMMU3_STLB_SPECIAL_BASE 0x40B1E80ull |
|---|
| 7700 | #define DCORE0_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7701 | #define DCORE0_HMMU3_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 7702 | #define mmDCORE0_HMMU3_SCRAMB_OUT_BASE 0x40B3000ull |
|---|
| 7703 | #define DCORE0_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 7704 | #define DCORE0_HMMU3_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 7705 | #define mmDCORE0_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x40B3E80ull |
|---|
| 7706 | #define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7707 | #define DCORE0_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 7708 | #define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x40B4000ull |
|---|
| 7709 | #define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7710 | #define DCORE0_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 7711 | #define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x40B4200ull |
|---|
| 7712 | #define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 7713 | #define DCORE0_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 7714 | #define mmDCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x40B4400ull |
|---|
| 7715 | #define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7716 | #define DCORE0_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 7717 | #define mmDCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x40B4600ull |
|---|
| 7718 | #define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 7719 | #define DCORE0_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 7720 | #define mmDCORE0_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x40B4800ull |
|---|
| 7721 | #define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 7722 | #define DCORE0_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 7723 | #define mmDCORE0_HMMU3_MSTR_IF_AXUSER_BASE 0x40B4A80ull |
|---|
| 7724 | #define DCORE0_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7725 | #define DCORE0_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 7726 | #define mmDCORE0_HMMU3_MSTR_IF_DBG_HBW_BASE 0x40B4B00ull |
|---|
| 7727 | #define DCORE0_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7728 | #define DCORE0_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 7729 | #define mmDCORE0_HMMU3_MSTR_IF_DBG_LBW_BASE 0x40B4B80ull |
|---|
| 7730 | #define DCORE0_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7731 | #define DCORE0_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 7732 | #define mmDCORE0_HMMU3_MSTR_IF_CORE_HBW_BASE 0x40B4C00ull |
|---|
| 7733 | #define DCORE0_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 7734 | #define DCORE0_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 7735 | #define mmDCORE0_HMMU3_MSTR_IF_CORE_LBW_BASE 0x40B4D80ull |
|---|
| 7736 | #define DCORE0_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 7737 | #define DCORE0_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 7738 | #define mmDCORE0_HMMU3_MSTR_IF_SPECIAL_BASE 0x40B4E80ull |
|---|
| 7739 | #define DCORE0_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7740 | #define DCORE0_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 7741 | #define mmDCORE0_MME_QM_ARC_DCCM_BASE 0x40C0000ull |
|---|
| 7742 | #define DCORE0_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 |
|---|
| 7743 | #define DCORE0_MME_QM_ARC_DCCM_SECTION 0x8000 |
|---|
| 7744 | #define mmDCORE0_MME_QM_ARC_AUX_BASE 0x40C8000ull |
|---|
| 7745 | #define DCORE0_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 7746 | #define DCORE0_MME_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 7747 | #define mmDCORE0_MME_QM_ARC_AUX_SPECIAL_BASE 0x40C8E80ull |
|---|
| 7748 | #define DCORE0_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7749 | #define DCORE0_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 |
|---|
| 7750 | #define mmDCORE0_MME_QM_ARC_DUP_ENG_BASE 0x40C9000ull |
|---|
| 7751 | #define DCORE0_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 |
|---|
| 7752 | #define DCORE0_MME_QM_ARC_DUP_ENG_SECTION 0x9000 |
|---|
| 7753 | #define mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x40C9900ull |
|---|
| 7754 | #define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7755 | #define DCORE0_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 |
|---|
| 7756 | #define mmDCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x40C9E80ull |
|---|
| 7757 | #define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7758 | #define DCORE0_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 7759 | #define mmDCORE0_MME_QM_BASE 0x40CA000ull |
|---|
| 7760 | #define DCORE0_MME_QM_MAX_OFFSET 0x1000 |
|---|
| 7761 | #define DCORE0_MME_QM_SECTION 0x9000 |
|---|
| 7762 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x40CA900ull |
|---|
| 7763 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 7764 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 7765 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x40CA908ull |
|---|
| 7766 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 7767 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 7768 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x40CA910ull |
|---|
| 7769 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 7770 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 7771 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x40CA918ull |
|---|
| 7772 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 7773 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 7774 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x40CA920ull |
|---|
| 7775 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 7776 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 7777 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x40CA928ull |
|---|
| 7778 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 7779 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 7780 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x40CA930ull |
|---|
| 7781 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 7782 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 7783 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x40CA938ull |
|---|
| 7784 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 7785 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 7786 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x40CA940ull |
|---|
| 7787 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 7788 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 7789 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x40CA948ull |
|---|
| 7790 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 7791 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 7792 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x40CA950ull |
|---|
| 7793 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 7794 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 7795 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x40CA958ull |
|---|
| 7796 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 7797 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 7798 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x40CA960ull |
|---|
| 7799 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 7800 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 7801 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x40CA968ull |
|---|
| 7802 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 7803 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 7804 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x40CA970ull |
|---|
| 7805 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 7806 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 7807 | #define mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x40CA978ull |
|---|
| 7808 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 7809 | #define DCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 7810 | #define mmDCORE0_MME_QM_AXUSER_SECURED_BASE 0x40CAB00ull |
|---|
| 7811 | #define DCORE0_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 7812 | #define DCORE0_MME_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 7813 | #define mmDCORE0_MME_QM_AXUSER_NONSECURED_BASE 0x40CAB80ull |
|---|
| 7814 | #define DCORE0_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 7815 | #define DCORE0_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 7816 | #define mmDCORE0_MME_QM_DBG_HBW_BASE 0x40CAC00ull |
|---|
| 7817 | #define DCORE0_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 7818 | #define DCORE0_MME_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 7819 | #define mmDCORE0_MME_QM_DBG_LBW_BASE 0x40CAC80ull |
|---|
| 7820 | #define DCORE0_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 7821 | #define DCORE0_MME_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 7822 | #define mmDCORE0_MME_QM_CGM_BASE 0x40CAD80ull |
|---|
| 7823 | #define DCORE0_MME_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 7824 | #define DCORE0_MME_QM_CGM_SECTION 0x1000 |
|---|
| 7825 | #define mmDCORE0_MME_QM_SPECIAL_BASE 0x40CAE80ull |
|---|
| 7826 | #define DCORE0_MME_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7827 | #define DCORE0_MME_QM_SPECIAL_SECTION 0x1800 |
|---|
| 7828 | #define mmDCORE0_MME_CTRL_LO_BASE 0x40CB000ull |
|---|
| 7829 | #define DCORE0_MME_CTRL_LO_MAX_OFFSET 0x1000 |
|---|
| 7830 | #define DCORE0_MME_CTRL_LO_SECTION 0x8000 |
|---|
| 7831 | #define mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x40CB008ull |
|---|
| 7832 | #define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 7833 | #define DCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 |
|---|
| 7834 | #define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x40CB028ull |
|---|
| 7835 | #define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 7836 | #define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 7837 | #define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x40CB040ull |
|---|
| 7838 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 7839 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 |
|---|
| 7840 | #define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x40CB098ull |
|---|
| 7841 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 7842 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 |
|---|
| 7843 | #define mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x40CB0F0ull |
|---|
| 7844 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 7845 | #define DCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 7846 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x40CB15Cull |
|---|
| 7847 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7848 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 7849 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x40CB170ull |
|---|
| 7850 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7851 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 7852 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x40CB184ull |
|---|
| 7853 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7854 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 7855 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x40CB198ull |
|---|
| 7856 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7857 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 7858 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x40CB1ACull |
|---|
| 7859 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7860 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 7861 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x40CB1C0ull |
|---|
| 7862 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7863 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 7864 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x40CB1D4ull |
|---|
| 7865 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7866 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 7867 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x40CB1E8ull |
|---|
| 7868 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7869 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 7870 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x40CB1FCull |
|---|
| 7871 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7872 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 7873 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x40CB210ull |
|---|
| 7874 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7875 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 7876 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x40CB22Cull |
|---|
| 7877 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7878 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 7879 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x40CB240ull |
|---|
| 7880 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7881 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 7882 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x40CB254ull |
|---|
| 7883 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7884 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 7885 | #define mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x40CB268ull |
|---|
| 7886 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7887 | #define DCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 7888 | #define mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x40CB280ull |
|---|
| 7889 | #define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 7890 | #define DCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 |
|---|
| 7891 | #define mmDCORE0_MME_CTRL_LO_MME_AXUSER_BASE 0x40CBE00ull |
|---|
| 7892 | #define DCORE0_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 7893 | #define DCORE0_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 |
|---|
| 7894 | #define mmDCORE0_MME_CTRL_LO_SPECIAL_BASE 0x40CBE80ull |
|---|
| 7895 | #define DCORE0_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 7896 | #define DCORE0_MME_CTRL_LO_SPECIAL_SECTION 0x1800 |
|---|
| 7897 | #define mmDCORE0_MME_CTRL_HI_BASE 0x40CC000ull |
|---|
| 7898 | #define DCORE0_MME_CTRL_HI_MAX_OFFSET 0x1000 |
|---|
| 7899 | #define DCORE0_MME_CTRL_HI_SECTION 0x8000 |
|---|
| 7900 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x40CC008ull |
|---|
| 7901 | #define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 7902 | #define DCORE0_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 |
|---|
| 7903 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x40CC028ull |
|---|
| 7904 | #define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 7905 | #define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 7906 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x40CC040ull |
|---|
| 7907 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 7908 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 |
|---|
| 7909 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x40CC098ull |
|---|
| 7910 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 7911 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 |
|---|
| 7912 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x40CC0F0ull |
|---|
| 7913 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 7914 | #define DCORE0_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 7915 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x40CC15Cull |
|---|
| 7916 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7917 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 7918 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x40CC170ull |
|---|
| 7919 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7920 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 7921 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x40CC184ull |
|---|
| 7922 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7923 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 7924 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x40CC198ull |
|---|
| 7925 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7926 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 7927 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x40CC1ACull |
|---|
| 7928 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7929 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 7930 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x40CC1C0ull |
|---|
| 7931 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7932 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 7933 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x40CC1D4ull |
|---|
| 7934 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7935 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 7936 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x40CC1E8ull |
|---|
| 7937 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7938 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 7939 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x40CC1FCull |
|---|
| 7940 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7941 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 7942 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x40CC210ull |
|---|
| 7943 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7944 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 7945 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x40CC22Cull |
|---|
| 7946 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7947 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 7948 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x40CC240ull |
|---|
| 7949 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7950 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 7951 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x40CC254ull |
|---|
| 7952 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7953 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 7954 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x40CC268ull |
|---|
| 7955 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7956 | #define DCORE0_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 7957 | #define mmDCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x40CC280ull |
|---|
| 7958 | #define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 7959 | #define DCORE0_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 7960 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x40CC308ull |
|---|
| 7961 | #define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 7962 | #define DCORE0_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 |
|---|
| 7963 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x40CC328ull |
|---|
| 7964 | #define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 7965 | #define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 7966 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x40CC340ull |
|---|
| 7967 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 7968 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 |
|---|
| 7969 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x40CC398ull |
|---|
| 7970 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 7971 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 |
|---|
| 7972 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x40CC3F0ull |
|---|
| 7973 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 7974 | #define DCORE0_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 7975 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x40CC45Cull |
|---|
| 7976 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7977 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 7978 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x40CC470ull |
|---|
| 7979 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7980 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 7981 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x40CC484ull |
|---|
| 7982 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7983 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 7984 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x40CC498ull |
|---|
| 7985 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7986 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 7987 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x40CC4ACull |
|---|
| 7988 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7989 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 7990 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x40CC4C0ull |
|---|
| 7991 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7992 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 7993 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x40CC4D4ull |
|---|
| 7994 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 7995 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 7996 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x40CC4E8ull |
|---|
| 7997 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 7998 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 7999 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x40CC4FCull |
|---|
| 8000 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8001 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 8002 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x40CC510ull |
|---|
| 8003 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8004 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 8005 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x40CC52Cull |
|---|
| 8006 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8007 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 8008 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x40CC540ull |
|---|
| 8009 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8010 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 8011 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x40CC554ull |
|---|
| 8012 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8013 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 8014 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x40CC568ull |
|---|
| 8015 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8016 | #define DCORE0_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 8017 | #define mmDCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x40CC580ull |
|---|
| 8018 | #define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 8019 | #define DCORE0_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 8020 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x40CC608ull |
|---|
| 8021 | #define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 8022 | #define DCORE0_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 |
|---|
| 8023 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x40CC628ull |
|---|
| 8024 | #define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 8025 | #define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 8026 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x40CC640ull |
|---|
| 8027 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 8028 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 |
|---|
| 8029 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x40CC698ull |
|---|
| 8030 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 8031 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 |
|---|
| 8032 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x40CC6F0ull |
|---|
| 8033 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 8034 | #define DCORE0_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 8035 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x40CC75Cull |
|---|
| 8036 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8037 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 8038 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x40CC770ull |
|---|
| 8039 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8040 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 8041 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x40CC784ull |
|---|
| 8042 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8043 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 8044 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x40CC798ull |
|---|
| 8045 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8046 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 8047 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x40CC7ACull |
|---|
| 8048 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8049 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 8050 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x40CC7C0ull |
|---|
| 8051 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8052 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 8053 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x40CC7D4ull |
|---|
| 8054 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8055 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 8056 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x40CC7E8ull |
|---|
| 8057 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8058 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 8059 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x40CC7FCull |
|---|
| 8060 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8061 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 8062 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x40CC810ull |
|---|
| 8063 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8064 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 8065 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x40CC82Cull |
|---|
| 8066 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8067 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 8068 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x40CC840ull |
|---|
| 8069 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8070 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 8071 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x40CC854ull |
|---|
| 8072 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8073 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 8074 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x40CC868ull |
|---|
| 8075 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8076 | #define DCORE0_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 8077 | #define mmDCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x40CC880ull |
|---|
| 8078 | #define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 8079 | #define DCORE0_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 8080 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x40CC908ull |
|---|
| 8081 | #define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 8082 | #define DCORE0_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 |
|---|
| 8083 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x40CC928ull |
|---|
| 8084 | #define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 8085 | #define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 8086 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x40CC940ull |
|---|
| 8087 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 8088 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 |
|---|
| 8089 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x40CC998ull |
|---|
| 8090 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 8091 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 |
|---|
| 8092 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x40CC9F0ull |
|---|
| 8093 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 8094 | #define DCORE0_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 8095 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x40CCA5Cull |
|---|
| 8096 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8097 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 8098 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x40CCA70ull |
|---|
| 8099 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8100 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 8101 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x40CCA84ull |
|---|
| 8102 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8103 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 8104 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x40CCA98ull |
|---|
| 8105 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8106 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 8107 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x40CCAACull |
|---|
| 8108 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8109 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 8110 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x40CCAC0ull |
|---|
| 8111 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8112 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 8113 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x40CCAD4ull |
|---|
| 8114 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8115 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 8116 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x40CCAE8ull |
|---|
| 8117 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8118 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 8119 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x40CCAFCull |
|---|
| 8120 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8121 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 8122 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x40CCB10ull |
|---|
| 8123 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8124 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 8125 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x40CCB2Cull |
|---|
| 8126 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8127 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 8128 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x40CCB40ull |
|---|
| 8129 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8130 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 8131 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x40CCB54ull |
|---|
| 8132 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 8133 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 8134 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x40CCB68ull |
|---|
| 8135 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 8136 | #define DCORE0_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 8137 | #define mmDCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x40CCB80ull |
|---|
| 8138 | #define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 8139 | #define DCORE0_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 |
|---|
| 8140 | #define mmDCORE0_MME_CTRL_HI_SPECIAL_BASE 0x40CCE80ull |
|---|
| 8141 | #define DCORE0_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8142 | #define DCORE0_MME_CTRL_HI_SPECIAL_SECTION 0x1800 |
|---|
| 8143 | #define mmDCORE0_MME_EU_BIST_BASE 0x40CD000ull |
|---|
| 8144 | #define DCORE0_MME_EU_BIST_MAX_OFFSET 0x1000 |
|---|
| 8145 | #define DCORE0_MME_EU_BIST_SECTION 0xE800 |
|---|
| 8146 | #define mmDCORE0_MME_EU_BIST_SPECIAL_BASE 0x40CDE80ull |
|---|
| 8147 | #define DCORE0_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8148 | #define DCORE0_MME_EU_BIST_SPECIAL_SECTION 0x1800 |
|---|
| 8149 | #define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x40CE000ull |
|---|
| 8150 | #define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8151 | #define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8152 | #define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x40CE200ull |
|---|
| 8153 | #define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8154 | #define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8155 | #define mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x40CE400ull |
|---|
| 8156 | #define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8157 | #define DCORE0_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8158 | #define mmDCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x40CE600ull |
|---|
| 8159 | #define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8160 | #define DCORE0_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8161 | #define mmDCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x40CE800ull |
|---|
| 8162 | #define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8163 | #define DCORE0_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8164 | #define mmDCORE0_MME_CTRL_MSTR_IF_AXUSER_BASE 0x40CEA80ull |
|---|
| 8165 | #define DCORE0_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8166 | #define DCORE0_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8167 | #define mmDCORE0_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x40CEB00ull |
|---|
| 8168 | #define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8169 | #define DCORE0_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8170 | #define mmDCORE0_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x40CEB80ull |
|---|
| 8171 | #define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8172 | #define DCORE0_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8173 | #define mmDCORE0_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x40CEC00ull |
|---|
| 8174 | #define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8175 | #define DCORE0_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8176 | #define mmDCORE0_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x40CED80ull |
|---|
| 8177 | #define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8178 | #define DCORE0_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8179 | #define mmDCORE0_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x40CEE80ull |
|---|
| 8180 | #define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8181 | #define DCORE0_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8182 | #define mmDCORE0_MME_QM_ARC_ACP_ENG_BASE 0x40CF000ull |
|---|
| 8183 | #define DCORE0_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 |
|---|
| 8184 | #define DCORE0_MME_QM_ARC_ACP_ENG_SECTION 0xE800 |
|---|
| 8185 | #define mmDCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x40CFE80ull |
|---|
| 8186 | #define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8187 | #define DCORE0_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 8188 | #define mmDCORE0_MME_SBTE0_BASE 0x40D0000ull |
|---|
| 8189 | #define DCORE0_MME_SBTE0_MAX_OFFSET 0x1000 |
|---|
| 8190 | #define DCORE0_MME_SBTE0_SECTION 0xE800 |
|---|
| 8191 | #define mmDCORE0_MME_SBTE0_SPECIAL_BASE 0x40D0E80ull |
|---|
| 8192 | #define DCORE0_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8193 | #define DCORE0_MME_SBTE0_SPECIAL_SECTION 0x1800 |
|---|
| 8194 | #define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x40D1000ull |
|---|
| 8195 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8196 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8197 | #define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x40D1200ull |
|---|
| 8198 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8199 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8200 | #define mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x40D1400ull |
|---|
| 8201 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8202 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8203 | #define mmDCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x40D1600ull |
|---|
| 8204 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8205 | #define DCORE0_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8206 | #define mmDCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x40D1800ull |
|---|
| 8207 | #define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8208 | #define DCORE0_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8209 | #define mmDCORE0_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x40D1A80ull |
|---|
| 8210 | #define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8211 | #define DCORE0_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8212 | #define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x40D1B00ull |
|---|
| 8213 | #define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8214 | #define DCORE0_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8215 | #define mmDCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x40D1B80ull |
|---|
| 8216 | #define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8217 | #define DCORE0_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8218 | #define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x40D1C00ull |
|---|
| 8219 | #define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8220 | #define DCORE0_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8221 | #define mmDCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x40D1D80ull |
|---|
| 8222 | #define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8223 | #define DCORE0_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8224 | #define mmDCORE0_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x40D1E80ull |
|---|
| 8225 | #define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8226 | #define DCORE0_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 8227 | #define mmDCORE0_MME_SBTE1_BASE 0x40D8000ull |
|---|
| 8228 | #define DCORE0_MME_SBTE1_MAX_OFFSET 0x1000 |
|---|
| 8229 | #define DCORE0_MME_SBTE1_SECTION 0xE800 |
|---|
| 8230 | #define mmDCORE0_MME_SBTE1_SPECIAL_BASE 0x40D8E80ull |
|---|
| 8231 | #define DCORE0_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8232 | #define DCORE0_MME_SBTE1_SPECIAL_SECTION 0x1800 |
|---|
| 8233 | #define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x40D9000ull |
|---|
| 8234 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8235 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8236 | #define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x40D9200ull |
|---|
| 8237 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8238 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8239 | #define mmDCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x40D9400ull |
|---|
| 8240 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8241 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8242 | #define mmDCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x40D9600ull |
|---|
| 8243 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8244 | #define DCORE0_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8245 | #define mmDCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x40D9800ull |
|---|
| 8246 | #define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8247 | #define DCORE0_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8248 | #define mmDCORE0_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x40D9A80ull |
|---|
| 8249 | #define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8250 | #define DCORE0_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8251 | #define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x40D9B00ull |
|---|
| 8252 | #define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8253 | #define DCORE0_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8254 | #define mmDCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x40D9B80ull |
|---|
| 8255 | #define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8256 | #define DCORE0_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8257 | #define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x40D9C00ull |
|---|
| 8258 | #define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8259 | #define DCORE0_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8260 | #define mmDCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x40D9D80ull |
|---|
| 8261 | #define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8262 | #define DCORE0_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8263 | #define mmDCORE0_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x40D9E80ull |
|---|
| 8264 | #define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8265 | #define DCORE0_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 8266 | #define mmDCORE0_MME_SBTE2_BASE 0x40E0000ull |
|---|
| 8267 | #define DCORE0_MME_SBTE2_MAX_OFFSET 0x1000 |
|---|
| 8268 | #define DCORE0_MME_SBTE2_SECTION 0xE800 |
|---|
| 8269 | #define mmDCORE0_MME_SBTE2_SPECIAL_BASE 0x40E0E80ull |
|---|
| 8270 | #define DCORE0_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8271 | #define DCORE0_MME_SBTE2_SPECIAL_SECTION 0x1800 |
|---|
| 8272 | #define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x40E1000ull |
|---|
| 8273 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8274 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8275 | #define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x40E1200ull |
|---|
| 8276 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8277 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8278 | #define mmDCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x40E1400ull |
|---|
| 8279 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8280 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8281 | #define mmDCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x40E1600ull |
|---|
| 8282 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8283 | #define DCORE0_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8284 | #define mmDCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x40E1800ull |
|---|
| 8285 | #define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8286 | #define DCORE0_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8287 | #define mmDCORE0_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x40E1A80ull |
|---|
| 8288 | #define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8289 | #define DCORE0_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8290 | #define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x40E1B00ull |
|---|
| 8291 | #define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8292 | #define DCORE0_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8293 | #define mmDCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x40E1B80ull |
|---|
| 8294 | #define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8295 | #define DCORE0_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8296 | #define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x40E1C00ull |
|---|
| 8297 | #define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8298 | #define DCORE0_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8299 | #define mmDCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x40E1D80ull |
|---|
| 8300 | #define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8301 | #define DCORE0_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8302 | #define mmDCORE0_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x40E1E80ull |
|---|
| 8303 | #define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8304 | #define DCORE0_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 8305 | #define mmDCORE0_MME_SBTE3_BASE 0x40E8000ull |
|---|
| 8306 | #define DCORE0_MME_SBTE3_MAX_OFFSET 0x1000 |
|---|
| 8307 | #define DCORE0_MME_SBTE3_SECTION 0xE800 |
|---|
| 8308 | #define mmDCORE0_MME_SBTE3_SPECIAL_BASE 0x40E8E80ull |
|---|
| 8309 | #define DCORE0_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8310 | #define DCORE0_MME_SBTE3_SPECIAL_SECTION 0x1800 |
|---|
| 8311 | #define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x40E9000ull |
|---|
| 8312 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8313 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8314 | #define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x40E9200ull |
|---|
| 8315 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8316 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8317 | #define mmDCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x40E9400ull |
|---|
| 8318 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8319 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8320 | #define mmDCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x40E9600ull |
|---|
| 8321 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8322 | #define DCORE0_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8323 | #define mmDCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x40E9800ull |
|---|
| 8324 | #define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8325 | #define DCORE0_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8326 | #define mmDCORE0_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x40E9A80ull |
|---|
| 8327 | #define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8328 | #define DCORE0_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8329 | #define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x40E9B00ull |
|---|
| 8330 | #define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8331 | #define DCORE0_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8332 | #define mmDCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x40E9B80ull |
|---|
| 8333 | #define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8334 | #define DCORE0_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8335 | #define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x40E9C00ull |
|---|
| 8336 | #define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8337 | #define DCORE0_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8338 | #define mmDCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x40E9D80ull |
|---|
| 8339 | #define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8340 | #define DCORE0_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8341 | #define mmDCORE0_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x40E9E80ull |
|---|
| 8342 | #define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8343 | #define DCORE0_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 8344 | #define mmDCORE0_MME_SBTE4_BASE 0x40F0000ull |
|---|
| 8345 | #define DCORE0_MME_SBTE4_MAX_OFFSET 0x1000 |
|---|
| 8346 | #define DCORE0_MME_SBTE4_SECTION 0xE800 |
|---|
| 8347 | #define mmDCORE0_MME_SBTE4_SPECIAL_BASE 0x40F0E80ull |
|---|
| 8348 | #define DCORE0_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8349 | #define DCORE0_MME_SBTE4_SPECIAL_SECTION 0x1800 |
|---|
| 8350 | #define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x40F1000ull |
|---|
| 8351 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8352 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8353 | #define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x40F1200ull |
|---|
| 8354 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8355 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8356 | #define mmDCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x40F1400ull |
|---|
| 8357 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8358 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8359 | #define mmDCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x40F1600ull |
|---|
| 8360 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8361 | #define DCORE0_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8362 | #define mmDCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x40F1800ull |
|---|
| 8363 | #define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8364 | #define DCORE0_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8365 | #define mmDCORE0_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x40F1A80ull |
|---|
| 8366 | #define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8367 | #define DCORE0_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8368 | #define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x40F1B00ull |
|---|
| 8369 | #define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8370 | #define DCORE0_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8371 | #define mmDCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x40F1B80ull |
|---|
| 8372 | #define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8373 | #define DCORE0_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8374 | #define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x40F1C00ull |
|---|
| 8375 | #define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8376 | #define DCORE0_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8377 | #define mmDCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x40F1D80ull |
|---|
| 8378 | #define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8379 | #define DCORE0_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8380 | #define mmDCORE0_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x40F1E80ull |
|---|
| 8381 | #define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8382 | #define DCORE0_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 8383 | #define mmDCORE0_MME_ACC_BASE 0x40F8000ull |
|---|
| 8384 | #define DCORE0_MME_ACC_MAX_OFFSET 0x1000 |
|---|
| 8385 | #define DCORE0_MME_ACC_SECTION 0xE800 |
|---|
| 8386 | #define mmDCORE0_MME_ACC_SPECIAL_BASE 0x40F8E80ull |
|---|
| 8387 | #define DCORE0_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8388 | #define DCORE0_MME_ACC_SPECIAL_SECTION 0x1800 |
|---|
| 8389 | #define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x40F9000ull |
|---|
| 8390 | #define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8391 | #define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8392 | #define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x40F9200ull |
|---|
| 8393 | #define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8394 | #define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8395 | #define mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x40F9400ull |
|---|
| 8396 | #define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8397 | #define DCORE0_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8398 | #define mmDCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x40F9600ull |
|---|
| 8399 | #define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8400 | #define DCORE0_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8401 | #define mmDCORE0_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x40F9800ull |
|---|
| 8402 | #define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8403 | #define DCORE0_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8404 | #define mmDCORE0_MME_WB0_MSTR_IF_AXUSER_BASE 0x40F9A80ull |
|---|
| 8405 | #define DCORE0_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8406 | #define DCORE0_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8407 | #define mmDCORE0_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x40F9B00ull |
|---|
| 8408 | #define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8409 | #define DCORE0_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8410 | #define mmDCORE0_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x40F9B80ull |
|---|
| 8411 | #define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8412 | #define DCORE0_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8413 | #define mmDCORE0_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x40F9C00ull |
|---|
| 8414 | #define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8415 | #define DCORE0_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8416 | #define mmDCORE0_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x40F9D80ull |
|---|
| 8417 | #define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8418 | #define DCORE0_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8419 | #define mmDCORE0_MME_WB0_MSTR_IF_SPECIAL_BASE 0x40F9E80ull |
|---|
| 8420 | #define DCORE0_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8421 | #define DCORE0_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8422 | #define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x40FA000ull |
|---|
| 8423 | #define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8424 | #define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8425 | #define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x40FA200ull |
|---|
| 8426 | #define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8427 | #define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8428 | #define mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x40FA400ull |
|---|
| 8429 | #define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8430 | #define DCORE0_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8431 | #define mmDCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x40FA600ull |
|---|
| 8432 | #define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8433 | #define DCORE0_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8434 | #define mmDCORE0_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x40FA800ull |
|---|
| 8435 | #define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8436 | #define DCORE0_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8437 | #define mmDCORE0_MME_WB1_MSTR_IF_AXUSER_BASE 0x40FAA80ull |
|---|
| 8438 | #define DCORE0_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8439 | #define DCORE0_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8440 | #define mmDCORE0_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x40FAB00ull |
|---|
| 8441 | #define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8442 | #define DCORE0_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8443 | #define mmDCORE0_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x40FAB80ull |
|---|
| 8444 | #define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8445 | #define DCORE0_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8446 | #define mmDCORE0_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x40FAC00ull |
|---|
| 8447 | #define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8448 | #define DCORE0_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8449 | #define mmDCORE0_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x40FAD80ull |
|---|
| 8450 | #define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8451 | #define DCORE0_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8452 | #define mmDCORE0_MME_WB1_MSTR_IF_SPECIAL_BASE 0x40FAE80ull |
|---|
| 8453 | #define DCORE0_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8454 | #define DCORE0_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 |
|---|
| 8455 | #define mmDCORE0_SYNC_MNGR_OBJS_BASE 0x4100000ull |
|---|
| 8456 | #define DCORE0_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 |
|---|
| 8457 | #define DCORE0_SYNC_MNGR_OBJS_SECTION 0x1E000 |
|---|
| 8458 | #define mmDCORE0_SYNC_MNGR_GLBL_BASE 0x411E000ull |
|---|
| 8459 | #define DCORE0_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 |
|---|
| 8460 | #define DCORE0_SYNC_MNGR_GLBL_SECTION 0xE800 |
|---|
| 8461 | #define mmDCORE0_SYNC_MNGR_GLBL_SPECIAL_BASE 0x411EE80ull |
|---|
| 8462 | #define DCORE0_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8463 | #define DCORE0_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 |
|---|
| 8464 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x411F000ull |
|---|
| 8465 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8466 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8467 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x411F200ull |
|---|
| 8468 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8469 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8470 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x411F400ull |
|---|
| 8471 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8472 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8473 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x411F600ull |
|---|
| 8474 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8475 | #define DCORE0_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8476 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x411F800ull |
|---|
| 8477 | #define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8478 | #define DCORE0_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8479 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x411FA80ull |
|---|
| 8480 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8481 | #define DCORE0_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8482 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x411FB00ull |
|---|
| 8483 | #define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8484 | #define DCORE0_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8485 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x411FB80ull |
|---|
| 8486 | #define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8487 | #define DCORE0_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8488 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x411FC00ull |
|---|
| 8489 | #define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8490 | #define DCORE0_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8491 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x411FD80ull |
|---|
| 8492 | #define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8493 | #define DCORE0_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8494 | #define mmDCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x411FE80ull |
|---|
| 8495 | #define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8496 | #define DCORE0_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8497 | #define mmDCORE0_HIF0_BASE 0x4120000ull |
|---|
| 8498 | #define DCORE0_HIF0_MAX_OFFSET 0x1000 |
|---|
| 8499 | #define DCORE0_HIF0_SECTION 0xE800 |
|---|
| 8500 | #define mmDCORE0_HIF0_SPECIAL_BASE 0x4120E80ull |
|---|
| 8501 | #define DCORE0_HIF0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8502 | #define DCORE0_HIF0_SPECIAL_SECTION 0x3180 |
|---|
| 8503 | #define mmDCORE0_HIF1_BASE 0x4124000ull |
|---|
| 8504 | #define DCORE0_HIF1_MAX_OFFSET 0x1000 |
|---|
| 8505 | #define DCORE0_HIF1_SECTION 0xE800 |
|---|
| 8506 | #define mmDCORE0_HIF1_SPECIAL_BASE 0x4124E80ull |
|---|
| 8507 | #define DCORE0_HIF1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8508 | #define DCORE0_HIF1_SPECIAL_SECTION 0x3180 |
|---|
| 8509 | #define mmDCORE0_HIF2_BASE 0x4128000ull |
|---|
| 8510 | #define DCORE0_HIF2_MAX_OFFSET 0x1000 |
|---|
| 8511 | #define DCORE0_HIF2_SECTION 0xE800 |
|---|
| 8512 | #define mmDCORE0_HIF2_SPECIAL_BASE 0x4128E80ull |
|---|
| 8513 | #define DCORE0_HIF2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8514 | #define DCORE0_HIF2_SPECIAL_SECTION 0x3180 |
|---|
| 8515 | #define mmDCORE0_HIF3_BASE 0x412C000ull |
|---|
| 8516 | #define DCORE0_HIF3_MAX_OFFSET 0x1000 |
|---|
| 8517 | #define DCORE0_HIF3_SECTION 0xE800 |
|---|
| 8518 | #define mmDCORE0_HIF3_SPECIAL_BASE 0x412CE80ull |
|---|
| 8519 | #define DCORE0_HIF3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8520 | #define DCORE0_HIF3_SPECIAL_SECTION 0x13180 |
|---|
| 8521 | #define mmDCORE0_RTR0_CTRL_BASE 0x4140000ull |
|---|
| 8522 | #define DCORE0_RTR0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 8523 | #define DCORE0_RTR0_CTRL_SECTION 0xE800 |
|---|
| 8524 | #define mmDCORE0_RTR0_CTRL_SPECIAL_BASE 0x4140E80ull |
|---|
| 8525 | #define DCORE0_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8526 | #define DCORE0_RTR0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 8527 | #define mmDCORE0_RTR0_H3_BASE 0x4141000ull |
|---|
| 8528 | #define DCORE0_RTR0_H3_MAX_OFFSET 0x1000 |
|---|
| 8529 | #define DCORE0_RTR0_H3_SECTION 0xE800 |
|---|
| 8530 | #define mmDCORE0_RTR0_H3_SPECIAL_BASE 0x4141E80ull |
|---|
| 8531 | #define DCORE0_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8532 | #define DCORE0_RTR0_H3_SPECIAL_SECTION 0x1800 |
|---|
| 8533 | #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4142000ull |
|---|
| 8534 | #define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8535 | #define DCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8536 | #define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4142200ull |
|---|
| 8537 | #define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8538 | #define DCORE0_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8539 | #define mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4142400ull |
|---|
| 8540 | #define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8541 | #define DCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8542 | #define mmDCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4142600ull |
|---|
| 8543 | #define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8544 | #define DCORE0_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8545 | #define mmDCORE0_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4142800ull |
|---|
| 8546 | #define DCORE0_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8547 | #define DCORE0_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8548 | #define mmDCORE0_RTR0_MSTR_IF_AXUSER_BASE 0x4142A80ull |
|---|
| 8549 | #define DCORE0_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8550 | #define DCORE0_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8551 | #define mmDCORE0_RTR0_MSTR_IF_DBG_HBW_BASE 0x4142B00ull |
|---|
| 8552 | #define DCORE0_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8553 | #define DCORE0_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8554 | #define mmDCORE0_RTR0_MSTR_IF_DBG_LBW_BASE 0x4142B80ull |
|---|
| 8555 | #define DCORE0_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8556 | #define DCORE0_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8557 | #define mmDCORE0_RTR0_MSTR_IF_CORE_HBW_BASE 0x4142C00ull |
|---|
| 8558 | #define DCORE0_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8559 | #define DCORE0_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8560 | #define mmDCORE0_RTR0_MSTR_IF_CORE_LBW_BASE 0x4142D80ull |
|---|
| 8561 | #define DCORE0_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8562 | #define DCORE0_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8563 | #define mmDCORE0_RTR0_MSTR_IF_SPECIAL_BASE 0x4142E80ull |
|---|
| 8564 | #define DCORE0_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8565 | #define DCORE0_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8566 | #define mmDCORE0_RTR0_ADD_DEC_HBW_BASE 0x4143000ull |
|---|
| 8567 | #define DCORE0_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 8568 | #define DCORE0_RTR0_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 8569 | #define mmDCORE0_RTR0_ADD_DEC_LBW_BASE 0x4143400ull |
|---|
| 8570 | #define DCORE0_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 8571 | #define DCORE0_RTR0_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 8572 | #define mmDCORE0_RTR0_ADD_DEC_SPECIAL_BASE 0x4143E80ull |
|---|
| 8573 | #define DCORE0_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8574 | #define DCORE0_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 8575 | #define mmDCORE0_RTR0_BASE 0x4144000ull |
|---|
| 8576 | #define DCORE0_RTR0_MAX_OFFSET 0x1000 |
|---|
| 8577 | #define DCORE0_RTR0_SECTION 0x3000 |
|---|
| 8578 | #define mmDCORE0_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4144300ull |
|---|
| 8579 | #define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8580 | #define DCORE0_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8581 | #define mmDCORE0_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4144340ull |
|---|
| 8582 | #define DCORE0_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8583 | #define DCORE0_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8584 | #define mmDCORE0_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4144380ull |
|---|
| 8585 | #define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8586 | #define DCORE0_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8587 | #define mmDCORE0_RTR0_HBW_WR_RS_LL_STAT_BASE 0x41443C0ull |
|---|
| 8588 | #define DCORE0_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8589 | #define DCORE0_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8590 | #define mmDCORE0_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4144400ull |
|---|
| 8591 | #define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8592 | #define DCORE0_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8593 | #define mmDCORE0_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4144440ull |
|---|
| 8594 | #define DCORE0_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8595 | #define DCORE0_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8596 | #define mmDCORE0_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4144480ull |
|---|
| 8597 | #define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8598 | #define DCORE0_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8599 | #define mmDCORE0_RTR0_LBW_WR_RS_LL_STAT_BASE 0x41444C0ull |
|---|
| 8600 | #define DCORE0_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8601 | #define DCORE0_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8602 | #define mmDCORE0_RTR0_HBW_MFIFO_BASE 0x4144500ull |
|---|
| 8603 | #define DCORE0_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 8604 | #define DCORE0_RTR0_HBW_MFIFO_SECTION 0x4000 |
|---|
| 8605 | #define mmDCORE0_RTR0_E2E_RD_LL_STAT_BASE 0x4144540ull |
|---|
| 8606 | #define DCORE0_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8607 | #define DCORE0_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 8608 | #define mmDCORE0_RTR0_E2E_WR_LL_STAT_BASE 0x4144580ull |
|---|
| 8609 | #define DCORE0_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8610 | #define DCORE0_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 8611 | #define mmDCORE0_RTR0_RTR_HBW_XACT_STAT_BASE 0x4144600ull |
|---|
| 8612 | #define DCORE0_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8613 | #define DCORE0_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8614 | #define mmDCORE0_RTR0_RTR_LBW_XACT_STAT_BASE 0x4144680ull |
|---|
| 8615 | #define DCORE0_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8616 | #define DCORE0_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8617 | #define mmDCORE0_RTR0_RTR_E2E_XACT_STAT_BASE 0x4144700ull |
|---|
| 8618 | #define DCORE0_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8619 | #define DCORE0_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 8620 | #define mmDCORE0_RTR0_SPECIAL_BASE 0x4144E80ull |
|---|
| 8621 | #define DCORE0_RTR0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8622 | #define DCORE0_RTR0_SPECIAL_SECTION 0x1800 |
|---|
| 8623 | #define mmDCORE0_RTR0_DBG_ADDR_BASE 0x4145000ull |
|---|
| 8624 | #define DCORE0_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 8625 | #define DCORE0_RTR0_DBG_ADDR_SECTION 0xE800 |
|---|
| 8626 | #define mmDCORE0_RTR0_DBG_ADDR_SPECIAL_BASE 0x4145E80ull |
|---|
| 8627 | #define DCORE0_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8628 | #define DCORE0_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 8629 | #define mmDCORE0_RTR1_CTRL_BASE 0x4148000ull |
|---|
| 8630 | #define DCORE0_RTR1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 8631 | #define DCORE0_RTR1_CTRL_SECTION 0xE800 |
|---|
| 8632 | #define mmDCORE0_RTR1_CTRL_SPECIAL_BASE 0x4148E80ull |
|---|
| 8633 | #define DCORE0_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8634 | #define DCORE0_RTR1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 8635 | #define mmDCORE0_RTR1_H3_BASE 0x4149000ull |
|---|
| 8636 | #define DCORE0_RTR1_H3_MAX_OFFSET 0x1000 |
|---|
| 8637 | #define DCORE0_RTR1_H3_SECTION 0xE800 |
|---|
| 8638 | #define mmDCORE0_RTR1_H3_SPECIAL_BASE 0x4149E80ull |
|---|
| 8639 | #define DCORE0_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8640 | #define DCORE0_RTR1_H3_SPECIAL_SECTION 0x1800 |
|---|
| 8641 | #define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x414A000ull |
|---|
| 8642 | #define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8643 | #define DCORE0_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8644 | #define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x414A200ull |
|---|
| 8645 | #define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8646 | #define DCORE0_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8647 | #define mmDCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x414A400ull |
|---|
| 8648 | #define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8649 | #define DCORE0_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8650 | #define mmDCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x414A600ull |
|---|
| 8651 | #define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8652 | #define DCORE0_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8653 | #define mmDCORE0_RTR1_MSTR_IF_E2E_CRDT_BASE 0x414A800ull |
|---|
| 8654 | #define DCORE0_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8655 | #define DCORE0_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8656 | #define mmDCORE0_RTR1_MSTR_IF_AXUSER_BASE 0x414AA80ull |
|---|
| 8657 | #define DCORE0_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8658 | #define DCORE0_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8659 | #define mmDCORE0_RTR1_MSTR_IF_DBG_HBW_BASE 0x414AB00ull |
|---|
| 8660 | #define DCORE0_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8661 | #define DCORE0_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8662 | #define mmDCORE0_RTR1_MSTR_IF_DBG_LBW_BASE 0x414AB80ull |
|---|
| 8663 | #define DCORE0_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8664 | #define DCORE0_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8665 | #define mmDCORE0_RTR1_MSTR_IF_CORE_HBW_BASE 0x414AC00ull |
|---|
| 8666 | #define DCORE0_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8667 | #define DCORE0_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8668 | #define mmDCORE0_RTR1_MSTR_IF_CORE_LBW_BASE 0x414AD80ull |
|---|
| 8669 | #define DCORE0_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8670 | #define DCORE0_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8671 | #define mmDCORE0_RTR1_MSTR_IF_SPECIAL_BASE 0x414AE80ull |
|---|
| 8672 | #define DCORE0_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8673 | #define DCORE0_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8674 | #define mmDCORE0_RTR1_ADD_DEC_HBW_BASE 0x414B000ull |
|---|
| 8675 | #define DCORE0_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 8676 | #define DCORE0_RTR1_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 8677 | #define mmDCORE0_RTR1_ADD_DEC_LBW_BASE 0x414B400ull |
|---|
| 8678 | #define DCORE0_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 8679 | #define DCORE0_RTR1_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 8680 | #define mmDCORE0_RTR1_ADD_DEC_SPECIAL_BASE 0x414BE80ull |
|---|
| 8681 | #define DCORE0_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8682 | #define DCORE0_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 8683 | #define mmDCORE0_RTR1_BASE 0x414C000ull |
|---|
| 8684 | #define DCORE0_RTR1_MAX_OFFSET 0x1000 |
|---|
| 8685 | #define DCORE0_RTR1_SECTION 0x3000 |
|---|
| 8686 | #define mmDCORE0_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x414C300ull |
|---|
| 8687 | #define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8688 | #define DCORE0_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8689 | #define mmDCORE0_RTR1_HBW_RD_RS_LL_STAT_BASE 0x414C340ull |
|---|
| 8690 | #define DCORE0_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8691 | #define DCORE0_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8692 | #define mmDCORE0_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x414C380ull |
|---|
| 8693 | #define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8694 | #define DCORE0_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8695 | #define mmDCORE0_RTR1_HBW_WR_RS_LL_STAT_BASE 0x414C3C0ull |
|---|
| 8696 | #define DCORE0_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8697 | #define DCORE0_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8698 | #define mmDCORE0_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x414C400ull |
|---|
| 8699 | #define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8700 | #define DCORE0_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8701 | #define mmDCORE0_RTR1_LBW_RD_RS_LL_STAT_BASE 0x414C440ull |
|---|
| 8702 | #define DCORE0_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8703 | #define DCORE0_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8704 | #define mmDCORE0_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x414C480ull |
|---|
| 8705 | #define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8706 | #define DCORE0_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8707 | #define mmDCORE0_RTR1_LBW_WR_RS_LL_STAT_BASE 0x414C4C0ull |
|---|
| 8708 | #define DCORE0_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8709 | #define DCORE0_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8710 | #define mmDCORE0_RTR1_HBW_MFIFO_BASE 0x414C500ull |
|---|
| 8711 | #define DCORE0_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 8712 | #define DCORE0_RTR1_HBW_MFIFO_SECTION 0x4000 |
|---|
| 8713 | #define mmDCORE0_RTR1_E2E_RD_LL_STAT_BASE 0x414C540ull |
|---|
| 8714 | #define DCORE0_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8715 | #define DCORE0_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 8716 | #define mmDCORE0_RTR1_E2E_WR_LL_STAT_BASE 0x414C580ull |
|---|
| 8717 | #define DCORE0_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8718 | #define DCORE0_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 8719 | #define mmDCORE0_RTR1_RTR_HBW_XACT_STAT_BASE 0x414C600ull |
|---|
| 8720 | #define DCORE0_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8721 | #define DCORE0_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8722 | #define mmDCORE0_RTR1_RTR_LBW_XACT_STAT_BASE 0x414C680ull |
|---|
| 8723 | #define DCORE0_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8724 | #define DCORE0_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8725 | #define mmDCORE0_RTR1_RTR_E2E_XACT_STAT_BASE 0x414C700ull |
|---|
| 8726 | #define DCORE0_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8727 | #define DCORE0_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 8728 | #define mmDCORE0_RTR1_SPECIAL_BASE 0x414CE80ull |
|---|
| 8729 | #define DCORE0_RTR1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8730 | #define DCORE0_RTR1_SPECIAL_SECTION 0x1800 |
|---|
| 8731 | #define mmDCORE0_RTR1_DBG_ADDR_BASE 0x414D000ull |
|---|
| 8732 | #define DCORE0_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 8733 | #define DCORE0_RTR1_DBG_ADDR_SECTION 0xE800 |
|---|
| 8734 | #define mmDCORE0_RTR1_DBG_ADDR_SPECIAL_BASE 0x414DE80ull |
|---|
| 8735 | #define DCORE0_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8736 | #define DCORE0_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 8737 | #define mmDCORE0_RTR2_CTRL_BASE 0x4150000ull |
|---|
| 8738 | #define DCORE0_RTR2_CTRL_MAX_OFFSET 0x1000 |
|---|
| 8739 | #define DCORE0_RTR2_CTRL_SECTION 0xE800 |
|---|
| 8740 | #define mmDCORE0_RTR2_CTRL_SPECIAL_BASE 0x4150E80ull |
|---|
| 8741 | #define DCORE0_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8742 | #define DCORE0_RTR2_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 8743 | #define mmDCORE0_RTR2_H3_BASE 0x4151000ull |
|---|
| 8744 | #define DCORE0_RTR2_H3_MAX_OFFSET 0x1000 |
|---|
| 8745 | #define DCORE0_RTR2_H3_SECTION 0xE800 |
|---|
| 8746 | #define mmDCORE0_RTR2_H3_SPECIAL_BASE 0x4151E80ull |
|---|
| 8747 | #define DCORE0_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8748 | #define DCORE0_RTR2_H3_SPECIAL_SECTION 0x1800 |
|---|
| 8749 | #define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4152000ull |
|---|
| 8750 | #define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8751 | #define DCORE0_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8752 | #define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4152200ull |
|---|
| 8753 | #define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8754 | #define DCORE0_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8755 | #define mmDCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4152400ull |
|---|
| 8756 | #define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8757 | #define DCORE0_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8758 | #define mmDCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4152600ull |
|---|
| 8759 | #define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8760 | #define DCORE0_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8761 | #define mmDCORE0_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4152800ull |
|---|
| 8762 | #define DCORE0_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8763 | #define DCORE0_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8764 | #define mmDCORE0_RTR2_MSTR_IF_AXUSER_BASE 0x4152A80ull |
|---|
| 8765 | #define DCORE0_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8766 | #define DCORE0_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8767 | #define mmDCORE0_RTR2_MSTR_IF_DBG_HBW_BASE 0x4152B00ull |
|---|
| 8768 | #define DCORE0_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8769 | #define DCORE0_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8770 | #define mmDCORE0_RTR2_MSTR_IF_DBG_LBW_BASE 0x4152B80ull |
|---|
| 8771 | #define DCORE0_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8772 | #define DCORE0_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8773 | #define mmDCORE0_RTR2_MSTR_IF_CORE_HBW_BASE 0x4152C00ull |
|---|
| 8774 | #define DCORE0_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8775 | #define DCORE0_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8776 | #define mmDCORE0_RTR2_MSTR_IF_CORE_LBW_BASE 0x4152D80ull |
|---|
| 8777 | #define DCORE0_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8778 | #define DCORE0_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8779 | #define mmDCORE0_RTR2_MSTR_IF_SPECIAL_BASE 0x4152E80ull |
|---|
| 8780 | #define DCORE0_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8781 | #define DCORE0_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8782 | #define mmDCORE0_RTR2_ADD_DEC_HBW_BASE 0x4153000ull |
|---|
| 8783 | #define DCORE0_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 8784 | #define DCORE0_RTR2_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 8785 | #define mmDCORE0_RTR2_ADD_DEC_LBW_BASE 0x4153400ull |
|---|
| 8786 | #define DCORE0_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 8787 | #define DCORE0_RTR2_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 8788 | #define mmDCORE0_RTR2_ADD_DEC_SPECIAL_BASE 0x4153E80ull |
|---|
| 8789 | #define DCORE0_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8790 | #define DCORE0_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 8791 | #define mmDCORE0_RTR2_BASE 0x4154000ull |
|---|
| 8792 | #define DCORE0_RTR2_MAX_OFFSET 0x1000 |
|---|
| 8793 | #define DCORE0_RTR2_SECTION 0x3000 |
|---|
| 8794 | #define mmDCORE0_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4154300ull |
|---|
| 8795 | #define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8796 | #define DCORE0_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8797 | #define mmDCORE0_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4154340ull |
|---|
| 8798 | #define DCORE0_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8799 | #define DCORE0_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8800 | #define mmDCORE0_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4154380ull |
|---|
| 8801 | #define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8802 | #define DCORE0_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8803 | #define mmDCORE0_RTR2_HBW_WR_RS_LL_STAT_BASE 0x41543C0ull |
|---|
| 8804 | #define DCORE0_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8805 | #define DCORE0_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8806 | #define mmDCORE0_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4154400ull |
|---|
| 8807 | #define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8808 | #define DCORE0_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8809 | #define mmDCORE0_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4154440ull |
|---|
| 8810 | #define DCORE0_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8811 | #define DCORE0_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8812 | #define mmDCORE0_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4154480ull |
|---|
| 8813 | #define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8814 | #define DCORE0_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8815 | #define mmDCORE0_RTR2_LBW_WR_RS_LL_STAT_BASE 0x41544C0ull |
|---|
| 8816 | #define DCORE0_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8817 | #define DCORE0_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8818 | #define mmDCORE0_RTR2_HBW_MFIFO_BASE 0x4154500ull |
|---|
| 8819 | #define DCORE0_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 8820 | #define DCORE0_RTR2_HBW_MFIFO_SECTION 0x4000 |
|---|
| 8821 | #define mmDCORE0_RTR2_E2E_RD_LL_STAT_BASE 0x4154540ull |
|---|
| 8822 | #define DCORE0_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8823 | #define DCORE0_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 8824 | #define mmDCORE0_RTR2_E2E_WR_LL_STAT_BASE 0x4154580ull |
|---|
| 8825 | #define DCORE0_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8826 | #define DCORE0_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 8827 | #define mmDCORE0_RTR2_RTR_HBW_XACT_STAT_BASE 0x4154600ull |
|---|
| 8828 | #define DCORE0_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8829 | #define DCORE0_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8830 | #define mmDCORE0_RTR2_RTR_LBW_XACT_STAT_BASE 0x4154680ull |
|---|
| 8831 | #define DCORE0_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8832 | #define DCORE0_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8833 | #define mmDCORE0_RTR2_RTR_E2E_XACT_STAT_BASE 0x4154700ull |
|---|
| 8834 | #define DCORE0_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8835 | #define DCORE0_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 8836 | #define mmDCORE0_RTR2_SPECIAL_BASE 0x4154E80ull |
|---|
| 8837 | #define DCORE0_RTR2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8838 | #define DCORE0_RTR2_SPECIAL_SECTION 0x1800 |
|---|
| 8839 | #define mmDCORE0_RTR2_DBG_ADDR_BASE 0x4155000ull |
|---|
| 8840 | #define DCORE0_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 8841 | #define DCORE0_RTR2_DBG_ADDR_SECTION 0xE800 |
|---|
| 8842 | #define mmDCORE0_RTR2_DBG_ADDR_SPECIAL_BASE 0x4155E80ull |
|---|
| 8843 | #define DCORE0_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8844 | #define DCORE0_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 8845 | #define mmDCORE0_RTR3_CTRL_BASE 0x4158000ull |
|---|
| 8846 | #define DCORE0_RTR3_CTRL_MAX_OFFSET 0x1000 |
|---|
| 8847 | #define DCORE0_RTR3_CTRL_SECTION 0xE800 |
|---|
| 8848 | #define mmDCORE0_RTR3_CTRL_SPECIAL_BASE 0x4158E80ull |
|---|
| 8849 | #define DCORE0_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8850 | #define DCORE0_RTR3_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 8851 | #define mmDCORE0_RTR3_H3_BASE 0x4159000ull |
|---|
| 8852 | #define DCORE0_RTR3_H3_MAX_OFFSET 0x1000 |
|---|
| 8853 | #define DCORE0_RTR3_H3_SECTION 0xE800 |
|---|
| 8854 | #define mmDCORE0_RTR3_H3_SPECIAL_BASE 0x4159E80ull |
|---|
| 8855 | #define DCORE0_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8856 | #define DCORE0_RTR3_H3_SPECIAL_SECTION 0x1800 |
|---|
| 8857 | #define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x415A000ull |
|---|
| 8858 | #define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8859 | #define DCORE0_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8860 | #define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x415A200ull |
|---|
| 8861 | #define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8862 | #define DCORE0_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8863 | #define mmDCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x415A400ull |
|---|
| 8864 | #define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8865 | #define DCORE0_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8866 | #define mmDCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x415A600ull |
|---|
| 8867 | #define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8868 | #define DCORE0_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8869 | #define mmDCORE0_RTR3_MSTR_IF_E2E_CRDT_BASE 0x415A800ull |
|---|
| 8870 | #define DCORE0_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8871 | #define DCORE0_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8872 | #define mmDCORE0_RTR3_MSTR_IF_AXUSER_BASE 0x415AA80ull |
|---|
| 8873 | #define DCORE0_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8874 | #define DCORE0_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8875 | #define mmDCORE0_RTR3_MSTR_IF_DBG_HBW_BASE 0x415AB00ull |
|---|
| 8876 | #define DCORE0_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8877 | #define DCORE0_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8878 | #define mmDCORE0_RTR3_MSTR_IF_DBG_LBW_BASE 0x415AB80ull |
|---|
| 8879 | #define DCORE0_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8880 | #define DCORE0_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8881 | #define mmDCORE0_RTR3_MSTR_IF_CORE_HBW_BASE 0x415AC00ull |
|---|
| 8882 | #define DCORE0_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8883 | #define DCORE0_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8884 | #define mmDCORE0_RTR3_MSTR_IF_CORE_LBW_BASE 0x415AD80ull |
|---|
| 8885 | #define DCORE0_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8886 | #define DCORE0_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8887 | #define mmDCORE0_RTR3_MSTR_IF_SPECIAL_BASE 0x415AE80ull |
|---|
| 8888 | #define DCORE0_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8889 | #define DCORE0_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8890 | #define mmDCORE0_RTR3_ADD_DEC_HBW_BASE 0x415B000ull |
|---|
| 8891 | #define DCORE0_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 8892 | #define DCORE0_RTR3_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 8893 | #define mmDCORE0_RTR3_ADD_DEC_LBW_BASE 0x415B400ull |
|---|
| 8894 | #define DCORE0_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 8895 | #define DCORE0_RTR3_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 8896 | #define mmDCORE0_RTR3_ADD_DEC_SPECIAL_BASE 0x415BE80ull |
|---|
| 8897 | #define DCORE0_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8898 | #define DCORE0_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 8899 | #define mmDCORE0_RTR3_BASE 0x415C000ull |
|---|
| 8900 | #define DCORE0_RTR3_MAX_OFFSET 0x1000 |
|---|
| 8901 | #define DCORE0_RTR3_SECTION 0x3000 |
|---|
| 8902 | #define mmDCORE0_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x415C300ull |
|---|
| 8903 | #define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8904 | #define DCORE0_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8905 | #define mmDCORE0_RTR3_HBW_RD_RS_LL_STAT_BASE 0x415C340ull |
|---|
| 8906 | #define DCORE0_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8907 | #define DCORE0_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8908 | #define mmDCORE0_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x415C380ull |
|---|
| 8909 | #define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8910 | #define DCORE0_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8911 | #define mmDCORE0_RTR3_HBW_WR_RS_LL_STAT_BASE 0x415C3C0ull |
|---|
| 8912 | #define DCORE0_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8913 | #define DCORE0_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8914 | #define mmDCORE0_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x415C400ull |
|---|
| 8915 | #define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8916 | #define DCORE0_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8917 | #define mmDCORE0_RTR3_LBW_RD_RS_LL_STAT_BASE 0x415C440ull |
|---|
| 8918 | #define DCORE0_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8919 | #define DCORE0_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8920 | #define mmDCORE0_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x415C480ull |
|---|
| 8921 | #define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8922 | #define DCORE0_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 8923 | #define mmDCORE0_RTR3_LBW_WR_RS_LL_STAT_BASE 0x415C4C0ull |
|---|
| 8924 | #define DCORE0_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8925 | #define DCORE0_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 8926 | #define mmDCORE0_RTR3_HBW_MFIFO_BASE 0x415C500ull |
|---|
| 8927 | #define DCORE0_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 8928 | #define DCORE0_RTR3_HBW_MFIFO_SECTION 0x4000 |
|---|
| 8929 | #define mmDCORE0_RTR3_E2E_RD_LL_STAT_BASE 0x415C540ull |
|---|
| 8930 | #define DCORE0_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8931 | #define DCORE0_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 8932 | #define mmDCORE0_RTR3_E2E_WR_LL_STAT_BASE 0x415C580ull |
|---|
| 8933 | #define DCORE0_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 8934 | #define DCORE0_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 8935 | #define mmDCORE0_RTR3_RTR_HBW_XACT_STAT_BASE 0x415C600ull |
|---|
| 8936 | #define DCORE0_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8937 | #define DCORE0_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8938 | #define mmDCORE0_RTR3_RTR_LBW_XACT_STAT_BASE 0x415C680ull |
|---|
| 8939 | #define DCORE0_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8940 | #define DCORE0_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 8941 | #define mmDCORE0_RTR3_RTR_E2E_XACT_STAT_BASE 0x415C700ull |
|---|
| 8942 | #define DCORE0_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 8943 | #define DCORE0_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 8944 | #define mmDCORE0_RTR3_SPECIAL_BASE 0x415CE80ull |
|---|
| 8945 | #define DCORE0_RTR3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8946 | #define DCORE0_RTR3_SPECIAL_SECTION 0x1800 |
|---|
| 8947 | #define mmDCORE0_RTR3_DBG_ADDR_BASE 0x415D000ull |
|---|
| 8948 | #define DCORE0_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 8949 | #define DCORE0_RTR3_DBG_ADDR_SECTION 0xE800 |
|---|
| 8950 | #define mmDCORE0_RTR3_DBG_ADDR_SPECIAL_BASE 0x415DE80ull |
|---|
| 8951 | #define DCORE0_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8952 | #define DCORE0_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 8953 | #define mmDCORE0_RTR4_CTRL_BASE 0x4160000ull |
|---|
| 8954 | #define DCORE0_RTR4_CTRL_MAX_OFFSET 0x1000 |
|---|
| 8955 | #define DCORE0_RTR4_CTRL_SECTION 0xE800 |
|---|
| 8956 | #define mmDCORE0_RTR4_CTRL_SPECIAL_BASE 0x4160E80ull |
|---|
| 8957 | #define DCORE0_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8958 | #define DCORE0_RTR4_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 8959 | #define mmDCORE0_RTR4_H3_BASE 0x4161000ull |
|---|
| 8960 | #define DCORE0_RTR4_H3_MAX_OFFSET 0x1000 |
|---|
| 8961 | #define DCORE0_RTR4_H3_SECTION 0xE800 |
|---|
| 8962 | #define mmDCORE0_RTR4_H3_SPECIAL_BASE 0x4161E80ull |
|---|
| 8963 | #define DCORE0_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8964 | #define DCORE0_RTR4_H3_SPECIAL_SECTION 0x1800 |
|---|
| 8965 | #define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4162000ull |
|---|
| 8966 | #define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8967 | #define DCORE0_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 8968 | #define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4162200ull |
|---|
| 8969 | #define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 8970 | #define DCORE0_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 8971 | #define mmDCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4162400ull |
|---|
| 8972 | #define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8973 | #define DCORE0_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 8974 | #define mmDCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4162600ull |
|---|
| 8975 | #define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 8976 | #define DCORE0_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 8977 | #define mmDCORE0_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4162800ull |
|---|
| 8978 | #define DCORE0_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 8979 | #define DCORE0_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 8980 | #define mmDCORE0_RTR4_MSTR_IF_AXUSER_BASE 0x4162A80ull |
|---|
| 8981 | #define DCORE0_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 8982 | #define DCORE0_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 8983 | #define mmDCORE0_RTR4_MSTR_IF_DBG_HBW_BASE 0x4162B00ull |
|---|
| 8984 | #define DCORE0_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 8985 | #define DCORE0_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 8986 | #define mmDCORE0_RTR4_MSTR_IF_DBG_LBW_BASE 0x4162B80ull |
|---|
| 8987 | #define DCORE0_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 8988 | #define DCORE0_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 8989 | #define mmDCORE0_RTR4_MSTR_IF_CORE_HBW_BASE 0x4162C00ull |
|---|
| 8990 | #define DCORE0_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 8991 | #define DCORE0_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 8992 | #define mmDCORE0_RTR4_MSTR_IF_CORE_LBW_BASE 0x4162D80ull |
|---|
| 8993 | #define DCORE0_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 8994 | #define DCORE0_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 8995 | #define mmDCORE0_RTR4_MSTR_IF_SPECIAL_BASE 0x4162E80ull |
|---|
| 8996 | #define DCORE0_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 8997 | #define DCORE0_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 8998 | #define mmDCORE0_RTR4_ADD_DEC_HBW_BASE 0x4163000ull |
|---|
| 8999 | #define DCORE0_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 9000 | #define DCORE0_RTR4_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 9001 | #define mmDCORE0_RTR4_ADD_DEC_LBW_BASE 0x4163400ull |
|---|
| 9002 | #define DCORE0_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 9003 | #define DCORE0_RTR4_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 9004 | #define mmDCORE0_RTR4_ADD_DEC_SPECIAL_BASE 0x4163E80ull |
|---|
| 9005 | #define DCORE0_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9006 | #define DCORE0_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 9007 | #define mmDCORE0_RTR4_BASE 0x4164000ull |
|---|
| 9008 | #define DCORE0_RTR4_MAX_OFFSET 0x1000 |
|---|
| 9009 | #define DCORE0_RTR4_SECTION 0x3000 |
|---|
| 9010 | #define mmDCORE0_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4164300ull |
|---|
| 9011 | #define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9012 | #define DCORE0_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9013 | #define mmDCORE0_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4164340ull |
|---|
| 9014 | #define DCORE0_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9015 | #define DCORE0_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9016 | #define mmDCORE0_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4164380ull |
|---|
| 9017 | #define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9018 | #define DCORE0_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9019 | #define mmDCORE0_RTR4_HBW_WR_RS_LL_STAT_BASE 0x41643C0ull |
|---|
| 9020 | #define DCORE0_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9021 | #define DCORE0_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9022 | #define mmDCORE0_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4164400ull |
|---|
| 9023 | #define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9024 | #define DCORE0_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9025 | #define mmDCORE0_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4164440ull |
|---|
| 9026 | #define DCORE0_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9027 | #define DCORE0_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9028 | #define mmDCORE0_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4164480ull |
|---|
| 9029 | #define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9030 | #define DCORE0_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9031 | #define mmDCORE0_RTR4_LBW_WR_RS_LL_STAT_BASE 0x41644C0ull |
|---|
| 9032 | #define DCORE0_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9033 | #define DCORE0_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9034 | #define mmDCORE0_RTR4_HBW_MFIFO_BASE 0x4164500ull |
|---|
| 9035 | #define DCORE0_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 9036 | #define DCORE0_RTR4_HBW_MFIFO_SECTION 0x4000 |
|---|
| 9037 | #define mmDCORE0_RTR4_E2E_RD_LL_STAT_BASE 0x4164540ull |
|---|
| 9038 | #define DCORE0_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9039 | #define DCORE0_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 9040 | #define mmDCORE0_RTR4_E2E_WR_LL_STAT_BASE 0x4164580ull |
|---|
| 9041 | #define DCORE0_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9042 | #define DCORE0_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 9043 | #define mmDCORE0_RTR4_RTR_HBW_XACT_STAT_BASE 0x4164600ull |
|---|
| 9044 | #define DCORE0_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9045 | #define DCORE0_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9046 | #define mmDCORE0_RTR4_RTR_LBW_XACT_STAT_BASE 0x4164680ull |
|---|
| 9047 | #define DCORE0_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9048 | #define DCORE0_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9049 | #define mmDCORE0_RTR4_RTR_E2E_XACT_STAT_BASE 0x4164700ull |
|---|
| 9050 | #define DCORE0_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9051 | #define DCORE0_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 9052 | #define mmDCORE0_RTR4_SPECIAL_BASE 0x4164E80ull |
|---|
| 9053 | #define DCORE0_RTR4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9054 | #define DCORE0_RTR4_SPECIAL_SECTION 0x1800 |
|---|
| 9055 | #define mmDCORE0_RTR4_DBG_ADDR_BASE 0x4165000ull |
|---|
| 9056 | #define DCORE0_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 9057 | #define DCORE0_RTR4_DBG_ADDR_SECTION 0xE800 |
|---|
| 9058 | #define mmDCORE0_RTR4_DBG_ADDR_SPECIAL_BASE 0x4165E80ull |
|---|
| 9059 | #define DCORE0_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9060 | #define DCORE0_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 9061 | #define mmDCORE0_RTR5_CTRL_BASE 0x4168000ull |
|---|
| 9062 | #define DCORE0_RTR5_CTRL_MAX_OFFSET 0x1000 |
|---|
| 9063 | #define DCORE0_RTR5_CTRL_SECTION 0xE800 |
|---|
| 9064 | #define mmDCORE0_RTR5_CTRL_SPECIAL_BASE 0x4168E80ull |
|---|
| 9065 | #define DCORE0_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9066 | #define DCORE0_RTR5_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 9067 | #define mmDCORE0_RTR5_H3_BASE 0x4169000ull |
|---|
| 9068 | #define DCORE0_RTR5_H3_MAX_OFFSET 0x1000 |
|---|
| 9069 | #define DCORE0_RTR5_H3_SECTION 0xE800 |
|---|
| 9070 | #define mmDCORE0_RTR5_H3_SPECIAL_BASE 0x4169E80ull |
|---|
| 9071 | #define DCORE0_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9072 | #define DCORE0_RTR5_H3_SPECIAL_SECTION 0x1800 |
|---|
| 9073 | #define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x416A000ull |
|---|
| 9074 | #define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9075 | #define DCORE0_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 9076 | #define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x416A200ull |
|---|
| 9077 | #define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9078 | #define DCORE0_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 9079 | #define mmDCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x416A400ull |
|---|
| 9080 | #define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9081 | #define DCORE0_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 9082 | #define mmDCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x416A600ull |
|---|
| 9083 | #define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9084 | #define DCORE0_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 9085 | #define mmDCORE0_RTR5_MSTR_IF_E2E_CRDT_BASE 0x416A800ull |
|---|
| 9086 | #define DCORE0_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 9087 | #define DCORE0_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 9088 | #define mmDCORE0_RTR5_MSTR_IF_AXUSER_BASE 0x416AA80ull |
|---|
| 9089 | #define DCORE0_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 9090 | #define DCORE0_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 9091 | #define mmDCORE0_RTR5_MSTR_IF_DBG_HBW_BASE 0x416AB00ull |
|---|
| 9092 | #define DCORE0_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 9093 | #define DCORE0_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 9094 | #define mmDCORE0_RTR5_MSTR_IF_DBG_LBW_BASE 0x416AB80ull |
|---|
| 9095 | #define DCORE0_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 9096 | #define DCORE0_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 9097 | #define mmDCORE0_RTR5_MSTR_IF_CORE_HBW_BASE 0x416AC00ull |
|---|
| 9098 | #define DCORE0_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 9099 | #define DCORE0_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 9100 | #define mmDCORE0_RTR5_MSTR_IF_CORE_LBW_BASE 0x416AD80ull |
|---|
| 9101 | #define DCORE0_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 9102 | #define DCORE0_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 9103 | #define mmDCORE0_RTR5_MSTR_IF_SPECIAL_BASE 0x416AE80ull |
|---|
| 9104 | #define DCORE0_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9105 | #define DCORE0_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 9106 | #define mmDCORE0_RTR5_ADD_DEC_HBW_BASE 0x416B000ull |
|---|
| 9107 | #define DCORE0_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 9108 | #define DCORE0_RTR5_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 9109 | #define mmDCORE0_RTR5_ADD_DEC_LBW_BASE 0x416B400ull |
|---|
| 9110 | #define DCORE0_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 9111 | #define DCORE0_RTR5_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 9112 | #define mmDCORE0_RTR5_ADD_DEC_SPECIAL_BASE 0x416BE80ull |
|---|
| 9113 | #define DCORE0_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9114 | #define DCORE0_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 9115 | #define mmDCORE0_RTR5_BASE 0x416C000ull |
|---|
| 9116 | #define DCORE0_RTR5_MAX_OFFSET 0x1000 |
|---|
| 9117 | #define DCORE0_RTR5_SECTION 0x3000 |
|---|
| 9118 | #define mmDCORE0_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x416C300ull |
|---|
| 9119 | #define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9120 | #define DCORE0_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9121 | #define mmDCORE0_RTR5_HBW_RD_RS_LL_STAT_BASE 0x416C340ull |
|---|
| 9122 | #define DCORE0_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9123 | #define DCORE0_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9124 | #define mmDCORE0_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x416C380ull |
|---|
| 9125 | #define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9126 | #define DCORE0_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9127 | #define mmDCORE0_RTR5_HBW_WR_RS_LL_STAT_BASE 0x416C3C0ull |
|---|
| 9128 | #define DCORE0_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9129 | #define DCORE0_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9130 | #define mmDCORE0_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x416C400ull |
|---|
| 9131 | #define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9132 | #define DCORE0_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9133 | #define mmDCORE0_RTR5_LBW_RD_RS_LL_STAT_BASE 0x416C440ull |
|---|
| 9134 | #define DCORE0_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9135 | #define DCORE0_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9136 | #define mmDCORE0_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x416C480ull |
|---|
| 9137 | #define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9138 | #define DCORE0_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9139 | #define mmDCORE0_RTR5_LBW_WR_RS_LL_STAT_BASE 0x416C4C0ull |
|---|
| 9140 | #define DCORE0_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9141 | #define DCORE0_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9142 | #define mmDCORE0_RTR5_HBW_MFIFO_BASE 0x416C500ull |
|---|
| 9143 | #define DCORE0_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 9144 | #define DCORE0_RTR5_HBW_MFIFO_SECTION 0x4000 |
|---|
| 9145 | #define mmDCORE0_RTR5_E2E_RD_LL_STAT_BASE 0x416C540ull |
|---|
| 9146 | #define DCORE0_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9147 | #define DCORE0_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 9148 | #define mmDCORE0_RTR5_E2E_WR_LL_STAT_BASE 0x416C580ull |
|---|
| 9149 | #define DCORE0_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9150 | #define DCORE0_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 9151 | #define mmDCORE0_RTR5_RTR_HBW_XACT_STAT_BASE 0x416C600ull |
|---|
| 9152 | #define DCORE0_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9153 | #define DCORE0_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9154 | #define mmDCORE0_RTR5_RTR_LBW_XACT_STAT_BASE 0x416C680ull |
|---|
| 9155 | #define DCORE0_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9156 | #define DCORE0_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9157 | #define mmDCORE0_RTR5_RTR_E2E_XACT_STAT_BASE 0x416C700ull |
|---|
| 9158 | #define DCORE0_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9159 | #define DCORE0_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 9160 | #define mmDCORE0_RTR5_SPECIAL_BASE 0x416CE80ull |
|---|
| 9161 | #define DCORE0_RTR5_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9162 | #define DCORE0_RTR5_SPECIAL_SECTION 0x1800 |
|---|
| 9163 | #define mmDCORE0_RTR5_DBG_ADDR_BASE 0x416D000ull |
|---|
| 9164 | #define DCORE0_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 9165 | #define DCORE0_RTR5_DBG_ADDR_SECTION 0xE800 |
|---|
| 9166 | #define mmDCORE0_RTR5_DBG_ADDR_SPECIAL_BASE 0x416DE80ull |
|---|
| 9167 | #define DCORE0_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9168 | #define DCORE0_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 9169 | #define mmDCORE0_RTR6_CTRL_BASE 0x4170000ull |
|---|
| 9170 | #define DCORE0_RTR6_CTRL_MAX_OFFSET 0x1000 |
|---|
| 9171 | #define DCORE0_RTR6_CTRL_SECTION 0xE800 |
|---|
| 9172 | #define mmDCORE0_RTR6_CTRL_SPECIAL_BASE 0x4170E80ull |
|---|
| 9173 | #define DCORE0_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9174 | #define DCORE0_RTR6_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 9175 | #define mmDCORE0_RTR6_H3_BASE 0x4171000ull |
|---|
| 9176 | #define DCORE0_RTR6_H3_MAX_OFFSET 0x1000 |
|---|
| 9177 | #define DCORE0_RTR6_H3_SECTION 0xE800 |
|---|
| 9178 | #define mmDCORE0_RTR6_H3_SPECIAL_BASE 0x4171E80ull |
|---|
| 9179 | #define DCORE0_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9180 | #define DCORE0_RTR6_H3_SPECIAL_SECTION 0x1800 |
|---|
| 9181 | #define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4172000ull |
|---|
| 9182 | #define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9183 | #define DCORE0_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 9184 | #define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4172200ull |
|---|
| 9185 | #define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9186 | #define DCORE0_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 9187 | #define mmDCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4172400ull |
|---|
| 9188 | #define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9189 | #define DCORE0_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 9190 | #define mmDCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4172600ull |
|---|
| 9191 | #define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9192 | #define DCORE0_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 9193 | #define mmDCORE0_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4172800ull |
|---|
| 9194 | #define DCORE0_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 9195 | #define DCORE0_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 9196 | #define mmDCORE0_RTR6_MSTR_IF_AXUSER_BASE 0x4172A80ull |
|---|
| 9197 | #define DCORE0_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 9198 | #define DCORE0_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 9199 | #define mmDCORE0_RTR6_MSTR_IF_DBG_HBW_BASE 0x4172B00ull |
|---|
| 9200 | #define DCORE0_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 9201 | #define DCORE0_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 9202 | #define mmDCORE0_RTR6_MSTR_IF_DBG_LBW_BASE 0x4172B80ull |
|---|
| 9203 | #define DCORE0_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 9204 | #define DCORE0_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 9205 | #define mmDCORE0_RTR6_MSTR_IF_CORE_HBW_BASE 0x4172C00ull |
|---|
| 9206 | #define DCORE0_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 9207 | #define DCORE0_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 9208 | #define mmDCORE0_RTR6_MSTR_IF_CORE_LBW_BASE 0x4172D80ull |
|---|
| 9209 | #define DCORE0_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 9210 | #define DCORE0_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 9211 | #define mmDCORE0_RTR6_MSTR_IF_SPECIAL_BASE 0x4172E80ull |
|---|
| 9212 | #define DCORE0_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9213 | #define DCORE0_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 9214 | #define mmDCORE0_RTR6_ADD_DEC_HBW_BASE 0x4173000ull |
|---|
| 9215 | #define DCORE0_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 9216 | #define DCORE0_RTR6_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 9217 | #define mmDCORE0_RTR6_ADD_DEC_LBW_BASE 0x4173400ull |
|---|
| 9218 | #define DCORE0_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 9219 | #define DCORE0_RTR6_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 9220 | #define mmDCORE0_RTR6_ADD_DEC_SPECIAL_BASE 0x4173E80ull |
|---|
| 9221 | #define DCORE0_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9222 | #define DCORE0_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 9223 | #define mmDCORE0_RTR6_BASE 0x4174000ull |
|---|
| 9224 | #define DCORE0_RTR6_MAX_OFFSET 0x1000 |
|---|
| 9225 | #define DCORE0_RTR6_SECTION 0x3000 |
|---|
| 9226 | #define mmDCORE0_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4174300ull |
|---|
| 9227 | #define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9228 | #define DCORE0_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9229 | #define mmDCORE0_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4174340ull |
|---|
| 9230 | #define DCORE0_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9231 | #define DCORE0_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9232 | #define mmDCORE0_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4174380ull |
|---|
| 9233 | #define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9234 | #define DCORE0_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9235 | #define mmDCORE0_RTR6_HBW_WR_RS_LL_STAT_BASE 0x41743C0ull |
|---|
| 9236 | #define DCORE0_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9237 | #define DCORE0_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9238 | #define mmDCORE0_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4174400ull |
|---|
| 9239 | #define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9240 | #define DCORE0_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9241 | #define mmDCORE0_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4174440ull |
|---|
| 9242 | #define DCORE0_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9243 | #define DCORE0_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9244 | #define mmDCORE0_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4174480ull |
|---|
| 9245 | #define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9246 | #define DCORE0_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9247 | #define mmDCORE0_RTR6_LBW_WR_RS_LL_STAT_BASE 0x41744C0ull |
|---|
| 9248 | #define DCORE0_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9249 | #define DCORE0_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9250 | #define mmDCORE0_RTR6_HBW_MFIFO_BASE 0x4174500ull |
|---|
| 9251 | #define DCORE0_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 9252 | #define DCORE0_RTR6_HBW_MFIFO_SECTION 0x4000 |
|---|
| 9253 | #define mmDCORE0_RTR6_E2E_RD_LL_STAT_BASE 0x4174540ull |
|---|
| 9254 | #define DCORE0_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9255 | #define DCORE0_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 9256 | #define mmDCORE0_RTR6_E2E_WR_LL_STAT_BASE 0x4174580ull |
|---|
| 9257 | #define DCORE0_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9258 | #define DCORE0_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 9259 | #define mmDCORE0_RTR6_RTR_HBW_XACT_STAT_BASE 0x4174600ull |
|---|
| 9260 | #define DCORE0_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9261 | #define DCORE0_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9262 | #define mmDCORE0_RTR6_RTR_LBW_XACT_STAT_BASE 0x4174680ull |
|---|
| 9263 | #define DCORE0_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9264 | #define DCORE0_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9265 | #define mmDCORE0_RTR6_RTR_E2E_XACT_STAT_BASE 0x4174700ull |
|---|
| 9266 | #define DCORE0_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9267 | #define DCORE0_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 9268 | #define mmDCORE0_RTR6_SPECIAL_BASE 0x4174E80ull |
|---|
| 9269 | #define DCORE0_RTR6_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9270 | #define DCORE0_RTR6_SPECIAL_SECTION 0x1800 |
|---|
| 9271 | #define mmDCORE0_RTR6_DBG_ADDR_BASE 0x4175000ull |
|---|
| 9272 | #define DCORE0_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 9273 | #define DCORE0_RTR6_DBG_ADDR_SECTION 0xE800 |
|---|
| 9274 | #define mmDCORE0_RTR6_DBG_ADDR_SPECIAL_BASE 0x4175E80ull |
|---|
| 9275 | #define DCORE0_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9276 | #define DCORE0_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 9277 | #define mmDCORE0_RTR7_CTRL_BASE 0x4178000ull |
|---|
| 9278 | #define DCORE0_RTR7_CTRL_MAX_OFFSET 0x1000 |
|---|
| 9279 | #define DCORE0_RTR7_CTRL_SECTION 0xE800 |
|---|
| 9280 | #define mmDCORE0_RTR7_CTRL_SPECIAL_BASE 0x4178E80ull |
|---|
| 9281 | #define DCORE0_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9282 | #define DCORE0_RTR7_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 9283 | #define mmDCORE0_RTR7_H3_BASE 0x4179000ull |
|---|
| 9284 | #define DCORE0_RTR7_H3_MAX_OFFSET 0x1000 |
|---|
| 9285 | #define DCORE0_RTR7_H3_SECTION 0xE800 |
|---|
| 9286 | #define mmDCORE0_RTR7_H3_SPECIAL_BASE 0x4179E80ull |
|---|
| 9287 | #define DCORE0_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9288 | #define DCORE0_RTR7_H3_SPECIAL_SECTION 0x1800 |
|---|
| 9289 | #define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x417A000ull |
|---|
| 9290 | #define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9291 | #define DCORE0_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 9292 | #define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x417A200ull |
|---|
| 9293 | #define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9294 | #define DCORE0_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 9295 | #define mmDCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x417A400ull |
|---|
| 9296 | #define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9297 | #define DCORE0_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 9298 | #define mmDCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x417A600ull |
|---|
| 9299 | #define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9300 | #define DCORE0_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 9301 | #define mmDCORE0_RTR7_MSTR_IF_E2E_CRDT_BASE 0x417A800ull |
|---|
| 9302 | #define DCORE0_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 9303 | #define DCORE0_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 9304 | #define mmDCORE0_RTR7_MSTR_IF_AXUSER_BASE 0x417AA80ull |
|---|
| 9305 | #define DCORE0_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 9306 | #define DCORE0_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 9307 | #define mmDCORE0_RTR7_MSTR_IF_DBG_HBW_BASE 0x417AB00ull |
|---|
| 9308 | #define DCORE0_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 9309 | #define DCORE0_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 9310 | #define mmDCORE0_RTR7_MSTR_IF_DBG_LBW_BASE 0x417AB80ull |
|---|
| 9311 | #define DCORE0_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 9312 | #define DCORE0_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 9313 | #define mmDCORE0_RTR7_MSTR_IF_CORE_HBW_BASE 0x417AC00ull |
|---|
| 9314 | #define DCORE0_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 9315 | #define DCORE0_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 9316 | #define mmDCORE0_RTR7_MSTR_IF_CORE_LBW_BASE 0x417AD80ull |
|---|
| 9317 | #define DCORE0_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 9318 | #define DCORE0_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 9319 | #define mmDCORE0_RTR7_MSTR_IF_SPECIAL_BASE 0x417AE80ull |
|---|
| 9320 | #define DCORE0_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9321 | #define DCORE0_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 9322 | #define mmDCORE0_RTR7_ADD_DEC_HBW_BASE 0x417B000ull |
|---|
| 9323 | #define DCORE0_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 9324 | #define DCORE0_RTR7_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 9325 | #define mmDCORE0_RTR7_ADD_DEC_LBW_BASE 0x417B400ull |
|---|
| 9326 | #define DCORE0_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 9327 | #define DCORE0_RTR7_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 9328 | #define mmDCORE0_RTR7_ADD_DEC_SPECIAL_BASE 0x417BE80ull |
|---|
| 9329 | #define DCORE0_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9330 | #define DCORE0_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 9331 | #define mmDCORE0_RTR7_BASE 0x417C000ull |
|---|
| 9332 | #define DCORE0_RTR7_MAX_OFFSET 0x1000 |
|---|
| 9333 | #define DCORE0_RTR7_SECTION 0x3000 |
|---|
| 9334 | #define mmDCORE0_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x417C300ull |
|---|
| 9335 | #define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9336 | #define DCORE0_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9337 | #define mmDCORE0_RTR7_HBW_RD_RS_LL_STAT_BASE 0x417C340ull |
|---|
| 9338 | #define DCORE0_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9339 | #define DCORE0_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9340 | #define mmDCORE0_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x417C380ull |
|---|
| 9341 | #define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9342 | #define DCORE0_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9343 | #define mmDCORE0_RTR7_HBW_WR_RS_LL_STAT_BASE 0x417C3C0ull |
|---|
| 9344 | #define DCORE0_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9345 | #define DCORE0_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9346 | #define mmDCORE0_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x417C400ull |
|---|
| 9347 | #define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9348 | #define DCORE0_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9349 | #define mmDCORE0_RTR7_LBW_RD_RS_LL_STAT_BASE 0x417C440ull |
|---|
| 9350 | #define DCORE0_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9351 | #define DCORE0_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9352 | #define mmDCORE0_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x417C480ull |
|---|
| 9353 | #define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9354 | #define DCORE0_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 9355 | #define mmDCORE0_RTR7_LBW_WR_RS_LL_STAT_BASE 0x417C4C0ull |
|---|
| 9356 | #define DCORE0_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9357 | #define DCORE0_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 9358 | #define mmDCORE0_RTR7_HBW_MFIFO_BASE 0x417C500ull |
|---|
| 9359 | #define DCORE0_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 9360 | #define DCORE0_RTR7_HBW_MFIFO_SECTION 0x4000 |
|---|
| 9361 | #define mmDCORE0_RTR7_E2E_RD_LL_STAT_BASE 0x417C540ull |
|---|
| 9362 | #define DCORE0_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9363 | #define DCORE0_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 9364 | #define mmDCORE0_RTR7_E2E_WR_LL_STAT_BASE 0x417C580ull |
|---|
| 9365 | #define DCORE0_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 9366 | #define DCORE0_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 9367 | #define mmDCORE0_RTR7_RTR_HBW_XACT_STAT_BASE 0x417C600ull |
|---|
| 9368 | #define DCORE0_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9369 | #define DCORE0_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9370 | #define mmDCORE0_RTR7_RTR_LBW_XACT_STAT_BASE 0x417C680ull |
|---|
| 9371 | #define DCORE0_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9372 | #define DCORE0_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 9373 | #define mmDCORE0_RTR7_RTR_E2E_XACT_STAT_BASE 0x417C700ull |
|---|
| 9374 | #define DCORE0_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 9375 | #define DCORE0_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 9376 | #define mmDCORE0_RTR7_SPECIAL_BASE 0x417CE80ull |
|---|
| 9377 | #define DCORE0_RTR7_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9378 | #define DCORE0_RTR7_SPECIAL_SECTION 0x1800 |
|---|
| 9379 | #define mmDCORE0_RTR7_DBG_ADDR_BASE 0x417D000ull |
|---|
| 9380 | #define DCORE0_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 9381 | #define DCORE0_RTR7_DBG_ADDR_SECTION 0xE800 |
|---|
| 9382 | #define mmDCORE0_RTR7_DBG_ADDR_SPECIAL_BASE 0x417DE80ull |
|---|
| 9383 | #define DCORE0_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9384 | #define DCORE0_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 9385 | #define mmDCORE0_SRAM0_BANK_BASE 0x4180000ull |
|---|
| 9386 | #define DCORE0_SRAM0_BANK_MAX_OFFSET 0x1000 |
|---|
| 9387 | #define DCORE0_SRAM0_BANK_SECTION 0xE800 |
|---|
| 9388 | #define mmDCORE0_SRAM0_BANK_SPECIAL_BASE 0x4180E80ull |
|---|
| 9389 | #define DCORE0_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9390 | #define DCORE0_SRAM0_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9391 | #define mmDCORE0_SRAM0_RTR_BASE 0x4181000ull |
|---|
| 9392 | #define DCORE0_SRAM0_RTR_MAX_OFFSET 0x1000 |
|---|
| 9393 | #define DCORE0_SRAM0_RTR_SECTION 0xE800 |
|---|
| 9394 | #define mmDCORE0_SRAM0_RTR_SPECIAL_BASE 0x4181E80ull |
|---|
| 9395 | #define DCORE0_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9396 | #define DCORE0_SRAM0_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9397 | #define mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4182000ull |
|---|
| 9398 | #define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9399 | #define DCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9400 | #define mmDCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4182100ull |
|---|
| 9401 | #define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9402 | #define DCORE0_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9403 | #define mmDCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4182200ull |
|---|
| 9404 | #define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9405 | #define DCORE0_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9406 | #define mmDCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4182300ull |
|---|
| 9407 | #define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9408 | #define DCORE0_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9409 | #define mmDCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4182400ull |
|---|
| 9410 | #define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9411 | #define DCORE0_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9412 | #define mmDCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4182500ull |
|---|
| 9413 | #define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9414 | #define DCORE0_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9415 | #define mmDCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4182600ull |
|---|
| 9416 | #define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9417 | #define DCORE0_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9418 | #define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4182700ull |
|---|
| 9419 | #define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9420 | #define DCORE0_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9421 | #define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4182780ull |
|---|
| 9422 | #define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9423 | #define DCORE0_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9424 | #define mmDCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4182800ull |
|---|
| 9425 | #define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9426 | #define DCORE0_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9427 | #define mmDCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4182880ull |
|---|
| 9428 | #define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9429 | #define DCORE0_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9430 | #define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4182900ull |
|---|
| 9431 | #define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9432 | #define DCORE0_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9433 | #define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4182980ull |
|---|
| 9434 | #define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9435 | #define DCORE0_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9436 | #define mmDCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4182A00ull |
|---|
| 9437 | #define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9438 | #define DCORE0_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9439 | #define mmDCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4182A80ull |
|---|
| 9440 | #define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9441 | #define DCORE0_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9442 | #define mmDCORE0_SRAM0_DBG_CNT_SPECIAL_BASE 0x4182E80ull |
|---|
| 9443 | #define DCORE0_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9444 | #define DCORE0_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9445 | #define mmDCORE0_SRAM1_BANK_BASE 0x4188000ull |
|---|
| 9446 | #define DCORE0_SRAM1_BANK_MAX_OFFSET 0x1000 |
|---|
| 9447 | #define DCORE0_SRAM1_BANK_SECTION 0xE800 |
|---|
| 9448 | #define mmDCORE0_SRAM1_BANK_SPECIAL_BASE 0x4188E80ull |
|---|
| 9449 | #define DCORE0_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9450 | #define DCORE0_SRAM1_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9451 | #define mmDCORE0_SRAM1_RTR_BASE 0x4189000ull |
|---|
| 9452 | #define DCORE0_SRAM1_RTR_MAX_OFFSET 0x1000 |
|---|
| 9453 | #define DCORE0_SRAM1_RTR_SECTION 0xE800 |
|---|
| 9454 | #define mmDCORE0_SRAM1_RTR_SPECIAL_BASE 0x4189E80ull |
|---|
| 9455 | #define DCORE0_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9456 | #define DCORE0_SRAM1_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9457 | #define mmDCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x418A000ull |
|---|
| 9458 | #define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9459 | #define DCORE0_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9460 | #define mmDCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x418A100ull |
|---|
| 9461 | #define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9462 | #define DCORE0_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9463 | #define mmDCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x418A200ull |
|---|
| 9464 | #define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9465 | #define DCORE0_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9466 | #define mmDCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x418A300ull |
|---|
| 9467 | #define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9468 | #define DCORE0_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9469 | #define mmDCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x418A400ull |
|---|
| 9470 | #define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9471 | #define DCORE0_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9472 | #define mmDCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x418A500ull |
|---|
| 9473 | #define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9474 | #define DCORE0_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9475 | #define mmDCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x418A600ull |
|---|
| 9476 | #define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9477 | #define DCORE0_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9478 | #define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x418A700ull |
|---|
| 9479 | #define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9480 | #define DCORE0_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9481 | #define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x418A780ull |
|---|
| 9482 | #define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9483 | #define DCORE0_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9484 | #define mmDCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x418A800ull |
|---|
| 9485 | #define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9486 | #define DCORE0_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9487 | #define mmDCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x418A880ull |
|---|
| 9488 | #define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9489 | #define DCORE0_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9490 | #define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x418A900ull |
|---|
| 9491 | #define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9492 | #define DCORE0_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9493 | #define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x418A980ull |
|---|
| 9494 | #define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9495 | #define DCORE0_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9496 | #define mmDCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x418AA00ull |
|---|
| 9497 | #define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9498 | #define DCORE0_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9499 | #define mmDCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x418AA80ull |
|---|
| 9500 | #define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9501 | #define DCORE0_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9502 | #define mmDCORE0_SRAM1_DBG_CNT_SPECIAL_BASE 0x418AE80ull |
|---|
| 9503 | #define DCORE0_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9504 | #define DCORE0_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9505 | #define mmDCORE0_SRAM2_BANK_BASE 0x4190000ull |
|---|
| 9506 | #define DCORE0_SRAM2_BANK_MAX_OFFSET 0x1000 |
|---|
| 9507 | #define DCORE0_SRAM2_BANK_SECTION 0xE800 |
|---|
| 9508 | #define mmDCORE0_SRAM2_BANK_SPECIAL_BASE 0x4190E80ull |
|---|
| 9509 | #define DCORE0_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9510 | #define DCORE0_SRAM2_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9511 | #define mmDCORE0_SRAM2_RTR_BASE 0x4191000ull |
|---|
| 9512 | #define DCORE0_SRAM2_RTR_MAX_OFFSET 0x1000 |
|---|
| 9513 | #define DCORE0_SRAM2_RTR_SECTION 0xE800 |
|---|
| 9514 | #define mmDCORE0_SRAM2_RTR_SPECIAL_BASE 0x4191E80ull |
|---|
| 9515 | #define DCORE0_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9516 | #define DCORE0_SRAM2_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9517 | #define mmDCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4192000ull |
|---|
| 9518 | #define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9519 | #define DCORE0_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9520 | #define mmDCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4192100ull |
|---|
| 9521 | #define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9522 | #define DCORE0_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9523 | #define mmDCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4192200ull |
|---|
| 9524 | #define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9525 | #define DCORE0_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9526 | #define mmDCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4192300ull |
|---|
| 9527 | #define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9528 | #define DCORE0_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9529 | #define mmDCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4192400ull |
|---|
| 9530 | #define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9531 | #define DCORE0_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9532 | #define mmDCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4192500ull |
|---|
| 9533 | #define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9534 | #define DCORE0_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9535 | #define mmDCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4192600ull |
|---|
| 9536 | #define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9537 | #define DCORE0_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9538 | #define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4192700ull |
|---|
| 9539 | #define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9540 | #define DCORE0_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9541 | #define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4192780ull |
|---|
| 9542 | #define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9543 | #define DCORE0_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9544 | #define mmDCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4192800ull |
|---|
| 9545 | #define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9546 | #define DCORE0_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9547 | #define mmDCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4192880ull |
|---|
| 9548 | #define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9549 | #define DCORE0_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9550 | #define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4192900ull |
|---|
| 9551 | #define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9552 | #define DCORE0_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9553 | #define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4192980ull |
|---|
| 9554 | #define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9555 | #define DCORE0_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9556 | #define mmDCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4192A00ull |
|---|
| 9557 | #define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9558 | #define DCORE0_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9559 | #define mmDCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4192A80ull |
|---|
| 9560 | #define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9561 | #define DCORE0_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9562 | #define mmDCORE0_SRAM2_DBG_CNT_SPECIAL_BASE 0x4192E80ull |
|---|
| 9563 | #define DCORE0_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9564 | #define DCORE0_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9565 | #define mmDCORE0_SRAM3_BANK_BASE 0x4198000ull |
|---|
| 9566 | #define DCORE0_SRAM3_BANK_MAX_OFFSET 0x1000 |
|---|
| 9567 | #define DCORE0_SRAM3_BANK_SECTION 0xE800 |
|---|
| 9568 | #define mmDCORE0_SRAM3_BANK_SPECIAL_BASE 0x4198E80ull |
|---|
| 9569 | #define DCORE0_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9570 | #define DCORE0_SRAM3_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9571 | #define mmDCORE0_SRAM3_RTR_BASE 0x4199000ull |
|---|
| 9572 | #define DCORE0_SRAM3_RTR_MAX_OFFSET 0x1000 |
|---|
| 9573 | #define DCORE0_SRAM3_RTR_SECTION 0xE800 |
|---|
| 9574 | #define mmDCORE0_SRAM3_RTR_SPECIAL_BASE 0x4199E80ull |
|---|
| 9575 | #define DCORE0_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9576 | #define DCORE0_SRAM3_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9577 | #define mmDCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x419A000ull |
|---|
| 9578 | #define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9579 | #define DCORE0_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9580 | #define mmDCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x419A100ull |
|---|
| 9581 | #define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9582 | #define DCORE0_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9583 | #define mmDCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x419A200ull |
|---|
| 9584 | #define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9585 | #define DCORE0_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9586 | #define mmDCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x419A300ull |
|---|
| 9587 | #define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9588 | #define DCORE0_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9589 | #define mmDCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x419A400ull |
|---|
| 9590 | #define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9591 | #define DCORE0_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9592 | #define mmDCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x419A500ull |
|---|
| 9593 | #define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9594 | #define DCORE0_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9595 | #define mmDCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x419A600ull |
|---|
| 9596 | #define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9597 | #define DCORE0_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9598 | #define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x419A700ull |
|---|
| 9599 | #define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9600 | #define DCORE0_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9601 | #define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x419A780ull |
|---|
| 9602 | #define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9603 | #define DCORE0_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9604 | #define mmDCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x419A800ull |
|---|
| 9605 | #define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9606 | #define DCORE0_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9607 | #define mmDCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x419A880ull |
|---|
| 9608 | #define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9609 | #define DCORE0_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9610 | #define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x419A900ull |
|---|
| 9611 | #define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9612 | #define DCORE0_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9613 | #define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x419A980ull |
|---|
| 9614 | #define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9615 | #define DCORE0_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9616 | #define mmDCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x419AA00ull |
|---|
| 9617 | #define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9618 | #define DCORE0_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9619 | #define mmDCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x419AA80ull |
|---|
| 9620 | #define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9621 | #define DCORE0_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9622 | #define mmDCORE0_SRAM3_DBG_CNT_SPECIAL_BASE 0x419AE80ull |
|---|
| 9623 | #define DCORE0_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9624 | #define DCORE0_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9625 | #define mmDCORE0_SRAM4_BANK_BASE 0x41A0000ull |
|---|
| 9626 | #define DCORE0_SRAM4_BANK_MAX_OFFSET 0x1000 |
|---|
| 9627 | #define DCORE0_SRAM4_BANK_SECTION 0xE800 |
|---|
| 9628 | #define mmDCORE0_SRAM4_BANK_SPECIAL_BASE 0x41A0E80ull |
|---|
| 9629 | #define DCORE0_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9630 | #define DCORE0_SRAM4_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9631 | #define mmDCORE0_SRAM4_RTR_BASE 0x41A1000ull |
|---|
| 9632 | #define DCORE0_SRAM4_RTR_MAX_OFFSET 0x1000 |
|---|
| 9633 | #define DCORE0_SRAM4_RTR_SECTION 0xE800 |
|---|
| 9634 | #define mmDCORE0_SRAM4_RTR_SPECIAL_BASE 0x41A1E80ull |
|---|
| 9635 | #define DCORE0_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9636 | #define DCORE0_SRAM4_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9637 | #define mmDCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41A2000ull |
|---|
| 9638 | #define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9639 | #define DCORE0_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9640 | #define mmDCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41A2100ull |
|---|
| 9641 | #define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9642 | #define DCORE0_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9643 | #define mmDCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41A2200ull |
|---|
| 9644 | #define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9645 | #define DCORE0_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9646 | #define mmDCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41A2300ull |
|---|
| 9647 | #define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9648 | #define DCORE0_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9649 | #define mmDCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41A2400ull |
|---|
| 9650 | #define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9651 | #define DCORE0_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9652 | #define mmDCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41A2500ull |
|---|
| 9653 | #define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9654 | #define DCORE0_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9655 | #define mmDCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41A2600ull |
|---|
| 9656 | #define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9657 | #define DCORE0_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9658 | #define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2700ull |
|---|
| 9659 | #define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9660 | #define DCORE0_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9661 | #define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2780ull |
|---|
| 9662 | #define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9663 | #define DCORE0_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9664 | #define mmDCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41A2800ull |
|---|
| 9665 | #define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9666 | #define DCORE0_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9667 | #define mmDCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41A2880ull |
|---|
| 9668 | #define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9669 | #define DCORE0_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9670 | #define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41A2900ull |
|---|
| 9671 | #define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9672 | #define DCORE0_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9673 | #define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41A2980ull |
|---|
| 9674 | #define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9675 | #define DCORE0_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9676 | #define mmDCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41A2A00ull |
|---|
| 9677 | #define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9678 | #define DCORE0_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9679 | #define mmDCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41A2A80ull |
|---|
| 9680 | #define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9681 | #define DCORE0_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9682 | #define mmDCORE0_SRAM4_DBG_CNT_SPECIAL_BASE 0x41A2E80ull |
|---|
| 9683 | #define DCORE0_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9684 | #define DCORE0_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9685 | #define mmDCORE0_SRAM5_BANK_BASE 0x41A8000ull |
|---|
| 9686 | #define DCORE0_SRAM5_BANK_MAX_OFFSET 0x1000 |
|---|
| 9687 | #define DCORE0_SRAM5_BANK_SECTION 0xE800 |
|---|
| 9688 | #define mmDCORE0_SRAM5_BANK_SPECIAL_BASE 0x41A8E80ull |
|---|
| 9689 | #define DCORE0_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9690 | #define DCORE0_SRAM5_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9691 | #define mmDCORE0_SRAM5_RTR_BASE 0x41A9000ull |
|---|
| 9692 | #define DCORE0_SRAM5_RTR_MAX_OFFSET 0x1000 |
|---|
| 9693 | #define DCORE0_SRAM5_RTR_SECTION 0xE800 |
|---|
| 9694 | #define mmDCORE0_SRAM5_RTR_SPECIAL_BASE 0x41A9E80ull |
|---|
| 9695 | #define DCORE0_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9696 | #define DCORE0_SRAM5_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9697 | #define mmDCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41AA000ull |
|---|
| 9698 | #define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9699 | #define DCORE0_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9700 | #define mmDCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41AA100ull |
|---|
| 9701 | #define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9702 | #define DCORE0_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9703 | #define mmDCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41AA200ull |
|---|
| 9704 | #define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9705 | #define DCORE0_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9706 | #define mmDCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41AA300ull |
|---|
| 9707 | #define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9708 | #define DCORE0_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9709 | #define mmDCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41AA400ull |
|---|
| 9710 | #define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9711 | #define DCORE0_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9712 | #define mmDCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41AA500ull |
|---|
| 9713 | #define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9714 | #define DCORE0_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9715 | #define mmDCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41AA600ull |
|---|
| 9716 | #define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9717 | #define DCORE0_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9718 | #define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA700ull |
|---|
| 9719 | #define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9720 | #define DCORE0_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9721 | #define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA780ull |
|---|
| 9722 | #define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9723 | #define DCORE0_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9724 | #define mmDCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41AA800ull |
|---|
| 9725 | #define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9726 | #define DCORE0_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9727 | #define mmDCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41AA880ull |
|---|
| 9728 | #define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9729 | #define DCORE0_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9730 | #define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41AA900ull |
|---|
| 9731 | #define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9732 | #define DCORE0_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9733 | #define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41AA980ull |
|---|
| 9734 | #define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9735 | #define DCORE0_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9736 | #define mmDCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41AAA00ull |
|---|
| 9737 | #define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9738 | #define DCORE0_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9739 | #define mmDCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41AAA80ull |
|---|
| 9740 | #define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9741 | #define DCORE0_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9742 | #define mmDCORE0_SRAM5_DBG_CNT_SPECIAL_BASE 0x41AAE80ull |
|---|
| 9743 | #define DCORE0_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9744 | #define DCORE0_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9745 | #define mmDCORE0_SRAM6_BANK_BASE 0x41B0000ull |
|---|
| 9746 | #define DCORE0_SRAM6_BANK_MAX_OFFSET 0x1000 |
|---|
| 9747 | #define DCORE0_SRAM6_BANK_SECTION 0xE800 |
|---|
| 9748 | #define mmDCORE0_SRAM6_BANK_SPECIAL_BASE 0x41B0E80ull |
|---|
| 9749 | #define DCORE0_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9750 | #define DCORE0_SRAM6_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9751 | #define mmDCORE0_SRAM6_RTR_BASE 0x41B1000ull |
|---|
| 9752 | #define DCORE0_SRAM6_RTR_MAX_OFFSET 0x1000 |
|---|
| 9753 | #define DCORE0_SRAM6_RTR_SECTION 0xE800 |
|---|
| 9754 | #define mmDCORE0_SRAM6_RTR_SPECIAL_BASE 0x41B1E80ull |
|---|
| 9755 | #define DCORE0_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9756 | #define DCORE0_SRAM6_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9757 | #define mmDCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41B2000ull |
|---|
| 9758 | #define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9759 | #define DCORE0_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9760 | #define mmDCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41B2100ull |
|---|
| 9761 | #define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9762 | #define DCORE0_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9763 | #define mmDCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41B2200ull |
|---|
| 9764 | #define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9765 | #define DCORE0_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9766 | #define mmDCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41B2300ull |
|---|
| 9767 | #define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9768 | #define DCORE0_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9769 | #define mmDCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41B2400ull |
|---|
| 9770 | #define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9771 | #define DCORE0_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9772 | #define mmDCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41B2500ull |
|---|
| 9773 | #define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9774 | #define DCORE0_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9775 | #define mmDCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41B2600ull |
|---|
| 9776 | #define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9777 | #define DCORE0_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9778 | #define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2700ull |
|---|
| 9779 | #define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9780 | #define DCORE0_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9781 | #define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2780ull |
|---|
| 9782 | #define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9783 | #define DCORE0_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9784 | #define mmDCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41B2800ull |
|---|
| 9785 | #define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9786 | #define DCORE0_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9787 | #define mmDCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41B2880ull |
|---|
| 9788 | #define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9789 | #define DCORE0_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9790 | #define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41B2900ull |
|---|
| 9791 | #define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9792 | #define DCORE0_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9793 | #define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41B2980ull |
|---|
| 9794 | #define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9795 | #define DCORE0_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9796 | #define mmDCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41B2A00ull |
|---|
| 9797 | #define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9798 | #define DCORE0_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9799 | #define mmDCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41B2A80ull |
|---|
| 9800 | #define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9801 | #define DCORE0_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9802 | #define mmDCORE0_SRAM6_DBG_CNT_SPECIAL_BASE 0x41B2E80ull |
|---|
| 9803 | #define DCORE0_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9804 | #define DCORE0_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9805 | #define mmDCORE0_SRAM7_BANK_BASE 0x41B8000ull |
|---|
| 9806 | #define DCORE0_SRAM7_BANK_MAX_OFFSET 0x1000 |
|---|
| 9807 | #define DCORE0_SRAM7_BANK_SECTION 0xE800 |
|---|
| 9808 | #define mmDCORE0_SRAM7_BANK_SPECIAL_BASE 0x41B8E80ull |
|---|
| 9809 | #define DCORE0_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9810 | #define DCORE0_SRAM7_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 9811 | #define mmDCORE0_SRAM7_RTR_BASE 0x41B9000ull |
|---|
| 9812 | #define DCORE0_SRAM7_RTR_MAX_OFFSET 0x1000 |
|---|
| 9813 | #define DCORE0_SRAM7_RTR_SECTION 0xE800 |
|---|
| 9814 | #define mmDCORE0_SRAM7_RTR_SPECIAL_BASE 0x41B9E80ull |
|---|
| 9815 | #define DCORE0_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9816 | #define DCORE0_SRAM7_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 9817 | #define mmDCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x41BA000ull |
|---|
| 9818 | #define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9819 | #define DCORE0_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9820 | #define mmDCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x41BA100ull |
|---|
| 9821 | #define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9822 | #define DCORE0_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9823 | #define mmDCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x41BA200ull |
|---|
| 9824 | #define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9825 | #define DCORE0_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9826 | #define mmDCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x41BA300ull |
|---|
| 9827 | #define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9828 | #define DCORE0_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9829 | #define mmDCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x41BA400ull |
|---|
| 9830 | #define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9831 | #define DCORE0_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9832 | #define mmDCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x41BA500ull |
|---|
| 9833 | #define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9834 | #define DCORE0_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9835 | #define mmDCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x41BA600ull |
|---|
| 9836 | #define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 9837 | #define DCORE0_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 9838 | #define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA700ull |
|---|
| 9839 | #define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9840 | #define DCORE0_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9841 | #define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA780ull |
|---|
| 9842 | #define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9843 | #define DCORE0_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9844 | #define mmDCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x41BA800ull |
|---|
| 9845 | #define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9846 | #define DCORE0_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9847 | #define mmDCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x41BA880ull |
|---|
| 9848 | #define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9849 | #define DCORE0_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9850 | #define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x41BA900ull |
|---|
| 9851 | #define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9852 | #define DCORE0_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9853 | #define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x41BA980ull |
|---|
| 9854 | #define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9855 | #define DCORE0_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9856 | #define mmDCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x41BAA00ull |
|---|
| 9857 | #define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9858 | #define DCORE0_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 9859 | #define mmDCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x41BAA80ull |
|---|
| 9860 | #define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 9861 | #define DCORE0_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 9862 | #define mmDCORE0_SRAM7_DBG_CNT_SPECIAL_BASE 0x41BAE80ull |
|---|
| 9863 | #define DCORE0_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9864 | #define DCORE0_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 9865 | #define mmDCORE0_EDMA0_QM_DCCM_BASE 0x41C0000ull |
|---|
| 9866 | #define DCORE0_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 9867 | #define DCORE0_EDMA0_QM_DCCM_SECTION 0x8000 |
|---|
| 9868 | #define mmDCORE0_EDMA0_QM_ARC_AUX_BASE 0x41C8000ull |
|---|
| 9869 | #define DCORE0_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 9870 | #define DCORE0_EDMA0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 9871 | #define mmDCORE0_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x41C8E80ull |
|---|
| 9872 | #define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9873 | #define DCORE0_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 9874 | #define mmDCORE0_EDMA0_QM_BASE 0x41CA000ull |
|---|
| 9875 | #define DCORE0_EDMA0_QM_MAX_OFFSET 0x1000 |
|---|
| 9876 | #define DCORE0_EDMA0_QM_SECTION 0x9000 |
|---|
| 9877 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41CA900ull |
|---|
| 9878 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 9879 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 9880 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41CA908ull |
|---|
| 9881 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 9882 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 9883 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41CA910ull |
|---|
| 9884 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 9885 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 9886 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41CA918ull |
|---|
| 9887 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 9888 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 9889 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41CA920ull |
|---|
| 9890 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 9891 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 9892 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41CA928ull |
|---|
| 9893 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 9894 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 9895 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41CA930ull |
|---|
| 9896 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 9897 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 9898 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41CA938ull |
|---|
| 9899 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 9900 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 9901 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41CA940ull |
|---|
| 9902 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 9903 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 9904 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41CA948ull |
|---|
| 9905 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 9906 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 9907 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41CA950ull |
|---|
| 9908 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 9909 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 9910 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41CA958ull |
|---|
| 9911 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 9912 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 9913 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41CA960ull |
|---|
| 9914 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 9915 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 9916 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41CA968ull |
|---|
| 9917 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 9918 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 9919 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41CA970ull |
|---|
| 9920 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 9921 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 9922 | #define mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41CA978ull |
|---|
| 9923 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 9924 | #define DCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 9925 | #define mmDCORE0_EDMA0_QM_AXUSER_SECURED_BASE 0x41CAB00ull |
|---|
| 9926 | #define DCORE0_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 9927 | #define DCORE0_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 9928 | #define mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_BASE 0x41CAB80ull |
|---|
| 9929 | #define DCORE0_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 9930 | #define DCORE0_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 9931 | #define mmDCORE0_EDMA0_QM_DBG_HBW_BASE 0x41CAC00ull |
|---|
| 9932 | #define DCORE0_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 9933 | #define DCORE0_EDMA0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 9934 | #define mmDCORE0_EDMA0_QM_DBG_LBW_BASE 0x41CAC80ull |
|---|
| 9935 | #define DCORE0_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 9936 | #define DCORE0_EDMA0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 9937 | #define mmDCORE0_EDMA0_QM_CGM_BASE 0x41CAD80ull |
|---|
| 9938 | #define DCORE0_EDMA0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 9939 | #define DCORE0_EDMA0_QM_CGM_SECTION 0x1000 |
|---|
| 9940 | #define mmDCORE0_EDMA0_QM_SPECIAL_BASE 0x41CAE80ull |
|---|
| 9941 | #define DCORE0_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9942 | #define DCORE0_EDMA0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 9943 | #define mmDCORE0_EDMA0_CORE_BASE 0x41CB000ull |
|---|
| 9944 | #define DCORE0_EDMA0_CORE_MAX_OFFSET 0x1000 |
|---|
| 9945 | #define DCORE0_EDMA0_CORE_SECTION 0x8000 |
|---|
| 9946 | #define mmDCORE0_EDMA0_CORE_CTX_AXUSER_BASE 0x41CB800ull |
|---|
| 9947 | #define DCORE0_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 9948 | #define DCORE0_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 9949 | #define mmDCORE0_EDMA0_CORE_CTX_BASE 0x41CB860ull |
|---|
| 9950 | #define DCORE0_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 9951 | #define DCORE0_EDMA0_CORE_CTX_SECTION 0x5A00 |
|---|
| 9952 | #define mmDCORE0_EDMA0_CORE_KDMA_CGM_BASE 0x41CBE00ull |
|---|
| 9953 | #define DCORE0_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 9954 | #define DCORE0_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 9955 | #define mmDCORE0_EDMA0_CORE_SPECIAL_BASE 0x41CBE80ull |
|---|
| 9956 | #define DCORE0_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9957 | #define DCORE0_EDMA0_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 9958 | #define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x41CC000ull |
|---|
| 9959 | #define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9960 | #define DCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 9961 | #define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x41CC200ull |
|---|
| 9962 | #define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 9963 | #define DCORE0_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 9964 | #define mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x41CC400ull |
|---|
| 9965 | #define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9966 | #define DCORE0_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 9967 | #define mmDCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x41CC600ull |
|---|
| 9968 | #define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 9969 | #define DCORE0_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 9970 | #define mmDCORE0_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x41CC800ull |
|---|
| 9971 | #define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 9972 | #define DCORE0_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 9973 | #define mmDCORE0_EDMA0_MSTR_IF_AXUSER_BASE 0x41CCA80ull |
|---|
| 9974 | #define DCORE0_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 9975 | #define DCORE0_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 9976 | #define mmDCORE0_EDMA0_MSTR_IF_DBG_HBW_BASE 0x41CCB00ull |
|---|
| 9977 | #define DCORE0_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 9978 | #define DCORE0_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 9979 | #define mmDCORE0_EDMA0_MSTR_IF_DBG_LBW_BASE 0x41CCB80ull |
|---|
| 9980 | #define DCORE0_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 9981 | #define DCORE0_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 9982 | #define mmDCORE0_EDMA0_MSTR_IF_CORE_HBW_BASE 0x41CCC00ull |
|---|
| 9983 | #define DCORE0_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 9984 | #define DCORE0_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 9985 | #define mmDCORE0_EDMA0_MSTR_IF_CORE_LBW_BASE 0x41CCD80ull |
|---|
| 9986 | #define DCORE0_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 9987 | #define DCORE0_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 9988 | #define mmDCORE0_EDMA0_MSTR_IF_SPECIAL_BASE 0x41CCE80ull |
|---|
| 9989 | #define DCORE0_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9990 | #define DCORE0_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 9991 | #define mmDCORE0_EDMA1_QM_DCCM_BASE 0x41D0000ull |
|---|
| 9992 | #define DCORE0_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 9993 | #define DCORE0_EDMA1_QM_DCCM_SECTION 0x8000 |
|---|
| 9994 | #define mmDCORE0_EDMA1_QM_ARC_AUX_BASE 0x41D8000ull |
|---|
| 9995 | #define DCORE0_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 9996 | #define DCORE0_EDMA1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 9997 | #define mmDCORE0_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x41D8E80ull |
|---|
| 9998 | #define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 9999 | #define DCORE0_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 10000 | #define mmDCORE0_EDMA1_QM_BASE 0x41DA000ull |
|---|
| 10001 | #define DCORE0_EDMA1_QM_MAX_OFFSET 0x1000 |
|---|
| 10002 | #define DCORE0_EDMA1_QM_SECTION 0x9000 |
|---|
| 10003 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x41DA900ull |
|---|
| 10004 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 10005 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 10006 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x41DA908ull |
|---|
| 10007 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 10008 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 10009 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x41DA910ull |
|---|
| 10010 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 10011 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 10012 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x41DA918ull |
|---|
| 10013 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 10014 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 10015 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x41DA920ull |
|---|
| 10016 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 10017 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 10018 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x41DA928ull |
|---|
| 10019 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 10020 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 10021 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x41DA930ull |
|---|
| 10022 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 10023 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 10024 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x41DA938ull |
|---|
| 10025 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 10026 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 10027 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x41DA940ull |
|---|
| 10028 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 10029 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 10030 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x41DA948ull |
|---|
| 10031 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 10032 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 10033 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x41DA950ull |
|---|
| 10034 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 10035 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 10036 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x41DA958ull |
|---|
| 10037 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 10038 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 10039 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x41DA960ull |
|---|
| 10040 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 10041 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 10042 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x41DA968ull |
|---|
| 10043 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 10044 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 10045 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x41DA970ull |
|---|
| 10046 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 10047 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 10048 | #define mmDCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x41DA978ull |
|---|
| 10049 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 10050 | #define DCORE0_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 10051 | #define mmDCORE0_EDMA1_QM_AXUSER_SECURED_BASE 0x41DAB00ull |
|---|
| 10052 | #define DCORE0_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 10053 | #define DCORE0_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 10054 | #define mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_BASE 0x41DAB80ull |
|---|
| 10055 | #define DCORE0_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 10056 | #define DCORE0_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 10057 | #define mmDCORE0_EDMA1_QM_DBG_HBW_BASE 0x41DAC00ull |
|---|
| 10058 | #define DCORE0_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10059 | #define DCORE0_EDMA1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 10060 | #define mmDCORE0_EDMA1_QM_DBG_LBW_BASE 0x41DAC80ull |
|---|
| 10061 | #define DCORE0_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10062 | #define DCORE0_EDMA1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 10063 | #define mmDCORE0_EDMA1_QM_CGM_BASE 0x41DAD80ull |
|---|
| 10064 | #define DCORE0_EDMA1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 10065 | #define DCORE0_EDMA1_QM_CGM_SECTION 0x1000 |
|---|
| 10066 | #define mmDCORE0_EDMA1_QM_SPECIAL_BASE 0x41DAE80ull |
|---|
| 10067 | #define DCORE0_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10068 | #define DCORE0_EDMA1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10069 | #define mmDCORE0_EDMA1_CORE_BASE 0x41DB000ull |
|---|
| 10070 | #define DCORE0_EDMA1_CORE_MAX_OFFSET 0x1000 |
|---|
| 10071 | #define DCORE0_EDMA1_CORE_SECTION 0x8000 |
|---|
| 10072 | #define mmDCORE0_EDMA1_CORE_CTX_AXUSER_BASE 0x41DB800ull |
|---|
| 10073 | #define DCORE0_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10074 | #define DCORE0_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 10075 | #define mmDCORE0_EDMA1_CORE_CTX_BASE 0x41DB860ull |
|---|
| 10076 | #define DCORE0_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 10077 | #define DCORE0_EDMA1_CORE_CTX_SECTION 0x5A00 |
|---|
| 10078 | #define mmDCORE0_EDMA1_CORE_KDMA_CGM_BASE 0x41DBE00ull |
|---|
| 10079 | #define DCORE0_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 10080 | #define DCORE0_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 10081 | #define mmDCORE0_EDMA1_CORE_SPECIAL_BASE 0x41DBE80ull |
|---|
| 10082 | #define DCORE0_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10083 | #define DCORE0_EDMA1_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 10084 | #define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x41DC000ull |
|---|
| 10085 | #define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10086 | #define DCORE0_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10087 | #define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x41DC200ull |
|---|
| 10088 | #define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10089 | #define DCORE0_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10090 | #define mmDCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x41DC400ull |
|---|
| 10091 | #define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10092 | #define DCORE0_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10093 | #define mmDCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x41DC600ull |
|---|
| 10094 | #define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10095 | #define DCORE0_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10096 | #define mmDCORE0_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x41DC800ull |
|---|
| 10097 | #define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10098 | #define DCORE0_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10099 | #define mmDCORE0_EDMA1_MSTR_IF_AXUSER_BASE 0x41DCA80ull |
|---|
| 10100 | #define DCORE0_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10101 | #define DCORE0_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10102 | #define mmDCORE0_EDMA1_MSTR_IF_DBG_HBW_BASE 0x41DCB00ull |
|---|
| 10103 | #define DCORE0_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10104 | #define DCORE0_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10105 | #define mmDCORE0_EDMA1_MSTR_IF_DBG_LBW_BASE 0x41DCB80ull |
|---|
| 10106 | #define DCORE0_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10107 | #define DCORE0_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10108 | #define mmDCORE0_EDMA1_MSTR_IF_CORE_HBW_BASE 0x41DCC00ull |
|---|
| 10109 | #define DCORE0_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10110 | #define DCORE0_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10111 | #define mmDCORE0_EDMA1_MSTR_IF_CORE_LBW_BASE 0x41DCD80ull |
|---|
| 10112 | #define DCORE0_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10113 | #define DCORE0_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10114 | #define mmDCORE0_EDMA1_MSTR_IF_SPECIAL_BASE 0x41DCE80ull |
|---|
| 10115 | #define DCORE0_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10116 | #define DCORE0_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 10117 | #define mmDCORE0_DEC0_CMD_BASE 0x41E0000ull |
|---|
| 10118 | #define DCORE0_DEC0_CMD_MAX_OFFSET 0x1100 |
|---|
| 10119 | #define DCORE0_DEC0_CMD_SECTION 0x1000 |
|---|
| 10120 | #define mmDCORE0_DEC0_VSI_BASE 0x41E1000ull |
|---|
| 10121 | #define DCORE0_DEC0_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 10122 | #define DCORE0_DEC0_VSI_SECTION 0x1000 |
|---|
| 10123 | #define mmDCORE0_DEC0_L2C_BASE 0x41E2000ull |
|---|
| 10124 | #define DCORE0_DEC0_L2C_MAX_OFFSET 0x39C0 |
|---|
| 10125 | #define DCORE0_DEC0_L2C_SECTION 0x1000 |
|---|
| 10126 | #define mmDCORE0_VDEC0_BRDG_CTRL_BASE 0x41E3000ull |
|---|
| 10127 | #define DCORE0_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 10128 | #define DCORE0_VDEC0_BRDG_CTRL_SECTION 0x8000 |
|---|
| 10129 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41E3800ull |
|---|
| 10130 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 10131 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 10132 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41E3900ull |
|---|
| 10133 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 10134 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 10135 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41E3A00ull |
|---|
| 10136 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 10137 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 10138 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41E3B00ull |
|---|
| 10139 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 10140 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 10141 | #define mmDCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x41E3C00ull |
|---|
| 10142 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 10143 | #define DCORE0_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 10144 | #define mmDCORE0_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x41E3E80ull |
|---|
| 10145 | #define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10146 | #define DCORE0_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 10147 | #define mmDCORE0_VDEC0_CTRL_BASE 0x41E4000ull |
|---|
| 10148 | #define DCORE0_VDEC0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 10149 | #define DCORE0_VDEC0_CTRL_SECTION 0xE800 |
|---|
| 10150 | #define mmDCORE0_VDEC0_CTRL_SPECIAL_BASE 0x41E4E80ull |
|---|
| 10151 | #define DCORE0_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10152 | #define DCORE0_VDEC0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 10153 | #define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x41E5000ull |
|---|
| 10154 | #define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10155 | #define DCORE0_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10156 | #define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x41E5200ull |
|---|
| 10157 | #define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10158 | #define DCORE0_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10159 | #define mmDCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x41E5400ull |
|---|
| 10160 | #define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10161 | #define DCORE0_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10162 | #define mmDCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x41E5600ull |
|---|
| 10163 | #define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10164 | #define DCORE0_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10165 | #define mmDCORE0_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x41E5800ull |
|---|
| 10166 | #define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10167 | #define DCORE0_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10168 | #define mmDCORE0_VDEC0_MSTR_IF_AXUSER_BASE 0x41E5A80ull |
|---|
| 10169 | #define DCORE0_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10170 | #define DCORE0_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10171 | #define mmDCORE0_VDEC0_MSTR_IF_DBG_HBW_BASE 0x41E5B00ull |
|---|
| 10172 | #define DCORE0_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10173 | #define DCORE0_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10174 | #define mmDCORE0_VDEC0_MSTR_IF_DBG_LBW_BASE 0x41E5B80ull |
|---|
| 10175 | #define DCORE0_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10176 | #define DCORE0_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10177 | #define mmDCORE0_VDEC0_MSTR_IF_CORE_HBW_BASE 0x41E5C00ull |
|---|
| 10178 | #define DCORE0_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10179 | #define DCORE0_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10180 | #define mmDCORE0_VDEC0_MSTR_IF_CORE_LBW_BASE 0x41E5D80ull |
|---|
| 10181 | #define DCORE0_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10182 | #define DCORE0_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10183 | #define mmDCORE0_VDEC0_MSTR_IF_SPECIAL_BASE 0x41E5E80ull |
|---|
| 10184 | #define DCORE0_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10185 | #define DCORE0_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 10186 | #define mmDCORE0_DEC1_CMD_BASE 0x41F0000ull |
|---|
| 10187 | #define DCORE0_DEC1_CMD_MAX_OFFSET 0x1100 |
|---|
| 10188 | #define DCORE0_DEC1_CMD_SECTION 0x1000 |
|---|
| 10189 | #define mmDCORE0_DEC1_VSI_BASE 0x41F1000ull |
|---|
| 10190 | #define DCORE0_DEC1_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 10191 | #define DCORE0_DEC1_VSI_SECTION 0x1000 |
|---|
| 10192 | #define mmDCORE0_DEC1_L2C_BASE 0x41F2000ull |
|---|
| 10193 | #define DCORE0_DEC1_L2C_MAX_OFFSET 0x39C0 |
|---|
| 10194 | #define DCORE0_DEC1_L2C_SECTION 0x1000 |
|---|
| 10195 | #define mmDCORE0_VDEC1_BRDG_CTRL_BASE 0x41F3000ull |
|---|
| 10196 | #define DCORE0_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 10197 | #define DCORE0_VDEC1_BRDG_CTRL_SECTION 0x8000 |
|---|
| 10198 | #define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x41F3800ull |
|---|
| 10199 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 10200 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 10201 | #define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x41F3900ull |
|---|
| 10202 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 10203 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 10204 | #define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x41F3A00ull |
|---|
| 10205 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 10206 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 10207 | #define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x41F3B00ull |
|---|
| 10208 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 10209 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 10210 | #define mmDCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x41F3C00ull |
|---|
| 10211 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 10212 | #define DCORE0_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 10213 | #define mmDCORE0_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x41F3E80ull |
|---|
| 10214 | #define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10215 | #define DCORE0_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 10216 | #define mmDCORE0_VDEC1_CTRL_BASE 0x41F4000ull |
|---|
| 10217 | #define DCORE0_VDEC1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 10218 | #define DCORE0_VDEC1_CTRL_SECTION 0xE800 |
|---|
| 10219 | #define mmDCORE0_VDEC1_CTRL_SPECIAL_BASE 0x41F4E80ull |
|---|
| 10220 | #define DCORE0_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10221 | #define DCORE0_VDEC1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 10222 | #define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x41F5000ull |
|---|
| 10223 | #define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10224 | #define DCORE0_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10225 | #define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x41F5200ull |
|---|
| 10226 | #define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10227 | #define DCORE0_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10228 | #define mmDCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x41F5400ull |
|---|
| 10229 | #define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10230 | #define DCORE0_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10231 | #define mmDCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x41F5600ull |
|---|
| 10232 | #define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10233 | #define DCORE0_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10234 | #define mmDCORE0_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x41F5800ull |
|---|
| 10235 | #define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10236 | #define DCORE0_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10237 | #define mmDCORE0_VDEC1_MSTR_IF_AXUSER_BASE 0x41F5A80ull |
|---|
| 10238 | #define DCORE0_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10239 | #define DCORE0_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10240 | #define mmDCORE0_VDEC1_MSTR_IF_DBG_HBW_BASE 0x41F5B00ull |
|---|
| 10241 | #define DCORE0_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10242 | #define DCORE0_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10243 | #define mmDCORE0_VDEC1_MSTR_IF_DBG_LBW_BASE 0x41F5B80ull |
|---|
| 10244 | #define DCORE0_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10245 | #define DCORE0_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10246 | #define mmDCORE0_VDEC1_MSTR_IF_CORE_HBW_BASE 0x41F5C00ull |
|---|
| 10247 | #define DCORE0_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10248 | #define DCORE0_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10249 | #define mmDCORE0_VDEC1_MSTR_IF_CORE_LBW_BASE 0x41F5D80ull |
|---|
| 10250 | #define DCORE0_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10251 | #define DCORE0_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10252 | #define mmDCORE0_VDEC1_MSTR_IF_SPECIAL_BASE 0x41F5E80ull |
|---|
| 10253 | #define DCORE0_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10254 | #define DCORE0_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 10255 | #define mmDCORE1_TPC0_QM_DCCM_BASE 0x4200000ull |
|---|
| 10256 | #define DCORE1_TPC0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 10257 | #define DCORE1_TPC0_QM_DCCM_SECTION 0x8000 |
|---|
| 10258 | #define mmDCORE1_TPC0_QM_ARC_AUX_BASE 0x4208000ull |
|---|
| 10259 | #define DCORE1_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 10260 | #define DCORE1_TPC0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 10261 | #define mmDCORE1_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4208E80ull |
|---|
| 10262 | #define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10263 | #define DCORE1_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 10264 | #define mmDCORE1_TPC0_QM_BASE 0x420A000ull |
|---|
| 10265 | #define DCORE1_TPC0_QM_MAX_OFFSET 0x1000 |
|---|
| 10266 | #define DCORE1_TPC0_QM_SECTION 0x9000 |
|---|
| 10267 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x420A900ull |
|---|
| 10268 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 10269 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 10270 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x420A908ull |
|---|
| 10271 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 10272 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 10273 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x420A910ull |
|---|
| 10274 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 10275 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 10276 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x420A918ull |
|---|
| 10277 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 10278 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 10279 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x420A920ull |
|---|
| 10280 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 10281 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 10282 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x420A928ull |
|---|
| 10283 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 10284 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 10285 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x420A930ull |
|---|
| 10286 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 10287 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 10288 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x420A938ull |
|---|
| 10289 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 10290 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 10291 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x420A940ull |
|---|
| 10292 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 10293 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 10294 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x420A948ull |
|---|
| 10295 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 10296 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 10297 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x420A950ull |
|---|
| 10298 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 10299 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 10300 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x420A958ull |
|---|
| 10301 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 10302 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 10303 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x420A960ull |
|---|
| 10304 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 10305 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 10306 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x420A968ull |
|---|
| 10307 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 10308 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 10309 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x420A970ull |
|---|
| 10310 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 10311 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 10312 | #define mmDCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x420A978ull |
|---|
| 10313 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 10314 | #define DCORE1_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 10315 | #define mmDCORE1_TPC0_QM_AXUSER_SECURED_BASE 0x420AB00ull |
|---|
| 10316 | #define DCORE1_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 10317 | #define DCORE1_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 10318 | #define mmDCORE1_TPC0_QM_AXUSER_NONSECURED_BASE 0x420AB80ull |
|---|
| 10319 | #define DCORE1_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 10320 | #define DCORE1_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 10321 | #define mmDCORE1_TPC0_QM_DBG_HBW_BASE 0x420AC00ull |
|---|
| 10322 | #define DCORE1_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10323 | #define DCORE1_TPC0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 10324 | #define mmDCORE1_TPC0_QM_DBG_LBW_BASE 0x420AC80ull |
|---|
| 10325 | #define DCORE1_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10326 | #define DCORE1_TPC0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 10327 | #define mmDCORE1_TPC0_QM_CGM_BASE 0x420AD80ull |
|---|
| 10328 | #define DCORE1_TPC0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 10329 | #define DCORE1_TPC0_QM_CGM_SECTION 0x1000 |
|---|
| 10330 | #define mmDCORE1_TPC0_QM_SPECIAL_BASE 0x420AE80ull |
|---|
| 10331 | #define DCORE1_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10332 | #define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10333 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x420B000ull |
|---|
| 10334 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10335 | #define DCORE1_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10336 | #define mmDCORE1_TPC0_CFG_BASE 0x420B000ull |
|---|
| 10337 | #define DCORE1_TPC0_CFG_MAX_OFFSET 0x1000 |
|---|
| 10338 | #define DCORE1_TPC0_CFG_SECTION 0x5000 |
|---|
| 10339 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x420B050ull |
|---|
| 10340 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10341 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 10342 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x420B0A0ull |
|---|
| 10343 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10344 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 10345 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x420B0F0ull |
|---|
| 10346 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10347 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 10348 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x420B140ull |
|---|
| 10349 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10350 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 10351 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x420B190ull |
|---|
| 10352 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10353 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 10354 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x420B1E0ull |
|---|
| 10355 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10356 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 10357 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x420B230ull |
|---|
| 10358 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10359 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 10360 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x420B280ull |
|---|
| 10361 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10362 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 10363 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x420B2D0ull |
|---|
| 10364 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10365 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 10366 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x420B320ull |
|---|
| 10367 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10368 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 10369 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x420B370ull |
|---|
| 10370 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10371 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 10372 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x420B3C0ull |
|---|
| 10373 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10374 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 10375 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x420B410ull |
|---|
| 10376 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10377 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 10378 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x420B460ull |
|---|
| 10379 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10380 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 10381 | #define mmDCORE1_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x420B4B0ull |
|---|
| 10382 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10383 | #define DCORE1_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 10384 | #define mmDCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x420B500ull |
|---|
| 10385 | #define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10386 | #define DCORE1_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10387 | #define mmDCORE1_TPC0_CFG_KERNEL_BASE 0x420B508ull |
|---|
| 10388 | #define DCORE1_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 10389 | #define DCORE1_TPC0_CFG_KERNEL_SECTION 0xD400 |
|---|
| 10390 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_0_BASE 0x420B5DCull |
|---|
| 10391 | #define DCORE1_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10392 | #define DCORE1_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 10393 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_1_BASE 0x420B62Cull |
|---|
| 10394 | #define DCORE1_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10395 | #define DCORE1_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 10396 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_2_BASE 0x420B67Cull |
|---|
| 10397 | #define DCORE1_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10398 | #define DCORE1_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 10399 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_3_BASE 0x420B6CCull |
|---|
| 10400 | #define DCORE1_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10401 | #define DCORE1_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 10402 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_4_BASE 0x420B71Cull |
|---|
| 10403 | #define DCORE1_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10404 | #define DCORE1_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 10405 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_5_BASE 0x420B76Cull |
|---|
| 10406 | #define DCORE1_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10407 | #define DCORE1_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 10408 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_6_BASE 0x420B7BCull |
|---|
| 10409 | #define DCORE1_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10410 | #define DCORE1_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 10411 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_7_BASE 0x420B80Cull |
|---|
| 10412 | #define DCORE1_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10413 | #define DCORE1_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 10414 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_8_BASE 0x420B85Cull |
|---|
| 10415 | #define DCORE1_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10416 | #define DCORE1_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 10417 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_9_BASE 0x420B8ACull |
|---|
| 10418 | #define DCORE1_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10419 | #define DCORE1_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 10420 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_10_BASE 0x420B8FCull |
|---|
| 10421 | #define DCORE1_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10422 | #define DCORE1_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 10423 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_11_BASE 0x420B94Cull |
|---|
| 10424 | #define DCORE1_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10425 | #define DCORE1_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 10426 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_12_BASE 0x420B99Cull |
|---|
| 10427 | #define DCORE1_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10428 | #define DCORE1_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 10429 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_13_BASE 0x420B9ECull |
|---|
| 10430 | #define DCORE1_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10431 | #define DCORE1_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 10432 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_14_BASE 0x420BA3Cull |
|---|
| 10433 | #define DCORE1_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10434 | #define DCORE1_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 10435 | #define mmDCORE1_TPC0_CFG_QM_TENSOR_15_BASE 0x420BA8Cull |
|---|
| 10436 | #define DCORE1_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10437 | #define DCORE1_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 10438 | #define mmDCORE1_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x420BADCull |
|---|
| 10439 | #define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10440 | #define DCORE1_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10441 | #define mmDCORE1_TPC0_CFG_QM_BASE 0x420BAE4ull |
|---|
| 10442 | #define DCORE1_TPC0_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 10443 | #define DCORE1_TPC0_CFG_QM_SECTION 0x31C0 |
|---|
| 10444 | #define mmDCORE1_TPC0_CFG_AXUSER_BASE 0x420BE00ull |
|---|
| 10445 | #define DCORE1_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10446 | #define DCORE1_TPC0_CFG_AXUSER_SECTION 0x8000 |
|---|
| 10447 | #define mmDCORE1_TPC0_CFG_SPECIAL_BASE 0x420BE80ull |
|---|
| 10448 | #define DCORE1_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10449 | #define DCORE1_TPC0_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 10450 | #define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x420C000ull |
|---|
| 10451 | #define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10452 | #define DCORE1_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10453 | #define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x420C200ull |
|---|
| 10454 | #define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10455 | #define DCORE1_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10456 | #define mmDCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x420C400ull |
|---|
| 10457 | #define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10458 | #define DCORE1_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10459 | #define mmDCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x420C600ull |
|---|
| 10460 | #define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10461 | #define DCORE1_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10462 | #define mmDCORE1_TPC0_MSTR_IF_E2E_CRDT_BASE 0x420C800ull |
|---|
| 10463 | #define DCORE1_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10464 | #define DCORE1_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10465 | #define mmDCORE1_TPC0_MSTR_IF_AXUSER_BASE 0x420CA80ull |
|---|
| 10466 | #define DCORE1_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10467 | #define DCORE1_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10468 | #define mmDCORE1_TPC0_MSTR_IF_DBG_HBW_BASE 0x420CB00ull |
|---|
| 10469 | #define DCORE1_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10470 | #define DCORE1_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10471 | #define mmDCORE1_TPC0_MSTR_IF_DBG_LBW_BASE 0x420CB80ull |
|---|
| 10472 | #define DCORE1_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10473 | #define DCORE1_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10474 | #define mmDCORE1_TPC0_MSTR_IF_CORE_HBW_BASE 0x420CC00ull |
|---|
| 10475 | #define DCORE1_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10476 | #define DCORE1_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10477 | #define mmDCORE1_TPC0_MSTR_IF_CORE_LBW_BASE 0x420CD80ull |
|---|
| 10478 | #define DCORE1_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10479 | #define DCORE1_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10480 | #define mmDCORE1_TPC0_MSTR_IF_SPECIAL_BASE 0x420CE80ull |
|---|
| 10481 | #define DCORE1_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10482 | #define DCORE1_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 10483 | #define mmDCORE1_TPC1_QM_DCCM_BASE 0x4210000ull |
|---|
| 10484 | #define DCORE1_TPC1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 10485 | #define DCORE1_TPC1_QM_DCCM_SECTION 0x8000 |
|---|
| 10486 | #define mmDCORE1_TPC1_QM_ARC_AUX_BASE 0x4218000ull |
|---|
| 10487 | #define DCORE1_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 10488 | #define DCORE1_TPC1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 10489 | #define mmDCORE1_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4218E80ull |
|---|
| 10490 | #define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10491 | #define DCORE1_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 10492 | #define mmDCORE1_TPC1_QM_BASE 0x421A000ull |
|---|
| 10493 | #define DCORE1_TPC1_QM_MAX_OFFSET 0x1000 |
|---|
| 10494 | #define DCORE1_TPC1_QM_SECTION 0x9000 |
|---|
| 10495 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x421A900ull |
|---|
| 10496 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 10497 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 10498 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x421A908ull |
|---|
| 10499 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 10500 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 10501 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x421A910ull |
|---|
| 10502 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 10503 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 10504 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x421A918ull |
|---|
| 10505 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 10506 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 10507 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x421A920ull |
|---|
| 10508 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 10509 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 10510 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x421A928ull |
|---|
| 10511 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 10512 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 10513 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x421A930ull |
|---|
| 10514 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 10515 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 10516 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x421A938ull |
|---|
| 10517 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 10518 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 10519 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x421A940ull |
|---|
| 10520 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 10521 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 10522 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x421A948ull |
|---|
| 10523 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 10524 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 10525 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x421A950ull |
|---|
| 10526 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 10527 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 10528 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x421A958ull |
|---|
| 10529 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 10530 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 10531 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x421A960ull |
|---|
| 10532 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 10533 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 10534 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x421A968ull |
|---|
| 10535 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 10536 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 10537 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x421A970ull |
|---|
| 10538 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 10539 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 10540 | #define mmDCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x421A978ull |
|---|
| 10541 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 10542 | #define DCORE1_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 10543 | #define mmDCORE1_TPC1_QM_AXUSER_SECURED_BASE 0x421AB00ull |
|---|
| 10544 | #define DCORE1_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 10545 | #define DCORE1_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 10546 | #define mmDCORE1_TPC1_QM_AXUSER_NONSECURED_BASE 0x421AB80ull |
|---|
| 10547 | #define DCORE1_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 10548 | #define DCORE1_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 10549 | #define mmDCORE1_TPC1_QM_DBG_HBW_BASE 0x421AC00ull |
|---|
| 10550 | #define DCORE1_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10551 | #define DCORE1_TPC1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 10552 | #define mmDCORE1_TPC1_QM_DBG_LBW_BASE 0x421AC80ull |
|---|
| 10553 | #define DCORE1_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10554 | #define DCORE1_TPC1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 10555 | #define mmDCORE1_TPC1_QM_CGM_BASE 0x421AD80ull |
|---|
| 10556 | #define DCORE1_TPC1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 10557 | #define DCORE1_TPC1_QM_CGM_SECTION 0x1000 |
|---|
| 10558 | #define mmDCORE1_TPC1_QM_SPECIAL_BASE 0x421AE80ull |
|---|
| 10559 | #define DCORE1_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10560 | #define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10561 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x421B000ull |
|---|
| 10562 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10563 | #define DCORE1_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10564 | #define mmDCORE1_TPC1_CFG_BASE 0x421B000ull |
|---|
| 10565 | #define DCORE1_TPC1_CFG_MAX_OFFSET 0x1000 |
|---|
| 10566 | #define DCORE1_TPC1_CFG_SECTION 0x5000 |
|---|
| 10567 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x421B050ull |
|---|
| 10568 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10569 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 10570 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x421B0A0ull |
|---|
| 10571 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10572 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 10573 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x421B0F0ull |
|---|
| 10574 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10575 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 10576 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x421B140ull |
|---|
| 10577 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10578 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 10579 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x421B190ull |
|---|
| 10580 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10581 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 10582 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x421B1E0ull |
|---|
| 10583 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10584 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 10585 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x421B230ull |
|---|
| 10586 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10587 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 10588 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x421B280ull |
|---|
| 10589 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10590 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 10591 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x421B2D0ull |
|---|
| 10592 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10593 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 10594 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x421B320ull |
|---|
| 10595 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10596 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 10597 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x421B370ull |
|---|
| 10598 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10599 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 10600 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x421B3C0ull |
|---|
| 10601 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10602 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 10603 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x421B410ull |
|---|
| 10604 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10605 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 10606 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x421B460ull |
|---|
| 10607 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10608 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 10609 | #define mmDCORE1_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x421B4B0ull |
|---|
| 10610 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10611 | #define DCORE1_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 10612 | #define mmDCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x421B500ull |
|---|
| 10613 | #define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10614 | #define DCORE1_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10615 | #define mmDCORE1_TPC1_CFG_KERNEL_BASE 0x421B508ull |
|---|
| 10616 | #define DCORE1_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 10617 | #define DCORE1_TPC1_CFG_KERNEL_SECTION 0xD400 |
|---|
| 10618 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_0_BASE 0x421B5DCull |
|---|
| 10619 | #define DCORE1_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10620 | #define DCORE1_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 10621 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_1_BASE 0x421B62Cull |
|---|
| 10622 | #define DCORE1_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10623 | #define DCORE1_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 10624 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_2_BASE 0x421B67Cull |
|---|
| 10625 | #define DCORE1_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10626 | #define DCORE1_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 10627 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_3_BASE 0x421B6CCull |
|---|
| 10628 | #define DCORE1_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10629 | #define DCORE1_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 10630 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_4_BASE 0x421B71Cull |
|---|
| 10631 | #define DCORE1_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10632 | #define DCORE1_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 10633 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_5_BASE 0x421B76Cull |
|---|
| 10634 | #define DCORE1_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10635 | #define DCORE1_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 10636 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_6_BASE 0x421B7BCull |
|---|
| 10637 | #define DCORE1_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10638 | #define DCORE1_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 10639 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_7_BASE 0x421B80Cull |
|---|
| 10640 | #define DCORE1_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10641 | #define DCORE1_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 10642 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_8_BASE 0x421B85Cull |
|---|
| 10643 | #define DCORE1_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10644 | #define DCORE1_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 10645 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_9_BASE 0x421B8ACull |
|---|
| 10646 | #define DCORE1_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10647 | #define DCORE1_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 10648 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_10_BASE 0x421B8FCull |
|---|
| 10649 | #define DCORE1_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10650 | #define DCORE1_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 10651 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_11_BASE 0x421B94Cull |
|---|
| 10652 | #define DCORE1_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10653 | #define DCORE1_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 10654 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_12_BASE 0x421B99Cull |
|---|
| 10655 | #define DCORE1_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10656 | #define DCORE1_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 10657 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_13_BASE 0x421B9ECull |
|---|
| 10658 | #define DCORE1_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10659 | #define DCORE1_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 10660 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_14_BASE 0x421BA3Cull |
|---|
| 10661 | #define DCORE1_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10662 | #define DCORE1_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 10663 | #define mmDCORE1_TPC1_CFG_QM_TENSOR_15_BASE 0x421BA8Cull |
|---|
| 10664 | #define DCORE1_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10665 | #define DCORE1_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 10666 | #define mmDCORE1_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x421BADCull |
|---|
| 10667 | #define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10668 | #define DCORE1_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10669 | #define mmDCORE1_TPC1_CFG_QM_BASE 0x421BAE4ull |
|---|
| 10670 | #define DCORE1_TPC1_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 10671 | #define DCORE1_TPC1_CFG_QM_SECTION 0x31C0 |
|---|
| 10672 | #define mmDCORE1_TPC1_CFG_AXUSER_BASE 0x421BE00ull |
|---|
| 10673 | #define DCORE1_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10674 | #define DCORE1_TPC1_CFG_AXUSER_SECTION 0x8000 |
|---|
| 10675 | #define mmDCORE1_TPC1_CFG_SPECIAL_BASE 0x421BE80ull |
|---|
| 10676 | #define DCORE1_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10677 | #define DCORE1_TPC1_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 10678 | #define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x421C000ull |
|---|
| 10679 | #define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10680 | #define DCORE1_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10681 | #define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x421C200ull |
|---|
| 10682 | #define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10683 | #define DCORE1_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10684 | #define mmDCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x421C400ull |
|---|
| 10685 | #define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10686 | #define DCORE1_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10687 | #define mmDCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x421C600ull |
|---|
| 10688 | #define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10689 | #define DCORE1_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10690 | #define mmDCORE1_TPC1_MSTR_IF_E2E_CRDT_BASE 0x421C800ull |
|---|
| 10691 | #define DCORE1_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10692 | #define DCORE1_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10693 | #define mmDCORE1_TPC1_MSTR_IF_AXUSER_BASE 0x421CA80ull |
|---|
| 10694 | #define DCORE1_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10695 | #define DCORE1_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10696 | #define mmDCORE1_TPC1_MSTR_IF_DBG_HBW_BASE 0x421CB00ull |
|---|
| 10697 | #define DCORE1_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10698 | #define DCORE1_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10699 | #define mmDCORE1_TPC1_MSTR_IF_DBG_LBW_BASE 0x421CB80ull |
|---|
| 10700 | #define DCORE1_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10701 | #define DCORE1_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10702 | #define mmDCORE1_TPC1_MSTR_IF_CORE_HBW_BASE 0x421CC00ull |
|---|
| 10703 | #define DCORE1_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10704 | #define DCORE1_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10705 | #define mmDCORE1_TPC1_MSTR_IF_CORE_LBW_BASE 0x421CD80ull |
|---|
| 10706 | #define DCORE1_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10707 | #define DCORE1_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10708 | #define mmDCORE1_TPC1_MSTR_IF_SPECIAL_BASE 0x421CE80ull |
|---|
| 10709 | #define DCORE1_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10710 | #define DCORE1_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 10711 | #define mmDCORE1_TPC2_QM_DCCM_BASE 0x4220000ull |
|---|
| 10712 | #define DCORE1_TPC2_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 10713 | #define DCORE1_TPC2_QM_DCCM_SECTION 0x8000 |
|---|
| 10714 | #define mmDCORE1_TPC2_QM_ARC_AUX_BASE 0x4228000ull |
|---|
| 10715 | #define DCORE1_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 10716 | #define DCORE1_TPC2_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 10717 | #define mmDCORE1_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4228E80ull |
|---|
| 10718 | #define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10719 | #define DCORE1_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 10720 | #define mmDCORE1_TPC2_QM_BASE 0x422A000ull |
|---|
| 10721 | #define DCORE1_TPC2_QM_MAX_OFFSET 0x1000 |
|---|
| 10722 | #define DCORE1_TPC2_QM_SECTION 0x9000 |
|---|
| 10723 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x422A900ull |
|---|
| 10724 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 10725 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 10726 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x422A908ull |
|---|
| 10727 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 10728 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 10729 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x422A910ull |
|---|
| 10730 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 10731 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 10732 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x422A918ull |
|---|
| 10733 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 10734 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 10735 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x422A920ull |
|---|
| 10736 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 10737 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 10738 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x422A928ull |
|---|
| 10739 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 10740 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 10741 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x422A930ull |
|---|
| 10742 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 10743 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 10744 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x422A938ull |
|---|
| 10745 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 10746 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 10747 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x422A940ull |
|---|
| 10748 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 10749 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 10750 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x422A948ull |
|---|
| 10751 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 10752 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 10753 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x422A950ull |
|---|
| 10754 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 10755 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 10756 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x422A958ull |
|---|
| 10757 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 10758 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 10759 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x422A960ull |
|---|
| 10760 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 10761 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 10762 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x422A968ull |
|---|
| 10763 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 10764 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 10765 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x422A970ull |
|---|
| 10766 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 10767 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 10768 | #define mmDCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x422A978ull |
|---|
| 10769 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 10770 | #define DCORE1_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 10771 | #define mmDCORE1_TPC2_QM_AXUSER_SECURED_BASE 0x422AB00ull |
|---|
| 10772 | #define DCORE1_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 10773 | #define DCORE1_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 10774 | #define mmDCORE1_TPC2_QM_AXUSER_NONSECURED_BASE 0x422AB80ull |
|---|
| 10775 | #define DCORE1_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 10776 | #define DCORE1_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 10777 | #define mmDCORE1_TPC2_QM_DBG_HBW_BASE 0x422AC00ull |
|---|
| 10778 | #define DCORE1_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10779 | #define DCORE1_TPC2_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 10780 | #define mmDCORE1_TPC2_QM_DBG_LBW_BASE 0x422AC80ull |
|---|
| 10781 | #define DCORE1_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10782 | #define DCORE1_TPC2_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 10783 | #define mmDCORE1_TPC2_QM_CGM_BASE 0x422AD80ull |
|---|
| 10784 | #define DCORE1_TPC2_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 10785 | #define DCORE1_TPC2_QM_CGM_SECTION 0x1000 |
|---|
| 10786 | #define mmDCORE1_TPC2_QM_SPECIAL_BASE 0x422AE80ull |
|---|
| 10787 | #define DCORE1_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10788 | #define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10789 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x422B000ull |
|---|
| 10790 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10791 | #define DCORE1_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 10792 | #define mmDCORE1_TPC2_CFG_BASE 0x422B000ull |
|---|
| 10793 | #define DCORE1_TPC2_CFG_MAX_OFFSET 0x1000 |
|---|
| 10794 | #define DCORE1_TPC2_CFG_SECTION 0x5000 |
|---|
| 10795 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x422B050ull |
|---|
| 10796 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10797 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 10798 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x422B0A0ull |
|---|
| 10799 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10800 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 10801 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x422B0F0ull |
|---|
| 10802 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10803 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 10804 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x422B140ull |
|---|
| 10805 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10806 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 10807 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x422B190ull |
|---|
| 10808 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10809 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 10810 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x422B1E0ull |
|---|
| 10811 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10812 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 10813 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x422B230ull |
|---|
| 10814 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10815 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 10816 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x422B280ull |
|---|
| 10817 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10818 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 10819 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x422B2D0ull |
|---|
| 10820 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10821 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 10822 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x422B320ull |
|---|
| 10823 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10824 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 10825 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x422B370ull |
|---|
| 10826 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10827 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 10828 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x422B3C0ull |
|---|
| 10829 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10830 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 10831 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x422B410ull |
|---|
| 10832 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10833 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 10834 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x422B460ull |
|---|
| 10835 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10836 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 10837 | #define mmDCORE1_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x422B4B0ull |
|---|
| 10838 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10839 | #define DCORE1_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 10840 | #define mmDCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x422B500ull |
|---|
| 10841 | #define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10842 | #define DCORE1_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10843 | #define mmDCORE1_TPC2_CFG_KERNEL_BASE 0x422B508ull |
|---|
| 10844 | #define DCORE1_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 10845 | #define DCORE1_TPC2_CFG_KERNEL_SECTION 0xD400 |
|---|
| 10846 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_0_BASE 0x422B5DCull |
|---|
| 10847 | #define DCORE1_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 10848 | #define DCORE1_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 10849 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_1_BASE 0x422B62Cull |
|---|
| 10850 | #define DCORE1_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 10851 | #define DCORE1_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 10852 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_2_BASE 0x422B67Cull |
|---|
| 10853 | #define DCORE1_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 10854 | #define DCORE1_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 10855 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_3_BASE 0x422B6CCull |
|---|
| 10856 | #define DCORE1_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 10857 | #define DCORE1_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 10858 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_4_BASE 0x422B71Cull |
|---|
| 10859 | #define DCORE1_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 10860 | #define DCORE1_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 10861 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_5_BASE 0x422B76Cull |
|---|
| 10862 | #define DCORE1_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 10863 | #define DCORE1_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 10864 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_6_BASE 0x422B7BCull |
|---|
| 10865 | #define DCORE1_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 10866 | #define DCORE1_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 10867 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_7_BASE 0x422B80Cull |
|---|
| 10868 | #define DCORE1_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 10869 | #define DCORE1_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 10870 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_8_BASE 0x422B85Cull |
|---|
| 10871 | #define DCORE1_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 10872 | #define DCORE1_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 10873 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_9_BASE 0x422B8ACull |
|---|
| 10874 | #define DCORE1_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 10875 | #define DCORE1_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 10876 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_10_BASE 0x422B8FCull |
|---|
| 10877 | #define DCORE1_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 10878 | #define DCORE1_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 10879 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_11_BASE 0x422B94Cull |
|---|
| 10880 | #define DCORE1_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 10881 | #define DCORE1_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 10882 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_12_BASE 0x422B99Cull |
|---|
| 10883 | #define DCORE1_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 10884 | #define DCORE1_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 10885 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_13_BASE 0x422B9ECull |
|---|
| 10886 | #define DCORE1_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 10887 | #define DCORE1_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 10888 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_14_BASE 0x422BA3Cull |
|---|
| 10889 | #define DCORE1_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 10890 | #define DCORE1_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 10891 | #define mmDCORE1_TPC2_CFG_QM_TENSOR_15_BASE 0x422BA8Cull |
|---|
| 10892 | #define DCORE1_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 10893 | #define DCORE1_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 10894 | #define mmDCORE1_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x422BADCull |
|---|
| 10895 | #define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 10896 | #define DCORE1_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 10897 | #define mmDCORE1_TPC2_CFG_QM_BASE 0x422BAE4ull |
|---|
| 10898 | #define DCORE1_TPC2_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 10899 | #define DCORE1_TPC2_CFG_QM_SECTION 0x31C0 |
|---|
| 10900 | #define mmDCORE1_TPC2_CFG_AXUSER_BASE 0x422BE00ull |
|---|
| 10901 | #define DCORE1_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10902 | #define DCORE1_TPC2_CFG_AXUSER_SECTION 0x8000 |
|---|
| 10903 | #define mmDCORE1_TPC2_CFG_SPECIAL_BASE 0x422BE80ull |
|---|
| 10904 | #define DCORE1_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10905 | #define DCORE1_TPC2_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 10906 | #define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x422C000ull |
|---|
| 10907 | #define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10908 | #define DCORE1_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 10909 | #define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x422C200ull |
|---|
| 10910 | #define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 10911 | #define DCORE1_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 10912 | #define mmDCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x422C400ull |
|---|
| 10913 | #define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10914 | #define DCORE1_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 10915 | #define mmDCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x422C600ull |
|---|
| 10916 | #define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 10917 | #define DCORE1_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 10918 | #define mmDCORE1_TPC2_MSTR_IF_E2E_CRDT_BASE 0x422C800ull |
|---|
| 10919 | #define DCORE1_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 10920 | #define DCORE1_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 10921 | #define mmDCORE1_TPC2_MSTR_IF_AXUSER_BASE 0x422CA80ull |
|---|
| 10922 | #define DCORE1_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 10923 | #define DCORE1_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 10924 | #define mmDCORE1_TPC2_MSTR_IF_DBG_HBW_BASE 0x422CB00ull |
|---|
| 10925 | #define DCORE1_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 10926 | #define DCORE1_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 10927 | #define mmDCORE1_TPC2_MSTR_IF_DBG_LBW_BASE 0x422CB80ull |
|---|
| 10928 | #define DCORE1_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 10929 | #define DCORE1_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 10930 | #define mmDCORE1_TPC2_MSTR_IF_CORE_HBW_BASE 0x422CC00ull |
|---|
| 10931 | #define DCORE1_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 10932 | #define DCORE1_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 10933 | #define mmDCORE1_TPC2_MSTR_IF_CORE_LBW_BASE 0x422CD80ull |
|---|
| 10934 | #define DCORE1_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 10935 | #define DCORE1_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 10936 | #define mmDCORE1_TPC2_MSTR_IF_SPECIAL_BASE 0x422CE80ull |
|---|
| 10937 | #define DCORE1_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10938 | #define DCORE1_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 10939 | #define mmDCORE1_TPC3_QM_DCCM_BASE 0x4230000ull |
|---|
| 10940 | #define DCORE1_TPC3_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 10941 | #define DCORE1_TPC3_QM_DCCM_SECTION 0x8000 |
|---|
| 10942 | #define mmDCORE1_TPC3_QM_ARC_AUX_BASE 0x4238000ull |
|---|
| 10943 | #define DCORE1_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 10944 | #define DCORE1_TPC3_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 10945 | #define mmDCORE1_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4238E80ull |
|---|
| 10946 | #define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 10947 | #define DCORE1_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 10948 | #define mmDCORE1_TPC3_QM_BASE 0x423A000ull |
|---|
| 10949 | #define DCORE1_TPC3_QM_MAX_OFFSET 0x1000 |
|---|
| 10950 | #define DCORE1_TPC3_QM_SECTION 0x9000 |
|---|
| 10951 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x423A900ull |
|---|
| 10952 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 10953 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 10954 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x423A908ull |
|---|
| 10955 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 10956 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 10957 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x423A910ull |
|---|
| 10958 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 10959 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 10960 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x423A918ull |
|---|
| 10961 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 10962 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 10963 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x423A920ull |
|---|
| 10964 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 10965 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 10966 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x423A928ull |
|---|
| 10967 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 10968 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 10969 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x423A930ull |
|---|
| 10970 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 10971 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 10972 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x423A938ull |
|---|
| 10973 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 10974 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 10975 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x423A940ull |
|---|
| 10976 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 10977 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 10978 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x423A948ull |
|---|
| 10979 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 10980 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 10981 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x423A950ull |
|---|
| 10982 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 10983 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 10984 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x423A958ull |
|---|
| 10985 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 10986 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 10987 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x423A960ull |
|---|
| 10988 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 10989 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 10990 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x423A968ull |
|---|
| 10991 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 10992 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 10993 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x423A970ull |
|---|
| 10994 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 10995 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 10996 | #define mmDCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x423A978ull |
|---|
| 10997 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 10998 | #define DCORE1_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 10999 | #define mmDCORE1_TPC3_QM_AXUSER_SECURED_BASE 0x423AB00ull |
|---|
| 11000 | #define DCORE1_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 11001 | #define DCORE1_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 11002 | #define mmDCORE1_TPC3_QM_AXUSER_NONSECURED_BASE 0x423AB80ull |
|---|
| 11003 | #define DCORE1_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 11004 | #define DCORE1_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 11005 | #define mmDCORE1_TPC3_QM_DBG_HBW_BASE 0x423AC00ull |
|---|
| 11006 | #define DCORE1_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11007 | #define DCORE1_TPC3_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 11008 | #define mmDCORE1_TPC3_QM_DBG_LBW_BASE 0x423AC80ull |
|---|
| 11009 | #define DCORE1_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11010 | #define DCORE1_TPC3_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 11011 | #define mmDCORE1_TPC3_QM_CGM_BASE 0x423AD80ull |
|---|
| 11012 | #define DCORE1_TPC3_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 11013 | #define DCORE1_TPC3_QM_CGM_SECTION 0x1000 |
|---|
| 11014 | #define mmDCORE1_TPC3_QM_SPECIAL_BASE 0x423AE80ull |
|---|
| 11015 | #define DCORE1_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11016 | #define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11017 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x423B000ull |
|---|
| 11018 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11019 | #define DCORE1_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11020 | #define mmDCORE1_TPC3_CFG_BASE 0x423B000ull |
|---|
| 11021 | #define DCORE1_TPC3_CFG_MAX_OFFSET 0x1000 |
|---|
| 11022 | #define DCORE1_TPC3_CFG_SECTION 0x5000 |
|---|
| 11023 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x423B050ull |
|---|
| 11024 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11025 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 11026 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x423B0A0ull |
|---|
| 11027 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11028 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 11029 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x423B0F0ull |
|---|
| 11030 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11031 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 11032 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x423B140ull |
|---|
| 11033 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11034 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 11035 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x423B190ull |
|---|
| 11036 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11037 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 11038 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x423B1E0ull |
|---|
| 11039 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11040 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 11041 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x423B230ull |
|---|
| 11042 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11043 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 11044 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x423B280ull |
|---|
| 11045 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11046 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 11047 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x423B2D0ull |
|---|
| 11048 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11049 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 11050 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x423B320ull |
|---|
| 11051 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11052 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 11053 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x423B370ull |
|---|
| 11054 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11055 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 11056 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x423B3C0ull |
|---|
| 11057 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11058 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 11059 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x423B410ull |
|---|
| 11060 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11061 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 11062 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x423B460ull |
|---|
| 11063 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11064 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 11065 | #define mmDCORE1_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x423B4B0ull |
|---|
| 11066 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11067 | #define DCORE1_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 11068 | #define mmDCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x423B500ull |
|---|
| 11069 | #define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11070 | #define DCORE1_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11071 | #define mmDCORE1_TPC3_CFG_KERNEL_BASE 0x423B508ull |
|---|
| 11072 | #define DCORE1_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 11073 | #define DCORE1_TPC3_CFG_KERNEL_SECTION 0xD400 |
|---|
| 11074 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_0_BASE 0x423B5DCull |
|---|
| 11075 | #define DCORE1_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11076 | #define DCORE1_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 11077 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_1_BASE 0x423B62Cull |
|---|
| 11078 | #define DCORE1_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11079 | #define DCORE1_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 11080 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_2_BASE 0x423B67Cull |
|---|
| 11081 | #define DCORE1_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11082 | #define DCORE1_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 11083 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_3_BASE 0x423B6CCull |
|---|
| 11084 | #define DCORE1_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11085 | #define DCORE1_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 11086 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_4_BASE 0x423B71Cull |
|---|
| 11087 | #define DCORE1_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11088 | #define DCORE1_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 11089 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_5_BASE 0x423B76Cull |
|---|
| 11090 | #define DCORE1_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11091 | #define DCORE1_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 11092 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_6_BASE 0x423B7BCull |
|---|
| 11093 | #define DCORE1_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11094 | #define DCORE1_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 11095 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_7_BASE 0x423B80Cull |
|---|
| 11096 | #define DCORE1_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11097 | #define DCORE1_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 11098 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_8_BASE 0x423B85Cull |
|---|
| 11099 | #define DCORE1_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11100 | #define DCORE1_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 11101 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_9_BASE 0x423B8ACull |
|---|
| 11102 | #define DCORE1_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11103 | #define DCORE1_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 11104 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_10_BASE 0x423B8FCull |
|---|
| 11105 | #define DCORE1_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11106 | #define DCORE1_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 11107 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_11_BASE 0x423B94Cull |
|---|
| 11108 | #define DCORE1_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11109 | #define DCORE1_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 11110 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_12_BASE 0x423B99Cull |
|---|
| 11111 | #define DCORE1_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11112 | #define DCORE1_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 11113 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_13_BASE 0x423B9ECull |
|---|
| 11114 | #define DCORE1_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11115 | #define DCORE1_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 11116 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_14_BASE 0x423BA3Cull |
|---|
| 11117 | #define DCORE1_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11118 | #define DCORE1_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 11119 | #define mmDCORE1_TPC3_CFG_QM_TENSOR_15_BASE 0x423BA8Cull |
|---|
| 11120 | #define DCORE1_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11121 | #define DCORE1_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 11122 | #define mmDCORE1_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x423BADCull |
|---|
| 11123 | #define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11124 | #define DCORE1_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11125 | #define mmDCORE1_TPC3_CFG_QM_BASE 0x423BAE4ull |
|---|
| 11126 | #define DCORE1_TPC3_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 11127 | #define DCORE1_TPC3_CFG_QM_SECTION 0x31C0 |
|---|
| 11128 | #define mmDCORE1_TPC3_CFG_AXUSER_BASE 0x423BE00ull |
|---|
| 11129 | #define DCORE1_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11130 | #define DCORE1_TPC3_CFG_AXUSER_SECTION 0x8000 |
|---|
| 11131 | #define mmDCORE1_TPC3_CFG_SPECIAL_BASE 0x423BE80ull |
|---|
| 11132 | #define DCORE1_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11133 | #define DCORE1_TPC3_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 11134 | #define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x423C000ull |
|---|
| 11135 | #define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11136 | #define DCORE1_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11137 | #define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x423C200ull |
|---|
| 11138 | #define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11139 | #define DCORE1_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11140 | #define mmDCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x423C400ull |
|---|
| 11141 | #define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11142 | #define DCORE1_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11143 | #define mmDCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x423C600ull |
|---|
| 11144 | #define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11145 | #define DCORE1_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11146 | #define mmDCORE1_TPC3_MSTR_IF_E2E_CRDT_BASE 0x423C800ull |
|---|
| 11147 | #define DCORE1_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11148 | #define DCORE1_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11149 | #define mmDCORE1_TPC3_MSTR_IF_AXUSER_BASE 0x423CA80ull |
|---|
| 11150 | #define DCORE1_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11151 | #define DCORE1_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11152 | #define mmDCORE1_TPC3_MSTR_IF_DBG_HBW_BASE 0x423CB00ull |
|---|
| 11153 | #define DCORE1_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11154 | #define DCORE1_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11155 | #define mmDCORE1_TPC3_MSTR_IF_DBG_LBW_BASE 0x423CB80ull |
|---|
| 11156 | #define DCORE1_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11157 | #define DCORE1_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11158 | #define mmDCORE1_TPC3_MSTR_IF_CORE_HBW_BASE 0x423CC00ull |
|---|
| 11159 | #define DCORE1_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11160 | #define DCORE1_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11161 | #define mmDCORE1_TPC3_MSTR_IF_CORE_LBW_BASE 0x423CD80ull |
|---|
| 11162 | #define DCORE1_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11163 | #define DCORE1_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11164 | #define mmDCORE1_TPC3_MSTR_IF_SPECIAL_BASE 0x423CE80ull |
|---|
| 11165 | #define DCORE1_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11166 | #define DCORE1_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 11167 | #define mmDCORE1_TPC4_QM_DCCM_BASE 0x4240000ull |
|---|
| 11168 | #define DCORE1_TPC4_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 11169 | #define DCORE1_TPC4_QM_DCCM_SECTION 0x8000 |
|---|
| 11170 | #define mmDCORE1_TPC4_QM_ARC_AUX_BASE 0x4248000ull |
|---|
| 11171 | #define DCORE1_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 11172 | #define DCORE1_TPC4_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 11173 | #define mmDCORE1_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4248E80ull |
|---|
| 11174 | #define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11175 | #define DCORE1_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 11176 | #define mmDCORE1_TPC4_QM_BASE 0x424A000ull |
|---|
| 11177 | #define DCORE1_TPC4_QM_MAX_OFFSET 0x1000 |
|---|
| 11178 | #define DCORE1_TPC4_QM_SECTION 0x9000 |
|---|
| 11179 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x424A900ull |
|---|
| 11180 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 11181 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 11182 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x424A908ull |
|---|
| 11183 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 11184 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 11185 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x424A910ull |
|---|
| 11186 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 11187 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 11188 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x424A918ull |
|---|
| 11189 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 11190 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 11191 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x424A920ull |
|---|
| 11192 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 11193 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 11194 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x424A928ull |
|---|
| 11195 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 11196 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 11197 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x424A930ull |
|---|
| 11198 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 11199 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 11200 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x424A938ull |
|---|
| 11201 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 11202 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 11203 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x424A940ull |
|---|
| 11204 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 11205 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 11206 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x424A948ull |
|---|
| 11207 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 11208 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 11209 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x424A950ull |
|---|
| 11210 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 11211 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 11212 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x424A958ull |
|---|
| 11213 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 11214 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 11215 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x424A960ull |
|---|
| 11216 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 11217 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 11218 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x424A968ull |
|---|
| 11219 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 11220 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 11221 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x424A970ull |
|---|
| 11222 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 11223 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 11224 | #define mmDCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x424A978ull |
|---|
| 11225 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 11226 | #define DCORE1_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 11227 | #define mmDCORE1_TPC4_QM_AXUSER_SECURED_BASE 0x424AB00ull |
|---|
| 11228 | #define DCORE1_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 11229 | #define DCORE1_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 11230 | #define mmDCORE1_TPC4_QM_AXUSER_NONSECURED_BASE 0x424AB80ull |
|---|
| 11231 | #define DCORE1_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 11232 | #define DCORE1_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 11233 | #define mmDCORE1_TPC4_QM_DBG_HBW_BASE 0x424AC00ull |
|---|
| 11234 | #define DCORE1_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11235 | #define DCORE1_TPC4_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 11236 | #define mmDCORE1_TPC4_QM_DBG_LBW_BASE 0x424AC80ull |
|---|
| 11237 | #define DCORE1_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11238 | #define DCORE1_TPC4_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 11239 | #define mmDCORE1_TPC4_QM_CGM_BASE 0x424AD80ull |
|---|
| 11240 | #define DCORE1_TPC4_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 11241 | #define DCORE1_TPC4_QM_CGM_SECTION 0x1000 |
|---|
| 11242 | #define mmDCORE1_TPC4_QM_SPECIAL_BASE 0x424AE80ull |
|---|
| 11243 | #define DCORE1_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11244 | #define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11245 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x424B000ull |
|---|
| 11246 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11247 | #define DCORE1_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11248 | #define mmDCORE1_TPC4_CFG_BASE 0x424B000ull |
|---|
| 11249 | #define DCORE1_TPC4_CFG_MAX_OFFSET 0x1000 |
|---|
| 11250 | #define DCORE1_TPC4_CFG_SECTION 0x5000 |
|---|
| 11251 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x424B050ull |
|---|
| 11252 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11253 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 11254 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x424B0A0ull |
|---|
| 11255 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11256 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 11257 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x424B0F0ull |
|---|
| 11258 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11259 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 11260 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x424B140ull |
|---|
| 11261 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11262 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 11263 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x424B190ull |
|---|
| 11264 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11265 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 11266 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x424B1E0ull |
|---|
| 11267 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11268 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 11269 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x424B230ull |
|---|
| 11270 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11271 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 11272 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x424B280ull |
|---|
| 11273 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11274 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 11275 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x424B2D0ull |
|---|
| 11276 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11277 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 11278 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x424B320ull |
|---|
| 11279 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11280 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 11281 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x424B370ull |
|---|
| 11282 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11283 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 11284 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x424B3C0ull |
|---|
| 11285 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11286 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 11287 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x424B410ull |
|---|
| 11288 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11289 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 11290 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x424B460ull |
|---|
| 11291 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11292 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 11293 | #define mmDCORE1_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x424B4B0ull |
|---|
| 11294 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11295 | #define DCORE1_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 11296 | #define mmDCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x424B500ull |
|---|
| 11297 | #define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11298 | #define DCORE1_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11299 | #define mmDCORE1_TPC4_CFG_KERNEL_BASE 0x424B508ull |
|---|
| 11300 | #define DCORE1_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 11301 | #define DCORE1_TPC4_CFG_KERNEL_SECTION 0xD400 |
|---|
| 11302 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_0_BASE 0x424B5DCull |
|---|
| 11303 | #define DCORE1_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11304 | #define DCORE1_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 11305 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_1_BASE 0x424B62Cull |
|---|
| 11306 | #define DCORE1_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11307 | #define DCORE1_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 11308 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_2_BASE 0x424B67Cull |
|---|
| 11309 | #define DCORE1_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11310 | #define DCORE1_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 11311 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_3_BASE 0x424B6CCull |
|---|
| 11312 | #define DCORE1_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11313 | #define DCORE1_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 11314 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_4_BASE 0x424B71Cull |
|---|
| 11315 | #define DCORE1_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11316 | #define DCORE1_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 11317 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_5_BASE 0x424B76Cull |
|---|
| 11318 | #define DCORE1_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11319 | #define DCORE1_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 11320 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_6_BASE 0x424B7BCull |
|---|
| 11321 | #define DCORE1_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11322 | #define DCORE1_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 11323 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_7_BASE 0x424B80Cull |
|---|
| 11324 | #define DCORE1_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11325 | #define DCORE1_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 11326 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_8_BASE 0x424B85Cull |
|---|
| 11327 | #define DCORE1_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11328 | #define DCORE1_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 11329 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_9_BASE 0x424B8ACull |
|---|
| 11330 | #define DCORE1_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11331 | #define DCORE1_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 11332 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_10_BASE 0x424B8FCull |
|---|
| 11333 | #define DCORE1_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11334 | #define DCORE1_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 11335 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_11_BASE 0x424B94Cull |
|---|
| 11336 | #define DCORE1_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11337 | #define DCORE1_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 11338 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_12_BASE 0x424B99Cull |
|---|
| 11339 | #define DCORE1_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11340 | #define DCORE1_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 11341 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_13_BASE 0x424B9ECull |
|---|
| 11342 | #define DCORE1_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11343 | #define DCORE1_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 11344 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_14_BASE 0x424BA3Cull |
|---|
| 11345 | #define DCORE1_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11346 | #define DCORE1_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 11347 | #define mmDCORE1_TPC4_CFG_QM_TENSOR_15_BASE 0x424BA8Cull |
|---|
| 11348 | #define DCORE1_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11349 | #define DCORE1_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 11350 | #define mmDCORE1_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x424BADCull |
|---|
| 11351 | #define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11352 | #define DCORE1_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11353 | #define mmDCORE1_TPC4_CFG_QM_BASE 0x424BAE4ull |
|---|
| 11354 | #define DCORE1_TPC4_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 11355 | #define DCORE1_TPC4_CFG_QM_SECTION 0x31C0 |
|---|
| 11356 | #define mmDCORE1_TPC4_CFG_AXUSER_BASE 0x424BE00ull |
|---|
| 11357 | #define DCORE1_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11358 | #define DCORE1_TPC4_CFG_AXUSER_SECTION 0x8000 |
|---|
| 11359 | #define mmDCORE1_TPC4_CFG_SPECIAL_BASE 0x424BE80ull |
|---|
| 11360 | #define DCORE1_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11361 | #define DCORE1_TPC4_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 11362 | #define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x424C000ull |
|---|
| 11363 | #define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11364 | #define DCORE1_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11365 | #define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x424C200ull |
|---|
| 11366 | #define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11367 | #define DCORE1_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11368 | #define mmDCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x424C400ull |
|---|
| 11369 | #define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11370 | #define DCORE1_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11371 | #define mmDCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x424C600ull |
|---|
| 11372 | #define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11373 | #define DCORE1_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11374 | #define mmDCORE1_TPC4_MSTR_IF_E2E_CRDT_BASE 0x424C800ull |
|---|
| 11375 | #define DCORE1_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11376 | #define DCORE1_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11377 | #define mmDCORE1_TPC4_MSTR_IF_AXUSER_BASE 0x424CA80ull |
|---|
| 11378 | #define DCORE1_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11379 | #define DCORE1_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11380 | #define mmDCORE1_TPC4_MSTR_IF_DBG_HBW_BASE 0x424CB00ull |
|---|
| 11381 | #define DCORE1_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11382 | #define DCORE1_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11383 | #define mmDCORE1_TPC4_MSTR_IF_DBG_LBW_BASE 0x424CB80ull |
|---|
| 11384 | #define DCORE1_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11385 | #define DCORE1_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11386 | #define mmDCORE1_TPC4_MSTR_IF_CORE_HBW_BASE 0x424CC00ull |
|---|
| 11387 | #define DCORE1_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11388 | #define DCORE1_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11389 | #define mmDCORE1_TPC4_MSTR_IF_CORE_LBW_BASE 0x424CD80ull |
|---|
| 11390 | #define DCORE1_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11391 | #define DCORE1_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11392 | #define mmDCORE1_TPC4_MSTR_IF_SPECIAL_BASE 0x424CE80ull |
|---|
| 11393 | #define DCORE1_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11394 | #define DCORE1_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 11395 | #define mmDCORE1_TPC5_QM_DCCM_BASE 0x4250000ull |
|---|
| 11396 | #define DCORE1_TPC5_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 11397 | #define DCORE1_TPC5_QM_DCCM_SECTION 0x8000 |
|---|
| 11398 | #define mmDCORE1_TPC5_QM_ARC_AUX_BASE 0x4258000ull |
|---|
| 11399 | #define DCORE1_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 11400 | #define DCORE1_TPC5_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 11401 | #define mmDCORE1_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4258E80ull |
|---|
| 11402 | #define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11403 | #define DCORE1_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 11404 | #define mmDCORE1_TPC5_QM_BASE 0x425A000ull |
|---|
| 11405 | #define DCORE1_TPC5_QM_MAX_OFFSET 0x1000 |
|---|
| 11406 | #define DCORE1_TPC5_QM_SECTION 0x9000 |
|---|
| 11407 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x425A900ull |
|---|
| 11408 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 11409 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 11410 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x425A908ull |
|---|
| 11411 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 11412 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 11413 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x425A910ull |
|---|
| 11414 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 11415 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 11416 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x425A918ull |
|---|
| 11417 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 11418 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 11419 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x425A920ull |
|---|
| 11420 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 11421 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 11422 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x425A928ull |
|---|
| 11423 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 11424 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 11425 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x425A930ull |
|---|
| 11426 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 11427 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 11428 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x425A938ull |
|---|
| 11429 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 11430 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 11431 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x425A940ull |
|---|
| 11432 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 11433 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 11434 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x425A948ull |
|---|
| 11435 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 11436 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 11437 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x425A950ull |
|---|
| 11438 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 11439 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 11440 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x425A958ull |
|---|
| 11441 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 11442 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 11443 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x425A960ull |
|---|
| 11444 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 11445 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 11446 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x425A968ull |
|---|
| 11447 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 11448 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 11449 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x425A970ull |
|---|
| 11450 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 11451 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 11452 | #define mmDCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x425A978ull |
|---|
| 11453 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 11454 | #define DCORE1_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 11455 | #define mmDCORE1_TPC5_QM_AXUSER_SECURED_BASE 0x425AB00ull |
|---|
| 11456 | #define DCORE1_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 11457 | #define DCORE1_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 11458 | #define mmDCORE1_TPC5_QM_AXUSER_NONSECURED_BASE 0x425AB80ull |
|---|
| 11459 | #define DCORE1_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 11460 | #define DCORE1_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 11461 | #define mmDCORE1_TPC5_QM_DBG_HBW_BASE 0x425AC00ull |
|---|
| 11462 | #define DCORE1_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11463 | #define DCORE1_TPC5_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 11464 | #define mmDCORE1_TPC5_QM_DBG_LBW_BASE 0x425AC80ull |
|---|
| 11465 | #define DCORE1_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11466 | #define DCORE1_TPC5_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 11467 | #define mmDCORE1_TPC5_QM_CGM_BASE 0x425AD80ull |
|---|
| 11468 | #define DCORE1_TPC5_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 11469 | #define DCORE1_TPC5_QM_CGM_SECTION 0x1000 |
|---|
| 11470 | #define mmDCORE1_TPC5_QM_SPECIAL_BASE 0x425AE80ull |
|---|
| 11471 | #define DCORE1_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11472 | #define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11473 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x425B000ull |
|---|
| 11474 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11475 | #define DCORE1_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11476 | #define mmDCORE1_TPC5_CFG_BASE 0x425B000ull |
|---|
| 11477 | #define DCORE1_TPC5_CFG_MAX_OFFSET 0x1000 |
|---|
| 11478 | #define DCORE1_TPC5_CFG_SECTION 0x5000 |
|---|
| 11479 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x425B050ull |
|---|
| 11480 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11481 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 11482 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x425B0A0ull |
|---|
| 11483 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11484 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 11485 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x425B0F0ull |
|---|
| 11486 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11487 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 11488 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x425B140ull |
|---|
| 11489 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11490 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 11491 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x425B190ull |
|---|
| 11492 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11493 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 11494 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x425B1E0ull |
|---|
| 11495 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11496 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 11497 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x425B230ull |
|---|
| 11498 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11499 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 11500 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x425B280ull |
|---|
| 11501 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11502 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 11503 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x425B2D0ull |
|---|
| 11504 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11505 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 11506 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x425B320ull |
|---|
| 11507 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11508 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 11509 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x425B370ull |
|---|
| 11510 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11511 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 11512 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x425B3C0ull |
|---|
| 11513 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11514 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 11515 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x425B410ull |
|---|
| 11516 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11517 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 11518 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x425B460ull |
|---|
| 11519 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11520 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 11521 | #define mmDCORE1_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x425B4B0ull |
|---|
| 11522 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11523 | #define DCORE1_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 11524 | #define mmDCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x425B500ull |
|---|
| 11525 | #define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11526 | #define DCORE1_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11527 | #define mmDCORE1_TPC5_CFG_KERNEL_BASE 0x425B508ull |
|---|
| 11528 | #define DCORE1_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 11529 | #define DCORE1_TPC5_CFG_KERNEL_SECTION 0xD400 |
|---|
| 11530 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_0_BASE 0x425B5DCull |
|---|
| 11531 | #define DCORE1_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 11532 | #define DCORE1_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 11533 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_1_BASE 0x425B62Cull |
|---|
| 11534 | #define DCORE1_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 11535 | #define DCORE1_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 11536 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_2_BASE 0x425B67Cull |
|---|
| 11537 | #define DCORE1_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 11538 | #define DCORE1_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 11539 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_3_BASE 0x425B6CCull |
|---|
| 11540 | #define DCORE1_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 11541 | #define DCORE1_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 11542 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_4_BASE 0x425B71Cull |
|---|
| 11543 | #define DCORE1_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 11544 | #define DCORE1_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 11545 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_5_BASE 0x425B76Cull |
|---|
| 11546 | #define DCORE1_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 11547 | #define DCORE1_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 11548 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_6_BASE 0x425B7BCull |
|---|
| 11549 | #define DCORE1_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 11550 | #define DCORE1_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 11551 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_7_BASE 0x425B80Cull |
|---|
| 11552 | #define DCORE1_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 11553 | #define DCORE1_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 11554 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_8_BASE 0x425B85Cull |
|---|
| 11555 | #define DCORE1_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 11556 | #define DCORE1_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 11557 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_9_BASE 0x425B8ACull |
|---|
| 11558 | #define DCORE1_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 11559 | #define DCORE1_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 11560 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_10_BASE 0x425B8FCull |
|---|
| 11561 | #define DCORE1_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 11562 | #define DCORE1_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 11563 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_11_BASE 0x425B94Cull |
|---|
| 11564 | #define DCORE1_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 11565 | #define DCORE1_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 11566 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_12_BASE 0x425B99Cull |
|---|
| 11567 | #define DCORE1_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 11568 | #define DCORE1_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 11569 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_13_BASE 0x425B9ECull |
|---|
| 11570 | #define DCORE1_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 11571 | #define DCORE1_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 11572 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_14_BASE 0x425BA3Cull |
|---|
| 11573 | #define DCORE1_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 11574 | #define DCORE1_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 11575 | #define mmDCORE1_TPC5_CFG_QM_TENSOR_15_BASE 0x425BA8Cull |
|---|
| 11576 | #define DCORE1_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 11577 | #define DCORE1_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 11578 | #define mmDCORE1_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x425BADCull |
|---|
| 11579 | #define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 11580 | #define DCORE1_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 11581 | #define mmDCORE1_TPC5_CFG_QM_BASE 0x425BAE4ull |
|---|
| 11582 | #define DCORE1_TPC5_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 11583 | #define DCORE1_TPC5_CFG_QM_SECTION 0x31C0 |
|---|
| 11584 | #define mmDCORE1_TPC5_CFG_AXUSER_BASE 0x425BE00ull |
|---|
| 11585 | #define DCORE1_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11586 | #define DCORE1_TPC5_CFG_AXUSER_SECTION 0x8000 |
|---|
| 11587 | #define mmDCORE1_TPC5_CFG_SPECIAL_BASE 0x425BE80ull |
|---|
| 11588 | #define DCORE1_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11589 | #define DCORE1_TPC5_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 11590 | #define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x425C000ull |
|---|
| 11591 | #define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11592 | #define DCORE1_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11593 | #define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x425C200ull |
|---|
| 11594 | #define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11595 | #define DCORE1_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11596 | #define mmDCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x425C400ull |
|---|
| 11597 | #define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11598 | #define DCORE1_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11599 | #define mmDCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x425C600ull |
|---|
| 11600 | #define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11601 | #define DCORE1_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11602 | #define mmDCORE1_TPC5_MSTR_IF_E2E_CRDT_BASE 0x425C800ull |
|---|
| 11603 | #define DCORE1_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11604 | #define DCORE1_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11605 | #define mmDCORE1_TPC5_MSTR_IF_AXUSER_BASE 0x425CA80ull |
|---|
| 11606 | #define DCORE1_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11607 | #define DCORE1_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11608 | #define mmDCORE1_TPC5_MSTR_IF_DBG_HBW_BASE 0x425CB00ull |
|---|
| 11609 | #define DCORE1_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11610 | #define DCORE1_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11611 | #define mmDCORE1_TPC5_MSTR_IF_DBG_LBW_BASE 0x425CB80ull |
|---|
| 11612 | #define DCORE1_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11613 | #define DCORE1_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11614 | #define mmDCORE1_TPC5_MSTR_IF_CORE_HBW_BASE 0x425CC00ull |
|---|
| 11615 | #define DCORE1_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11616 | #define DCORE1_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11617 | #define mmDCORE1_TPC5_MSTR_IF_CORE_LBW_BASE 0x425CD80ull |
|---|
| 11618 | #define DCORE1_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11619 | #define DCORE1_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11620 | #define mmDCORE1_TPC5_MSTR_IF_SPECIAL_BASE 0x425CE80ull |
|---|
| 11621 | #define DCORE1_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11622 | #define DCORE1_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 |
|---|
| 11623 | #define mmDCORE1_HMMU0_MMU_BASE 0x4280000ull |
|---|
| 11624 | #define DCORE1_HMMU0_MMU_MAX_OFFSET 0x1000 |
|---|
| 11625 | #define DCORE1_HMMU0_MMU_SECTION 0xE800 |
|---|
| 11626 | #define mmDCORE1_HMMU0_MMU_SPECIAL_BASE 0x4280E80ull |
|---|
| 11627 | #define DCORE1_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11628 | #define DCORE1_HMMU0_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 11629 | #define mmDCORE1_HMMU0_STLB_BASE 0x4281000ull |
|---|
| 11630 | #define DCORE1_HMMU0_STLB_MAX_OFFSET 0x1000 |
|---|
| 11631 | #define DCORE1_HMMU0_STLB_SECTION 0xE800 |
|---|
| 11632 | #define mmDCORE1_HMMU0_STLB_SPECIAL_BASE 0x4281E80ull |
|---|
| 11633 | #define DCORE1_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11634 | #define DCORE1_HMMU0_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 11635 | #define mmDCORE1_HMMU0_SCRAMB_OUT_BASE 0x4283000ull |
|---|
| 11636 | #define DCORE1_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 11637 | #define DCORE1_HMMU0_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 11638 | #define mmDCORE1_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4283E80ull |
|---|
| 11639 | #define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11640 | #define DCORE1_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 11641 | #define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4284000ull |
|---|
| 11642 | #define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11643 | #define DCORE1_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11644 | #define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4284200ull |
|---|
| 11645 | #define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11646 | #define DCORE1_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11647 | #define mmDCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4284400ull |
|---|
| 11648 | #define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11649 | #define DCORE1_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11650 | #define mmDCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4284600ull |
|---|
| 11651 | #define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11652 | #define DCORE1_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11653 | #define mmDCORE1_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4284800ull |
|---|
| 11654 | #define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11655 | #define DCORE1_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11656 | #define mmDCORE1_HMMU0_MSTR_IF_AXUSER_BASE 0x4284A80ull |
|---|
| 11657 | #define DCORE1_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11658 | #define DCORE1_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11659 | #define mmDCORE1_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4284B00ull |
|---|
| 11660 | #define DCORE1_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11661 | #define DCORE1_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11662 | #define mmDCORE1_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4284B80ull |
|---|
| 11663 | #define DCORE1_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11664 | #define DCORE1_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11665 | #define mmDCORE1_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4284C00ull |
|---|
| 11666 | #define DCORE1_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11667 | #define DCORE1_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11668 | #define mmDCORE1_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4284D80ull |
|---|
| 11669 | #define DCORE1_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11670 | #define DCORE1_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11671 | #define mmDCORE1_HMMU0_MSTR_IF_SPECIAL_BASE 0x4284E80ull |
|---|
| 11672 | #define DCORE1_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11673 | #define DCORE1_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 11674 | #define mmDCORE1_HMMU1_MMU_BASE 0x4290000ull |
|---|
| 11675 | #define DCORE1_HMMU1_MMU_MAX_OFFSET 0x1000 |
|---|
| 11676 | #define DCORE1_HMMU1_MMU_SECTION 0xE800 |
|---|
| 11677 | #define mmDCORE1_HMMU1_MMU_SPECIAL_BASE 0x4290E80ull |
|---|
| 11678 | #define DCORE1_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11679 | #define DCORE1_HMMU1_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 11680 | #define mmDCORE1_HMMU1_STLB_BASE 0x4291000ull |
|---|
| 11681 | #define DCORE1_HMMU1_STLB_MAX_OFFSET 0x1000 |
|---|
| 11682 | #define DCORE1_HMMU1_STLB_SECTION 0xE800 |
|---|
| 11683 | #define mmDCORE1_HMMU1_STLB_SPECIAL_BASE 0x4291E80ull |
|---|
| 11684 | #define DCORE1_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11685 | #define DCORE1_HMMU1_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 11686 | #define mmDCORE1_HMMU1_SCRAMB_OUT_BASE 0x4293000ull |
|---|
| 11687 | #define DCORE1_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 11688 | #define DCORE1_HMMU1_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 11689 | #define mmDCORE1_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4293E80ull |
|---|
| 11690 | #define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11691 | #define DCORE1_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 11692 | #define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4294000ull |
|---|
| 11693 | #define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11694 | #define DCORE1_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11695 | #define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4294200ull |
|---|
| 11696 | #define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11697 | #define DCORE1_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11698 | #define mmDCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4294400ull |
|---|
| 11699 | #define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11700 | #define DCORE1_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11701 | #define mmDCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4294600ull |
|---|
| 11702 | #define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11703 | #define DCORE1_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11704 | #define mmDCORE1_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4294800ull |
|---|
| 11705 | #define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11706 | #define DCORE1_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11707 | #define mmDCORE1_HMMU1_MSTR_IF_AXUSER_BASE 0x4294A80ull |
|---|
| 11708 | #define DCORE1_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11709 | #define DCORE1_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11710 | #define mmDCORE1_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4294B00ull |
|---|
| 11711 | #define DCORE1_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11712 | #define DCORE1_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11713 | #define mmDCORE1_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4294B80ull |
|---|
| 11714 | #define DCORE1_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11715 | #define DCORE1_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11716 | #define mmDCORE1_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4294C00ull |
|---|
| 11717 | #define DCORE1_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11718 | #define DCORE1_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11719 | #define mmDCORE1_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4294D80ull |
|---|
| 11720 | #define DCORE1_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11721 | #define DCORE1_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11722 | #define mmDCORE1_HMMU1_MSTR_IF_SPECIAL_BASE 0x4294E80ull |
|---|
| 11723 | #define DCORE1_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11724 | #define DCORE1_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 11725 | #define mmDCORE1_HMMU2_MMU_BASE 0x42A0000ull |
|---|
| 11726 | #define DCORE1_HMMU2_MMU_MAX_OFFSET 0x1000 |
|---|
| 11727 | #define DCORE1_HMMU2_MMU_SECTION 0xE800 |
|---|
| 11728 | #define mmDCORE1_HMMU2_MMU_SPECIAL_BASE 0x42A0E80ull |
|---|
| 11729 | #define DCORE1_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11730 | #define DCORE1_HMMU2_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 11731 | #define mmDCORE1_HMMU2_STLB_BASE 0x42A1000ull |
|---|
| 11732 | #define DCORE1_HMMU2_STLB_MAX_OFFSET 0x1000 |
|---|
| 11733 | #define DCORE1_HMMU2_STLB_SECTION 0xE800 |
|---|
| 11734 | #define mmDCORE1_HMMU2_STLB_SPECIAL_BASE 0x42A1E80ull |
|---|
| 11735 | #define DCORE1_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11736 | #define DCORE1_HMMU2_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 11737 | #define mmDCORE1_HMMU2_SCRAMB_OUT_BASE 0x42A3000ull |
|---|
| 11738 | #define DCORE1_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 11739 | #define DCORE1_HMMU2_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 11740 | #define mmDCORE1_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x42A3E80ull |
|---|
| 11741 | #define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11742 | #define DCORE1_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 11743 | #define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x42A4000ull |
|---|
| 11744 | #define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11745 | #define DCORE1_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11746 | #define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x42A4200ull |
|---|
| 11747 | #define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11748 | #define DCORE1_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11749 | #define mmDCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x42A4400ull |
|---|
| 11750 | #define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11751 | #define DCORE1_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11752 | #define mmDCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x42A4600ull |
|---|
| 11753 | #define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11754 | #define DCORE1_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11755 | #define mmDCORE1_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x42A4800ull |
|---|
| 11756 | #define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11757 | #define DCORE1_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11758 | #define mmDCORE1_HMMU2_MSTR_IF_AXUSER_BASE 0x42A4A80ull |
|---|
| 11759 | #define DCORE1_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11760 | #define DCORE1_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11761 | #define mmDCORE1_HMMU2_MSTR_IF_DBG_HBW_BASE 0x42A4B00ull |
|---|
| 11762 | #define DCORE1_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11763 | #define DCORE1_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11764 | #define mmDCORE1_HMMU2_MSTR_IF_DBG_LBW_BASE 0x42A4B80ull |
|---|
| 11765 | #define DCORE1_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11766 | #define DCORE1_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11767 | #define mmDCORE1_HMMU2_MSTR_IF_CORE_HBW_BASE 0x42A4C00ull |
|---|
| 11768 | #define DCORE1_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11769 | #define DCORE1_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11770 | #define mmDCORE1_HMMU2_MSTR_IF_CORE_LBW_BASE 0x42A4D80ull |
|---|
| 11771 | #define DCORE1_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11772 | #define DCORE1_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11773 | #define mmDCORE1_HMMU2_MSTR_IF_SPECIAL_BASE 0x42A4E80ull |
|---|
| 11774 | #define DCORE1_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11775 | #define DCORE1_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 11776 | #define mmDCORE1_HMMU3_MMU_BASE 0x42B0000ull |
|---|
| 11777 | #define DCORE1_HMMU3_MMU_MAX_OFFSET 0x1000 |
|---|
| 11778 | #define DCORE1_HMMU3_MMU_SECTION 0xE800 |
|---|
| 11779 | #define mmDCORE1_HMMU3_MMU_SPECIAL_BASE 0x42B0E80ull |
|---|
| 11780 | #define DCORE1_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11781 | #define DCORE1_HMMU3_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 11782 | #define mmDCORE1_HMMU3_STLB_BASE 0x42B1000ull |
|---|
| 11783 | #define DCORE1_HMMU3_STLB_MAX_OFFSET 0x1000 |
|---|
| 11784 | #define DCORE1_HMMU3_STLB_SECTION 0xE800 |
|---|
| 11785 | #define mmDCORE1_HMMU3_STLB_SPECIAL_BASE 0x42B1E80ull |
|---|
| 11786 | #define DCORE1_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11787 | #define DCORE1_HMMU3_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 11788 | #define mmDCORE1_HMMU3_SCRAMB_OUT_BASE 0x42B3000ull |
|---|
| 11789 | #define DCORE1_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 11790 | #define DCORE1_HMMU3_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 11791 | #define mmDCORE1_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x42B3E80ull |
|---|
| 11792 | #define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11793 | #define DCORE1_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 11794 | #define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x42B4000ull |
|---|
| 11795 | #define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11796 | #define DCORE1_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 11797 | #define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x42B4200ull |
|---|
| 11798 | #define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 11799 | #define DCORE1_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 11800 | #define mmDCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x42B4400ull |
|---|
| 11801 | #define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11802 | #define DCORE1_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 11803 | #define mmDCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x42B4600ull |
|---|
| 11804 | #define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 11805 | #define DCORE1_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 11806 | #define mmDCORE1_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x42B4800ull |
|---|
| 11807 | #define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 11808 | #define DCORE1_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 11809 | #define mmDCORE1_HMMU3_MSTR_IF_AXUSER_BASE 0x42B4A80ull |
|---|
| 11810 | #define DCORE1_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11811 | #define DCORE1_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 11812 | #define mmDCORE1_HMMU3_MSTR_IF_DBG_HBW_BASE 0x42B4B00ull |
|---|
| 11813 | #define DCORE1_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11814 | #define DCORE1_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 11815 | #define mmDCORE1_HMMU3_MSTR_IF_DBG_LBW_BASE 0x42B4B80ull |
|---|
| 11816 | #define DCORE1_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11817 | #define DCORE1_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 11818 | #define mmDCORE1_HMMU3_MSTR_IF_CORE_HBW_BASE 0x42B4C00ull |
|---|
| 11819 | #define DCORE1_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 11820 | #define DCORE1_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 11821 | #define mmDCORE1_HMMU3_MSTR_IF_CORE_LBW_BASE 0x42B4D80ull |
|---|
| 11822 | #define DCORE1_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 11823 | #define DCORE1_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 11824 | #define mmDCORE1_HMMU3_MSTR_IF_SPECIAL_BASE 0x42B4E80ull |
|---|
| 11825 | #define DCORE1_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11826 | #define DCORE1_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 11827 | #define mmDCORE1_MME_QM_ARC_DCCM_BASE 0x42C0000ull |
|---|
| 11828 | #define DCORE1_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 |
|---|
| 11829 | #define DCORE1_MME_QM_ARC_DCCM_SECTION 0x8000 |
|---|
| 11830 | #define mmDCORE1_MME_QM_ARC_AUX_BASE 0x42C8000ull |
|---|
| 11831 | #define DCORE1_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 11832 | #define DCORE1_MME_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 11833 | #define mmDCORE1_MME_QM_ARC_AUX_SPECIAL_BASE 0x42C8E80ull |
|---|
| 11834 | #define DCORE1_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11835 | #define DCORE1_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 |
|---|
| 11836 | #define mmDCORE1_MME_QM_ARC_DUP_ENG_BASE 0x42C9000ull |
|---|
| 11837 | #define DCORE1_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 |
|---|
| 11838 | #define DCORE1_MME_QM_ARC_DUP_ENG_SECTION 0x9000 |
|---|
| 11839 | #define mmDCORE1_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x42C9900ull |
|---|
| 11840 | #define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11841 | #define DCORE1_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 |
|---|
| 11842 | #define mmDCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x42C9E80ull |
|---|
| 11843 | #define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11844 | #define DCORE1_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 11845 | #define mmDCORE1_MME_QM_BASE 0x42CA000ull |
|---|
| 11846 | #define DCORE1_MME_QM_MAX_OFFSET 0x1000 |
|---|
| 11847 | #define DCORE1_MME_QM_SECTION 0x9000 |
|---|
| 11848 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x42CA900ull |
|---|
| 11849 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 11850 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 11851 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x42CA908ull |
|---|
| 11852 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 11853 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 11854 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x42CA910ull |
|---|
| 11855 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 11856 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 11857 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x42CA918ull |
|---|
| 11858 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 11859 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 11860 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x42CA920ull |
|---|
| 11861 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 11862 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 11863 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x42CA928ull |
|---|
| 11864 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 11865 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 11866 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x42CA930ull |
|---|
| 11867 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 11868 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 11869 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x42CA938ull |
|---|
| 11870 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 11871 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 11872 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x42CA940ull |
|---|
| 11873 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 11874 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 11875 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x42CA948ull |
|---|
| 11876 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 11877 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 11878 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x42CA950ull |
|---|
| 11879 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 11880 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 11881 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x42CA958ull |
|---|
| 11882 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 11883 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 11884 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x42CA960ull |
|---|
| 11885 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 11886 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 11887 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x42CA968ull |
|---|
| 11888 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 11889 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 11890 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x42CA970ull |
|---|
| 11891 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 11892 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 11893 | #define mmDCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x42CA978ull |
|---|
| 11894 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 11895 | #define DCORE1_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 11896 | #define mmDCORE1_MME_QM_AXUSER_SECURED_BASE 0x42CAB00ull |
|---|
| 11897 | #define DCORE1_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 11898 | #define DCORE1_MME_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 11899 | #define mmDCORE1_MME_QM_AXUSER_NONSECURED_BASE 0x42CAB80ull |
|---|
| 11900 | #define DCORE1_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 11901 | #define DCORE1_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 11902 | #define mmDCORE1_MME_QM_DBG_HBW_BASE 0x42CAC00ull |
|---|
| 11903 | #define DCORE1_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 11904 | #define DCORE1_MME_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 11905 | #define mmDCORE1_MME_QM_DBG_LBW_BASE 0x42CAC80ull |
|---|
| 11906 | #define DCORE1_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 11907 | #define DCORE1_MME_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 11908 | #define mmDCORE1_MME_QM_CGM_BASE 0x42CAD80ull |
|---|
| 11909 | #define DCORE1_MME_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 11910 | #define DCORE1_MME_QM_CGM_SECTION 0x1000 |
|---|
| 11911 | #define mmDCORE1_MME_QM_SPECIAL_BASE 0x42CAE80ull |
|---|
| 11912 | #define DCORE1_MME_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11913 | #define DCORE1_MME_QM_SPECIAL_SECTION 0x1800 |
|---|
| 11914 | #define mmDCORE1_MME_CTRL_LO_BASE 0x42CB000ull |
|---|
| 11915 | #define DCORE1_MME_CTRL_LO_MAX_OFFSET 0x1000 |
|---|
| 11916 | #define DCORE1_MME_CTRL_LO_SECTION 0x8000 |
|---|
| 11917 | #define mmDCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x42CB008ull |
|---|
| 11918 | #define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 11919 | #define DCORE1_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 |
|---|
| 11920 | #define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x42CB028ull |
|---|
| 11921 | #define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 11922 | #define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 11923 | #define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x42CB040ull |
|---|
| 11924 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 11925 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 |
|---|
| 11926 | #define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x42CB098ull |
|---|
| 11927 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 11928 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 |
|---|
| 11929 | #define mmDCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x42CB0F0ull |
|---|
| 11930 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 11931 | #define DCORE1_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 11932 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x42CB15Cull |
|---|
| 11933 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11934 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 11935 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x42CB170ull |
|---|
| 11936 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11937 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 11938 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x42CB184ull |
|---|
| 11939 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11940 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 11941 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x42CB198ull |
|---|
| 11942 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11943 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 11944 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x42CB1ACull |
|---|
| 11945 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11946 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 11947 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x42CB1C0ull |
|---|
| 11948 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11949 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 11950 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x42CB1D4ull |
|---|
| 11951 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11952 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 11953 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x42CB1E8ull |
|---|
| 11954 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11955 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 11956 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x42CB1FCull |
|---|
| 11957 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11958 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 11959 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x42CB210ull |
|---|
| 11960 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11961 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 11962 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x42CB22Cull |
|---|
| 11963 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11964 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 11965 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x42CB240ull |
|---|
| 11966 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11967 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 11968 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x42CB254ull |
|---|
| 11969 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 11970 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 11971 | #define mmDCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x42CB268ull |
|---|
| 11972 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 11973 | #define DCORE1_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 11974 | #define mmDCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x42CB280ull |
|---|
| 11975 | #define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 11976 | #define DCORE1_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 |
|---|
| 11977 | #define mmDCORE1_MME_CTRL_LO_MME_AXUSER_BASE 0x42CBE00ull |
|---|
| 11978 | #define DCORE1_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 11979 | #define DCORE1_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 |
|---|
| 11980 | #define mmDCORE1_MME_CTRL_LO_SPECIAL_BASE 0x42CBE80ull |
|---|
| 11981 | #define DCORE1_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 11982 | #define DCORE1_MME_CTRL_LO_SPECIAL_SECTION 0x1800 |
|---|
| 11983 | #define mmDCORE1_MME_CTRL_HI_BASE 0x42CC000ull |
|---|
| 11984 | #define DCORE1_MME_CTRL_HI_MAX_OFFSET 0x1000 |
|---|
| 11985 | #define DCORE1_MME_CTRL_HI_SECTION 0x8000 |
|---|
| 11986 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x42CC008ull |
|---|
| 11987 | #define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 11988 | #define DCORE1_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 |
|---|
| 11989 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x42CC028ull |
|---|
| 11990 | #define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 11991 | #define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 11992 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x42CC040ull |
|---|
| 11993 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 11994 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 |
|---|
| 11995 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x42CC098ull |
|---|
| 11996 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 11997 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 |
|---|
| 11998 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x42CC0F0ull |
|---|
| 11999 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 12000 | #define DCORE1_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 12001 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x42CC15Cull |
|---|
| 12002 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12003 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 12004 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x42CC170ull |
|---|
| 12005 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12006 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 12007 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x42CC184ull |
|---|
| 12008 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12009 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 12010 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x42CC198ull |
|---|
| 12011 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12012 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 12013 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x42CC1ACull |
|---|
| 12014 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12015 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 12016 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x42CC1C0ull |
|---|
| 12017 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12018 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 12019 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x42CC1D4ull |
|---|
| 12020 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12021 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 12022 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x42CC1E8ull |
|---|
| 12023 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12024 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 12025 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x42CC1FCull |
|---|
| 12026 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12027 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 12028 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x42CC210ull |
|---|
| 12029 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12030 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 12031 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x42CC22Cull |
|---|
| 12032 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12033 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 12034 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x42CC240ull |
|---|
| 12035 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12036 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 12037 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x42CC254ull |
|---|
| 12038 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12039 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 12040 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x42CC268ull |
|---|
| 12041 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12042 | #define DCORE1_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 12043 | #define mmDCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x42CC280ull |
|---|
| 12044 | #define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 12045 | #define DCORE1_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 12046 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x42CC308ull |
|---|
| 12047 | #define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 12048 | #define DCORE1_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 |
|---|
| 12049 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x42CC328ull |
|---|
| 12050 | #define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 12051 | #define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 12052 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x42CC340ull |
|---|
| 12053 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 12054 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 |
|---|
| 12055 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x42CC398ull |
|---|
| 12056 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 12057 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 |
|---|
| 12058 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x42CC3F0ull |
|---|
| 12059 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 12060 | #define DCORE1_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 12061 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x42CC45Cull |
|---|
| 12062 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12063 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 12064 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x42CC470ull |
|---|
| 12065 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12066 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 12067 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x42CC484ull |
|---|
| 12068 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12069 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 12070 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x42CC498ull |
|---|
| 12071 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12072 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 12073 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x42CC4ACull |
|---|
| 12074 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12075 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 12076 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x42CC4C0ull |
|---|
| 12077 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12078 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 12079 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x42CC4D4ull |
|---|
| 12080 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12081 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 12082 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x42CC4E8ull |
|---|
| 12083 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12084 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 12085 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x42CC4FCull |
|---|
| 12086 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12087 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 12088 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x42CC510ull |
|---|
| 12089 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12090 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 12091 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x42CC52Cull |
|---|
| 12092 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12093 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 12094 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x42CC540ull |
|---|
| 12095 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12096 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 12097 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x42CC554ull |
|---|
| 12098 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12099 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 12100 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x42CC568ull |
|---|
| 12101 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12102 | #define DCORE1_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 12103 | #define mmDCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x42CC580ull |
|---|
| 12104 | #define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 12105 | #define DCORE1_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 12106 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x42CC608ull |
|---|
| 12107 | #define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 12108 | #define DCORE1_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 |
|---|
| 12109 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x42CC628ull |
|---|
| 12110 | #define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 12111 | #define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 12112 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x42CC640ull |
|---|
| 12113 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 12114 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 |
|---|
| 12115 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x42CC698ull |
|---|
| 12116 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 12117 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 |
|---|
| 12118 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x42CC6F0ull |
|---|
| 12119 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 12120 | #define DCORE1_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 12121 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x42CC75Cull |
|---|
| 12122 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12123 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 12124 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x42CC770ull |
|---|
| 12125 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12126 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 12127 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x42CC784ull |
|---|
| 12128 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12129 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 12130 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x42CC798ull |
|---|
| 12131 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12132 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 12133 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x42CC7ACull |
|---|
| 12134 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12135 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 12136 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x42CC7C0ull |
|---|
| 12137 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12138 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 12139 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x42CC7D4ull |
|---|
| 12140 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12141 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 12142 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x42CC7E8ull |
|---|
| 12143 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12144 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 12145 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x42CC7FCull |
|---|
| 12146 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12147 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 12148 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x42CC810ull |
|---|
| 12149 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12150 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 12151 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x42CC82Cull |
|---|
| 12152 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12153 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 12154 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x42CC840ull |
|---|
| 12155 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12156 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 12157 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x42CC854ull |
|---|
| 12158 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12159 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 12160 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x42CC868ull |
|---|
| 12161 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12162 | #define DCORE1_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 12163 | #define mmDCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x42CC880ull |
|---|
| 12164 | #define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 12165 | #define DCORE1_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 12166 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x42CC908ull |
|---|
| 12167 | #define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 12168 | #define DCORE1_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 |
|---|
| 12169 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x42CC928ull |
|---|
| 12170 | #define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 12171 | #define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 12172 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x42CC940ull |
|---|
| 12173 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 12174 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 |
|---|
| 12175 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x42CC998ull |
|---|
| 12176 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 12177 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 |
|---|
| 12178 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x42CC9F0ull |
|---|
| 12179 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 12180 | #define DCORE1_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 12181 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x42CCA5Cull |
|---|
| 12182 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12183 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 12184 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x42CCA70ull |
|---|
| 12185 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12186 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 12187 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x42CCA84ull |
|---|
| 12188 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12189 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 12190 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x42CCA98ull |
|---|
| 12191 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12192 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 12193 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x42CCAACull |
|---|
| 12194 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12195 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 12196 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x42CCAC0ull |
|---|
| 12197 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12198 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 12199 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x42CCAD4ull |
|---|
| 12200 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12201 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 12202 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x42CCAE8ull |
|---|
| 12203 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12204 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 12205 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x42CCAFCull |
|---|
| 12206 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12207 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 12208 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x42CCB10ull |
|---|
| 12209 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12210 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 12211 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x42CCB2Cull |
|---|
| 12212 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12213 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 12214 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x42CCB40ull |
|---|
| 12215 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12216 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 12217 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x42CCB54ull |
|---|
| 12218 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 12219 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 12220 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x42CCB68ull |
|---|
| 12221 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 12222 | #define DCORE1_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 12223 | #define mmDCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x42CCB80ull |
|---|
| 12224 | #define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 12225 | #define DCORE1_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 |
|---|
| 12226 | #define mmDCORE1_MME_CTRL_HI_SPECIAL_BASE 0x42CCE80ull |
|---|
| 12227 | #define DCORE1_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12228 | #define DCORE1_MME_CTRL_HI_SPECIAL_SECTION 0x1800 |
|---|
| 12229 | #define mmDCORE1_MME_EU_BIST_BASE 0x42CD000ull |
|---|
| 12230 | #define DCORE1_MME_EU_BIST_MAX_OFFSET 0x1000 |
|---|
| 12231 | #define DCORE1_MME_EU_BIST_SECTION 0xE800 |
|---|
| 12232 | #define mmDCORE1_MME_EU_BIST_SPECIAL_BASE 0x42CDE80ull |
|---|
| 12233 | #define DCORE1_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12234 | #define DCORE1_MME_EU_BIST_SPECIAL_SECTION 0x1800 |
|---|
| 12235 | #define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x42CE000ull |
|---|
| 12236 | #define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12237 | #define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12238 | #define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x42CE200ull |
|---|
| 12239 | #define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12240 | #define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12241 | #define mmDCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x42CE400ull |
|---|
| 12242 | #define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12243 | #define DCORE1_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12244 | #define mmDCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x42CE600ull |
|---|
| 12245 | #define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12246 | #define DCORE1_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12247 | #define mmDCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x42CE800ull |
|---|
| 12248 | #define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12249 | #define DCORE1_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12250 | #define mmDCORE1_MME_CTRL_MSTR_IF_AXUSER_BASE 0x42CEA80ull |
|---|
| 12251 | #define DCORE1_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12252 | #define DCORE1_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12253 | #define mmDCORE1_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x42CEB00ull |
|---|
| 12254 | #define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12255 | #define DCORE1_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12256 | #define mmDCORE1_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x42CEB80ull |
|---|
| 12257 | #define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12258 | #define DCORE1_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12259 | #define mmDCORE1_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x42CEC00ull |
|---|
| 12260 | #define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12261 | #define DCORE1_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12262 | #define mmDCORE1_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x42CED80ull |
|---|
| 12263 | #define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12264 | #define DCORE1_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12265 | #define mmDCORE1_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x42CEE80ull |
|---|
| 12266 | #define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12267 | #define DCORE1_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12268 | #define mmDCORE1_MME_QM_ARC_ACP_ENG_BASE 0x42CF000ull |
|---|
| 12269 | #define DCORE1_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 |
|---|
| 12270 | #define DCORE1_MME_QM_ARC_ACP_ENG_SECTION 0xE800 |
|---|
| 12271 | #define mmDCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x42CFE80ull |
|---|
| 12272 | #define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12273 | #define DCORE1_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 12274 | #define mmDCORE1_MME_SBTE0_BASE 0x42D0000ull |
|---|
| 12275 | #define DCORE1_MME_SBTE0_MAX_OFFSET 0x1000 |
|---|
| 12276 | #define DCORE1_MME_SBTE0_SECTION 0xE800 |
|---|
| 12277 | #define mmDCORE1_MME_SBTE0_SPECIAL_BASE 0x42D0E80ull |
|---|
| 12278 | #define DCORE1_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12279 | #define DCORE1_MME_SBTE0_SPECIAL_SECTION 0x1800 |
|---|
| 12280 | #define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x42D1000ull |
|---|
| 12281 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12282 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12283 | #define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x42D1200ull |
|---|
| 12284 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12285 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12286 | #define mmDCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x42D1400ull |
|---|
| 12287 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12288 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12289 | #define mmDCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x42D1600ull |
|---|
| 12290 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12291 | #define DCORE1_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12292 | #define mmDCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x42D1800ull |
|---|
| 12293 | #define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12294 | #define DCORE1_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12295 | #define mmDCORE1_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x42D1A80ull |
|---|
| 12296 | #define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12297 | #define DCORE1_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12298 | #define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x42D1B00ull |
|---|
| 12299 | #define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12300 | #define DCORE1_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12301 | #define mmDCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x42D1B80ull |
|---|
| 12302 | #define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12303 | #define DCORE1_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12304 | #define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x42D1C00ull |
|---|
| 12305 | #define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12306 | #define DCORE1_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12307 | #define mmDCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x42D1D80ull |
|---|
| 12308 | #define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12309 | #define DCORE1_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12310 | #define mmDCORE1_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x42D1E80ull |
|---|
| 12311 | #define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12312 | #define DCORE1_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 12313 | #define mmDCORE1_MME_SBTE1_BASE 0x42D8000ull |
|---|
| 12314 | #define DCORE1_MME_SBTE1_MAX_OFFSET 0x1000 |
|---|
| 12315 | #define DCORE1_MME_SBTE1_SECTION 0xE800 |
|---|
| 12316 | #define mmDCORE1_MME_SBTE1_SPECIAL_BASE 0x42D8E80ull |
|---|
| 12317 | #define DCORE1_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12318 | #define DCORE1_MME_SBTE1_SPECIAL_SECTION 0x1800 |
|---|
| 12319 | #define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x42D9000ull |
|---|
| 12320 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12321 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12322 | #define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x42D9200ull |
|---|
| 12323 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12324 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12325 | #define mmDCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x42D9400ull |
|---|
| 12326 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12327 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12328 | #define mmDCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x42D9600ull |
|---|
| 12329 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12330 | #define DCORE1_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12331 | #define mmDCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x42D9800ull |
|---|
| 12332 | #define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12333 | #define DCORE1_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12334 | #define mmDCORE1_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x42D9A80ull |
|---|
| 12335 | #define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12336 | #define DCORE1_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12337 | #define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x42D9B00ull |
|---|
| 12338 | #define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12339 | #define DCORE1_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12340 | #define mmDCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x42D9B80ull |
|---|
| 12341 | #define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12342 | #define DCORE1_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12343 | #define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x42D9C00ull |
|---|
| 12344 | #define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12345 | #define DCORE1_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12346 | #define mmDCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x42D9D80ull |
|---|
| 12347 | #define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12348 | #define DCORE1_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12349 | #define mmDCORE1_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x42D9E80ull |
|---|
| 12350 | #define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12351 | #define DCORE1_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 12352 | #define mmDCORE1_MME_SBTE2_BASE 0x42E0000ull |
|---|
| 12353 | #define DCORE1_MME_SBTE2_MAX_OFFSET 0x1000 |
|---|
| 12354 | #define DCORE1_MME_SBTE2_SECTION 0xE800 |
|---|
| 12355 | #define mmDCORE1_MME_SBTE2_SPECIAL_BASE 0x42E0E80ull |
|---|
| 12356 | #define DCORE1_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12357 | #define DCORE1_MME_SBTE2_SPECIAL_SECTION 0x1800 |
|---|
| 12358 | #define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x42E1000ull |
|---|
| 12359 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12360 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12361 | #define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x42E1200ull |
|---|
| 12362 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12363 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12364 | #define mmDCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x42E1400ull |
|---|
| 12365 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12366 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12367 | #define mmDCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x42E1600ull |
|---|
| 12368 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12369 | #define DCORE1_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12370 | #define mmDCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x42E1800ull |
|---|
| 12371 | #define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12372 | #define DCORE1_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12373 | #define mmDCORE1_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x42E1A80ull |
|---|
| 12374 | #define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12375 | #define DCORE1_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12376 | #define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x42E1B00ull |
|---|
| 12377 | #define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12378 | #define DCORE1_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12379 | #define mmDCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x42E1B80ull |
|---|
| 12380 | #define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12381 | #define DCORE1_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12382 | #define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x42E1C00ull |
|---|
| 12383 | #define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12384 | #define DCORE1_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12385 | #define mmDCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x42E1D80ull |
|---|
| 12386 | #define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12387 | #define DCORE1_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12388 | #define mmDCORE1_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x42E1E80ull |
|---|
| 12389 | #define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12390 | #define DCORE1_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 12391 | #define mmDCORE1_MME_SBTE3_BASE 0x42E8000ull |
|---|
| 12392 | #define DCORE1_MME_SBTE3_MAX_OFFSET 0x1000 |
|---|
| 12393 | #define DCORE1_MME_SBTE3_SECTION 0xE800 |
|---|
| 12394 | #define mmDCORE1_MME_SBTE3_SPECIAL_BASE 0x42E8E80ull |
|---|
| 12395 | #define DCORE1_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12396 | #define DCORE1_MME_SBTE3_SPECIAL_SECTION 0x1800 |
|---|
| 12397 | #define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x42E9000ull |
|---|
| 12398 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12399 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12400 | #define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x42E9200ull |
|---|
| 12401 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12402 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12403 | #define mmDCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x42E9400ull |
|---|
| 12404 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12405 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12406 | #define mmDCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x42E9600ull |
|---|
| 12407 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12408 | #define DCORE1_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12409 | #define mmDCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x42E9800ull |
|---|
| 12410 | #define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12411 | #define DCORE1_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12412 | #define mmDCORE1_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x42E9A80ull |
|---|
| 12413 | #define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12414 | #define DCORE1_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12415 | #define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x42E9B00ull |
|---|
| 12416 | #define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12417 | #define DCORE1_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12418 | #define mmDCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x42E9B80ull |
|---|
| 12419 | #define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12420 | #define DCORE1_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12421 | #define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x42E9C00ull |
|---|
| 12422 | #define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12423 | #define DCORE1_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12424 | #define mmDCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x42E9D80ull |
|---|
| 12425 | #define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12426 | #define DCORE1_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12427 | #define mmDCORE1_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x42E9E80ull |
|---|
| 12428 | #define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12429 | #define DCORE1_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 12430 | #define mmDCORE1_MME_SBTE4_BASE 0x42F0000ull |
|---|
| 12431 | #define DCORE1_MME_SBTE4_MAX_OFFSET 0x1000 |
|---|
| 12432 | #define DCORE1_MME_SBTE4_SECTION 0xE800 |
|---|
| 12433 | #define mmDCORE1_MME_SBTE4_SPECIAL_BASE 0x42F0E80ull |
|---|
| 12434 | #define DCORE1_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12435 | #define DCORE1_MME_SBTE4_SPECIAL_SECTION 0x1800 |
|---|
| 12436 | #define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x42F1000ull |
|---|
| 12437 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12438 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12439 | #define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x42F1200ull |
|---|
| 12440 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12441 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12442 | #define mmDCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x42F1400ull |
|---|
| 12443 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12444 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12445 | #define mmDCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x42F1600ull |
|---|
| 12446 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12447 | #define DCORE1_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12448 | #define mmDCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x42F1800ull |
|---|
| 12449 | #define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12450 | #define DCORE1_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12451 | #define mmDCORE1_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x42F1A80ull |
|---|
| 12452 | #define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12453 | #define DCORE1_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12454 | #define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x42F1B00ull |
|---|
| 12455 | #define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12456 | #define DCORE1_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12457 | #define mmDCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x42F1B80ull |
|---|
| 12458 | #define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12459 | #define DCORE1_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12460 | #define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x42F1C00ull |
|---|
| 12461 | #define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12462 | #define DCORE1_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12463 | #define mmDCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x42F1D80ull |
|---|
| 12464 | #define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12465 | #define DCORE1_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12466 | #define mmDCORE1_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x42F1E80ull |
|---|
| 12467 | #define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12468 | #define DCORE1_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 12469 | #define mmDCORE1_MME_ACC_BASE 0x42F8000ull |
|---|
| 12470 | #define DCORE1_MME_ACC_MAX_OFFSET 0x1000 |
|---|
| 12471 | #define DCORE1_MME_ACC_SECTION 0xE800 |
|---|
| 12472 | #define mmDCORE1_MME_ACC_SPECIAL_BASE 0x42F8E80ull |
|---|
| 12473 | #define DCORE1_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12474 | #define DCORE1_MME_ACC_SPECIAL_SECTION 0x1800 |
|---|
| 12475 | #define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x42F9000ull |
|---|
| 12476 | #define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12477 | #define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12478 | #define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x42F9200ull |
|---|
| 12479 | #define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12480 | #define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12481 | #define mmDCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x42F9400ull |
|---|
| 12482 | #define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12483 | #define DCORE1_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12484 | #define mmDCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x42F9600ull |
|---|
| 12485 | #define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12486 | #define DCORE1_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12487 | #define mmDCORE1_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x42F9800ull |
|---|
| 12488 | #define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12489 | #define DCORE1_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12490 | #define mmDCORE1_MME_WB0_MSTR_IF_AXUSER_BASE 0x42F9A80ull |
|---|
| 12491 | #define DCORE1_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12492 | #define DCORE1_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12493 | #define mmDCORE1_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x42F9B00ull |
|---|
| 12494 | #define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12495 | #define DCORE1_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12496 | #define mmDCORE1_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x42F9B80ull |
|---|
| 12497 | #define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12498 | #define DCORE1_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12499 | #define mmDCORE1_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x42F9C00ull |
|---|
| 12500 | #define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12501 | #define DCORE1_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12502 | #define mmDCORE1_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x42F9D80ull |
|---|
| 12503 | #define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12504 | #define DCORE1_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12505 | #define mmDCORE1_MME_WB0_MSTR_IF_SPECIAL_BASE 0x42F9E80ull |
|---|
| 12506 | #define DCORE1_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12507 | #define DCORE1_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12508 | #define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x42FA000ull |
|---|
| 12509 | #define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12510 | #define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12511 | #define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x42FA200ull |
|---|
| 12512 | #define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12513 | #define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12514 | #define mmDCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x42FA400ull |
|---|
| 12515 | #define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12516 | #define DCORE1_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12517 | #define mmDCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x42FA600ull |
|---|
| 12518 | #define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12519 | #define DCORE1_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12520 | #define mmDCORE1_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x42FA800ull |
|---|
| 12521 | #define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12522 | #define DCORE1_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12523 | #define mmDCORE1_MME_WB1_MSTR_IF_AXUSER_BASE 0x42FAA80ull |
|---|
| 12524 | #define DCORE1_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12525 | #define DCORE1_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12526 | #define mmDCORE1_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x42FAB00ull |
|---|
| 12527 | #define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12528 | #define DCORE1_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12529 | #define mmDCORE1_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x42FAB80ull |
|---|
| 12530 | #define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12531 | #define DCORE1_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12532 | #define mmDCORE1_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x42FAC00ull |
|---|
| 12533 | #define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12534 | #define DCORE1_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12535 | #define mmDCORE1_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x42FAD80ull |
|---|
| 12536 | #define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12537 | #define DCORE1_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12538 | #define mmDCORE1_MME_WB1_MSTR_IF_SPECIAL_BASE 0x42FAE80ull |
|---|
| 12539 | #define DCORE1_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12540 | #define DCORE1_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 |
|---|
| 12541 | #define mmDCORE1_SYNC_MNGR_OBJS_BASE 0x4300000ull |
|---|
| 12542 | #define DCORE1_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 |
|---|
| 12543 | #define DCORE1_SYNC_MNGR_OBJS_SECTION 0x1E000 |
|---|
| 12544 | #define mmDCORE1_SYNC_MNGR_GLBL_BASE 0x431E000ull |
|---|
| 12545 | #define DCORE1_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 |
|---|
| 12546 | #define DCORE1_SYNC_MNGR_GLBL_SECTION 0xE800 |
|---|
| 12547 | #define mmDCORE1_SYNC_MNGR_GLBL_SPECIAL_BASE 0x431EE80ull |
|---|
| 12548 | #define DCORE1_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12549 | #define DCORE1_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 |
|---|
| 12550 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x431F000ull |
|---|
| 12551 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12552 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12553 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x431F200ull |
|---|
| 12554 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12555 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12556 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x431F400ull |
|---|
| 12557 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12558 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12559 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x431F600ull |
|---|
| 12560 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12561 | #define DCORE1_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12562 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x431F800ull |
|---|
| 12563 | #define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12564 | #define DCORE1_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12565 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x431FA80ull |
|---|
| 12566 | #define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12567 | #define DCORE1_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12568 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x431FB00ull |
|---|
| 12569 | #define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12570 | #define DCORE1_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12571 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x431FB80ull |
|---|
| 12572 | #define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12573 | #define DCORE1_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12574 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x431FC00ull |
|---|
| 12575 | #define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12576 | #define DCORE1_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12577 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x431FD80ull |
|---|
| 12578 | #define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12579 | #define DCORE1_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12580 | #define mmDCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x431FE80ull |
|---|
| 12581 | #define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12582 | #define DCORE1_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12583 | #define mmDCORE1_HIF0_BASE 0x4320000ull |
|---|
| 12584 | #define DCORE1_HIF0_MAX_OFFSET 0x1000 |
|---|
| 12585 | #define DCORE1_HIF0_SECTION 0xE800 |
|---|
| 12586 | #define mmDCORE1_HIF0_SPECIAL_BASE 0x4320E80ull |
|---|
| 12587 | #define DCORE1_HIF0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12588 | #define DCORE1_HIF0_SPECIAL_SECTION 0x3180 |
|---|
| 12589 | #define mmDCORE1_HIF1_BASE 0x4324000ull |
|---|
| 12590 | #define DCORE1_HIF1_MAX_OFFSET 0x1000 |
|---|
| 12591 | #define DCORE1_HIF1_SECTION 0xE800 |
|---|
| 12592 | #define mmDCORE1_HIF1_SPECIAL_BASE 0x4324E80ull |
|---|
| 12593 | #define DCORE1_HIF1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12594 | #define DCORE1_HIF1_SPECIAL_SECTION 0x3180 |
|---|
| 12595 | #define mmDCORE1_HIF2_BASE 0x4328000ull |
|---|
| 12596 | #define DCORE1_HIF2_MAX_OFFSET 0x1000 |
|---|
| 12597 | #define DCORE1_HIF2_SECTION 0xE800 |
|---|
| 12598 | #define mmDCORE1_HIF2_SPECIAL_BASE 0x4328E80ull |
|---|
| 12599 | #define DCORE1_HIF2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12600 | #define DCORE1_HIF2_SPECIAL_SECTION 0x3180 |
|---|
| 12601 | #define mmDCORE1_HIF3_BASE 0x432C000ull |
|---|
| 12602 | #define DCORE1_HIF3_MAX_OFFSET 0x1000 |
|---|
| 12603 | #define DCORE1_HIF3_SECTION 0xE800 |
|---|
| 12604 | #define mmDCORE1_HIF3_SPECIAL_BASE 0x432CE80ull |
|---|
| 12605 | #define DCORE1_HIF3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12606 | #define DCORE1_HIF3_SPECIAL_SECTION 0x13180 |
|---|
| 12607 | #define mmDCORE1_RTR0_CTRL_BASE 0x4340000ull |
|---|
| 12608 | #define DCORE1_RTR0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 12609 | #define DCORE1_RTR0_CTRL_SECTION 0xE800 |
|---|
| 12610 | #define mmDCORE1_RTR0_CTRL_SPECIAL_BASE 0x4340E80ull |
|---|
| 12611 | #define DCORE1_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12612 | #define DCORE1_RTR0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 12613 | #define mmDCORE1_RTR0_H3_BASE 0x4341000ull |
|---|
| 12614 | #define DCORE1_RTR0_H3_MAX_OFFSET 0x1000 |
|---|
| 12615 | #define DCORE1_RTR0_H3_SECTION 0xE800 |
|---|
| 12616 | #define mmDCORE1_RTR0_H3_SPECIAL_BASE 0x4341E80ull |
|---|
| 12617 | #define DCORE1_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12618 | #define DCORE1_RTR0_H3_SPECIAL_SECTION 0x1800 |
|---|
| 12619 | #define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4342000ull |
|---|
| 12620 | #define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12621 | #define DCORE1_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12622 | #define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4342200ull |
|---|
| 12623 | #define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12624 | #define DCORE1_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12625 | #define mmDCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4342400ull |
|---|
| 12626 | #define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12627 | #define DCORE1_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12628 | #define mmDCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4342600ull |
|---|
| 12629 | #define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12630 | #define DCORE1_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12631 | #define mmDCORE1_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4342800ull |
|---|
| 12632 | #define DCORE1_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12633 | #define DCORE1_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12634 | #define mmDCORE1_RTR0_MSTR_IF_AXUSER_BASE 0x4342A80ull |
|---|
| 12635 | #define DCORE1_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12636 | #define DCORE1_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12637 | #define mmDCORE1_RTR0_MSTR_IF_DBG_HBW_BASE 0x4342B00ull |
|---|
| 12638 | #define DCORE1_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12639 | #define DCORE1_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12640 | #define mmDCORE1_RTR0_MSTR_IF_DBG_LBW_BASE 0x4342B80ull |
|---|
| 12641 | #define DCORE1_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12642 | #define DCORE1_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12643 | #define mmDCORE1_RTR0_MSTR_IF_CORE_HBW_BASE 0x4342C00ull |
|---|
| 12644 | #define DCORE1_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12645 | #define DCORE1_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12646 | #define mmDCORE1_RTR0_MSTR_IF_CORE_LBW_BASE 0x4342D80ull |
|---|
| 12647 | #define DCORE1_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12648 | #define DCORE1_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12649 | #define mmDCORE1_RTR0_MSTR_IF_SPECIAL_BASE 0x4342E80ull |
|---|
| 12650 | #define DCORE1_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12651 | #define DCORE1_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12652 | #define mmDCORE1_RTR0_ADD_DEC_HBW_BASE 0x4343000ull |
|---|
| 12653 | #define DCORE1_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 12654 | #define DCORE1_RTR0_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 12655 | #define mmDCORE1_RTR0_ADD_DEC_LBW_BASE 0x4343400ull |
|---|
| 12656 | #define DCORE1_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 12657 | #define DCORE1_RTR0_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 12658 | #define mmDCORE1_RTR0_ADD_DEC_SPECIAL_BASE 0x4343E80ull |
|---|
| 12659 | #define DCORE1_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12660 | #define DCORE1_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 12661 | #define mmDCORE1_RTR0_BASE 0x4344000ull |
|---|
| 12662 | #define DCORE1_RTR0_MAX_OFFSET 0x1000 |
|---|
| 12663 | #define DCORE1_RTR0_SECTION 0x3000 |
|---|
| 12664 | #define mmDCORE1_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4344300ull |
|---|
| 12665 | #define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12666 | #define DCORE1_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12667 | #define mmDCORE1_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4344340ull |
|---|
| 12668 | #define DCORE1_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12669 | #define DCORE1_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12670 | #define mmDCORE1_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4344380ull |
|---|
| 12671 | #define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12672 | #define DCORE1_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12673 | #define mmDCORE1_RTR0_HBW_WR_RS_LL_STAT_BASE 0x43443C0ull |
|---|
| 12674 | #define DCORE1_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12675 | #define DCORE1_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12676 | #define mmDCORE1_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4344400ull |
|---|
| 12677 | #define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12678 | #define DCORE1_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12679 | #define mmDCORE1_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4344440ull |
|---|
| 12680 | #define DCORE1_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12681 | #define DCORE1_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12682 | #define mmDCORE1_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4344480ull |
|---|
| 12683 | #define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12684 | #define DCORE1_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12685 | #define mmDCORE1_RTR0_LBW_WR_RS_LL_STAT_BASE 0x43444C0ull |
|---|
| 12686 | #define DCORE1_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12687 | #define DCORE1_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12688 | #define mmDCORE1_RTR0_HBW_MFIFO_BASE 0x4344500ull |
|---|
| 12689 | #define DCORE1_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 12690 | #define DCORE1_RTR0_HBW_MFIFO_SECTION 0x4000 |
|---|
| 12691 | #define mmDCORE1_RTR0_E2E_RD_LL_STAT_BASE 0x4344540ull |
|---|
| 12692 | #define DCORE1_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12693 | #define DCORE1_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 12694 | #define mmDCORE1_RTR0_E2E_WR_LL_STAT_BASE 0x4344580ull |
|---|
| 12695 | #define DCORE1_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12696 | #define DCORE1_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 12697 | #define mmDCORE1_RTR0_RTR_HBW_XACT_STAT_BASE 0x4344600ull |
|---|
| 12698 | #define DCORE1_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12699 | #define DCORE1_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12700 | #define mmDCORE1_RTR0_RTR_LBW_XACT_STAT_BASE 0x4344680ull |
|---|
| 12701 | #define DCORE1_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12702 | #define DCORE1_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12703 | #define mmDCORE1_RTR0_RTR_E2E_XACT_STAT_BASE 0x4344700ull |
|---|
| 12704 | #define DCORE1_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12705 | #define DCORE1_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 12706 | #define mmDCORE1_RTR0_SPECIAL_BASE 0x4344E80ull |
|---|
| 12707 | #define DCORE1_RTR0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12708 | #define DCORE1_RTR0_SPECIAL_SECTION 0x1800 |
|---|
| 12709 | #define mmDCORE1_RTR0_DBG_ADDR_BASE 0x4345000ull |
|---|
| 12710 | #define DCORE1_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 12711 | #define DCORE1_RTR0_DBG_ADDR_SECTION 0xE800 |
|---|
| 12712 | #define mmDCORE1_RTR0_DBG_ADDR_SPECIAL_BASE 0x4345E80ull |
|---|
| 12713 | #define DCORE1_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12714 | #define DCORE1_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 12715 | #define mmDCORE1_RTR1_CTRL_BASE 0x4348000ull |
|---|
| 12716 | #define DCORE1_RTR1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 12717 | #define DCORE1_RTR1_CTRL_SECTION 0xE800 |
|---|
| 12718 | #define mmDCORE1_RTR1_CTRL_SPECIAL_BASE 0x4348E80ull |
|---|
| 12719 | #define DCORE1_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12720 | #define DCORE1_RTR1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 12721 | #define mmDCORE1_RTR1_H3_BASE 0x4349000ull |
|---|
| 12722 | #define DCORE1_RTR1_H3_MAX_OFFSET 0x1000 |
|---|
| 12723 | #define DCORE1_RTR1_H3_SECTION 0xE800 |
|---|
| 12724 | #define mmDCORE1_RTR1_H3_SPECIAL_BASE 0x4349E80ull |
|---|
| 12725 | #define DCORE1_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12726 | #define DCORE1_RTR1_H3_SPECIAL_SECTION 0x1800 |
|---|
| 12727 | #define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x434A000ull |
|---|
| 12728 | #define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12729 | #define DCORE1_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12730 | #define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x434A200ull |
|---|
| 12731 | #define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12732 | #define DCORE1_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12733 | #define mmDCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x434A400ull |
|---|
| 12734 | #define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12735 | #define DCORE1_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12736 | #define mmDCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x434A600ull |
|---|
| 12737 | #define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12738 | #define DCORE1_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12739 | #define mmDCORE1_RTR1_MSTR_IF_E2E_CRDT_BASE 0x434A800ull |
|---|
| 12740 | #define DCORE1_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12741 | #define DCORE1_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12742 | #define mmDCORE1_RTR1_MSTR_IF_AXUSER_BASE 0x434AA80ull |
|---|
| 12743 | #define DCORE1_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12744 | #define DCORE1_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12745 | #define mmDCORE1_RTR1_MSTR_IF_DBG_HBW_BASE 0x434AB00ull |
|---|
| 12746 | #define DCORE1_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12747 | #define DCORE1_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12748 | #define mmDCORE1_RTR1_MSTR_IF_DBG_LBW_BASE 0x434AB80ull |
|---|
| 12749 | #define DCORE1_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12750 | #define DCORE1_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12751 | #define mmDCORE1_RTR1_MSTR_IF_CORE_HBW_BASE 0x434AC00ull |
|---|
| 12752 | #define DCORE1_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12753 | #define DCORE1_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12754 | #define mmDCORE1_RTR1_MSTR_IF_CORE_LBW_BASE 0x434AD80ull |
|---|
| 12755 | #define DCORE1_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12756 | #define DCORE1_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12757 | #define mmDCORE1_RTR1_MSTR_IF_SPECIAL_BASE 0x434AE80ull |
|---|
| 12758 | #define DCORE1_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12759 | #define DCORE1_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12760 | #define mmDCORE1_RTR1_ADD_DEC_HBW_BASE 0x434B000ull |
|---|
| 12761 | #define DCORE1_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 12762 | #define DCORE1_RTR1_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 12763 | #define mmDCORE1_RTR1_ADD_DEC_LBW_BASE 0x434B400ull |
|---|
| 12764 | #define DCORE1_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 12765 | #define DCORE1_RTR1_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 12766 | #define mmDCORE1_RTR1_ADD_DEC_SPECIAL_BASE 0x434BE80ull |
|---|
| 12767 | #define DCORE1_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12768 | #define DCORE1_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 12769 | #define mmDCORE1_RTR1_BASE 0x434C000ull |
|---|
| 12770 | #define DCORE1_RTR1_MAX_OFFSET 0x1000 |
|---|
| 12771 | #define DCORE1_RTR1_SECTION 0x3000 |
|---|
| 12772 | #define mmDCORE1_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x434C300ull |
|---|
| 12773 | #define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12774 | #define DCORE1_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12775 | #define mmDCORE1_RTR1_HBW_RD_RS_LL_STAT_BASE 0x434C340ull |
|---|
| 12776 | #define DCORE1_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12777 | #define DCORE1_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12778 | #define mmDCORE1_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x434C380ull |
|---|
| 12779 | #define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12780 | #define DCORE1_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12781 | #define mmDCORE1_RTR1_HBW_WR_RS_LL_STAT_BASE 0x434C3C0ull |
|---|
| 12782 | #define DCORE1_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12783 | #define DCORE1_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12784 | #define mmDCORE1_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x434C400ull |
|---|
| 12785 | #define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12786 | #define DCORE1_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12787 | #define mmDCORE1_RTR1_LBW_RD_RS_LL_STAT_BASE 0x434C440ull |
|---|
| 12788 | #define DCORE1_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12789 | #define DCORE1_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12790 | #define mmDCORE1_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x434C480ull |
|---|
| 12791 | #define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12792 | #define DCORE1_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12793 | #define mmDCORE1_RTR1_LBW_WR_RS_LL_STAT_BASE 0x434C4C0ull |
|---|
| 12794 | #define DCORE1_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12795 | #define DCORE1_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12796 | #define mmDCORE1_RTR1_HBW_MFIFO_BASE 0x434C500ull |
|---|
| 12797 | #define DCORE1_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 12798 | #define DCORE1_RTR1_HBW_MFIFO_SECTION 0x4000 |
|---|
| 12799 | #define mmDCORE1_RTR1_E2E_RD_LL_STAT_BASE 0x434C540ull |
|---|
| 12800 | #define DCORE1_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12801 | #define DCORE1_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 12802 | #define mmDCORE1_RTR1_E2E_WR_LL_STAT_BASE 0x434C580ull |
|---|
| 12803 | #define DCORE1_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12804 | #define DCORE1_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 12805 | #define mmDCORE1_RTR1_RTR_HBW_XACT_STAT_BASE 0x434C600ull |
|---|
| 12806 | #define DCORE1_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12807 | #define DCORE1_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12808 | #define mmDCORE1_RTR1_RTR_LBW_XACT_STAT_BASE 0x434C680ull |
|---|
| 12809 | #define DCORE1_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12810 | #define DCORE1_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12811 | #define mmDCORE1_RTR1_RTR_E2E_XACT_STAT_BASE 0x434C700ull |
|---|
| 12812 | #define DCORE1_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12813 | #define DCORE1_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 12814 | #define mmDCORE1_RTR1_SPECIAL_BASE 0x434CE80ull |
|---|
| 12815 | #define DCORE1_RTR1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12816 | #define DCORE1_RTR1_SPECIAL_SECTION 0x1800 |
|---|
| 12817 | #define mmDCORE1_RTR1_DBG_ADDR_BASE 0x434D000ull |
|---|
| 12818 | #define DCORE1_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 12819 | #define DCORE1_RTR1_DBG_ADDR_SECTION 0xE800 |
|---|
| 12820 | #define mmDCORE1_RTR1_DBG_ADDR_SPECIAL_BASE 0x434DE80ull |
|---|
| 12821 | #define DCORE1_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12822 | #define DCORE1_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 12823 | #define mmDCORE1_RTR2_CTRL_BASE 0x4350000ull |
|---|
| 12824 | #define DCORE1_RTR2_CTRL_MAX_OFFSET 0x1000 |
|---|
| 12825 | #define DCORE1_RTR2_CTRL_SECTION 0xE800 |
|---|
| 12826 | #define mmDCORE1_RTR2_CTRL_SPECIAL_BASE 0x4350E80ull |
|---|
| 12827 | #define DCORE1_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12828 | #define DCORE1_RTR2_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 12829 | #define mmDCORE1_RTR2_H3_BASE 0x4351000ull |
|---|
| 12830 | #define DCORE1_RTR2_H3_MAX_OFFSET 0x1000 |
|---|
| 12831 | #define DCORE1_RTR2_H3_SECTION 0xE800 |
|---|
| 12832 | #define mmDCORE1_RTR2_H3_SPECIAL_BASE 0x4351E80ull |
|---|
| 12833 | #define DCORE1_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12834 | #define DCORE1_RTR2_H3_SPECIAL_SECTION 0x1800 |
|---|
| 12835 | #define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4352000ull |
|---|
| 12836 | #define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12837 | #define DCORE1_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12838 | #define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4352200ull |
|---|
| 12839 | #define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12840 | #define DCORE1_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12841 | #define mmDCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4352400ull |
|---|
| 12842 | #define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12843 | #define DCORE1_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12844 | #define mmDCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4352600ull |
|---|
| 12845 | #define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12846 | #define DCORE1_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12847 | #define mmDCORE1_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4352800ull |
|---|
| 12848 | #define DCORE1_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12849 | #define DCORE1_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12850 | #define mmDCORE1_RTR2_MSTR_IF_AXUSER_BASE 0x4352A80ull |
|---|
| 12851 | #define DCORE1_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12852 | #define DCORE1_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12853 | #define mmDCORE1_RTR2_MSTR_IF_DBG_HBW_BASE 0x4352B00ull |
|---|
| 12854 | #define DCORE1_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12855 | #define DCORE1_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12856 | #define mmDCORE1_RTR2_MSTR_IF_DBG_LBW_BASE 0x4352B80ull |
|---|
| 12857 | #define DCORE1_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12858 | #define DCORE1_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12859 | #define mmDCORE1_RTR2_MSTR_IF_CORE_HBW_BASE 0x4352C00ull |
|---|
| 12860 | #define DCORE1_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12861 | #define DCORE1_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12862 | #define mmDCORE1_RTR2_MSTR_IF_CORE_LBW_BASE 0x4352D80ull |
|---|
| 12863 | #define DCORE1_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12864 | #define DCORE1_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12865 | #define mmDCORE1_RTR2_MSTR_IF_SPECIAL_BASE 0x4352E80ull |
|---|
| 12866 | #define DCORE1_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12867 | #define DCORE1_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12868 | #define mmDCORE1_RTR2_ADD_DEC_HBW_BASE 0x4353000ull |
|---|
| 12869 | #define DCORE1_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 12870 | #define DCORE1_RTR2_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 12871 | #define mmDCORE1_RTR2_ADD_DEC_LBW_BASE 0x4353400ull |
|---|
| 12872 | #define DCORE1_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 12873 | #define DCORE1_RTR2_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 12874 | #define mmDCORE1_RTR2_ADD_DEC_SPECIAL_BASE 0x4353E80ull |
|---|
| 12875 | #define DCORE1_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12876 | #define DCORE1_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 12877 | #define mmDCORE1_RTR2_BASE 0x4354000ull |
|---|
| 12878 | #define DCORE1_RTR2_MAX_OFFSET 0x1000 |
|---|
| 12879 | #define DCORE1_RTR2_SECTION 0x3000 |
|---|
| 12880 | #define mmDCORE1_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4354300ull |
|---|
| 12881 | #define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12882 | #define DCORE1_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12883 | #define mmDCORE1_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4354340ull |
|---|
| 12884 | #define DCORE1_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12885 | #define DCORE1_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12886 | #define mmDCORE1_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4354380ull |
|---|
| 12887 | #define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12888 | #define DCORE1_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12889 | #define mmDCORE1_RTR2_HBW_WR_RS_LL_STAT_BASE 0x43543C0ull |
|---|
| 12890 | #define DCORE1_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12891 | #define DCORE1_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12892 | #define mmDCORE1_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4354400ull |
|---|
| 12893 | #define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12894 | #define DCORE1_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12895 | #define mmDCORE1_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4354440ull |
|---|
| 12896 | #define DCORE1_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12897 | #define DCORE1_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12898 | #define mmDCORE1_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4354480ull |
|---|
| 12899 | #define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12900 | #define DCORE1_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12901 | #define mmDCORE1_RTR2_LBW_WR_RS_LL_STAT_BASE 0x43544C0ull |
|---|
| 12902 | #define DCORE1_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12903 | #define DCORE1_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12904 | #define mmDCORE1_RTR2_HBW_MFIFO_BASE 0x4354500ull |
|---|
| 12905 | #define DCORE1_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 12906 | #define DCORE1_RTR2_HBW_MFIFO_SECTION 0x4000 |
|---|
| 12907 | #define mmDCORE1_RTR2_E2E_RD_LL_STAT_BASE 0x4354540ull |
|---|
| 12908 | #define DCORE1_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12909 | #define DCORE1_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 12910 | #define mmDCORE1_RTR2_E2E_WR_LL_STAT_BASE 0x4354580ull |
|---|
| 12911 | #define DCORE1_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12912 | #define DCORE1_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 12913 | #define mmDCORE1_RTR2_RTR_HBW_XACT_STAT_BASE 0x4354600ull |
|---|
| 12914 | #define DCORE1_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12915 | #define DCORE1_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12916 | #define mmDCORE1_RTR2_RTR_LBW_XACT_STAT_BASE 0x4354680ull |
|---|
| 12917 | #define DCORE1_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12918 | #define DCORE1_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 12919 | #define mmDCORE1_RTR2_RTR_E2E_XACT_STAT_BASE 0x4354700ull |
|---|
| 12920 | #define DCORE1_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 12921 | #define DCORE1_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 12922 | #define mmDCORE1_RTR2_SPECIAL_BASE 0x4354E80ull |
|---|
| 12923 | #define DCORE1_RTR2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12924 | #define DCORE1_RTR2_SPECIAL_SECTION 0x1800 |
|---|
| 12925 | #define mmDCORE1_RTR2_DBG_ADDR_BASE 0x4355000ull |
|---|
| 12926 | #define DCORE1_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 12927 | #define DCORE1_RTR2_DBG_ADDR_SECTION 0xE800 |
|---|
| 12928 | #define mmDCORE1_RTR2_DBG_ADDR_SPECIAL_BASE 0x4355E80ull |
|---|
| 12929 | #define DCORE1_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12930 | #define DCORE1_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 12931 | #define mmDCORE1_RTR3_CTRL_BASE 0x4358000ull |
|---|
| 12932 | #define DCORE1_RTR3_CTRL_MAX_OFFSET 0x1000 |
|---|
| 12933 | #define DCORE1_RTR3_CTRL_SECTION 0xE800 |
|---|
| 12934 | #define mmDCORE1_RTR3_CTRL_SPECIAL_BASE 0x4358E80ull |
|---|
| 12935 | #define DCORE1_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12936 | #define DCORE1_RTR3_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 12937 | #define mmDCORE1_RTR3_H3_BASE 0x4359000ull |
|---|
| 12938 | #define DCORE1_RTR3_H3_MAX_OFFSET 0x1000 |
|---|
| 12939 | #define DCORE1_RTR3_H3_SECTION 0xE800 |
|---|
| 12940 | #define mmDCORE1_RTR3_H3_SPECIAL_BASE 0x4359E80ull |
|---|
| 12941 | #define DCORE1_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12942 | #define DCORE1_RTR3_H3_SPECIAL_SECTION 0x1800 |
|---|
| 12943 | #define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x435A000ull |
|---|
| 12944 | #define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12945 | #define DCORE1_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 12946 | #define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x435A200ull |
|---|
| 12947 | #define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 12948 | #define DCORE1_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 12949 | #define mmDCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x435A400ull |
|---|
| 12950 | #define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12951 | #define DCORE1_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 12952 | #define mmDCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x435A600ull |
|---|
| 12953 | #define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 12954 | #define DCORE1_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 12955 | #define mmDCORE1_RTR3_MSTR_IF_E2E_CRDT_BASE 0x435A800ull |
|---|
| 12956 | #define DCORE1_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 12957 | #define DCORE1_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 12958 | #define mmDCORE1_RTR3_MSTR_IF_AXUSER_BASE 0x435AA80ull |
|---|
| 12959 | #define DCORE1_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 12960 | #define DCORE1_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 12961 | #define mmDCORE1_RTR3_MSTR_IF_DBG_HBW_BASE 0x435AB00ull |
|---|
| 12962 | #define DCORE1_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 12963 | #define DCORE1_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 12964 | #define mmDCORE1_RTR3_MSTR_IF_DBG_LBW_BASE 0x435AB80ull |
|---|
| 12965 | #define DCORE1_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 12966 | #define DCORE1_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 12967 | #define mmDCORE1_RTR3_MSTR_IF_CORE_HBW_BASE 0x435AC00ull |
|---|
| 12968 | #define DCORE1_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 12969 | #define DCORE1_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 12970 | #define mmDCORE1_RTR3_MSTR_IF_CORE_LBW_BASE 0x435AD80ull |
|---|
| 12971 | #define DCORE1_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 12972 | #define DCORE1_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 12973 | #define mmDCORE1_RTR3_MSTR_IF_SPECIAL_BASE 0x435AE80ull |
|---|
| 12974 | #define DCORE1_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12975 | #define DCORE1_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 12976 | #define mmDCORE1_RTR3_ADD_DEC_HBW_BASE 0x435B000ull |
|---|
| 12977 | #define DCORE1_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 12978 | #define DCORE1_RTR3_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 12979 | #define mmDCORE1_RTR3_ADD_DEC_LBW_BASE 0x435B400ull |
|---|
| 12980 | #define DCORE1_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 12981 | #define DCORE1_RTR3_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 12982 | #define mmDCORE1_RTR3_ADD_DEC_SPECIAL_BASE 0x435BE80ull |
|---|
| 12983 | #define DCORE1_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 12984 | #define DCORE1_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 12985 | #define mmDCORE1_RTR3_BASE 0x435C000ull |
|---|
| 12986 | #define DCORE1_RTR3_MAX_OFFSET 0x1000 |
|---|
| 12987 | #define DCORE1_RTR3_SECTION 0x3000 |
|---|
| 12988 | #define mmDCORE1_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x435C300ull |
|---|
| 12989 | #define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12990 | #define DCORE1_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12991 | #define mmDCORE1_RTR3_HBW_RD_RS_LL_STAT_BASE 0x435C340ull |
|---|
| 12992 | #define DCORE1_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12993 | #define DCORE1_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 12994 | #define mmDCORE1_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x435C380ull |
|---|
| 12995 | #define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12996 | #define DCORE1_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 12997 | #define mmDCORE1_RTR3_HBW_WR_RS_LL_STAT_BASE 0x435C3C0ull |
|---|
| 12998 | #define DCORE1_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 12999 | #define DCORE1_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13000 | #define mmDCORE1_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x435C400ull |
|---|
| 13001 | #define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13002 | #define DCORE1_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13003 | #define mmDCORE1_RTR3_LBW_RD_RS_LL_STAT_BASE 0x435C440ull |
|---|
| 13004 | #define DCORE1_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13005 | #define DCORE1_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13006 | #define mmDCORE1_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x435C480ull |
|---|
| 13007 | #define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13008 | #define DCORE1_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13009 | #define mmDCORE1_RTR3_LBW_WR_RS_LL_STAT_BASE 0x435C4C0ull |
|---|
| 13010 | #define DCORE1_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13011 | #define DCORE1_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13012 | #define mmDCORE1_RTR3_HBW_MFIFO_BASE 0x435C500ull |
|---|
| 13013 | #define DCORE1_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 13014 | #define DCORE1_RTR3_HBW_MFIFO_SECTION 0x4000 |
|---|
| 13015 | #define mmDCORE1_RTR3_E2E_RD_LL_STAT_BASE 0x435C540ull |
|---|
| 13016 | #define DCORE1_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13017 | #define DCORE1_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 13018 | #define mmDCORE1_RTR3_E2E_WR_LL_STAT_BASE 0x435C580ull |
|---|
| 13019 | #define DCORE1_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13020 | #define DCORE1_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 13021 | #define mmDCORE1_RTR3_RTR_HBW_XACT_STAT_BASE 0x435C600ull |
|---|
| 13022 | #define DCORE1_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13023 | #define DCORE1_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13024 | #define mmDCORE1_RTR3_RTR_LBW_XACT_STAT_BASE 0x435C680ull |
|---|
| 13025 | #define DCORE1_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13026 | #define DCORE1_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13027 | #define mmDCORE1_RTR3_RTR_E2E_XACT_STAT_BASE 0x435C700ull |
|---|
| 13028 | #define DCORE1_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13029 | #define DCORE1_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 13030 | #define mmDCORE1_RTR3_SPECIAL_BASE 0x435CE80ull |
|---|
| 13031 | #define DCORE1_RTR3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13032 | #define DCORE1_RTR3_SPECIAL_SECTION 0x1800 |
|---|
| 13033 | #define mmDCORE1_RTR3_DBG_ADDR_BASE 0x435D000ull |
|---|
| 13034 | #define DCORE1_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 13035 | #define DCORE1_RTR3_DBG_ADDR_SECTION 0xE800 |
|---|
| 13036 | #define mmDCORE1_RTR3_DBG_ADDR_SPECIAL_BASE 0x435DE80ull |
|---|
| 13037 | #define DCORE1_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13038 | #define DCORE1_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 13039 | #define mmDCORE1_RTR4_CTRL_BASE 0x4360000ull |
|---|
| 13040 | #define DCORE1_RTR4_CTRL_MAX_OFFSET 0x1000 |
|---|
| 13041 | #define DCORE1_RTR4_CTRL_SECTION 0xE800 |
|---|
| 13042 | #define mmDCORE1_RTR4_CTRL_SPECIAL_BASE 0x4360E80ull |
|---|
| 13043 | #define DCORE1_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13044 | #define DCORE1_RTR4_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 13045 | #define mmDCORE1_RTR4_H3_BASE 0x4361000ull |
|---|
| 13046 | #define DCORE1_RTR4_H3_MAX_OFFSET 0x1000 |
|---|
| 13047 | #define DCORE1_RTR4_H3_SECTION 0xE800 |
|---|
| 13048 | #define mmDCORE1_RTR4_H3_SPECIAL_BASE 0x4361E80ull |
|---|
| 13049 | #define DCORE1_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13050 | #define DCORE1_RTR4_H3_SPECIAL_SECTION 0x1800 |
|---|
| 13051 | #define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4362000ull |
|---|
| 13052 | #define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13053 | #define DCORE1_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 13054 | #define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4362200ull |
|---|
| 13055 | #define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13056 | #define DCORE1_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 13057 | #define mmDCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4362400ull |
|---|
| 13058 | #define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13059 | #define DCORE1_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 13060 | #define mmDCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4362600ull |
|---|
| 13061 | #define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13062 | #define DCORE1_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 13063 | #define mmDCORE1_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4362800ull |
|---|
| 13064 | #define DCORE1_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 13065 | #define DCORE1_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 13066 | #define mmDCORE1_RTR4_MSTR_IF_AXUSER_BASE 0x4362A80ull |
|---|
| 13067 | #define DCORE1_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 13068 | #define DCORE1_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 13069 | #define mmDCORE1_RTR4_MSTR_IF_DBG_HBW_BASE 0x4362B00ull |
|---|
| 13070 | #define DCORE1_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 13071 | #define DCORE1_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 13072 | #define mmDCORE1_RTR4_MSTR_IF_DBG_LBW_BASE 0x4362B80ull |
|---|
| 13073 | #define DCORE1_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 13074 | #define DCORE1_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 13075 | #define mmDCORE1_RTR4_MSTR_IF_CORE_HBW_BASE 0x4362C00ull |
|---|
| 13076 | #define DCORE1_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 13077 | #define DCORE1_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 13078 | #define mmDCORE1_RTR4_MSTR_IF_CORE_LBW_BASE 0x4362D80ull |
|---|
| 13079 | #define DCORE1_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 13080 | #define DCORE1_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 13081 | #define mmDCORE1_RTR4_MSTR_IF_SPECIAL_BASE 0x4362E80ull |
|---|
| 13082 | #define DCORE1_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13083 | #define DCORE1_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 13084 | #define mmDCORE1_RTR4_ADD_DEC_HBW_BASE 0x4363000ull |
|---|
| 13085 | #define DCORE1_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 13086 | #define DCORE1_RTR4_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 13087 | #define mmDCORE1_RTR4_ADD_DEC_LBW_BASE 0x4363400ull |
|---|
| 13088 | #define DCORE1_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 13089 | #define DCORE1_RTR4_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 13090 | #define mmDCORE1_RTR4_ADD_DEC_SPECIAL_BASE 0x4363E80ull |
|---|
| 13091 | #define DCORE1_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13092 | #define DCORE1_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 13093 | #define mmDCORE1_RTR4_BASE 0x4364000ull |
|---|
| 13094 | #define DCORE1_RTR4_MAX_OFFSET 0x1000 |
|---|
| 13095 | #define DCORE1_RTR4_SECTION 0x3000 |
|---|
| 13096 | #define mmDCORE1_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4364300ull |
|---|
| 13097 | #define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13098 | #define DCORE1_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13099 | #define mmDCORE1_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4364340ull |
|---|
| 13100 | #define DCORE1_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13101 | #define DCORE1_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13102 | #define mmDCORE1_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4364380ull |
|---|
| 13103 | #define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13104 | #define DCORE1_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13105 | #define mmDCORE1_RTR4_HBW_WR_RS_LL_STAT_BASE 0x43643C0ull |
|---|
| 13106 | #define DCORE1_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13107 | #define DCORE1_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13108 | #define mmDCORE1_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4364400ull |
|---|
| 13109 | #define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13110 | #define DCORE1_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13111 | #define mmDCORE1_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4364440ull |
|---|
| 13112 | #define DCORE1_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13113 | #define DCORE1_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13114 | #define mmDCORE1_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4364480ull |
|---|
| 13115 | #define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13116 | #define DCORE1_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13117 | #define mmDCORE1_RTR4_LBW_WR_RS_LL_STAT_BASE 0x43644C0ull |
|---|
| 13118 | #define DCORE1_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13119 | #define DCORE1_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13120 | #define mmDCORE1_RTR4_HBW_MFIFO_BASE 0x4364500ull |
|---|
| 13121 | #define DCORE1_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 13122 | #define DCORE1_RTR4_HBW_MFIFO_SECTION 0x4000 |
|---|
| 13123 | #define mmDCORE1_RTR4_E2E_RD_LL_STAT_BASE 0x4364540ull |
|---|
| 13124 | #define DCORE1_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13125 | #define DCORE1_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 13126 | #define mmDCORE1_RTR4_E2E_WR_LL_STAT_BASE 0x4364580ull |
|---|
| 13127 | #define DCORE1_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13128 | #define DCORE1_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 13129 | #define mmDCORE1_RTR4_RTR_HBW_XACT_STAT_BASE 0x4364600ull |
|---|
| 13130 | #define DCORE1_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13131 | #define DCORE1_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13132 | #define mmDCORE1_RTR4_RTR_LBW_XACT_STAT_BASE 0x4364680ull |
|---|
| 13133 | #define DCORE1_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13134 | #define DCORE1_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13135 | #define mmDCORE1_RTR4_RTR_E2E_XACT_STAT_BASE 0x4364700ull |
|---|
| 13136 | #define DCORE1_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13137 | #define DCORE1_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 13138 | #define mmDCORE1_RTR4_SPECIAL_BASE 0x4364E80ull |
|---|
| 13139 | #define DCORE1_RTR4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13140 | #define DCORE1_RTR4_SPECIAL_SECTION 0x1800 |
|---|
| 13141 | #define mmDCORE1_RTR4_DBG_ADDR_BASE 0x4365000ull |
|---|
| 13142 | #define DCORE1_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 13143 | #define DCORE1_RTR4_DBG_ADDR_SECTION 0xE800 |
|---|
| 13144 | #define mmDCORE1_RTR4_DBG_ADDR_SPECIAL_BASE 0x4365E80ull |
|---|
| 13145 | #define DCORE1_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13146 | #define DCORE1_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 13147 | #define mmDCORE1_RTR5_CTRL_BASE 0x4368000ull |
|---|
| 13148 | #define DCORE1_RTR5_CTRL_MAX_OFFSET 0x1000 |
|---|
| 13149 | #define DCORE1_RTR5_CTRL_SECTION 0xE800 |
|---|
| 13150 | #define mmDCORE1_RTR5_CTRL_SPECIAL_BASE 0x4368E80ull |
|---|
| 13151 | #define DCORE1_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13152 | #define DCORE1_RTR5_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 13153 | #define mmDCORE1_RTR5_H3_BASE 0x4369000ull |
|---|
| 13154 | #define DCORE1_RTR5_H3_MAX_OFFSET 0x1000 |
|---|
| 13155 | #define DCORE1_RTR5_H3_SECTION 0xE800 |
|---|
| 13156 | #define mmDCORE1_RTR5_H3_SPECIAL_BASE 0x4369E80ull |
|---|
| 13157 | #define DCORE1_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13158 | #define DCORE1_RTR5_H3_SPECIAL_SECTION 0x1800 |
|---|
| 13159 | #define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x436A000ull |
|---|
| 13160 | #define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13161 | #define DCORE1_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 13162 | #define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x436A200ull |
|---|
| 13163 | #define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13164 | #define DCORE1_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 13165 | #define mmDCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x436A400ull |
|---|
| 13166 | #define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13167 | #define DCORE1_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 13168 | #define mmDCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x436A600ull |
|---|
| 13169 | #define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13170 | #define DCORE1_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 13171 | #define mmDCORE1_RTR5_MSTR_IF_E2E_CRDT_BASE 0x436A800ull |
|---|
| 13172 | #define DCORE1_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 13173 | #define DCORE1_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 13174 | #define mmDCORE1_RTR5_MSTR_IF_AXUSER_BASE 0x436AA80ull |
|---|
| 13175 | #define DCORE1_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 13176 | #define DCORE1_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 13177 | #define mmDCORE1_RTR5_MSTR_IF_DBG_HBW_BASE 0x436AB00ull |
|---|
| 13178 | #define DCORE1_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 13179 | #define DCORE1_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 13180 | #define mmDCORE1_RTR5_MSTR_IF_DBG_LBW_BASE 0x436AB80ull |
|---|
| 13181 | #define DCORE1_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 13182 | #define DCORE1_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 13183 | #define mmDCORE1_RTR5_MSTR_IF_CORE_HBW_BASE 0x436AC00ull |
|---|
| 13184 | #define DCORE1_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 13185 | #define DCORE1_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 13186 | #define mmDCORE1_RTR5_MSTR_IF_CORE_LBW_BASE 0x436AD80ull |
|---|
| 13187 | #define DCORE1_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 13188 | #define DCORE1_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 13189 | #define mmDCORE1_RTR5_MSTR_IF_SPECIAL_BASE 0x436AE80ull |
|---|
| 13190 | #define DCORE1_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13191 | #define DCORE1_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 13192 | #define mmDCORE1_RTR5_ADD_DEC_HBW_BASE 0x436B000ull |
|---|
| 13193 | #define DCORE1_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 13194 | #define DCORE1_RTR5_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 13195 | #define mmDCORE1_RTR5_ADD_DEC_LBW_BASE 0x436B400ull |
|---|
| 13196 | #define DCORE1_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 13197 | #define DCORE1_RTR5_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 13198 | #define mmDCORE1_RTR5_ADD_DEC_SPECIAL_BASE 0x436BE80ull |
|---|
| 13199 | #define DCORE1_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13200 | #define DCORE1_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 13201 | #define mmDCORE1_RTR5_BASE 0x436C000ull |
|---|
| 13202 | #define DCORE1_RTR5_MAX_OFFSET 0x1000 |
|---|
| 13203 | #define DCORE1_RTR5_SECTION 0x3000 |
|---|
| 13204 | #define mmDCORE1_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x436C300ull |
|---|
| 13205 | #define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13206 | #define DCORE1_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13207 | #define mmDCORE1_RTR5_HBW_RD_RS_LL_STAT_BASE 0x436C340ull |
|---|
| 13208 | #define DCORE1_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13209 | #define DCORE1_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13210 | #define mmDCORE1_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x436C380ull |
|---|
| 13211 | #define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13212 | #define DCORE1_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13213 | #define mmDCORE1_RTR5_HBW_WR_RS_LL_STAT_BASE 0x436C3C0ull |
|---|
| 13214 | #define DCORE1_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13215 | #define DCORE1_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13216 | #define mmDCORE1_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x436C400ull |
|---|
| 13217 | #define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13218 | #define DCORE1_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13219 | #define mmDCORE1_RTR5_LBW_RD_RS_LL_STAT_BASE 0x436C440ull |
|---|
| 13220 | #define DCORE1_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13221 | #define DCORE1_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13222 | #define mmDCORE1_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x436C480ull |
|---|
| 13223 | #define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13224 | #define DCORE1_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13225 | #define mmDCORE1_RTR5_LBW_WR_RS_LL_STAT_BASE 0x436C4C0ull |
|---|
| 13226 | #define DCORE1_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13227 | #define DCORE1_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13228 | #define mmDCORE1_RTR5_HBW_MFIFO_BASE 0x436C500ull |
|---|
| 13229 | #define DCORE1_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 13230 | #define DCORE1_RTR5_HBW_MFIFO_SECTION 0x4000 |
|---|
| 13231 | #define mmDCORE1_RTR5_E2E_RD_LL_STAT_BASE 0x436C540ull |
|---|
| 13232 | #define DCORE1_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13233 | #define DCORE1_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 13234 | #define mmDCORE1_RTR5_E2E_WR_LL_STAT_BASE 0x436C580ull |
|---|
| 13235 | #define DCORE1_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13236 | #define DCORE1_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 13237 | #define mmDCORE1_RTR5_RTR_HBW_XACT_STAT_BASE 0x436C600ull |
|---|
| 13238 | #define DCORE1_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13239 | #define DCORE1_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13240 | #define mmDCORE1_RTR5_RTR_LBW_XACT_STAT_BASE 0x436C680ull |
|---|
| 13241 | #define DCORE1_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13242 | #define DCORE1_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13243 | #define mmDCORE1_RTR5_RTR_E2E_XACT_STAT_BASE 0x436C700ull |
|---|
| 13244 | #define DCORE1_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13245 | #define DCORE1_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 13246 | #define mmDCORE1_RTR5_SPECIAL_BASE 0x436CE80ull |
|---|
| 13247 | #define DCORE1_RTR5_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13248 | #define DCORE1_RTR5_SPECIAL_SECTION 0x1800 |
|---|
| 13249 | #define mmDCORE1_RTR5_DBG_ADDR_BASE 0x436D000ull |
|---|
| 13250 | #define DCORE1_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 13251 | #define DCORE1_RTR5_DBG_ADDR_SECTION 0xE800 |
|---|
| 13252 | #define mmDCORE1_RTR5_DBG_ADDR_SPECIAL_BASE 0x436DE80ull |
|---|
| 13253 | #define DCORE1_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13254 | #define DCORE1_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 13255 | #define mmDCORE1_RTR6_CTRL_BASE 0x4370000ull |
|---|
| 13256 | #define DCORE1_RTR6_CTRL_MAX_OFFSET 0x1000 |
|---|
| 13257 | #define DCORE1_RTR6_CTRL_SECTION 0xE800 |
|---|
| 13258 | #define mmDCORE1_RTR6_CTRL_SPECIAL_BASE 0x4370E80ull |
|---|
| 13259 | #define DCORE1_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13260 | #define DCORE1_RTR6_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 13261 | #define mmDCORE1_RTR6_H3_BASE 0x4371000ull |
|---|
| 13262 | #define DCORE1_RTR6_H3_MAX_OFFSET 0x1000 |
|---|
| 13263 | #define DCORE1_RTR6_H3_SECTION 0xE800 |
|---|
| 13264 | #define mmDCORE1_RTR6_H3_SPECIAL_BASE 0x4371E80ull |
|---|
| 13265 | #define DCORE1_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13266 | #define DCORE1_RTR6_H3_SPECIAL_SECTION 0x1800 |
|---|
| 13267 | #define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4372000ull |
|---|
| 13268 | #define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13269 | #define DCORE1_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 13270 | #define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4372200ull |
|---|
| 13271 | #define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13272 | #define DCORE1_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 13273 | #define mmDCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4372400ull |
|---|
| 13274 | #define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13275 | #define DCORE1_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 13276 | #define mmDCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4372600ull |
|---|
| 13277 | #define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13278 | #define DCORE1_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 13279 | #define mmDCORE1_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4372800ull |
|---|
| 13280 | #define DCORE1_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 13281 | #define DCORE1_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 13282 | #define mmDCORE1_RTR6_MSTR_IF_AXUSER_BASE 0x4372A80ull |
|---|
| 13283 | #define DCORE1_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 13284 | #define DCORE1_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 13285 | #define mmDCORE1_RTR6_MSTR_IF_DBG_HBW_BASE 0x4372B00ull |
|---|
| 13286 | #define DCORE1_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 13287 | #define DCORE1_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 13288 | #define mmDCORE1_RTR6_MSTR_IF_DBG_LBW_BASE 0x4372B80ull |
|---|
| 13289 | #define DCORE1_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 13290 | #define DCORE1_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 13291 | #define mmDCORE1_RTR6_MSTR_IF_CORE_HBW_BASE 0x4372C00ull |
|---|
| 13292 | #define DCORE1_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 13293 | #define DCORE1_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 13294 | #define mmDCORE1_RTR6_MSTR_IF_CORE_LBW_BASE 0x4372D80ull |
|---|
| 13295 | #define DCORE1_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 13296 | #define DCORE1_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 13297 | #define mmDCORE1_RTR6_MSTR_IF_SPECIAL_BASE 0x4372E80ull |
|---|
| 13298 | #define DCORE1_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13299 | #define DCORE1_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 13300 | #define mmDCORE1_RTR6_ADD_DEC_HBW_BASE 0x4373000ull |
|---|
| 13301 | #define DCORE1_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 13302 | #define DCORE1_RTR6_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 13303 | #define mmDCORE1_RTR6_ADD_DEC_LBW_BASE 0x4373400ull |
|---|
| 13304 | #define DCORE1_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 13305 | #define DCORE1_RTR6_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 13306 | #define mmDCORE1_RTR6_ADD_DEC_SPECIAL_BASE 0x4373E80ull |
|---|
| 13307 | #define DCORE1_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13308 | #define DCORE1_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 13309 | #define mmDCORE1_RTR6_BASE 0x4374000ull |
|---|
| 13310 | #define DCORE1_RTR6_MAX_OFFSET 0x1000 |
|---|
| 13311 | #define DCORE1_RTR6_SECTION 0x3000 |
|---|
| 13312 | #define mmDCORE1_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4374300ull |
|---|
| 13313 | #define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13314 | #define DCORE1_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13315 | #define mmDCORE1_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4374340ull |
|---|
| 13316 | #define DCORE1_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13317 | #define DCORE1_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13318 | #define mmDCORE1_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4374380ull |
|---|
| 13319 | #define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13320 | #define DCORE1_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13321 | #define mmDCORE1_RTR6_HBW_WR_RS_LL_STAT_BASE 0x43743C0ull |
|---|
| 13322 | #define DCORE1_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13323 | #define DCORE1_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13324 | #define mmDCORE1_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4374400ull |
|---|
| 13325 | #define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13326 | #define DCORE1_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13327 | #define mmDCORE1_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4374440ull |
|---|
| 13328 | #define DCORE1_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13329 | #define DCORE1_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13330 | #define mmDCORE1_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4374480ull |
|---|
| 13331 | #define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13332 | #define DCORE1_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13333 | #define mmDCORE1_RTR6_LBW_WR_RS_LL_STAT_BASE 0x43744C0ull |
|---|
| 13334 | #define DCORE1_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13335 | #define DCORE1_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13336 | #define mmDCORE1_RTR6_HBW_MFIFO_BASE 0x4374500ull |
|---|
| 13337 | #define DCORE1_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 13338 | #define DCORE1_RTR6_HBW_MFIFO_SECTION 0x4000 |
|---|
| 13339 | #define mmDCORE1_RTR6_E2E_RD_LL_STAT_BASE 0x4374540ull |
|---|
| 13340 | #define DCORE1_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13341 | #define DCORE1_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 13342 | #define mmDCORE1_RTR6_E2E_WR_LL_STAT_BASE 0x4374580ull |
|---|
| 13343 | #define DCORE1_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13344 | #define DCORE1_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 13345 | #define mmDCORE1_RTR6_RTR_HBW_XACT_STAT_BASE 0x4374600ull |
|---|
| 13346 | #define DCORE1_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13347 | #define DCORE1_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13348 | #define mmDCORE1_RTR6_RTR_LBW_XACT_STAT_BASE 0x4374680ull |
|---|
| 13349 | #define DCORE1_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13350 | #define DCORE1_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13351 | #define mmDCORE1_RTR6_RTR_E2E_XACT_STAT_BASE 0x4374700ull |
|---|
| 13352 | #define DCORE1_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13353 | #define DCORE1_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 13354 | #define mmDCORE1_RTR6_SPECIAL_BASE 0x4374E80ull |
|---|
| 13355 | #define DCORE1_RTR6_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13356 | #define DCORE1_RTR6_SPECIAL_SECTION 0x1800 |
|---|
| 13357 | #define mmDCORE1_RTR6_DBG_ADDR_BASE 0x4375000ull |
|---|
| 13358 | #define DCORE1_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 13359 | #define DCORE1_RTR6_DBG_ADDR_SECTION 0xE800 |
|---|
| 13360 | #define mmDCORE1_RTR6_DBG_ADDR_SPECIAL_BASE 0x4375E80ull |
|---|
| 13361 | #define DCORE1_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13362 | #define DCORE1_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 13363 | #define mmDCORE1_RTR7_CTRL_BASE 0x4378000ull |
|---|
| 13364 | #define DCORE1_RTR7_CTRL_MAX_OFFSET 0x1000 |
|---|
| 13365 | #define DCORE1_RTR7_CTRL_SECTION 0xE800 |
|---|
| 13366 | #define mmDCORE1_RTR7_CTRL_SPECIAL_BASE 0x4378E80ull |
|---|
| 13367 | #define DCORE1_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13368 | #define DCORE1_RTR7_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 13369 | #define mmDCORE1_RTR7_H3_BASE 0x4379000ull |
|---|
| 13370 | #define DCORE1_RTR7_H3_MAX_OFFSET 0x1000 |
|---|
| 13371 | #define DCORE1_RTR7_H3_SECTION 0xE800 |
|---|
| 13372 | #define mmDCORE1_RTR7_H3_SPECIAL_BASE 0x4379E80ull |
|---|
| 13373 | #define DCORE1_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13374 | #define DCORE1_RTR7_H3_SPECIAL_SECTION 0x1800 |
|---|
| 13375 | #define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x437A000ull |
|---|
| 13376 | #define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13377 | #define DCORE1_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 13378 | #define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x437A200ull |
|---|
| 13379 | #define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 13380 | #define DCORE1_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 13381 | #define mmDCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x437A400ull |
|---|
| 13382 | #define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13383 | #define DCORE1_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 13384 | #define mmDCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x437A600ull |
|---|
| 13385 | #define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 13386 | #define DCORE1_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 13387 | #define mmDCORE1_RTR7_MSTR_IF_E2E_CRDT_BASE 0x437A800ull |
|---|
| 13388 | #define DCORE1_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 13389 | #define DCORE1_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 13390 | #define mmDCORE1_RTR7_MSTR_IF_AXUSER_BASE 0x437AA80ull |
|---|
| 13391 | #define DCORE1_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 13392 | #define DCORE1_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 13393 | #define mmDCORE1_RTR7_MSTR_IF_DBG_HBW_BASE 0x437AB00ull |
|---|
| 13394 | #define DCORE1_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 13395 | #define DCORE1_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 13396 | #define mmDCORE1_RTR7_MSTR_IF_DBG_LBW_BASE 0x437AB80ull |
|---|
| 13397 | #define DCORE1_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 13398 | #define DCORE1_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 13399 | #define mmDCORE1_RTR7_MSTR_IF_CORE_HBW_BASE 0x437AC00ull |
|---|
| 13400 | #define DCORE1_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 13401 | #define DCORE1_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 13402 | #define mmDCORE1_RTR7_MSTR_IF_CORE_LBW_BASE 0x437AD80ull |
|---|
| 13403 | #define DCORE1_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 13404 | #define DCORE1_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 13405 | #define mmDCORE1_RTR7_MSTR_IF_SPECIAL_BASE 0x437AE80ull |
|---|
| 13406 | #define DCORE1_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13407 | #define DCORE1_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 13408 | #define mmDCORE1_RTR7_ADD_DEC_HBW_BASE 0x437B000ull |
|---|
| 13409 | #define DCORE1_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 13410 | #define DCORE1_RTR7_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 13411 | #define mmDCORE1_RTR7_ADD_DEC_LBW_BASE 0x437B400ull |
|---|
| 13412 | #define DCORE1_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 13413 | #define DCORE1_RTR7_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 13414 | #define mmDCORE1_RTR7_ADD_DEC_SPECIAL_BASE 0x437BE80ull |
|---|
| 13415 | #define DCORE1_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13416 | #define DCORE1_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 13417 | #define mmDCORE1_RTR7_BASE 0x437C000ull |
|---|
| 13418 | #define DCORE1_RTR7_MAX_OFFSET 0x1000 |
|---|
| 13419 | #define DCORE1_RTR7_SECTION 0x3000 |
|---|
| 13420 | #define mmDCORE1_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x437C300ull |
|---|
| 13421 | #define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13422 | #define DCORE1_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13423 | #define mmDCORE1_RTR7_HBW_RD_RS_LL_STAT_BASE 0x437C340ull |
|---|
| 13424 | #define DCORE1_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13425 | #define DCORE1_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13426 | #define mmDCORE1_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x437C380ull |
|---|
| 13427 | #define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13428 | #define DCORE1_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13429 | #define mmDCORE1_RTR7_HBW_WR_RS_LL_STAT_BASE 0x437C3C0ull |
|---|
| 13430 | #define DCORE1_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13431 | #define DCORE1_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13432 | #define mmDCORE1_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x437C400ull |
|---|
| 13433 | #define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13434 | #define DCORE1_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13435 | #define mmDCORE1_RTR7_LBW_RD_RS_LL_STAT_BASE 0x437C440ull |
|---|
| 13436 | #define DCORE1_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13437 | #define DCORE1_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13438 | #define mmDCORE1_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x437C480ull |
|---|
| 13439 | #define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13440 | #define DCORE1_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 13441 | #define mmDCORE1_RTR7_LBW_WR_RS_LL_STAT_BASE 0x437C4C0ull |
|---|
| 13442 | #define DCORE1_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13443 | #define DCORE1_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 13444 | #define mmDCORE1_RTR7_HBW_MFIFO_BASE 0x437C500ull |
|---|
| 13445 | #define DCORE1_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 13446 | #define DCORE1_RTR7_HBW_MFIFO_SECTION 0x4000 |
|---|
| 13447 | #define mmDCORE1_RTR7_E2E_RD_LL_STAT_BASE 0x437C540ull |
|---|
| 13448 | #define DCORE1_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13449 | #define DCORE1_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 13450 | #define mmDCORE1_RTR7_E2E_WR_LL_STAT_BASE 0x437C580ull |
|---|
| 13451 | #define DCORE1_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 13452 | #define DCORE1_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 13453 | #define mmDCORE1_RTR7_RTR_HBW_XACT_STAT_BASE 0x437C600ull |
|---|
| 13454 | #define DCORE1_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13455 | #define DCORE1_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13456 | #define mmDCORE1_RTR7_RTR_LBW_XACT_STAT_BASE 0x437C680ull |
|---|
| 13457 | #define DCORE1_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13458 | #define DCORE1_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 13459 | #define mmDCORE1_RTR7_RTR_E2E_XACT_STAT_BASE 0x437C700ull |
|---|
| 13460 | #define DCORE1_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 13461 | #define DCORE1_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 13462 | #define mmDCORE1_RTR7_SPECIAL_BASE 0x437CE80ull |
|---|
| 13463 | #define DCORE1_RTR7_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13464 | #define DCORE1_RTR7_SPECIAL_SECTION 0x1800 |
|---|
| 13465 | #define mmDCORE1_RTR7_DBG_ADDR_BASE 0x437D000ull |
|---|
| 13466 | #define DCORE1_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 13467 | #define DCORE1_RTR7_DBG_ADDR_SECTION 0xE800 |
|---|
| 13468 | #define mmDCORE1_RTR7_DBG_ADDR_SPECIAL_BASE 0x437DE80ull |
|---|
| 13469 | #define DCORE1_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13470 | #define DCORE1_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 13471 | #define mmDCORE1_SRAM0_BANK_BASE 0x4380000ull |
|---|
| 13472 | #define DCORE1_SRAM0_BANK_MAX_OFFSET 0x1000 |
|---|
| 13473 | #define DCORE1_SRAM0_BANK_SECTION 0xE800 |
|---|
| 13474 | #define mmDCORE1_SRAM0_BANK_SPECIAL_BASE 0x4380E80ull |
|---|
| 13475 | #define DCORE1_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13476 | #define DCORE1_SRAM0_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13477 | #define mmDCORE1_SRAM0_RTR_BASE 0x4381000ull |
|---|
| 13478 | #define DCORE1_SRAM0_RTR_MAX_OFFSET 0x1000 |
|---|
| 13479 | #define DCORE1_SRAM0_RTR_SECTION 0xE800 |
|---|
| 13480 | #define mmDCORE1_SRAM0_RTR_SPECIAL_BASE 0x4381E80ull |
|---|
| 13481 | #define DCORE1_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13482 | #define DCORE1_SRAM0_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13483 | #define mmDCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4382000ull |
|---|
| 13484 | #define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13485 | #define DCORE1_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13486 | #define mmDCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4382100ull |
|---|
| 13487 | #define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13488 | #define DCORE1_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13489 | #define mmDCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4382200ull |
|---|
| 13490 | #define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13491 | #define DCORE1_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13492 | #define mmDCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4382300ull |
|---|
| 13493 | #define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13494 | #define DCORE1_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13495 | #define mmDCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4382400ull |
|---|
| 13496 | #define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13497 | #define DCORE1_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13498 | #define mmDCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4382500ull |
|---|
| 13499 | #define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13500 | #define DCORE1_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13501 | #define mmDCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4382600ull |
|---|
| 13502 | #define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13503 | #define DCORE1_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13504 | #define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4382700ull |
|---|
| 13505 | #define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13506 | #define DCORE1_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13507 | #define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4382780ull |
|---|
| 13508 | #define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13509 | #define DCORE1_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13510 | #define mmDCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4382800ull |
|---|
| 13511 | #define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13512 | #define DCORE1_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13513 | #define mmDCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4382880ull |
|---|
| 13514 | #define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13515 | #define DCORE1_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13516 | #define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4382900ull |
|---|
| 13517 | #define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13518 | #define DCORE1_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13519 | #define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4382980ull |
|---|
| 13520 | #define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13521 | #define DCORE1_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13522 | #define mmDCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4382A00ull |
|---|
| 13523 | #define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13524 | #define DCORE1_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13525 | #define mmDCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4382A80ull |
|---|
| 13526 | #define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13527 | #define DCORE1_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13528 | #define mmDCORE1_SRAM0_DBG_CNT_SPECIAL_BASE 0x4382E80ull |
|---|
| 13529 | #define DCORE1_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13530 | #define DCORE1_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13531 | #define mmDCORE1_SRAM1_BANK_BASE 0x4388000ull |
|---|
| 13532 | #define DCORE1_SRAM1_BANK_MAX_OFFSET 0x1000 |
|---|
| 13533 | #define DCORE1_SRAM1_BANK_SECTION 0xE800 |
|---|
| 13534 | #define mmDCORE1_SRAM1_BANK_SPECIAL_BASE 0x4388E80ull |
|---|
| 13535 | #define DCORE1_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13536 | #define DCORE1_SRAM1_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13537 | #define mmDCORE1_SRAM1_RTR_BASE 0x4389000ull |
|---|
| 13538 | #define DCORE1_SRAM1_RTR_MAX_OFFSET 0x1000 |
|---|
| 13539 | #define DCORE1_SRAM1_RTR_SECTION 0xE800 |
|---|
| 13540 | #define mmDCORE1_SRAM1_RTR_SPECIAL_BASE 0x4389E80ull |
|---|
| 13541 | #define DCORE1_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13542 | #define DCORE1_SRAM1_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13543 | #define mmDCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x438A000ull |
|---|
| 13544 | #define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13545 | #define DCORE1_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13546 | #define mmDCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x438A100ull |
|---|
| 13547 | #define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13548 | #define DCORE1_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13549 | #define mmDCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x438A200ull |
|---|
| 13550 | #define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13551 | #define DCORE1_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13552 | #define mmDCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x438A300ull |
|---|
| 13553 | #define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13554 | #define DCORE1_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13555 | #define mmDCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x438A400ull |
|---|
| 13556 | #define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13557 | #define DCORE1_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13558 | #define mmDCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x438A500ull |
|---|
| 13559 | #define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13560 | #define DCORE1_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13561 | #define mmDCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x438A600ull |
|---|
| 13562 | #define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13563 | #define DCORE1_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13564 | #define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x438A700ull |
|---|
| 13565 | #define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13566 | #define DCORE1_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13567 | #define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x438A780ull |
|---|
| 13568 | #define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13569 | #define DCORE1_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13570 | #define mmDCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x438A800ull |
|---|
| 13571 | #define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13572 | #define DCORE1_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13573 | #define mmDCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x438A880ull |
|---|
| 13574 | #define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13575 | #define DCORE1_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13576 | #define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x438A900ull |
|---|
| 13577 | #define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13578 | #define DCORE1_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13579 | #define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x438A980ull |
|---|
| 13580 | #define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13581 | #define DCORE1_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13582 | #define mmDCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x438AA00ull |
|---|
| 13583 | #define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13584 | #define DCORE1_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13585 | #define mmDCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x438AA80ull |
|---|
| 13586 | #define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13587 | #define DCORE1_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13588 | #define mmDCORE1_SRAM1_DBG_CNT_SPECIAL_BASE 0x438AE80ull |
|---|
| 13589 | #define DCORE1_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13590 | #define DCORE1_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13591 | #define mmDCORE1_SRAM2_BANK_BASE 0x4390000ull |
|---|
| 13592 | #define DCORE1_SRAM2_BANK_MAX_OFFSET 0x1000 |
|---|
| 13593 | #define DCORE1_SRAM2_BANK_SECTION 0xE800 |
|---|
| 13594 | #define mmDCORE1_SRAM2_BANK_SPECIAL_BASE 0x4390E80ull |
|---|
| 13595 | #define DCORE1_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13596 | #define DCORE1_SRAM2_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13597 | #define mmDCORE1_SRAM2_RTR_BASE 0x4391000ull |
|---|
| 13598 | #define DCORE1_SRAM2_RTR_MAX_OFFSET 0x1000 |
|---|
| 13599 | #define DCORE1_SRAM2_RTR_SECTION 0xE800 |
|---|
| 13600 | #define mmDCORE1_SRAM2_RTR_SPECIAL_BASE 0x4391E80ull |
|---|
| 13601 | #define DCORE1_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13602 | #define DCORE1_SRAM2_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13603 | #define mmDCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4392000ull |
|---|
| 13604 | #define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13605 | #define DCORE1_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13606 | #define mmDCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4392100ull |
|---|
| 13607 | #define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13608 | #define DCORE1_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13609 | #define mmDCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4392200ull |
|---|
| 13610 | #define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13611 | #define DCORE1_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13612 | #define mmDCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4392300ull |
|---|
| 13613 | #define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13614 | #define DCORE1_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13615 | #define mmDCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4392400ull |
|---|
| 13616 | #define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13617 | #define DCORE1_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13618 | #define mmDCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4392500ull |
|---|
| 13619 | #define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13620 | #define DCORE1_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13621 | #define mmDCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4392600ull |
|---|
| 13622 | #define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13623 | #define DCORE1_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13624 | #define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4392700ull |
|---|
| 13625 | #define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13626 | #define DCORE1_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13627 | #define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4392780ull |
|---|
| 13628 | #define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13629 | #define DCORE1_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13630 | #define mmDCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4392800ull |
|---|
| 13631 | #define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13632 | #define DCORE1_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13633 | #define mmDCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4392880ull |
|---|
| 13634 | #define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13635 | #define DCORE1_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13636 | #define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4392900ull |
|---|
| 13637 | #define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13638 | #define DCORE1_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13639 | #define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4392980ull |
|---|
| 13640 | #define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13641 | #define DCORE1_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13642 | #define mmDCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4392A00ull |
|---|
| 13643 | #define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13644 | #define DCORE1_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13645 | #define mmDCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4392A80ull |
|---|
| 13646 | #define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13647 | #define DCORE1_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13648 | #define mmDCORE1_SRAM2_DBG_CNT_SPECIAL_BASE 0x4392E80ull |
|---|
| 13649 | #define DCORE1_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13650 | #define DCORE1_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13651 | #define mmDCORE1_SRAM3_BANK_BASE 0x4398000ull |
|---|
| 13652 | #define DCORE1_SRAM3_BANK_MAX_OFFSET 0x1000 |
|---|
| 13653 | #define DCORE1_SRAM3_BANK_SECTION 0xE800 |
|---|
| 13654 | #define mmDCORE1_SRAM3_BANK_SPECIAL_BASE 0x4398E80ull |
|---|
| 13655 | #define DCORE1_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13656 | #define DCORE1_SRAM3_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13657 | #define mmDCORE1_SRAM3_RTR_BASE 0x4399000ull |
|---|
| 13658 | #define DCORE1_SRAM3_RTR_MAX_OFFSET 0x1000 |
|---|
| 13659 | #define DCORE1_SRAM3_RTR_SECTION 0xE800 |
|---|
| 13660 | #define mmDCORE1_SRAM3_RTR_SPECIAL_BASE 0x4399E80ull |
|---|
| 13661 | #define DCORE1_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13662 | #define DCORE1_SRAM3_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13663 | #define mmDCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x439A000ull |
|---|
| 13664 | #define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13665 | #define DCORE1_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13666 | #define mmDCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x439A100ull |
|---|
| 13667 | #define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13668 | #define DCORE1_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13669 | #define mmDCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x439A200ull |
|---|
| 13670 | #define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13671 | #define DCORE1_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13672 | #define mmDCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x439A300ull |
|---|
| 13673 | #define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13674 | #define DCORE1_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13675 | #define mmDCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x439A400ull |
|---|
| 13676 | #define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13677 | #define DCORE1_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13678 | #define mmDCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x439A500ull |
|---|
| 13679 | #define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13680 | #define DCORE1_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13681 | #define mmDCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x439A600ull |
|---|
| 13682 | #define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13683 | #define DCORE1_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13684 | #define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x439A700ull |
|---|
| 13685 | #define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13686 | #define DCORE1_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13687 | #define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x439A780ull |
|---|
| 13688 | #define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13689 | #define DCORE1_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13690 | #define mmDCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x439A800ull |
|---|
| 13691 | #define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13692 | #define DCORE1_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13693 | #define mmDCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x439A880ull |
|---|
| 13694 | #define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13695 | #define DCORE1_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13696 | #define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x439A900ull |
|---|
| 13697 | #define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13698 | #define DCORE1_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13699 | #define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x439A980ull |
|---|
| 13700 | #define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13701 | #define DCORE1_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13702 | #define mmDCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x439AA00ull |
|---|
| 13703 | #define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13704 | #define DCORE1_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13705 | #define mmDCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x439AA80ull |
|---|
| 13706 | #define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13707 | #define DCORE1_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13708 | #define mmDCORE1_SRAM3_DBG_CNT_SPECIAL_BASE 0x439AE80ull |
|---|
| 13709 | #define DCORE1_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13710 | #define DCORE1_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13711 | #define mmDCORE1_SRAM4_BANK_BASE 0x43A0000ull |
|---|
| 13712 | #define DCORE1_SRAM4_BANK_MAX_OFFSET 0x1000 |
|---|
| 13713 | #define DCORE1_SRAM4_BANK_SECTION 0xE800 |
|---|
| 13714 | #define mmDCORE1_SRAM4_BANK_SPECIAL_BASE 0x43A0E80ull |
|---|
| 13715 | #define DCORE1_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13716 | #define DCORE1_SRAM4_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13717 | #define mmDCORE1_SRAM4_RTR_BASE 0x43A1000ull |
|---|
| 13718 | #define DCORE1_SRAM4_RTR_MAX_OFFSET 0x1000 |
|---|
| 13719 | #define DCORE1_SRAM4_RTR_SECTION 0xE800 |
|---|
| 13720 | #define mmDCORE1_SRAM4_RTR_SPECIAL_BASE 0x43A1E80ull |
|---|
| 13721 | #define DCORE1_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13722 | #define DCORE1_SRAM4_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13723 | #define mmDCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43A2000ull |
|---|
| 13724 | #define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13725 | #define DCORE1_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13726 | #define mmDCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43A2100ull |
|---|
| 13727 | #define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13728 | #define DCORE1_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13729 | #define mmDCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43A2200ull |
|---|
| 13730 | #define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13731 | #define DCORE1_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13732 | #define mmDCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43A2300ull |
|---|
| 13733 | #define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13734 | #define DCORE1_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13735 | #define mmDCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43A2400ull |
|---|
| 13736 | #define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13737 | #define DCORE1_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13738 | #define mmDCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43A2500ull |
|---|
| 13739 | #define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13740 | #define DCORE1_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13741 | #define mmDCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43A2600ull |
|---|
| 13742 | #define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13743 | #define DCORE1_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13744 | #define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2700ull |
|---|
| 13745 | #define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13746 | #define DCORE1_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13747 | #define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2780ull |
|---|
| 13748 | #define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13749 | #define DCORE1_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13750 | #define mmDCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43A2800ull |
|---|
| 13751 | #define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13752 | #define DCORE1_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13753 | #define mmDCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43A2880ull |
|---|
| 13754 | #define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13755 | #define DCORE1_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13756 | #define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43A2900ull |
|---|
| 13757 | #define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13758 | #define DCORE1_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13759 | #define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43A2980ull |
|---|
| 13760 | #define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13761 | #define DCORE1_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13762 | #define mmDCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43A2A00ull |
|---|
| 13763 | #define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13764 | #define DCORE1_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13765 | #define mmDCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43A2A80ull |
|---|
| 13766 | #define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13767 | #define DCORE1_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13768 | #define mmDCORE1_SRAM4_DBG_CNT_SPECIAL_BASE 0x43A2E80ull |
|---|
| 13769 | #define DCORE1_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13770 | #define DCORE1_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13771 | #define mmDCORE1_SRAM5_BANK_BASE 0x43A8000ull |
|---|
| 13772 | #define DCORE1_SRAM5_BANK_MAX_OFFSET 0x1000 |
|---|
| 13773 | #define DCORE1_SRAM5_BANK_SECTION 0xE800 |
|---|
| 13774 | #define mmDCORE1_SRAM5_BANK_SPECIAL_BASE 0x43A8E80ull |
|---|
| 13775 | #define DCORE1_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13776 | #define DCORE1_SRAM5_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13777 | #define mmDCORE1_SRAM5_RTR_BASE 0x43A9000ull |
|---|
| 13778 | #define DCORE1_SRAM5_RTR_MAX_OFFSET 0x1000 |
|---|
| 13779 | #define DCORE1_SRAM5_RTR_SECTION 0xE800 |
|---|
| 13780 | #define mmDCORE1_SRAM5_RTR_SPECIAL_BASE 0x43A9E80ull |
|---|
| 13781 | #define DCORE1_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13782 | #define DCORE1_SRAM5_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13783 | #define mmDCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43AA000ull |
|---|
| 13784 | #define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13785 | #define DCORE1_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13786 | #define mmDCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43AA100ull |
|---|
| 13787 | #define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13788 | #define DCORE1_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13789 | #define mmDCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43AA200ull |
|---|
| 13790 | #define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13791 | #define DCORE1_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13792 | #define mmDCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43AA300ull |
|---|
| 13793 | #define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13794 | #define DCORE1_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13795 | #define mmDCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43AA400ull |
|---|
| 13796 | #define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13797 | #define DCORE1_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13798 | #define mmDCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43AA500ull |
|---|
| 13799 | #define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13800 | #define DCORE1_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13801 | #define mmDCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43AA600ull |
|---|
| 13802 | #define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13803 | #define DCORE1_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13804 | #define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA700ull |
|---|
| 13805 | #define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13806 | #define DCORE1_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13807 | #define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA780ull |
|---|
| 13808 | #define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13809 | #define DCORE1_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13810 | #define mmDCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43AA800ull |
|---|
| 13811 | #define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13812 | #define DCORE1_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13813 | #define mmDCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43AA880ull |
|---|
| 13814 | #define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13815 | #define DCORE1_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13816 | #define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43AA900ull |
|---|
| 13817 | #define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13818 | #define DCORE1_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13819 | #define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43AA980ull |
|---|
| 13820 | #define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13821 | #define DCORE1_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13822 | #define mmDCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43AAA00ull |
|---|
| 13823 | #define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13824 | #define DCORE1_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13825 | #define mmDCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43AAA80ull |
|---|
| 13826 | #define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13827 | #define DCORE1_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13828 | #define mmDCORE1_SRAM5_DBG_CNT_SPECIAL_BASE 0x43AAE80ull |
|---|
| 13829 | #define DCORE1_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13830 | #define DCORE1_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13831 | #define mmDCORE1_SRAM6_BANK_BASE 0x43B0000ull |
|---|
| 13832 | #define DCORE1_SRAM6_BANK_MAX_OFFSET 0x1000 |
|---|
| 13833 | #define DCORE1_SRAM6_BANK_SECTION 0xE800 |
|---|
| 13834 | #define mmDCORE1_SRAM6_BANK_SPECIAL_BASE 0x43B0E80ull |
|---|
| 13835 | #define DCORE1_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13836 | #define DCORE1_SRAM6_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13837 | #define mmDCORE1_SRAM6_RTR_BASE 0x43B1000ull |
|---|
| 13838 | #define DCORE1_SRAM6_RTR_MAX_OFFSET 0x1000 |
|---|
| 13839 | #define DCORE1_SRAM6_RTR_SECTION 0xE800 |
|---|
| 13840 | #define mmDCORE1_SRAM6_RTR_SPECIAL_BASE 0x43B1E80ull |
|---|
| 13841 | #define DCORE1_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13842 | #define DCORE1_SRAM6_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13843 | #define mmDCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43B2000ull |
|---|
| 13844 | #define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13845 | #define DCORE1_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13846 | #define mmDCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43B2100ull |
|---|
| 13847 | #define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13848 | #define DCORE1_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13849 | #define mmDCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43B2200ull |
|---|
| 13850 | #define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13851 | #define DCORE1_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13852 | #define mmDCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43B2300ull |
|---|
| 13853 | #define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13854 | #define DCORE1_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13855 | #define mmDCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43B2400ull |
|---|
| 13856 | #define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13857 | #define DCORE1_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13858 | #define mmDCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43B2500ull |
|---|
| 13859 | #define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13860 | #define DCORE1_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13861 | #define mmDCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43B2600ull |
|---|
| 13862 | #define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13863 | #define DCORE1_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13864 | #define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2700ull |
|---|
| 13865 | #define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13866 | #define DCORE1_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13867 | #define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2780ull |
|---|
| 13868 | #define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13869 | #define DCORE1_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13870 | #define mmDCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43B2800ull |
|---|
| 13871 | #define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13872 | #define DCORE1_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13873 | #define mmDCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43B2880ull |
|---|
| 13874 | #define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13875 | #define DCORE1_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13876 | #define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43B2900ull |
|---|
| 13877 | #define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13878 | #define DCORE1_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13879 | #define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43B2980ull |
|---|
| 13880 | #define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13881 | #define DCORE1_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13882 | #define mmDCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43B2A00ull |
|---|
| 13883 | #define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13884 | #define DCORE1_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13885 | #define mmDCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43B2A80ull |
|---|
| 13886 | #define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13887 | #define DCORE1_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13888 | #define mmDCORE1_SRAM6_DBG_CNT_SPECIAL_BASE 0x43B2E80ull |
|---|
| 13889 | #define DCORE1_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13890 | #define DCORE1_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13891 | #define mmDCORE1_SRAM7_BANK_BASE 0x43B8000ull |
|---|
| 13892 | #define DCORE1_SRAM7_BANK_MAX_OFFSET 0x1000 |
|---|
| 13893 | #define DCORE1_SRAM7_BANK_SECTION 0xE800 |
|---|
| 13894 | #define mmDCORE1_SRAM7_BANK_SPECIAL_BASE 0x43B8E80ull |
|---|
| 13895 | #define DCORE1_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13896 | #define DCORE1_SRAM7_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 13897 | #define mmDCORE1_SRAM7_RTR_BASE 0x43B9000ull |
|---|
| 13898 | #define DCORE1_SRAM7_RTR_MAX_OFFSET 0x1000 |
|---|
| 13899 | #define DCORE1_SRAM7_RTR_SECTION 0xE800 |
|---|
| 13900 | #define mmDCORE1_SRAM7_RTR_SPECIAL_BASE 0x43B9E80ull |
|---|
| 13901 | #define DCORE1_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13902 | #define DCORE1_SRAM7_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 13903 | #define mmDCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x43BA000ull |
|---|
| 13904 | #define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13905 | #define DCORE1_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13906 | #define mmDCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x43BA100ull |
|---|
| 13907 | #define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13908 | #define DCORE1_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13909 | #define mmDCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x43BA200ull |
|---|
| 13910 | #define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13911 | #define DCORE1_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13912 | #define mmDCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x43BA300ull |
|---|
| 13913 | #define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13914 | #define DCORE1_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13915 | #define mmDCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x43BA400ull |
|---|
| 13916 | #define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13917 | #define DCORE1_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13918 | #define mmDCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x43BA500ull |
|---|
| 13919 | #define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13920 | #define DCORE1_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13921 | #define mmDCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x43BA600ull |
|---|
| 13922 | #define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 13923 | #define DCORE1_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 13924 | #define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA700ull |
|---|
| 13925 | #define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13926 | #define DCORE1_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13927 | #define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA780ull |
|---|
| 13928 | #define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13929 | #define DCORE1_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13930 | #define mmDCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x43BA800ull |
|---|
| 13931 | #define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13932 | #define DCORE1_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13933 | #define mmDCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x43BA880ull |
|---|
| 13934 | #define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13935 | #define DCORE1_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13936 | #define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x43BA900ull |
|---|
| 13937 | #define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13938 | #define DCORE1_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13939 | #define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x43BA980ull |
|---|
| 13940 | #define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13941 | #define DCORE1_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13942 | #define mmDCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x43BAA00ull |
|---|
| 13943 | #define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13944 | #define DCORE1_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 13945 | #define mmDCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x43BAA80ull |
|---|
| 13946 | #define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 13947 | #define DCORE1_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 13948 | #define mmDCORE1_SRAM7_DBG_CNT_SPECIAL_BASE 0x43BAE80ull |
|---|
| 13949 | #define DCORE1_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13950 | #define DCORE1_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 13951 | #define mmDCORE1_EDMA0_QM_DCCM_BASE 0x43C0000ull |
|---|
| 13952 | #define DCORE1_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 13953 | #define DCORE1_EDMA0_QM_DCCM_SECTION 0x8000 |
|---|
| 13954 | #define mmDCORE1_EDMA0_QM_ARC_AUX_BASE 0x43C8000ull |
|---|
| 13955 | #define DCORE1_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 13956 | #define DCORE1_EDMA0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 13957 | #define mmDCORE1_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x43C8E80ull |
|---|
| 13958 | #define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 13959 | #define DCORE1_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 13960 | #define mmDCORE1_EDMA0_QM_BASE 0x43CA000ull |
|---|
| 13961 | #define DCORE1_EDMA0_QM_MAX_OFFSET 0x1000 |
|---|
| 13962 | #define DCORE1_EDMA0_QM_SECTION 0x9000 |
|---|
| 13963 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43CA900ull |
|---|
| 13964 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 13965 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 13966 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43CA908ull |
|---|
| 13967 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 13968 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 13969 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43CA910ull |
|---|
| 13970 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 13971 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 13972 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43CA918ull |
|---|
| 13973 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 13974 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 13975 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43CA920ull |
|---|
| 13976 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 13977 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 13978 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43CA928ull |
|---|
| 13979 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 13980 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 13981 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43CA930ull |
|---|
| 13982 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 13983 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 13984 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43CA938ull |
|---|
| 13985 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 13986 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 13987 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43CA940ull |
|---|
| 13988 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 13989 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 13990 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43CA948ull |
|---|
| 13991 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 13992 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 13993 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43CA950ull |
|---|
| 13994 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 13995 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 13996 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43CA958ull |
|---|
| 13997 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 13998 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 13999 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43CA960ull |
|---|
| 14000 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 14001 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 14002 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43CA968ull |
|---|
| 14003 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 14004 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 14005 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43CA970ull |
|---|
| 14006 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 14007 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 14008 | #define mmDCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43CA978ull |
|---|
| 14009 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 14010 | #define DCORE1_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 14011 | #define mmDCORE1_EDMA0_QM_AXUSER_SECURED_BASE 0x43CAB00ull |
|---|
| 14012 | #define DCORE1_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 14013 | #define DCORE1_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 14014 | #define mmDCORE1_EDMA0_QM_AXUSER_NONSECURED_BASE 0x43CAB80ull |
|---|
| 14015 | #define DCORE1_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 14016 | #define DCORE1_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 14017 | #define mmDCORE1_EDMA0_QM_DBG_HBW_BASE 0x43CAC00ull |
|---|
| 14018 | #define DCORE1_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14019 | #define DCORE1_EDMA0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 14020 | #define mmDCORE1_EDMA0_QM_DBG_LBW_BASE 0x43CAC80ull |
|---|
| 14021 | #define DCORE1_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14022 | #define DCORE1_EDMA0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 14023 | #define mmDCORE1_EDMA0_QM_CGM_BASE 0x43CAD80ull |
|---|
| 14024 | #define DCORE1_EDMA0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 14025 | #define DCORE1_EDMA0_QM_CGM_SECTION 0x1000 |
|---|
| 14026 | #define mmDCORE1_EDMA0_QM_SPECIAL_BASE 0x43CAE80ull |
|---|
| 14027 | #define DCORE1_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14028 | #define DCORE1_EDMA0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14029 | #define mmDCORE1_EDMA0_CORE_BASE 0x43CB000ull |
|---|
| 14030 | #define DCORE1_EDMA0_CORE_MAX_OFFSET 0x1000 |
|---|
| 14031 | #define DCORE1_EDMA0_CORE_SECTION 0x8000 |
|---|
| 14032 | #define mmDCORE1_EDMA0_CORE_CTX_AXUSER_BASE 0x43CB800ull |
|---|
| 14033 | #define DCORE1_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14034 | #define DCORE1_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 14035 | #define mmDCORE1_EDMA0_CORE_CTX_BASE 0x43CB860ull |
|---|
| 14036 | #define DCORE1_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 14037 | #define DCORE1_EDMA0_CORE_CTX_SECTION 0x5A00 |
|---|
| 14038 | #define mmDCORE1_EDMA0_CORE_KDMA_CGM_BASE 0x43CBE00ull |
|---|
| 14039 | #define DCORE1_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 14040 | #define DCORE1_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 14041 | #define mmDCORE1_EDMA0_CORE_SPECIAL_BASE 0x43CBE80ull |
|---|
| 14042 | #define DCORE1_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14043 | #define DCORE1_EDMA0_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 14044 | #define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x43CC000ull |
|---|
| 14045 | #define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14046 | #define DCORE1_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14047 | #define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x43CC200ull |
|---|
| 14048 | #define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14049 | #define DCORE1_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14050 | #define mmDCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x43CC400ull |
|---|
| 14051 | #define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14052 | #define DCORE1_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14053 | #define mmDCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x43CC600ull |
|---|
| 14054 | #define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14055 | #define DCORE1_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14056 | #define mmDCORE1_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x43CC800ull |
|---|
| 14057 | #define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14058 | #define DCORE1_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14059 | #define mmDCORE1_EDMA0_MSTR_IF_AXUSER_BASE 0x43CCA80ull |
|---|
| 14060 | #define DCORE1_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14061 | #define DCORE1_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14062 | #define mmDCORE1_EDMA0_MSTR_IF_DBG_HBW_BASE 0x43CCB00ull |
|---|
| 14063 | #define DCORE1_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14064 | #define DCORE1_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14065 | #define mmDCORE1_EDMA0_MSTR_IF_DBG_LBW_BASE 0x43CCB80ull |
|---|
| 14066 | #define DCORE1_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14067 | #define DCORE1_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14068 | #define mmDCORE1_EDMA0_MSTR_IF_CORE_HBW_BASE 0x43CCC00ull |
|---|
| 14069 | #define DCORE1_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14070 | #define DCORE1_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14071 | #define mmDCORE1_EDMA0_MSTR_IF_CORE_LBW_BASE 0x43CCD80ull |
|---|
| 14072 | #define DCORE1_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14073 | #define DCORE1_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14074 | #define mmDCORE1_EDMA0_MSTR_IF_SPECIAL_BASE 0x43CCE80ull |
|---|
| 14075 | #define DCORE1_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14076 | #define DCORE1_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 14077 | #define mmDCORE1_EDMA1_QM_DCCM_BASE 0x43D0000ull |
|---|
| 14078 | #define DCORE1_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 14079 | #define DCORE1_EDMA1_QM_DCCM_SECTION 0x8000 |
|---|
| 14080 | #define mmDCORE1_EDMA1_QM_ARC_AUX_BASE 0x43D8000ull |
|---|
| 14081 | #define DCORE1_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 14082 | #define DCORE1_EDMA1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 14083 | #define mmDCORE1_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x43D8E80ull |
|---|
| 14084 | #define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14085 | #define DCORE1_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 14086 | #define mmDCORE1_EDMA1_QM_BASE 0x43DA000ull |
|---|
| 14087 | #define DCORE1_EDMA1_QM_MAX_OFFSET 0x1000 |
|---|
| 14088 | #define DCORE1_EDMA1_QM_SECTION 0x9000 |
|---|
| 14089 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x43DA900ull |
|---|
| 14090 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 14091 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 14092 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x43DA908ull |
|---|
| 14093 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 14094 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 14095 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x43DA910ull |
|---|
| 14096 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 14097 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 14098 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x43DA918ull |
|---|
| 14099 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 14100 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 14101 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x43DA920ull |
|---|
| 14102 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 14103 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 14104 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x43DA928ull |
|---|
| 14105 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 14106 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 14107 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x43DA930ull |
|---|
| 14108 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 14109 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 14110 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x43DA938ull |
|---|
| 14111 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 14112 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 14113 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x43DA940ull |
|---|
| 14114 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 14115 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 14116 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x43DA948ull |
|---|
| 14117 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 14118 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 14119 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x43DA950ull |
|---|
| 14120 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 14121 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 14122 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x43DA958ull |
|---|
| 14123 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 14124 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 14125 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x43DA960ull |
|---|
| 14126 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 14127 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 14128 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x43DA968ull |
|---|
| 14129 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 14130 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 14131 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x43DA970ull |
|---|
| 14132 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 14133 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 14134 | #define mmDCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x43DA978ull |
|---|
| 14135 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 14136 | #define DCORE1_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 14137 | #define mmDCORE1_EDMA1_QM_AXUSER_SECURED_BASE 0x43DAB00ull |
|---|
| 14138 | #define DCORE1_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 14139 | #define DCORE1_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 14140 | #define mmDCORE1_EDMA1_QM_AXUSER_NONSECURED_BASE 0x43DAB80ull |
|---|
| 14141 | #define DCORE1_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 14142 | #define DCORE1_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 14143 | #define mmDCORE1_EDMA1_QM_DBG_HBW_BASE 0x43DAC00ull |
|---|
| 14144 | #define DCORE1_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14145 | #define DCORE1_EDMA1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 14146 | #define mmDCORE1_EDMA1_QM_DBG_LBW_BASE 0x43DAC80ull |
|---|
| 14147 | #define DCORE1_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14148 | #define DCORE1_EDMA1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 14149 | #define mmDCORE1_EDMA1_QM_CGM_BASE 0x43DAD80ull |
|---|
| 14150 | #define DCORE1_EDMA1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 14151 | #define DCORE1_EDMA1_QM_CGM_SECTION 0x1000 |
|---|
| 14152 | #define mmDCORE1_EDMA1_QM_SPECIAL_BASE 0x43DAE80ull |
|---|
| 14153 | #define DCORE1_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14154 | #define DCORE1_EDMA1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14155 | #define mmDCORE1_EDMA1_CORE_BASE 0x43DB000ull |
|---|
| 14156 | #define DCORE1_EDMA1_CORE_MAX_OFFSET 0x1000 |
|---|
| 14157 | #define DCORE1_EDMA1_CORE_SECTION 0x8000 |
|---|
| 14158 | #define mmDCORE1_EDMA1_CORE_CTX_AXUSER_BASE 0x43DB800ull |
|---|
| 14159 | #define DCORE1_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14160 | #define DCORE1_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 14161 | #define mmDCORE1_EDMA1_CORE_CTX_BASE 0x43DB860ull |
|---|
| 14162 | #define DCORE1_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 14163 | #define DCORE1_EDMA1_CORE_CTX_SECTION 0x5A00 |
|---|
| 14164 | #define mmDCORE1_EDMA1_CORE_KDMA_CGM_BASE 0x43DBE00ull |
|---|
| 14165 | #define DCORE1_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 14166 | #define DCORE1_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 14167 | #define mmDCORE1_EDMA1_CORE_SPECIAL_BASE 0x43DBE80ull |
|---|
| 14168 | #define DCORE1_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14169 | #define DCORE1_EDMA1_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 14170 | #define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x43DC000ull |
|---|
| 14171 | #define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14172 | #define DCORE1_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14173 | #define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x43DC200ull |
|---|
| 14174 | #define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14175 | #define DCORE1_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14176 | #define mmDCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x43DC400ull |
|---|
| 14177 | #define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14178 | #define DCORE1_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14179 | #define mmDCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x43DC600ull |
|---|
| 14180 | #define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14181 | #define DCORE1_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14182 | #define mmDCORE1_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x43DC800ull |
|---|
| 14183 | #define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14184 | #define DCORE1_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14185 | #define mmDCORE1_EDMA1_MSTR_IF_AXUSER_BASE 0x43DCA80ull |
|---|
| 14186 | #define DCORE1_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14187 | #define DCORE1_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14188 | #define mmDCORE1_EDMA1_MSTR_IF_DBG_HBW_BASE 0x43DCB00ull |
|---|
| 14189 | #define DCORE1_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14190 | #define DCORE1_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14191 | #define mmDCORE1_EDMA1_MSTR_IF_DBG_LBW_BASE 0x43DCB80ull |
|---|
| 14192 | #define DCORE1_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14193 | #define DCORE1_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14194 | #define mmDCORE1_EDMA1_MSTR_IF_CORE_HBW_BASE 0x43DCC00ull |
|---|
| 14195 | #define DCORE1_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14196 | #define DCORE1_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14197 | #define mmDCORE1_EDMA1_MSTR_IF_CORE_LBW_BASE 0x43DCD80ull |
|---|
| 14198 | #define DCORE1_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14199 | #define DCORE1_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14200 | #define mmDCORE1_EDMA1_MSTR_IF_SPECIAL_BASE 0x43DCE80ull |
|---|
| 14201 | #define DCORE1_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14202 | #define DCORE1_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 14203 | #define mmDCORE1_DEC0_CMD_BASE 0x43E0000ull |
|---|
| 14204 | #define DCORE1_DEC0_CMD_MAX_OFFSET 0x1100 |
|---|
| 14205 | #define DCORE1_DEC0_CMD_SECTION 0x1000 |
|---|
| 14206 | #define mmDCORE1_DEC0_VSI_BASE 0x43E1000ull |
|---|
| 14207 | #define DCORE1_DEC0_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 14208 | #define DCORE1_DEC0_VSI_SECTION 0x1000 |
|---|
| 14209 | #define mmDCORE1_DEC0_L2C_BASE 0x43E2000ull |
|---|
| 14210 | #define DCORE1_DEC0_L2C_MAX_OFFSET 0x39C0 |
|---|
| 14211 | #define DCORE1_DEC0_L2C_SECTION 0x1000 |
|---|
| 14212 | #define mmDCORE1_VDEC0_BRDG_CTRL_BASE 0x43E3000ull |
|---|
| 14213 | #define DCORE1_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 14214 | #define DCORE1_VDEC0_BRDG_CTRL_SECTION 0x8000 |
|---|
| 14215 | #define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43E3800ull |
|---|
| 14216 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 14217 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 14218 | #define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43E3900ull |
|---|
| 14219 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 14220 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 14221 | #define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43E3A00ull |
|---|
| 14222 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 14223 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 14224 | #define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43E3B00ull |
|---|
| 14225 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 14226 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 14227 | #define mmDCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x43E3C00ull |
|---|
| 14228 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 14229 | #define DCORE1_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 14230 | #define mmDCORE1_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x43E3E80ull |
|---|
| 14231 | #define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14232 | #define DCORE1_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 14233 | #define mmDCORE1_VDEC0_CTRL_BASE 0x43E4000ull |
|---|
| 14234 | #define DCORE1_VDEC0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 14235 | #define DCORE1_VDEC0_CTRL_SECTION 0xE800 |
|---|
| 14236 | #define mmDCORE1_VDEC0_CTRL_SPECIAL_BASE 0x43E4E80ull |
|---|
| 14237 | #define DCORE1_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14238 | #define DCORE1_VDEC0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 14239 | #define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x43E5000ull |
|---|
| 14240 | #define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14241 | #define DCORE1_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14242 | #define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x43E5200ull |
|---|
| 14243 | #define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14244 | #define DCORE1_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14245 | #define mmDCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x43E5400ull |
|---|
| 14246 | #define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14247 | #define DCORE1_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14248 | #define mmDCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x43E5600ull |
|---|
| 14249 | #define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14250 | #define DCORE1_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14251 | #define mmDCORE1_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x43E5800ull |
|---|
| 14252 | #define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14253 | #define DCORE1_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14254 | #define mmDCORE1_VDEC0_MSTR_IF_AXUSER_BASE 0x43E5A80ull |
|---|
| 14255 | #define DCORE1_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14256 | #define DCORE1_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14257 | #define mmDCORE1_VDEC0_MSTR_IF_DBG_HBW_BASE 0x43E5B00ull |
|---|
| 14258 | #define DCORE1_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14259 | #define DCORE1_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14260 | #define mmDCORE1_VDEC0_MSTR_IF_DBG_LBW_BASE 0x43E5B80ull |
|---|
| 14261 | #define DCORE1_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14262 | #define DCORE1_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14263 | #define mmDCORE1_VDEC0_MSTR_IF_CORE_HBW_BASE 0x43E5C00ull |
|---|
| 14264 | #define DCORE1_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14265 | #define DCORE1_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14266 | #define mmDCORE1_VDEC0_MSTR_IF_CORE_LBW_BASE 0x43E5D80ull |
|---|
| 14267 | #define DCORE1_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14268 | #define DCORE1_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14269 | #define mmDCORE1_VDEC0_MSTR_IF_SPECIAL_BASE 0x43E5E80ull |
|---|
| 14270 | #define DCORE1_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14271 | #define DCORE1_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 14272 | #define mmDCORE1_DEC1_CMD_BASE 0x43F0000ull |
|---|
| 14273 | #define DCORE1_DEC1_CMD_MAX_OFFSET 0x1100 |
|---|
| 14274 | #define DCORE1_DEC1_CMD_SECTION 0x1000 |
|---|
| 14275 | #define mmDCORE1_DEC1_VSI_BASE 0x43F1000ull |
|---|
| 14276 | #define DCORE1_DEC1_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 14277 | #define DCORE1_DEC1_VSI_SECTION 0x1000 |
|---|
| 14278 | #define mmDCORE1_DEC1_L2C_BASE 0x43F2000ull |
|---|
| 14279 | #define DCORE1_DEC1_L2C_MAX_OFFSET 0x39C0 |
|---|
| 14280 | #define DCORE1_DEC1_L2C_SECTION 0x1000 |
|---|
| 14281 | #define mmDCORE1_VDEC1_BRDG_CTRL_BASE 0x43F3000ull |
|---|
| 14282 | #define DCORE1_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 14283 | #define DCORE1_VDEC1_BRDG_CTRL_SECTION 0x8000 |
|---|
| 14284 | #define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x43F3800ull |
|---|
| 14285 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 14286 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 14287 | #define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x43F3900ull |
|---|
| 14288 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 14289 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 14290 | #define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x43F3A00ull |
|---|
| 14291 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 14292 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 14293 | #define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x43F3B00ull |
|---|
| 14294 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 14295 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 14296 | #define mmDCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x43F3C00ull |
|---|
| 14297 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 14298 | #define DCORE1_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 14299 | #define mmDCORE1_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x43F3E80ull |
|---|
| 14300 | #define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14301 | #define DCORE1_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 14302 | #define mmDCORE1_VDEC1_CTRL_BASE 0x43F4000ull |
|---|
| 14303 | #define DCORE1_VDEC1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 14304 | #define DCORE1_VDEC1_CTRL_SECTION 0xE800 |
|---|
| 14305 | #define mmDCORE1_VDEC1_CTRL_SPECIAL_BASE 0x43F4E80ull |
|---|
| 14306 | #define DCORE1_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14307 | #define DCORE1_VDEC1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 14308 | #define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x43F5000ull |
|---|
| 14309 | #define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14310 | #define DCORE1_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14311 | #define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x43F5200ull |
|---|
| 14312 | #define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14313 | #define DCORE1_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14314 | #define mmDCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x43F5400ull |
|---|
| 14315 | #define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14316 | #define DCORE1_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14317 | #define mmDCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x43F5600ull |
|---|
| 14318 | #define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14319 | #define DCORE1_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14320 | #define mmDCORE1_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x43F5800ull |
|---|
| 14321 | #define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14322 | #define DCORE1_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14323 | #define mmDCORE1_VDEC1_MSTR_IF_AXUSER_BASE 0x43F5A80ull |
|---|
| 14324 | #define DCORE1_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14325 | #define DCORE1_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14326 | #define mmDCORE1_VDEC1_MSTR_IF_DBG_HBW_BASE 0x43F5B00ull |
|---|
| 14327 | #define DCORE1_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14328 | #define DCORE1_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14329 | #define mmDCORE1_VDEC1_MSTR_IF_DBG_LBW_BASE 0x43F5B80ull |
|---|
| 14330 | #define DCORE1_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14331 | #define DCORE1_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14332 | #define mmDCORE1_VDEC1_MSTR_IF_CORE_HBW_BASE 0x43F5C00ull |
|---|
| 14333 | #define DCORE1_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14334 | #define DCORE1_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14335 | #define mmDCORE1_VDEC1_MSTR_IF_CORE_LBW_BASE 0x43F5D80ull |
|---|
| 14336 | #define DCORE1_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14337 | #define DCORE1_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14338 | #define mmDCORE1_VDEC1_MSTR_IF_SPECIAL_BASE 0x43F5E80ull |
|---|
| 14339 | #define DCORE1_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14340 | #define DCORE1_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 14341 | #define mmDCORE2_TPC0_QM_DCCM_BASE 0x4400000ull |
|---|
| 14342 | #define DCORE2_TPC0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 14343 | #define DCORE2_TPC0_QM_DCCM_SECTION 0x8000 |
|---|
| 14344 | #define mmDCORE2_TPC0_QM_ARC_AUX_BASE 0x4408000ull |
|---|
| 14345 | #define DCORE2_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 14346 | #define DCORE2_TPC0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 14347 | #define mmDCORE2_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4408E80ull |
|---|
| 14348 | #define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14349 | #define DCORE2_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 14350 | #define mmDCORE2_TPC0_QM_BASE 0x440A000ull |
|---|
| 14351 | #define DCORE2_TPC0_QM_MAX_OFFSET 0x1000 |
|---|
| 14352 | #define DCORE2_TPC0_QM_SECTION 0x9000 |
|---|
| 14353 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x440A900ull |
|---|
| 14354 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 14355 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 14356 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x440A908ull |
|---|
| 14357 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 14358 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 14359 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x440A910ull |
|---|
| 14360 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 14361 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 14362 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x440A918ull |
|---|
| 14363 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 14364 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 14365 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x440A920ull |
|---|
| 14366 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 14367 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 14368 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x440A928ull |
|---|
| 14369 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 14370 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 14371 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x440A930ull |
|---|
| 14372 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 14373 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 14374 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x440A938ull |
|---|
| 14375 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 14376 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 14377 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x440A940ull |
|---|
| 14378 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 14379 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 14380 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x440A948ull |
|---|
| 14381 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 14382 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 14383 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x440A950ull |
|---|
| 14384 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 14385 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 14386 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x440A958ull |
|---|
| 14387 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 14388 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 14389 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x440A960ull |
|---|
| 14390 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 14391 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 14392 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x440A968ull |
|---|
| 14393 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 14394 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 14395 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x440A970ull |
|---|
| 14396 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 14397 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 14398 | #define mmDCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x440A978ull |
|---|
| 14399 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 14400 | #define DCORE2_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 14401 | #define mmDCORE2_TPC0_QM_AXUSER_SECURED_BASE 0x440AB00ull |
|---|
| 14402 | #define DCORE2_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 14403 | #define DCORE2_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 14404 | #define mmDCORE2_TPC0_QM_AXUSER_NONSECURED_BASE 0x440AB80ull |
|---|
| 14405 | #define DCORE2_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 14406 | #define DCORE2_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 14407 | #define mmDCORE2_TPC0_QM_DBG_HBW_BASE 0x440AC00ull |
|---|
| 14408 | #define DCORE2_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14409 | #define DCORE2_TPC0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 14410 | #define mmDCORE2_TPC0_QM_DBG_LBW_BASE 0x440AC80ull |
|---|
| 14411 | #define DCORE2_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14412 | #define DCORE2_TPC0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 14413 | #define mmDCORE2_TPC0_QM_CGM_BASE 0x440AD80ull |
|---|
| 14414 | #define DCORE2_TPC0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 14415 | #define DCORE2_TPC0_QM_CGM_SECTION 0x1000 |
|---|
| 14416 | #define mmDCORE2_TPC0_QM_SPECIAL_BASE 0x440AE80ull |
|---|
| 14417 | #define DCORE2_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14418 | #define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14419 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x440B000ull |
|---|
| 14420 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14421 | #define DCORE2_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14422 | #define mmDCORE2_TPC0_CFG_BASE 0x440B000ull |
|---|
| 14423 | #define DCORE2_TPC0_CFG_MAX_OFFSET 0x1000 |
|---|
| 14424 | #define DCORE2_TPC0_CFG_SECTION 0x5000 |
|---|
| 14425 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x440B050ull |
|---|
| 14426 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14427 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 14428 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x440B0A0ull |
|---|
| 14429 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14430 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 14431 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x440B0F0ull |
|---|
| 14432 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14433 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 14434 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x440B140ull |
|---|
| 14435 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14436 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 14437 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x440B190ull |
|---|
| 14438 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14439 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 14440 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x440B1E0ull |
|---|
| 14441 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14442 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 14443 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x440B230ull |
|---|
| 14444 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14445 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 14446 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x440B280ull |
|---|
| 14447 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14448 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 14449 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x440B2D0ull |
|---|
| 14450 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14451 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 14452 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x440B320ull |
|---|
| 14453 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14454 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 14455 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x440B370ull |
|---|
| 14456 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14457 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 14458 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x440B3C0ull |
|---|
| 14459 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14460 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 14461 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x440B410ull |
|---|
| 14462 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14463 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 14464 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x440B460ull |
|---|
| 14465 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14466 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 14467 | #define mmDCORE2_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x440B4B0ull |
|---|
| 14468 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14469 | #define DCORE2_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 14470 | #define mmDCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x440B500ull |
|---|
| 14471 | #define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14472 | #define DCORE2_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14473 | #define mmDCORE2_TPC0_CFG_KERNEL_BASE 0x440B508ull |
|---|
| 14474 | #define DCORE2_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 14475 | #define DCORE2_TPC0_CFG_KERNEL_SECTION 0xD400 |
|---|
| 14476 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_0_BASE 0x440B5DCull |
|---|
| 14477 | #define DCORE2_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14478 | #define DCORE2_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 14479 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_1_BASE 0x440B62Cull |
|---|
| 14480 | #define DCORE2_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14481 | #define DCORE2_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 14482 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_2_BASE 0x440B67Cull |
|---|
| 14483 | #define DCORE2_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14484 | #define DCORE2_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 14485 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_3_BASE 0x440B6CCull |
|---|
| 14486 | #define DCORE2_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14487 | #define DCORE2_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 14488 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_4_BASE 0x440B71Cull |
|---|
| 14489 | #define DCORE2_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14490 | #define DCORE2_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 14491 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_5_BASE 0x440B76Cull |
|---|
| 14492 | #define DCORE2_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14493 | #define DCORE2_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 14494 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_6_BASE 0x440B7BCull |
|---|
| 14495 | #define DCORE2_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14496 | #define DCORE2_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 14497 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_7_BASE 0x440B80Cull |
|---|
| 14498 | #define DCORE2_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14499 | #define DCORE2_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 14500 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_8_BASE 0x440B85Cull |
|---|
| 14501 | #define DCORE2_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14502 | #define DCORE2_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 14503 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_9_BASE 0x440B8ACull |
|---|
| 14504 | #define DCORE2_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14505 | #define DCORE2_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 14506 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_10_BASE 0x440B8FCull |
|---|
| 14507 | #define DCORE2_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14508 | #define DCORE2_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 14509 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_11_BASE 0x440B94Cull |
|---|
| 14510 | #define DCORE2_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14511 | #define DCORE2_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 14512 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_12_BASE 0x440B99Cull |
|---|
| 14513 | #define DCORE2_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14514 | #define DCORE2_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 14515 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_13_BASE 0x440B9ECull |
|---|
| 14516 | #define DCORE2_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14517 | #define DCORE2_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 14518 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_14_BASE 0x440BA3Cull |
|---|
| 14519 | #define DCORE2_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14520 | #define DCORE2_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 14521 | #define mmDCORE2_TPC0_CFG_QM_TENSOR_15_BASE 0x440BA8Cull |
|---|
| 14522 | #define DCORE2_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14523 | #define DCORE2_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 14524 | #define mmDCORE2_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x440BADCull |
|---|
| 14525 | #define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14526 | #define DCORE2_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14527 | #define mmDCORE2_TPC0_CFG_QM_BASE 0x440BAE4ull |
|---|
| 14528 | #define DCORE2_TPC0_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 14529 | #define DCORE2_TPC0_CFG_QM_SECTION 0x31C0 |
|---|
| 14530 | #define mmDCORE2_TPC0_CFG_AXUSER_BASE 0x440BE00ull |
|---|
| 14531 | #define DCORE2_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14532 | #define DCORE2_TPC0_CFG_AXUSER_SECTION 0x8000 |
|---|
| 14533 | #define mmDCORE2_TPC0_CFG_SPECIAL_BASE 0x440BE80ull |
|---|
| 14534 | #define DCORE2_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14535 | #define DCORE2_TPC0_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 14536 | #define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x440C000ull |
|---|
| 14537 | #define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14538 | #define DCORE2_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14539 | #define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x440C200ull |
|---|
| 14540 | #define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14541 | #define DCORE2_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14542 | #define mmDCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x440C400ull |
|---|
| 14543 | #define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14544 | #define DCORE2_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14545 | #define mmDCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x440C600ull |
|---|
| 14546 | #define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14547 | #define DCORE2_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14548 | #define mmDCORE2_TPC0_MSTR_IF_E2E_CRDT_BASE 0x440C800ull |
|---|
| 14549 | #define DCORE2_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14550 | #define DCORE2_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14551 | #define mmDCORE2_TPC0_MSTR_IF_AXUSER_BASE 0x440CA80ull |
|---|
| 14552 | #define DCORE2_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14553 | #define DCORE2_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14554 | #define mmDCORE2_TPC0_MSTR_IF_DBG_HBW_BASE 0x440CB00ull |
|---|
| 14555 | #define DCORE2_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14556 | #define DCORE2_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14557 | #define mmDCORE2_TPC0_MSTR_IF_DBG_LBW_BASE 0x440CB80ull |
|---|
| 14558 | #define DCORE2_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14559 | #define DCORE2_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14560 | #define mmDCORE2_TPC0_MSTR_IF_CORE_HBW_BASE 0x440CC00ull |
|---|
| 14561 | #define DCORE2_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14562 | #define DCORE2_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14563 | #define mmDCORE2_TPC0_MSTR_IF_CORE_LBW_BASE 0x440CD80ull |
|---|
| 14564 | #define DCORE2_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14565 | #define DCORE2_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14566 | #define mmDCORE2_TPC0_MSTR_IF_SPECIAL_BASE 0x440CE80ull |
|---|
| 14567 | #define DCORE2_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14568 | #define DCORE2_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 14569 | #define mmDCORE2_TPC1_QM_DCCM_BASE 0x4410000ull |
|---|
| 14570 | #define DCORE2_TPC1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 14571 | #define DCORE2_TPC1_QM_DCCM_SECTION 0x8000 |
|---|
| 14572 | #define mmDCORE2_TPC1_QM_ARC_AUX_BASE 0x4418000ull |
|---|
| 14573 | #define DCORE2_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 14574 | #define DCORE2_TPC1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 14575 | #define mmDCORE2_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4418E80ull |
|---|
| 14576 | #define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14577 | #define DCORE2_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 14578 | #define mmDCORE2_TPC1_QM_BASE 0x441A000ull |
|---|
| 14579 | #define DCORE2_TPC1_QM_MAX_OFFSET 0x1000 |
|---|
| 14580 | #define DCORE2_TPC1_QM_SECTION 0x9000 |
|---|
| 14581 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x441A900ull |
|---|
| 14582 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 14583 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 14584 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x441A908ull |
|---|
| 14585 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 14586 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 14587 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x441A910ull |
|---|
| 14588 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 14589 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 14590 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x441A918ull |
|---|
| 14591 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 14592 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 14593 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x441A920ull |
|---|
| 14594 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 14595 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 14596 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x441A928ull |
|---|
| 14597 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 14598 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 14599 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x441A930ull |
|---|
| 14600 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 14601 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 14602 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x441A938ull |
|---|
| 14603 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 14604 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 14605 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x441A940ull |
|---|
| 14606 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 14607 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 14608 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x441A948ull |
|---|
| 14609 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 14610 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 14611 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x441A950ull |
|---|
| 14612 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 14613 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 14614 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x441A958ull |
|---|
| 14615 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 14616 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 14617 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x441A960ull |
|---|
| 14618 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 14619 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 14620 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x441A968ull |
|---|
| 14621 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 14622 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 14623 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x441A970ull |
|---|
| 14624 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 14625 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 14626 | #define mmDCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x441A978ull |
|---|
| 14627 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 14628 | #define DCORE2_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 14629 | #define mmDCORE2_TPC1_QM_AXUSER_SECURED_BASE 0x441AB00ull |
|---|
| 14630 | #define DCORE2_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 14631 | #define DCORE2_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 14632 | #define mmDCORE2_TPC1_QM_AXUSER_NONSECURED_BASE 0x441AB80ull |
|---|
| 14633 | #define DCORE2_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 14634 | #define DCORE2_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 14635 | #define mmDCORE2_TPC1_QM_DBG_HBW_BASE 0x441AC00ull |
|---|
| 14636 | #define DCORE2_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14637 | #define DCORE2_TPC1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 14638 | #define mmDCORE2_TPC1_QM_DBG_LBW_BASE 0x441AC80ull |
|---|
| 14639 | #define DCORE2_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14640 | #define DCORE2_TPC1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 14641 | #define mmDCORE2_TPC1_QM_CGM_BASE 0x441AD80ull |
|---|
| 14642 | #define DCORE2_TPC1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 14643 | #define DCORE2_TPC1_QM_CGM_SECTION 0x1000 |
|---|
| 14644 | #define mmDCORE2_TPC1_QM_SPECIAL_BASE 0x441AE80ull |
|---|
| 14645 | #define DCORE2_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14646 | #define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14647 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x441B000ull |
|---|
| 14648 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14649 | #define DCORE2_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14650 | #define mmDCORE2_TPC1_CFG_BASE 0x441B000ull |
|---|
| 14651 | #define DCORE2_TPC1_CFG_MAX_OFFSET 0x1000 |
|---|
| 14652 | #define DCORE2_TPC1_CFG_SECTION 0x5000 |
|---|
| 14653 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x441B050ull |
|---|
| 14654 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14655 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 14656 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x441B0A0ull |
|---|
| 14657 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14658 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 14659 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x441B0F0ull |
|---|
| 14660 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14661 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 14662 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x441B140ull |
|---|
| 14663 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14664 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 14665 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x441B190ull |
|---|
| 14666 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14667 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 14668 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x441B1E0ull |
|---|
| 14669 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14670 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 14671 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x441B230ull |
|---|
| 14672 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14673 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 14674 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x441B280ull |
|---|
| 14675 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14676 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 14677 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x441B2D0ull |
|---|
| 14678 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14679 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 14680 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x441B320ull |
|---|
| 14681 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14682 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 14683 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x441B370ull |
|---|
| 14684 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14685 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 14686 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x441B3C0ull |
|---|
| 14687 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14688 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 14689 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x441B410ull |
|---|
| 14690 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14691 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 14692 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x441B460ull |
|---|
| 14693 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14694 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 14695 | #define mmDCORE2_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x441B4B0ull |
|---|
| 14696 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14697 | #define DCORE2_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 14698 | #define mmDCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x441B500ull |
|---|
| 14699 | #define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14700 | #define DCORE2_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14701 | #define mmDCORE2_TPC1_CFG_KERNEL_BASE 0x441B508ull |
|---|
| 14702 | #define DCORE2_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 14703 | #define DCORE2_TPC1_CFG_KERNEL_SECTION 0xD400 |
|---|
| 14704 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_0_BASE 0x441B5DCull |
|---|
| 14705 | #define DCORE2_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14706 | #define DCORE2_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 14707 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_1_BASE 0x441B62Cull |
|---|
| 14708 | #define DCORE2_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14709 | #define DCORE2_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 14710 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_2_BASE 0x441B67Cull |
|---|
| 14711 | #define DCORE2_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14712 | #define DCORE2_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 14713 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_3_BASE 0x441B6CCull |
|---|
| 14714 | #define DCORE2_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14715 | #define DCORE2_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 14716 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_4_BASE 0x441B71Cull |
|---|
| 14717 | #define DCORE2_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14718 | #define DCORE2_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 14719 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_5_BASE 0x441B76Cull |
|---|
| 14720 | #define DCORE2_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14721 | #define DCORE2_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 14722 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_6_BASE 0x441B7BCull |
|---|
| 14723 | #define DCORE2_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14724 | #define DCORE2_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 14725 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_7_BASE 0x441B80Cull |
|---|
| 14726 | #define DCORE2_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14727 | #define DCORE2_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 14728 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_8_BASE 0x441B85Cull |
|---|
| 14729 | #define DCORE2_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14730 | #define DCORE2_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 14731 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_9_BASE 0x441B8ACull |
|---|
| 14732 | #define DCORE2_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14733 | #define DCORE2_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 14734 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_10_BASE 0x441B8FCull |
|---|
| 14735 | #define DCORE2_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14736 | #define DCORE2_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 14737 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_11_BASE 0x441B94Cull |
|---|
| 14738 | #define DCORE2_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14739 | #define DCORE2_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 14740 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_12_BASE 0x441B99Cull |
|---|
| 14741 | #define DCORE2_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14742 | #define DCORE2_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 14743 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_13_BASE 0x441B9ECull |
|---|
| 14744 | #define DCORE2_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14745 | #define DCORE2_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 14746 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_14_BASE 0x441BA3Cull |
|---|
| 14747 | #define DCORE2_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14748 | #define DCORE2_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 14749 | #define mmDCORE2_TPC1_CFG_QM_TENSOR_15_BASE 0x441BA8Cull |
|---|
| 14750 | #define DCORE2_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14751 | #define DCORE2_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 14752 | #define mmDCORE2_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x441BADCull |
|---|
| 14753 | #define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14754 | #define DCORE2_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14755 | #define mmDCORE2_TPC1_CFG_QM_BASE 0x441BAE4ull |
|---|
| 14756 | #define DCORE2_TPC1_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 14757 | #define DCORE2_TPC1_CFG_QM_SECTION 0x31C0 |
|---|
| 14758 | #define mmDCORE2_TPC1_CFG_AXUSER_BASE 0x441BE00ull |
|---|
| 14759 | #define DCORE2_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14760 | #define DCORE2_TPC1_CFG_AXUSER_SECTION 0x8000 |
|---|
| 14761 | #define mmDCORE2_TPC1_CFG_SPECIAL_BASE 0x441BE80ull |
|---|
| 14762 | #define DCORE2_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14763 | #define DCORE2_TPC1_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 14764 | #define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x441C000ull |
|---|
| 14765 | #define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14766 | #define DCORE2_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14767 | #define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x441C200ull |
|---|
| 14768 | #define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14769 | #define DCORE2_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14770 | #define mmDCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x441C400ull |
|---|
| 14771 | #define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14772 | #define DCORE2_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 14773 | #define mmDCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x441C600ull |
|---|
| 14774 | #define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 14775 | #define DCORE2_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 14776 | #define mmDCORE2_TPC1_MSTR_IF_E2E_CRDT_BASE 0x441C800ull |
|---|
| 14777 | #define DCORE2_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 14778 | #define DCORE2_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 14779 | #define mmDCORE2_TPC1_MSTR_IF_AXUSER_BASE 0x441CA80ull |
|---|
| 14780 | #define DCORE2_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14781 | #define DCORE2_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 14782 | #define mmDCORE2_TPC1_MSTR_IF_DBG_HBW_BASE 0x441CB00ull |
|---|
| 14783 | #define DCORE2_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14784 | #define DCORE2_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 14785 | #define mmDCORE2_TPC1_MSTR_IF_DBG_LBW_BASE 0x441CB80ull |
|---|
| 14786 | #define DCORE2_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14787 | #define DCORE2_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 14788 | #define mmDCORE2_TPC1_MSTR_IF_CORE_HBW_BASE 0x441CC00ull |
|---|
| 14789 | #define DCORE2_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 14790 | #define DCORE2_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 14791 | #define mmDCORE2_TPC1_MSTR_IF_CORE_LBW_BASE 0x441CD80ull |
|---|
| 14792 | #define DCORE2_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 14793 | #define DCORE2_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 14794 | #define mmDCORE2_TPC1_MSTR_IF_SPECIAL_BASE 0x441CE80ull |
|---|
| 14795 | #define DCORE2_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14796 | #define DCORE2_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 14797 | #define mmDCORE2_TPC2_QM_DCCM_BASE 0x4420000ull |
|---|
| 14798 | #define DCORE2_TPC2_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 14799 | #define DCORE2_TPC2_QM_DCCM_SECTION 0x8000 |
|---|
| 14800 | #define mmDCORE2_TPC2_QM_ARC_AUX_BASE 0x4428000ull |
|---|
| 14801 | #define DCORE2_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 14802 | #define DCORE2_TPC2_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 14803 | #define mmDCORE2_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4428E80ull |
|---|
| 14804 | #define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14805 | #define DCORE2_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 14806 | #define mmDCORE2_TPC2_QM_BASE 0x442A000ull |
|---|
| 14807 | #define DCORE2_TPC2_QM_MAX_OFFSET 0x1000 |
|---|
| 14808 | #define DCORE2_TPC2_QM_SECTION 0x9000 |
|---|
| 14809 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x442A900ull |
|---|
| 14810 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 14811 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 14812 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x442A908ull |
|---|
| 14813 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 14814 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 14815 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x442A910ull |
|---|
| 14816 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 14817 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 14818 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x442A918ull |
|---|
| 14819 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 14820 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 14821 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x442A920ull |
|---|
| 14822 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 14823 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 14824 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x442A928ull |
|---|
| 14825 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 14826 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 14827 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x442A930ull |
|---|
| 14828 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 14829 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 14830 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x442A938ull |
|---|
| 14831 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 14832 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 14833 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x442A940ull |
|---|
| 14834 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 14835 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 14836 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x442A948ull |
|---|
| 14837 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 14838 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 14839 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x442A950ull |
|---|
| 14840 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 14841 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 14842 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x442A958ull |
|---|
| 14843 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 14844 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 14845 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x442A960ull |
|---|
| 14846 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 14847 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 14848 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x442A968ull |
|---|
| 14849 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 14850 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 14851 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x442A970ull |
|---|
| 14852 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 14853 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 14854 | #define mmDCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x442A978ull |
|---|
| 14855 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 14856 | #define DCORE2_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 14857 | #define mmDCORE2_TPC2_QM_AXUSER_SECURED_BASE 0x442AB00ull |
|---|
| 14858 | #define DCORE2_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 14859 | #define DCORE2_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 14860 | #define mmDCORE2_TPC2_QM_AXUSER_NONSECURED_BASE 0x442AB80ull |
|---|
| 14861 | #define DCORE2_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 14862 | #define DCORE2_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 14863 | #define mmDCORE2_TPC2_QM_DBG_HBW_BASE 0x442AC00ull |
|---|
| 14864 | #define DCORE2_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 14865 | #define DCORE2_TPC2_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 14866 | #define mmDCORE2_TPC2_QM_DBG_LBW_BASE 0x442AC80ull |
|---|
| 14867 | #define DCORE2_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 14868 | #define DCORE2_TPC2_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 14869 | #define mmDCORE2_TPC2_QM_CGM_BASE 0x442AD80ull |
|---|
| 14870 | #define DCORE2_TPC2_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 14871 | #define DCORE2_TPC2_QM_CGM_SECTION 0x1000 |
|---|
| 14872 | #define mmDCORE2_TPC2_QM_SPECIAL_BASE 0x442AE80ull |
|---|
| 14873 | #define DCORE2_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14874 | #define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14875 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x442B000ull |
|---|
| 14876 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14877 | #define DCORE2_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 14878 | #define mmDCORE2_TPC2_CFG_BASE 0x442B000ull |
|---|
| 14879 | #define DCORE2_TPC2_CFG_MAX_OFFSET 0x1000 |
|---|
| 14880 | #define DCORE2_TPC2_CFG_SECTION 0x5000 |
|---|
| 14881 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x442B050ull |
|---|
| 14882 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14883 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 14884 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x442B0A0ull |
|---|
| 14885 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14886 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 14887 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x442B0F0ull |
|---|
| 14888 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14889 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 14890 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x442B140ull |
|---|
| 14891 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14892 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 14893 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x442B190ull |
|---|
| 14894 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14895 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 14896 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x442B1E0ull |
|---|
| 14897 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14898 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 14899 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x442B230ull |
|---|
| 14900 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14901 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 14902 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x442B280ull |
|---|
| 14903 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14904 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 14905 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x442B2D0ull |
|---|
| 14906 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14907 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 14908 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x442B320ull |
|---|
| 14909 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14910 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 14911 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x442B370ull |
|---|
| 14912 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14913 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 14914 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x442B3C0ull |
|---|
| 14915 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14916 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 14917 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x442B410ull |
|---|
| 14918 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14919 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 14920 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x442B460ull |
|---|
| 14921 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14922 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 14923 | #define mmDCORE2_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x442B4B0ull |
|---|
| 14924 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14925 | #define DCORE2_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 14926 | #define mmDCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x442B500ull |
|---|
| 14927 | #define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14928 | #define DCORE2_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14929 | #define mmDCORE2_TPC2_CFG_KERNEL_BASE 0x442B508ull |
|---|
| 14930 | #define DCORE2_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 14931 | #define DCORE2_TPC2_CFG_KERNEL_SECTION 0xD400 |
|---|
| 14932 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_0_BASE 0x442B5DCull |
|---|
| 14933 | #define DCORE2_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 14934 | #define DCORE2_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 14935 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_1_BASE 0x442B62Cull |
|---|
| 14936 | #define DCORE2_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 14937 | #define DCORE2_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 14938 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_2_BASE 0x442B67Cull |
|---|
| 14939 | #define DCORE2_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 14940 | #define DCORE2_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 14941 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_3_BASE 0x442B6CCull |
|---|
| 14942 | #define DCORE2_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 14943 | #define DCORE2_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 14944 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_4_BASE 0x442B71Cull |
|---|
| 14945 | #define DCORE2_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 14946 | #define DCORE2_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 14947 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_5_BASE 0x442B76Cull |
|---|
| 14948 | #define DCORE2_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 14949 | #define DCORE2_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 14950 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_6_BASE 0x442B7BCull |
|---|
| 14951 | #define DCORE2_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 14952 | #define DCORE2_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 14953 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_7_BASE 0x442B80Cull |
|---|
| 14954 | #define DCORE2_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 14955 | #define DCORE2_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 14956 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_8_BASE 0x442B85Cull |
|---|
| 14957 | #define DCORE2_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 14958 | #define DCORE2_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 14959 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_9_BASE 0x442B8ACull |
|---|
| 14960 | #define DCORE2_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 14961 | #define DCORE2_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 14962 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_10_BASE 0x442B8FCull |
|---|
| 14963 | #define DCORE2_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 14964 | #define DCORE2_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 14965 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_11_BASE 0x442B94Cull |
|---|
| 14966 | #define DCORE2_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 14967 | #define DCORE2_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 14968 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_12_BASE 0x442B99Cull |
|---|
| 14969 | #define DCORE2_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 14970 | #define DCORE2_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 14971 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_13_BASE 0x442B9ECull |
|---|
| 14972 | #define DCORE2_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 14973 | #define DCORE2_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 14974 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_14_BASE 0x442BA3Cull |
|---|
| 14975 | #define DCORE2_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 14976 | #define DCORE2_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 14977 | #define mmDCORE2_TPC2_CFG_QM_TENSOR_15_BASE 0x442BA8Cull |
|---|
| 14978 | #define DCORE2_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 14979 | #define DCORE2_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 14980 | #define mmDCORE2_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x442BADCull |
|---|
| 14981 | #define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 14982 | #define DCORE2_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 14983 | #define mmDCORE2_TPC2_CFG_QM_BASE 0x442BAE4ull |
|---|
| 14984 | #define DCORE2_TPC2_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 14985 | #define DCORE2_TPC2_CFG_QM_SECTION 0x31C0 |
|---|
| 14986 | #define mmDCORE2_TPC2_CFG_AXUSER_BASE 0x442BE00ull |
|---|
| 14987 | #define DCORE2_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 14988 | #define DCORE2_TPC2_CFG_AXUSER_SECTION 0x8000 |
|---|
| 14989 | #define mmDCORE2_TPC2_CFG_SPECIAL_BASE 0x442BE80ull |
|---|
| 14990 | #define DCORE2_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 14991 | #define DCORE2_TPC2_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 14992 | #define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x442C000ull |
|---|
| 14993 | #define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14994 | #define DCORE2_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 14995 | #define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x442C200ull |
|---|
| 14996 | #define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 14997 | #define DCORE2_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 14998 | #define mmDCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x442C400ull |
|---|
| 14999 | #define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15000 | #define DCORE2_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15001 | #define mmDCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x442C600ull |
|---|
| 15002 | #define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15003 | #define DCORE2_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15004 | #define mmDCORE2_TPC2_MSTR_IF_E2E_CRDT_BASE 0x442C800ull |
|---|
| 15005 | #define DCORE2_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15006 | #define DCORE2_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15007 | #define mmDCORE2_TPC2_MSTR_IF_AXUSER_BASE 0x442CA80ull |
|---|
| 15008 | #define DCORE2_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15009 | #define DCORE2_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15010 | #define mmDCORE2_TPC2_MSTR_IF_DBG_HBW_BASE 0x442CB00ull |
|---|
| 15011 | #define DCORE2_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15012 | #define DCORE2_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15013 | #define mmDCORE2_TPC2_MSTR_IF_DBG_LBW_BASE 0x442CB80ull |
|---|
| 15014 | #define DCORE2_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15015 | #define DCORE2_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15016 | #define mmDCORE2_TPC2_MSTR_IF_CORE_HBW_BASE 0x442CC00ull |
|---|
| 15017 | #define DCORE2_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15018 | #define DCORE2_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15019 | #define mmDCORE2_TPC2_MSTR_IF_CORE_LBW_BASE 0x442CD80ull |
|---|
| 15020 | #define DCORE2_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15021 | #define DCORE2_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15022 | #define mmDCORE2_TPC2_MSTR_IF_SPECIAL_BASE 0x442CE80ull |
|---|
| 15023 | #define DCORE2_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15024 | #define DCORE2_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 15025 | #define mmDCORE2_TPC3_QM_DCCM_BASE 0x4430000ull |
|---|
| 15026 | #define DCORE2_TPC3_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 15027 | #define DCORE2_TPC3_QM_DCCM_SECTION 0x8000 |
|---|
| 15028 | #define mmDCORE2_TPC3_QM_ARC_AUX_BASE 0x4438000ull |
|---|
| 15029 | #define DCORE2_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 15030 | #define DCORE2_TPC3_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 15031 | #define mmDCORE2_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4438E80ull |
|---|
| 15032 | #define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15033 | #define DCORE2_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 15034 | #define mmDCORE2_TPC3_QM_BASE 0x443A000ull |
|---|
| 15035 | #define DCORE2_TPC3_QM_MAX_OFFSET 0x1000 |
|---|
| 15036 | #define DCORE2_TPC3_QM_SECTION 0x9000 |
|---|
| 15037 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x443A900ull |
|---|
| 15038 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 15039 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 15040 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x443A908ull |
|---|
| 15041 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 15042 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 15043 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x443A910ull |
|---|
| 15044 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 15045 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 15046 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x443A918ull |
|---|
| 15047 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 15048 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 15049 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x443A920ull |
|---|
| 15050 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 15051 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 15052 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x443A928ull |
|---|
| 15053 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 15054 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 15055 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x443A930ull |
|---|
| 15056 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 15057 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 15058 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x443A938ull |
|---|
| 15059 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 15060 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 15061 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x443A940ull |
|---|
| 15062 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 15063 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 15064 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x443A948ull |
|---|
| 15065 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 15066 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 15067 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x443A950ull |
|---|
| 15068 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 15069 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 15070 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x443A958ull |
|---|
| 15071 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 15072 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 15073 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x443A960ull |
|---|
| 15074 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 15075 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 15076 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x443A968ull |
|---|
| 15077 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 15078 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 15079 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x443A970ull |
|---|
| 15080 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 15081 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 15082 | #define mmDCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x443A978ull |
|---|
| 15083 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 15084 | #define DCORE2_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 15085 | #define mmDCORE2_TPC3_QM_AXUSER_SECURED_BASE 0x443AB00ull |
|---|
| 15086 | #define DCORE2_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 15087 | #define DCORE2_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 15088 | #define mmDCORE2_TPC3_QM_AXUSER_NONSECURED_BASE 0x443AB80ull |
|---|
| 15089 | #define DCORE2_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 15090 | #define DCORE2_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 15091 | #define mmDCORE2_TPC3_QM_DBG_HBW_BASE 0x443AC00ull |
|---|
| 15092 | #define DCORE2_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15093 | #define DCORE2_TPC3_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 15094 | #define mmDCORE2_TPC3_QM_DBG_LBW_BASE 0x443AC80ull |
|---|
| 15095 | #define DCORE2_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15096 | #define DCORE2_TPC3_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 15097 | #define mmDCORE2_TPC3_QM_CGM_BASE 0x443AD80ull |
|---|
| 15098 | #define DCORE2_TPC3_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 15099 | #define DCORE2_TPC3_QM_CGM_SECTION 0x1000 |
|---|
| 15100 | #define mmDCORE2_TPC3_QM_SPECIAL_BASE 0x443AE80ull |
|---|
| 15101 | #define DCORE2_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15102 | #define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15103 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x443B000ull |
|---|
| 15104 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15105 | #define DCORE2_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15106 | #define mmDCORE2_TPC3_CFG_BASE 0x443B000ull |
|---|
| 15107 | #define DCORE2_TPC3_CFG_MAX_OFFSET 0x1000 |
|---|
| 15108 | #define DCORE2_TPC3_CFG_SECTION 0x5000 |
|---|
| 15109 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x443B050ull |
|---|
| 15110 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15111 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 15112 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x443B0A0ull |
|---|
| 15113 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15114 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 15115 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x443B0F0ull |
|---|
| 15116 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15117 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 15118 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x443B140ull |
|---|
| 15119 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15120 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 15121 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x443B190ull |
|---|
| 15122 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15123 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 15124 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x443B1E0ull |
|---|
| 15125 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15126 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 15127 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x443B230ull |
|---|
| 15128 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15129 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 15130 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x443B280ull |
|---|
| 15131 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15132 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 15133 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x443B2D0ull |
|---|
| 15134 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15135 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 15136 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x443B320ull |
|---|
| 15137 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15138 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 15139 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x443B370ull |
|---|
| 15140 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15141 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 15142 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x443B3C0ull |
|---|
| 15143 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15144 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 15145 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x443B410ull |
|---|
| 15146 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15147 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 15148 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x443B460ull |
|---|
| 15149 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15150 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 15151 | #define mmDCORE2_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x443B4B0ull |
|---|
| 15152 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15153 | #define DCORE2_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 15154 | #define mmDCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x443B500ull |
|---|
| 15155 | #define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15156 | #define DCORE2_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15157 | #define mmDCORE2_TPC3_CFG_KERNEL_BASE 0x443B508ull |
|---|
| 15158 | #define DCORE2_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 15159 | #define DCORE2_TPC3_CFG_KERNEL_SECTION 0xD400 |
|---|
| 15160 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_0_BASE 0x443B5DCull |
|---|
| 15161 | #define DCORE2_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15162 | #define DCORE2_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 15163 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_1_BASE 0x443B62Cull |
|---|
| 15164 | #define DCORE2_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15165 | #define DCORE2_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 15166 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_2_BASE 0x443B67Cull |
|---|
| 15167 | #define DCORE2_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15168 | #define DCORE2_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 15169 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_3_BASE 0x443B6CCull |
|---|
| 15170 | #define DCORE2_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15171 | #define DCORE2_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 15172 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_4_BASE 0x443B71Cull |
|---|
| 15173 | #define DCORE2_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15174 | #define DCORE2_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 15175 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_5_BASE 0x443B76Cull |
|---|
| 15176 | #define DCORE2_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15177 | #define DCORE2_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 15178 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_6_BASE 0x443B7BCull |
|---|
| 15179 | #define DCORE2_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15180 | #define DCORE2_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 15181 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_7_BASE 0x443B80Cull |
|---|
| 15182 | #define DCORE2_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15183 | #define DCORE2_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 15184 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_8_BASE 0x443B85Cull |
|---|
| 15185 | #define DCORE2_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15186 | #define DCORE2_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 15187 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_9_BASE 0x443B8ACull |
|---|
| 15188 | #define DCORE2_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15189 | #define DCORE2_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 15190 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_10_BASE 0x443B8FCull |
|---|
| 15191 | #define DCORE2_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15192 | #define DCORE2_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 15193 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_11_BASE 0x443B94Cull |
|---|
| 15194 | #define DCORE2_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15195 | #define DCORE2_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 15196 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_12_BASE 0x443B99Cull |
|---|
| 15197 | #define DCORE2_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15198 | #define DCORE2_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 15199 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_13_BASE 0x443B9ECull |
|---|
| 15200 | #define DCORE2_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15201 | #define DCORE2_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 15202 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_14_BASE 0x443BA3Cull |
|---|
| 15203 | #define DCORE2_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15204 | #define DCORE2_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 15205 | #define mmDCORE2_TPC3_CFG_QM_TENSOR_15_BASE 0x443BA8Cull |
|---|
| 15206 | #define DCORE2_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15207 | #define DCORE2_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 15208 | #define mmDCORE2_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x443BADCull |
|---|
| 15209 | #define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15210 | #define DCORE2_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15211 | #define mmDCORE2_TPC3_CFG_QM_BASE 0x443BAE4ull |
|---|
| 15212 | #define DCORE2_TPC3_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 15213 | #define DCORE2_TPC3_CFG_QM_SECTION 0x31C0 |
|---|
| 15214 | #define mmDCORE2_TPC3_CFG_AXUSER_BASE 0x443BE00ull |
|---|
| 15215 | #define DCORE2_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15216 | #define DCORE2_TPC3_CFG_AXUSER_SECTION 0x8000 |
|---|
| 15217 | #define mmDCORE2_TPC3_CFG_SPECIAL_BASE 0x443BE80ull |
|---|
| 15218 | #define DCORE2_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15219 | #define DCORE2_TPC3_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 15220 | #define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x443C000ull |
|---|
| 15221 | #define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15222 | #define DCORE2_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15223 | #define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x443C200ull |
|---|
| 15224 | #define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15225 | #define DCORE2_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15226 | #define mmDCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x443C400ull |
|---|
| 15227 | #define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15228 | #define DCORE2_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15229 | #define mmDCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x443C600ull |
|---|
| 15230 | #define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15231 | #define DCORE2_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15232 | #define mmDCORE2_TPC3_MSTR_IF_E2E_CRDT_BASE 0x443C800ull |
|---|
| 15233 | #define DCORE2_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15234 | #define DCORE2_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15235 | #define mmDCORE2_TPC3_MSTR_IF_AXUSER_BASE 0x443CA80ull |
|---|
| 15236 | #define DCORE2_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15237 | #define DCORE2_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15238 | #define mmDCORE2_TPC3_MSTR_IF_DBG_HBW_BASE 0x443CB00ull |
|---|
| 15239 | #define DCORE2_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15240 | #define DCORE2_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15241 | #define mmDCORE2_TPC3_MSTR_IF_DBG_LBW_BASE 0x443CB80ull |
|---|
| 15242 | #define DCORE2_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15243 | #define DCORE2_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15244 | #define mmDCORE2_TPC3_MSTR_IF_CORE_HBW_BASE 0x443CC00ull |
|---|
| 15245 | #define DCORE2_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15246 | #define DCORE2_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15247 | #define mmDCORE2_TPC3_MSTR_IF_CORE_LBW_BASE 0x443CD80ull |
|---|
| 15248 | #define DCORE2_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15249 | #define DCORE2_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15250 | #define mmDCORE2_TPC3_MSTR_IF_SPECIAL_BASE 0x443CE80ull |
|---|
| 15251 | #define DCORE2_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15252 | #define DCORE2_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 15253 | #define mmDCORE2_TPC4_QM_DCCM_BASE 0x4440000ull |
|---|
| 15254 | #define DCORE2_TPC4_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 15255 | #define DCORE2_TPC4_QM_DCCM_SECTION 0x8000 |
|---|
| 15256 | #define mmDCORE2_TPC4_QM_ARC_AUX_BASE 0x4448000ull |
|---|
| 15257 | #define DCORE2_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 15258 | #define DCORE2_TPC4_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 15259 | #define mmDCORE2_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4448E80ull |
|---|
| 15260 | #define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15261 | #define DCORE2_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 15262 | #define mmDCORE2_TPC4_QM_BASE 0x444A000ull |
|---|
| 15263 | #define DCORE2_TPC4_QM_MAX_OFFSET 0x1000 |
|---|
| 15264 | #define DCORE2_TPC4_QM_SECTION 0x9000 |
|---|
| 15265 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x444A900ull |
|---|
| 15266 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 15267 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 15268 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x444A908ull |
|---|
| 15269 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 15270 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 15271 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x444A910ull |
|---|
| 15272 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 15273 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 15274 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x444A918ull |
|---|
| 15275 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 15276 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 15277 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x444A920ull |
|---|
| 15278 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 15279 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 15280 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x444A928ull |
|---|
| 15281 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 15282 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 15283 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x444A930ull |
|---|
| 15284 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 15285 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 15286 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x444A938ull |
|---|
| 15287 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 15288 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 15289 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x444A940ull |
|---|
| 15290 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 15291 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 15292 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x444A948ull |
|---|
| 15293 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 15294 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 15295 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x444A950ull |
|---|
| 15296 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 15297 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 15298 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x444A958ull |
|---|
| 15299 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 15300 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 15301 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x444A960ull |
|---|
| 15302 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 15303 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 15304 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x444A968ull |
|---|
| 15305 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 15306 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 15307 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x444A970ull |
|---|
| 15308 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 15309 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 15310 | #define mmDCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x444A978ull |
|---|
| 15311 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 15312 | #define DCORE2_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 15313 | #define mmDCORE2_TPC4_QM_AXUSER_SECURED_BASE 0x444AB00ull |
|---|
| 15314 | #define DCORE2_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 15315 | #define DCORE2_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 15316 | #define mmDCORE2_TPC4_QM_AXUSER_NONSECURED_BASE 0x444AB80ull |
|---|
| 15317 | #define DCORE2_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 15318 | #define DCORE2_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 15319 | #define mmDCORE2_TPC4_QM_DBG_HBW_BASE 0x444AC00ull |
|---|
| 15320 | #define DCORE2_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15321 | #define DCORE2_TPC4_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 15322 | #define mmDCORE2_TPC4_QM_DBG_LBW_BASE 0x444AC80ull |
|---|
| 15323 | #define DCORE2_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15324 | #define DCORE2_TPC4_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 15325 | #define mmDCORE2_TPC4_QM_CGM_BASE 0x444AD80ull |
|---|
| 15326 | #define DCORE2_TPC4_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 15327 | #define DCORE2_TPC4_QM_CGM_SECTION 0x1000 |
|---|
| 15328 | #define mmDCORE2_TPC4_QM_SPECIAL_BASE 0x444AE80ull |
|---|
| 15329 | #define DCORE2_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15330 | #define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15331 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x444B000ull |
|---|
| 15332 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15333 | #define DCORE2_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15334 | #define mmDCORE2_TPC4_CFG_BASE 0x444B000ull |
|---|
| 15335 | #define DCORE2_TPC4_CFG_MAX_OFFSET 0x1000 |
|---|
| 15336 | #define DCORE2_TPC4_CFG_SECTION 0x5000 |
|---|
| 15337 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x444B050ull |
|---|
| 15338 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15339 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 15340 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x444B0A0ull |
|---|
| 15341 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15342 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 15343 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x444B0F0ull |
|---|
| 15344 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15345 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 15346 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x444B140ull |
|---|
| 15347 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15348 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 15349 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x444B190ull |
|---|
| 15350 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15351 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 15352 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x444B1E0ull |
|---|
| 15353 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15354 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 15355 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x444B230ull |
|---|
| 15356 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15357 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 15358 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x444B280ull |
|---|
| 15359 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15360 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 15361 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x444B2D0ull |
|---|
| 15362 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15363 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 15364 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x444B320ull |
|---|
| 15365 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15366 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 15367 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x444B370ull |
|---|
| 15368 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15369 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 15370 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x444B3C0ull |
|---|
| 15371 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15372 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 15373 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x444B410ull |
|---|
| 15374 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15375 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 15376 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x444B460ull |
|---|
| 15377 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15378 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 15379 | #define mmDCORE2_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x444B4B0ull |
|---|
| 15380 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15381 | #define DCORE2_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 15382 | #define mmDCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x444B500ull |
|---|
| 15383 | #define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15384 | #define DCORE2_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15385 | #define mmDCORE2_TPC4_CFG_KERNEL_BASE 0x444B508ull |
|---|
| 15386 | #define DCORE2_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 15387 | #define DCORE2_TPC4_CFG_KERNEL_SECTION 0xD400 |
|---|
| 15388 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_0_BASE 0x444B5DCull |
|---|
| 15389 | #define DCORE2_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15390 | #define DCORE2_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 15391 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_1_BASE 0x444B62Cull |
|---|
| 15392 | #define DCORE2_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15393 | #define DCORE2_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 15394 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_2_BASE 0x444B67Cull |
|---|
| 15395 | #define DCORE2_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15396 | #define DCORE2_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 15397 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_3_BASE 0x444B6CCull |
|---|
| 15398 | #define DCORE2_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15399 | #define DCORE2_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 15400 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_4_BASE 0x444B71Cull |
|---|
| 15401 | #define DCORE2_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15402 | #define DCORE2_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 15403 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_5_BASE 0x444B76Cull |
|---|
| 15404 | #define DCORE2_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15405 | #define DCORE2_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 15406 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_6_BASE 0x444B7BCull |
|---|
| 15407 | #define DCORE2_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15408 | #define DCORE2_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 15409 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_7_BASE 0x444B80Cull |
|---|
| 15410 | #define DCORE2_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15411 | #define DCORE2_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 15412 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_8_BASE 0x444B85Cull |
|---|
| 15413 | #define DCORE2_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15414 | #define DCORE2_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 15415 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_9_BASE 0x444B8ACull |
|---|
| 15416 | #define DCORE2_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15417 | #define DCORE2_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 15418 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_10_BASE 0x444B8FCull |
|---|
| 15419 | #define DCORE2_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15420 | #define DCORE2_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 15421 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_11_BASE 0x444B94Cull |
|---|
| 15422 | #define DCORE2_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15423 | #define DCORE2_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 15424 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_12_BASE 0x444B99Cull |
|---|
| 15425 | #define DCORE2_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15426 | #define DCORE2_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 15427 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_13_BASE 0x444B9ECull |
|---|
| 15428 | #define DCORE2_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15429 | #define DCORE2_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 15430 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_14_BASE 0x444BA3Cull |
|---|
| 15431 | #define DCORE2_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15432 | #define DCORE2_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 15433 | #define mmDCORE2_TPC4_CFG_QM_TENSOR_15_BASE 0x444BA8Cull |
|---|
| 15434 | #define DCORE2_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15435 | #define DCORE2_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 15436 | #define mmDCORE2_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x444BADCull |
|---|
| 15437 | #define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15438 | #define DCORE2_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15439 | #define mmDCORE2_TPC4_CFG_QM_BASE 0x444BAE4ull |
|---|
| 15440 | #define DCORE2_TPC4_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 15441 | #define DCORE2_TPC4_CFG_QM_SECTION 0x31C0 |
|---|
| 15442 | #define mmDCORE2_TPC4_CFG_AXUSER_BASE 0x444BE00ull |
|---|
| 15443 | #define DCORE2_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15444 | #define DCORE2_TPC4_CFG_AXUSER_SECTION 0x8000 |
|---|
| 15445 | #define mmDCORE2_TPC4_CFG_SPECIAL_BASE 0x444BE80ull |
|---|
| 15446 | #define DCORE2_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15447 | #define DCORE2_TPC4_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 15448 | #define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x444C000ull |
|---|
| 15449 | #define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15450 | #define DCORE2_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15451 | #define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x444C200ull |
|---|
| 15452 | #define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15453 | #define DCORE2_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15454 | #define mmDCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x444C400ull |
|---|
| 15455 | #define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15456 | #define DCORE2_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15457 | #define mmDCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x444C600ull |
|---|
| 15458 | #define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15459 | #define DCORE2_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15460 | #define mmDCORE2_TPC4_MSTR_IF_E2E_CRDT_BASE 0x444C800ull |
|---|
| 15461 | #define DCORE2_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15462 | #define DCORE2_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15463 | #define mmDCORE2_TPC4_MSTR_IF_AXUSER_BASE 0x444CA80ull |
|---|
| 15464 | #define DCORE2_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15465 | #define DCORE2_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15466 | #define mmDCORE2_TPC4_MSTR_IF_DBG_HBW_BASE 0x444CB00ull |
|---|
| 15467 | #define DCORE2_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15468 | #define DCORE2_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15469 | #define mmDCORE2_TPC4_MSTR_IF_DBG_LBW_BASE 0x444CB80ull |
|---|
| 15470 | #define DCORE2_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15471 | #define DCORE2_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15472 | #define mmDCORE2_TPC4_MSTR_IF_CORE_HBW_BASE 0x444CC00ull |
|---|
| 15473 | #define DCORE2_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15474 | #define DCORE2_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15475 | #define mmDCORE2_TPC4_MSTR_IF_CORE_LBW_BASE 0x444CD80ull |
|---|
| 15476 | #define DCORE2_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15477 | #define DCORE2_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15478 | #define mmDCORE2_TPC4_MSTR_IF_SPECIAL_BASE 0x444CE80ull |
|---|
| 15479 | #define DCORE2_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15480 | #define DCORE2_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 15481 | #define mmDCORE2_TPC5_QM_DCCM_BASE 0x4450000ull |
|---|
| 15482 | #define DCORE2_TPC5_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 15483 | #define DCORE2_TPC5_QM_DCCM_SECTION 0x8000 |
|---|
| 15484 | #define mmDCORE2_TPC5_QM_ARC_AUX_BASE 0x4458000ull |
|---|
| 15485 | #define DCORE2_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 15486 | #define DCORE2_TPC5_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 15487 | #define mmDCORE2_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4458E80ull |
|---|
| 15488 | #define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15489 | #define DCORE2_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 15490 | #define mmDCORE2_TPC5_QM_BASE 0x445A000ull |
|---|
| 15491 | #define DCORE2_TPC5_QM_MAX_OFFSET 0x1000 |
|---|
| 15492 | #define DCORE2_TPC5_QM_SECTION 0x9000 |
|---|
| 15493 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x445A900ull |
|---|
| 15494 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 15495 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 15496 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x445A908ull |
|---|
| 15497 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 15498 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 15499 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x445A910ull |
|---|
| 15500 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 15501 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 15502 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x445A918ull |
|---|
| 15503 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 15504 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 15505 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x445A920ull |
|---|
| 15506 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 15507 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 15508 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x445A928ull |
|---|
| 15509 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 15510 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 15511 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x445A930ull |
|---|
| 15512 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 15513 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 15514 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x445A938ull |
|---|
| 15515 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 15516 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 15517 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x445A940ull |
|---|
| 15518 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 15519 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 15520 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x445A948ull |
|---|
| 15521 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 15522 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 15523 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x445A950ull |
|---|
| 15524 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 15525 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 15526 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x445A958ull |
|---|
| 15527 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 15528 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 15529 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x445A960ull |
|---|
| 15530 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 15531 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 15532 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x445A968ull |
|---|
| 15533 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 15534 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 15535 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x445A970ull |
|---|
| 15536 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 15537 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 15538 | #define mmDCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x445A978ull |
|---|
| 15539 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 15540 | #define DCORE2_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 15541 | #define mmDCORE2_TPC5_QM_AXUSER_SECURED_BASE 0x445AB00ull |
|---|
| 15542 | #define DCORE2_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 15543 | #define DCORE2_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 15544 | #define mmDCORE2_TPC5_QM_AXUSER_NONSECURED_BASE 0x445AB80ull |
|---|
| 15545 | #define DCORE2_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 15546 | #define DCORE2_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 15547 | #define mmDCORE2_TPC5_QM_DBG_HBW_BASE 0x445AC00ull |
|---|
| 15548 | #define DCORE2_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15549 | #define DCORE2_TPC5_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 15550 | #define mmDCORE2_TPC5_QM_DBG_LBW_BASE 0x445AC80ull |
|---|
| 15551 | #define DCORE2_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15552 | #define DCORE2_TPC5_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 15553 | #define mmDCORE2_TPC5_QM_CGM_BASE 0x445AD80ull |
|---|
| 15554 | #define DCORE2_TPC5_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 15555 | #define DCORE2_TPC5_QM_CGM_SECTION 0x1000 |
|---|
| 15556 | #define mmDCORE2_TPC5_QM_SPECIAL_BASE 0x445AE80ull |
|---|
| 15557 | #define DCORE2_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15558 | #define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15559 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x445B000ull |
|---|
| 15560 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15561 | #define DCORE2_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 15562 | #define mmDCORE2_TPC5_CFG_BASE 0x445B000ull |
|---|
| 15563 | #define DCORE2_TPC5_CFG_MAX_OFFSET 0x1000 |
|---|
| 15564 | #define DCORE2_TPC5_CFG_SECTION 0x5000 |
|---|
| 15565 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x445B050ull |
|---|
| 15566 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15567 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 15568 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x445B0A0ull |
|---|
| 15569 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15570 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 15571 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x445B0F0ull |
|---|
| 15572 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15573 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 15574 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x445B140ull |
|---|
| 15575 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15576 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 15577 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x445B190ull |
|---|
| 15578 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15579 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 15580 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x445B1E0ull |
|---|
| 15581 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15582 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 15583 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x445B230ull |
|---|
| 15584 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15585 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 15586 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x445B280ull |
|---|
| 15587 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15588 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 15589 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x445B2D0ull |
|---|
| 15590 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15591 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 15592 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x445B320ull |
|---|
| 15593 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15594 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 15595 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x445B370ull |
|---|
| 15596 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15597 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 15598 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x445B3C0ull |
|---|
| 15599 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15600 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 15601 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x445B410ull |
|---|
| 15602 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15603 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 15604 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x445B460ull |
|---|
| 15605 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15606 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 15607 | #define mmDCORE2_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x445B4B0ull |
|---|
| 15608 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15609 | #define DCORE2_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 15610 | #define mmDCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x445B500ull |
|---|
| 15611 | #define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15612 | #define DCORE2_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15613 | #define mmDCORE2_TPC5_CFG_KERNEL_BASE 0x445B508ull |
|---|
| 15614 | #define DCORE2_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 15615 | #define DCORE2_TPC5_CFG_KERNEL_SECTION 0xD400 |
|---|
| 15616 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_0_BASE 0x445B5DCull |
|---|
| 15617 | #define DCORE2_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 15618 | #define DCORE2_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 15619 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_1_BASE 0x445B62Cull |
|---|
| 15620 | #define DCORE2_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 15621 | #define DCORE2_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 15622 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_2_BASE 0x445B67Cull |
|---|
| 15623 | #define DCORE2_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 15624 | #define DCORE2_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 15625 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_3_BASE 0x445B6CCull |
|---|
| 15626 | #define DCORE2_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 15627 | #define DCORE2_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 15628 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_4_BASE 0x445B71Cull |
|---|
| 15629 | #define DCORE2_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 15630 | #define DCORE2_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 15631 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_5_BASE 0x445B76Cull |
|---|
| 15632 | #define DCORE2_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 15633 | #define DCORE2_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 15634 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_6_BASE 0x445B7BCull |
|---|
| 15635 | #define DCORE2_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 15636 | #define DCORE2_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 15637 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_7_BASE 0x445B80Cull |
|---|
| 15638 | #define DCORE2_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 15639 | #define DCORE2_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 15640 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_8_BASE 0x445B85Cull |
|---|
| 15641 | #define DCORE2_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 15642 | #define DCORE2_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 15643 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_9_BASE 0x445B8ACull |
|---|
| 15644 | #define DCORE2_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 15645 | #define DCORE2_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 15646 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_10_BASE 0x445B8FCull |
|---|
| 15647 | #define DCORE2_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 15648 | #define DCORE2_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 15649 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_11_BASE 0x445B94Cull |
|---|
| 15650 | #define DCORE2_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 15651 | #define DCORE2_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 15652 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_12_BASE 0x445B99Cull |
|---|
| 15653 | #define DCORE2_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 15654 | #define DCORE2_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 15655 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_13_BASE 0x445B9ECull |
|---|
| 15656 | #define DCORE2_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 15657 | #define DCORE2_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 15658 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_14_BASE 0x445BA3Cull |
|---|
| 15659 | #define DCORE2_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 15660 | #define DCORE2_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 15661 | #define mmDCORE2_TPC5_CFG_QM_TENSOR_15_BASE 0x445BA8Cull |
|---|
| 15662 | #define DCORE2_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 15663 | #define DCORE2_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 15664 | #define mmDCORE2_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x445BADCull |
|---|
| 15665 | #define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 15666 | #define DCORE2_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 15667 | #define mmDCORE2_TPC5_CFG_QM_BASE 0x445BAE4ull |
|---|
| 15668 | #define DCORE2_TPC5_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 15669 | #define DCORE2_TPC5_CFG_QM_SECTION 0x31C0 |
|---|
| 15670 | #define mmDCORE2_TPC5_CFG_AXUSER_BASE 0x445BE00ull |
|---|
| 15671 | #define DCORE2_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15672 | #define DCORE2_TPC5_CFG_AXUSER_SECTION 0x8000 |
|---|
| 15673 | #define mmDCORE2_TPC5_CFG_SPECIAL_BASE 0x445BE80ull |
|---|
| 15674 | #define DCORE2_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15675 | #define DCORE2_TPC5_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 15676 | #define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x445C000ull |
|---|
| 15677 | #define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15678 | #define DCORE2_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15679 | #define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x445C200ull |
|---|
| 15680 | #define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15681 | #define DCORE2_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15682 | #define mmDCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x445C400ull |
|---|
| 15683 | #define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15684 | #define DCORE2_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15685 | #define mmDCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x445C600ull |
|---|
| 15686 | #define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15687 | #define DCORE2_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15688 | #define mmDCORE2_TPC5_MSTR_IF_E2E_CRDT_BASE 0x445C800ull |
|---|
| 15689 | #define DCORE2_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15690 | #define DCORE2_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15691 | #define mmDCORE2_TPC5_MSTR_IF_AXUSER_BASE 0x445CA80ull |
|---|
| 15692 | #define DCORE2_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15693 | #define DCORE2_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15694 | #define mmDCORE2_TPC5_MSTR_IF_DBG_HBW_BASE 0x445CB00ull |
|---|
| 15695 | #define DCORE2_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15696 | #define DCORE2_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15697 | #define mmDCORE2_TPC5_MSTR_IF_DBG_LBW_BASE 0x445CB80ull |
|---|
| 15698 | #define DCORE2_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15699 | #define DCORE2_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15700 | #define mmDCORE2_TPC5_MSTR_IF_CORE_HBW_BASE 0x445CC00ull |
|---|
| 15701 | #define DCORE2_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15702 | #define DCORE2_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15703 | #define mmDCORE2_TPC5_MSTR_IF_CORE_LBW_BASE 0x445CD80ull |
|---|
| 15704 | #define DCORE2_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15705 | #define DCORE2_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15706 | #define mmDCORE2_TPC5_MSTR_IF_SPECIAL_BASE 0x445CE80ull |
|---|
| 15707 | #define DCORE2_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15708 | #define DCORE2_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 |
|---|
| 15709 | #define mmDCORE2_HMMU0_MMU_BASE 0x4480000ull |
|---|
| 15710 | #define DCORE2_HMMU0_MMU_MAX_OFFSET 0x1000 |
|---|
| 15711 | #define DCORE2_HMMU0_MMU_SECTION 0xE800 |
|---|
| 15712 | #define mmDCORE2_HMMU0_MMU_SPECIAL_BASE 0x4480E80ull |
|---|
| 15713 | #define DCORE2_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15714 | #define DCORE2_HMMU0_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 15715 | #define mmDCORE2_HMMU0_STLB_BASE 0x4481000ull |
|---|
| 15716 | #define DCORE2_HMMU0_STLB_MAX_OFFSET 0x1000 |
|---|
| 15717 | #define DCORE2_HMMU0_STLB_SECTION 0xE800 |
|---|
| 15718 | #define mmDCORE2_HMMU0_STLB_SPECIAL_BASE 0x4481E80ull |
|---|
| 15719 | #define DCORE2_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15720 | #define DCORE2_HMMU0_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 15721 | #define mmDCORE2_HMMU0_SCRAMB_OUT_BASE 0x4483000ull |
|---|
| 15722 | #define DCORE2_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 15723 | #define DCORE2_HMMU0_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 15724 | #define mmDCORE2_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4483E80ull |
|---|
| 15725 | #define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15726 | #define DCORE2_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 15727 | #define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4484000ull |
|---|
| 15728 | #define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15729 | #define DCORE2_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15730 | #define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4484200ull |
|---|
| 15731 | #define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15732 | #define DCORE2_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15733 | #define mmDCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4484400ull |
|---|
| 15734 | #define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15735 | #define DCORE2_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15736 | #define mmDCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4484600ull |
|---|
| 15737 | #define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15738 | #define DCORE2_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15739 | #define mmDCORE2_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4484800ull |
|---|
| 15740 | #define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15741 | #define DCORE2_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15742 | #define mmDCORE2_HMMU0_MSTR_IF_AXUSER_BASE 0x4484A80ull |
|---|
| 15743 | #define DCORE2_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15744 | #define DCORE2_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15745 | #define mmDCORE2_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4484B00ull |
|---|
| 15746 | #define DCORE2_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15747 | #define DCORE2_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15748 | #define mmDCORE2_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4484B80ull |
|---|
| 15749 | #define DCORE2_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15750 | #define DCORE2_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15751 | #define mmDCORE2_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4484C00ull |
|---|
| 15752 | #define DCORE2_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15753 | #define DCORE2_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15754 | #define mmDCORE2_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4484D80ull |
|---|
| 15755 | #define DCORE2_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15756 | #define DCORE2_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15757 | #define mmDCORE2_HMMU0_MSTR_IF_SPECIAL_BASE 0x4484E80ull |
|---|
| 15758 | #define DCORE2_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15759 | #define DCORE2_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 15760 | #define mmDCORE2_HMMU1_MMU_BASE 0x4490000ull |
|---|
| 15761 | #define DCORE2_HMMU1_MMU_MAX_OFFSET 0x1000 |
|---|
| 15762 | #define DCORE2_HMMU1_MMU_SECTION 0xE800 |
|---|
| 15763 | #define mmDCORE2_HMMU1_MMU_SPECIAL_BASE 0x4490E80ull |
|---|
| 15764 | #define DCORE2_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15765 | #define DCORE2_HMMU1_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 15766 | #define mmDCORE2_HMMU1_STLB_BASE 0x4491000ull |
|---|
| 15767 | #define DCORE2_HMMU1_STLB_MAX_OFFSET 0x1000 |
|---|
| 15768 | #define DCORE2_HMMU1_STLB_SECTION 0xE800 |
|---|
| 15769 | #define mmDCORE2_HMMU1_STLB_SPECIAL_BASE 0x4491E80ull |
|---|
| 15770 | #define DCORE2_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15771 | #define DCORE2_HMMU1_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 15772 | #define mmDCORE2_HMMU1_SCRAMB_OUT_BASE 0x4493000ull |
|---|
| 15773 | #define DCORE2_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 15774 | #define DCORE2_HMMU1_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 15775 | #define mmDCORE2_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4493E80ull |
|---|
| 15776 | #define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15777 | #define DCORE2_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 15778 | #define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4494000ull |
|---|
| 15779 | #define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15780 | #define DCORE2_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15781 | #define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4494200ull |
|---|
| 15782 | #define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15783 | #define DCORE2_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15784 | #define mmDCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4494400ull |
|---|
| 15785 | #define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15786 | #define DCORE2_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15787 | #define mmDCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4494600ull |
|---|
| 15788 | #define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15789 | #define DCORE2_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15790 | #define mmDCORE2_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4494800ull |
|---|
| 15791 | #define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15792 | #define DCORE2_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15793 | #define mmDCORE2_HMMU1_MSTR_IF_AXUSER_BASE 0x4494A80ull |
|---|
| 15794 | #define DCORE2_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15795 | #define DCORE2_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15796 | #define mmDCORE2_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4494B00ull |
|---|
| 15797 | #define DCORE2_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15798 | #define DCORE2_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15799 | #define mmDCORE2_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4494B80ull |
|---|
| 15800 | #define DCORE2_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15801 | #define DCORE2_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15802 | #define mmDCORE2_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4494C00ull |
|---|
| 15803 | #define DCORE2_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15804 | #define DCORE2_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15805 | #define mmDCORE2_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4494D80ull |
|---|
| 15806 | #define DCORE2_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15807 | #define DCORE2_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15808 | #define mmDCORE2_HMMU1_MSTR_IF_SPECIAL_BASE 0x4494E80ull |
|---|
| 15809 | #define DCORE2_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15810 | #define DCORE2_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 15811 | #define mmDCORE2_HMMU2_MMU_BASE 0x44A0000ull |
|---|
| 15812 | #define DCORE2_HMMU2_MMU_MAX_OFFSET 0x1000 |
|---|
| 15813 | #define DCORE2_HMMU2_MMU_SECTION 0xE800 |
|---|
| 15814 | #define mmDCORE2_HMMU2_MMU_SPECIAL_BASE 0x44A0E80ull |
|---|
| 15815 | #define DCORE2_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15816 | #define DCORE2_HMMU2_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 15817 | #define mmDCORE2_HMMU2_STLB_BASE 0x44A1000ull |
|---|
| 15818 | #define DCORE2_HMMU2_STLB_MAX_OFFSET 0x1000 |
|---|
| 15819 | #define DCORE2_HMMU2_STLB_SECTION 0xE800 |
|---|
| 15820 | #define mmDCORE2_HMMU2_STLB_SPECIAL_BASE 0x44A1E80ull |
|---|
| 15821 | #define DCORE2_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15822 | #define DCORE2_HMMU2_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 15823 | #define mmDCORE2_HMMU2_SCRAMB_OUT_BASE 0x44A3000ull |
|---|
| 15824 | #define DCORE2_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 15825 | #define DCORE2_HMMU2_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 15826 | #define mmDCORE2_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x44A3E80ull |
|---|
| 15827 | #define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15828 | #define DCORE2_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 15829 | #define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x44A4000ull |
|---|
| 15830 | #define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15831 | #define DCORE2_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15832 | #define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x44A4200ull |
|---|
| 15833 | #define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15834 | #define DCORE2_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15835 | #define mmDCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x44A4400ull |
|---|
| 15836 | #define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15837 | #define DCORE2_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15838 | #define mmDCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x44A4600ull |
|---|
| 15839 | #define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15840 | #define DCORE2_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15841 | #define mmDCORE2_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x44A4800ull |
|---|
| 15842 | #define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15843 | #define DCORE2_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15844 | #define mmDCORE2_HMMU2_MSTR_IF_AXUSER_BASE 0x44A4A80ull |
|---|
| 15845 | #define DCORE2_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15846 | #define DCORE2_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15847 | #define mmDCORE2_HMMU2_MSTR_IF_DBG_HBW_BASE 0x44A4B00ull |
|---|
| 15848 | #define DCORE2_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15849 | #define DCORE2_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15850 | #define mmDCORE2_HMMU2_MSTR_IF_DBG_LBW_BASE 0x44A4B80ull |
|---|
| 15851 | #define DCORE2_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15852 | #define DCORE2_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15853 | #define mmDCORE2_HMMU2_MSTR_IF_CORE_HBW_BASE 0x44A4C00ull |
|---|
| 15854 | #define DCORE2_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15855 | #define DCORE2_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15856 | #define mmDCORE2_HMMU2_MSTR_IF_CORE_LBW_BASE 0x44A4D80ull |
|---|
| 15857 | #define DCORE2_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15858 | #define DCORE2_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15859 | #define mmDCORE2_HMMU2_MSTR_IF_SPECIAL_BASE 0x44A4E80ull |
|---|
| 15860 | #define DCORE2_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15861 | #define DCORE2_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 15862 | #define mmDCORE2_HMMU3_MMU_BASE 0x44B0000ull |
|---|
| 15863 | #define DCORE2_HMMU3_MMU_MAX_OFFSET 0x1000 |
|---|
| 15864 | #define DCORE2_HMMU3_MMU_SECTION 0xE800 |
|---|
| 15865 | #define mmDCORE2_HMMU3_MMU_SPECIAL_BASE 0x44B0E80ull |
|---|
| 15866 | #define DCORE2_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15867 | #define DCORE2_HMMU3_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 15868 | #define mmDCORE2_HMMU3_STLB_BASE 0x44B1000ull |
|---|
| 15869 | #define DCORE2_HMMU3_STLB_MAX_OFFSET 0x1000 |
|---|
| 15870 | #define DCORE2_HMMU3_STLB_SECTION 0xE800 |
|---|
| 15871 | #define mmDCORE2_HMMU3_STLB_SPECIAL_BASE 0x44B1E80ull |
|---|
| 15872 | #define DCORE2_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15873 | #define DCORE2_HMMU3_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 15874 | #define mmDCORE2_HMMU3_SCRAMB_OUT_BASE 0x44B3000ull |
|---|
| 15875 | #define DCORE2_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 15876 | #define DCORE2_HMMU3_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 15877 | #define mmDCORE2_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x44B3E80ull |
|---|
| 15878 | #define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15879 | #define DCORE2_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 15880 | #define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x44B4000ull |
|---|
| 15881 | #define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15882 | #define DCORE2_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 15883 | #define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x44B4200ull |
|---|
| 15884 | #define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 15885 | #define DCORE2_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 15886 | #define mmDCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x44B4400ull |
|---|
| 15887 | #define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15888 | #define DCORE2_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 15889 | #define mmDCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x44B4600ull |
|---|
| 15890 | #define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 15891 | #define DCORE2_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 15892 | #define mmDCORE2_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x44B4800ull |
|---|
| 15893 | #define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 15894 | #define DCORE2_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 15895 | #define mmDCORE2_HMMU3_MSTR_IF_AXUSER_BASE 0x44B4A80ull |
|---|
| 15896 | #define DCORE2_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15897 | #define DCORE2_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 15898 | #define mmDCORE2_HMMU3_MSTR_IF_DBG_HBW_BASE 0x44B4B00ull |
|---|
| 15899 | #define DCORE2_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15900 | #define DCORE2_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 15901 | #define mmDCORE2_HMMU3_MSTR_IF_DBG_LBW_BASE 0x44B4B80ull |
|---|
| 15902 | #define DCORE2_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15903 | #define DCORE2_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 15904 | #define mmDCORE2_HMMU3_MSTR_IF_CORE_HBW_BASE 0x44B4C00ull |
|---|
| 15905 | #define DCORE2_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 15906 | #define DCORE2_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 15907 | #define mmDCORE2_HMMU3_MSTR_IF_CORE_LBW_BASE 0x44B4D80ull |
|---|
| 15908 | #define DCORE2_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 15909 | #define DCORE2_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 15910 | #define mmDCORE2_HMMU3_MSTR_IF_SPECIAL_BASE 0x44B4E80ull |
|---|
| 15911 | #define DCORE2_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15912 | #define DCORE2_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 15913 | #define mmDCORE2_MME_QM_ARC_DCCM_BASE 0x44C0000ull |
|---|
| 15914 | #define DCORE2_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 |
|---|
| 15915 | #define DCORE2_MME_QM_ARC_DCCM_SECTION 0x8000 |
|---|
| 15916 | #define mmDCORE2_MME_QM_ARC_AUX_BASE 0x44C8000ull |
|---|
| 15917 | #define DCORE2_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 15918 | #define DCORE2_MME_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 15919 | #define mmDCORE2_MME_QM_ARC_AUX_SPECIAL_BASE 0x44C8E80ull |
|---|
| 15920 | #define DCORE2_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15921 | #define DCORE2_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 |
|---|
| 15922 | #define mmDCORE2_MME_QM_ARC_DUP_ENG_BASE 0x44C9000ull |
|---|
| 15923 | #define DCORE2_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 |
|---|
| 15924 | #define DCORE2_MME_QM_ARC_DUP_ENG_SECTION 0x9000 |
|---|
| 15925 | #define mmDCORE2_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x44C9900ull |
|---|
| 15926 | #define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 15927 | #define DCORE2_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 |
|---|
| 15928 | #define mmDCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x44C9E80ull |
|---|
| 15929 | #define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15930 | #define DCORE2_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 15931 | #define mmDCORE2_MME_QM_BASE 0x44CA000ull |
|---|
| 15932 | #define DCORE2_MME_QM_MAX_OFFSET 0x1000 |
|---|
| 15933 | #define DCORE2_MME_QM_SECTION 0x9000 |
|---|
| 15934 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x44CA900ull |
|---|
| 15935 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 15936 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 15937 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x44CA908ull |
|---|
| 15938 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 15939 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 15940 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x44CA910ull |
|---|
| 15941 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 15942 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 15943 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x44CA918ull |
|---|
| 15944 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 15945 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 15946 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x44CA920ull |
|---|
| 15947 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 15948 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 15949 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x44CA928ull |
|---|
| 15950 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 15951 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 15952 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x44CA930ull |
|---|
| 15953 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 15954 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 15955 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x44CA938ull |
|---|
| 15956 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 15957 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 15958 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x44CA940ull |
|---|
| 15959 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 15960 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 15961 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x44CA948ull |
|---|
| 15962 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 15963 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 15964 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x44CA950ull |
|---|
| 15965 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 15966 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 15967 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x44CA958ull |
|---|
| 15968 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 15969 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 15970 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x44CA960ull |
|---|
| 15971 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 15972 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 15973 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x44CA968ull |
|---|
| 15974 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 15975 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 15976 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x44CA970ull |
|---|
| 15977 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 15978 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 15979 | #define mmDCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x44CA978ull |
|---|
| 15980 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 15981 | #define DCORE2_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 15982 | #define mmDCORE2_MME_QM_AXUSER_SECURED_BASE 0x44CAB00ull |
|---|
| 15983 | #define DCORE2_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 15984 | #define DCORE2_MME_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 15985 | #define mmDCORE2_MME_QM_AXUSER_NONSECURED_BASE 0x44CAB80ull |
|---|
| 15986 | #define DCORE2_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 15987 | #define DCORE2_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 15988 | #define mmDCORE2_MME_QM_DBG_HBW_BASE 0x44CAC00ull |
|---|
| 15989 | #define DCORE2_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 15990 | #define DCORE2_MME_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 15991 | #define mmDCORE2_MME_QM_DBG_LBW_BASE 0x44CAC80ull |
|---|
| 15992 | #define DCORE2_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 15993 | #define DCORE2_MME_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 15994 | #define mmDCORE2_MME_QM_CGM_BASE 0x44CAD80ull |
|---|
| 15995 | #define DCORE2_MME_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 15996 | #define DCORE2_MME_QM_CGM_SECTION 0x1000 |
|---|
| 15997 | #define mmDCORE2_MME_QM_SPECIAL_BASE 0x44CAE80ull |
|---|
| 15998 | #define DCORE2_MME_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 15999 | #define DCORE2_MME_QM_SPECIAL_SECTION 0x1800 |
|---|
| 16000 | #define mmDCORE2_MME_CTRL_LO_BASE 0x44CB000ull |
|---|
| 16001 | #define DCORE2_MME_CTRL_LO_MAX_OFFSET 0x1000 |
|---|
| 16002 | #define DCORE2_MME_CTRL_LO_SECTION 0x8000 |
|---|
| 16003 | #define mmDCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x44CB008ull |
|---|
| 16004 | #define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 16005 | #define DCORE2_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 |
|---|
| 16006 | #define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x44CB028ull |
|---|
| 16007 | #define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 16008 | #define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 16009 | #define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x44CB040ull |
|---|
| 16010 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 16011 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 |
|---|
| 16012 | #define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x44CB098ull |
|---|
| 16013 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 16014 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 |
|---|
| 16015 | #define mmDCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x44CB0F0ull |
|---|
| 16016 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 16017 | #define DCORE2_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 16018 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x44CB15Cull |
|---|
| 16019 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16020 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 16021 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x44CB170ull |
|---|
| 16022 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16023 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 16024 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x44CB184ull |
|---|
| 16025 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16026 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 16027 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x44CB198ull |
|---|
| 16028 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16029 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 16030 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x44CB1ACull |
|---|
| 16031 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16032 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 16033 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x44CB1C0ull |
|---|
| 16034 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16035 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 16036 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x44CB1D4ull |
|---|
| 16037 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16038 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 16039 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x44CB1E8ull |
|---|
| 16040 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16041 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 16042 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x44CB1FCull |
|---|
| 16043 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16044 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 16045 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x44CB210ull |
|---|
| 16046 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16047 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 16048 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x44CB22Cull |
|---|
| 16049 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16050 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 16051 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x44CB240ull |
|---|
| 16052 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16053 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 16054 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x44CB254ull |
|---|
| 16055 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16056 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 16057 | #define mmDCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x44CB268ull |
|---|
| 16058 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16059 | #define DCORE2_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 16060 | #define mmDCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x44CB280ull |
|---|
| 16061 | #define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 16062 | #define DCORE2_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 |
|---|
| 16063 | #define mmDCORE2_MME_CTRL_LO_MME_AXUSER_BASE 0x44CBE00ull |
|---|
| 16064 | #define DCORE2_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16065 | #define DCORE2_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 |
|---|
| 16066 | #define mmDCORE2_MME_CTRL_LO_SPECIAL_BASE 0x44CBE80ull |
|---|
| 16067 | #define DCORE2_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16068 | #define DCORE2_MME_CTRL_LO_SPECIAL_SECTION 0x1800 |
|---|
| 16069 | #define mmDCORE2_MME_CTRL_HI_BASE 0x44CC000ull |
|---|
| 16070 | #define DCORE2_MME_CTRL_HI_MAX_OFFSET 0x1000 |
|---|
| 16071 | #define DCORE2_MME_CTRL_HI_SECTION 0x8000 |
|---|
| 16072 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x44CC008ull |
|---|
| 16073 | #define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 16074 | #define DCORE2_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 |
|---|
| 16075 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x44CC028ull |
|---|
| 16076 | #define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 16077 | #define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 16078 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x44CC040ull |
|---|
| 16079 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 16080 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 |
|---|
| 16081 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x44CC098ull |
|---|
| 16082 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 16083 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 |
|---|
| 16084 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x44CC0F0ull |
|---|
| 16085 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 16086 | #define DCORE2_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 16087 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x44CC15Cull |
|---|
| 16088 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16089 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 16090 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x44CC170ull |
|---|
| 16091 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16092 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 16093 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x44CC184ull |
|---|
| 16094 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16095 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 16096 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x44CC198ull |
|---|
| 16097 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16098 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 16099 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x44CC1ACull |
|---|
| 16100 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16101 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 16102 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x44CC1C0ull |
|---|
| 16103 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16104 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 16105 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x44CC1D4ull |
|---|
| 16106 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16107 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 16108 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x44CC1E8ull |
|---|
| 16109 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16110 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 16111 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x44CC1FCull |
|---|
| 16112 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16113 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 16114 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x44CC210ull |
|---|
| 16115 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16116 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 16117 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x44CC22Cull |
|---|
| 16118 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16119 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 16120 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x44CC240ull |
|---|
| 16121 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16122 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 16123 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x44CC254ull |
|---|
| 16124 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16125 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 16126 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x44CC268ull |
|---|
| 16127 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16128 | #define DCORE2_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 16129 | #define mmDCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x44CC280ull |
|---|
| 16130 | #define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 16131 | #define DCORE2_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 16132 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x44CC308ull |
|---|
| 16133 | #define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 16134 | #define DCORE2_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 |
|---|
| 16135 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x44CC328ull |
|---|
| 16136 | #define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 16137 | #define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 16138 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x44CC340ull |
|---|
| 16139 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 16140 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 |
|---|
| 16141 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x44CC398ull |
|---|
| 16142 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 16143 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 |
|---|
| 16144 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x44CC3F0ull |
|---|
| 16145 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 16146 | #define DCORE2_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 16147 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x44CC45Cull |
|---|
| 16148 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16149 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 16150 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x44CC470ull |
|---|
| 16151 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16152 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 16153 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x44CC484ull |
|---|
| 16154 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16155 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 16156 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x44CC498ull |
|---|
| 16157 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16158 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 16159 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x44CC4ACull |
|---|
| 16160 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16161 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 16162 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x44CC4C0ull |
|---|
| 16163 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16164 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 16165 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x44CC4D4ull |
|---|
| 16166 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16167 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 16168 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x44CC4E8ull |
|---|
| 16169 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16170 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 16171 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x44CC4FCull |
|---|
| 16172 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16173 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 16174 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x44CC510ull |
|---|
| 16175 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16176 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 16177 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x44CC52Cull |
|---|
| 16178 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16179 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 16180 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x44CC540ull |
|---|
| 16181 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16182 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 16183 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x44CC554ull |
|---|
| 16184 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16185 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 16186 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x44CC568ull |
|---|
| 16187 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16188 | #define DCORE2_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 16189 | #define mmDCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x44CC580ull |
|---|
| 16190 | #define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 16191 | #define DCORE2_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 16192 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x44CC608ull |
|---|
| 16193 | #define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 16194 | #define DCORE2_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 |
|---|
| 16195 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x44CC628ull |
|---|
| 16196 | #define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 16197 | #define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 16198 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x44CC640ull |
|---|
| 16199 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 16200 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 |
|---|
| 16201 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x44CC698ull |
|---|
| 16202 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 16203 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 |
|---|
| 16204 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x44CC6F0ull |
|---|
| 16205 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 16206 | #define DCORE2_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 16207 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x44CC75Cull |
|---|
| 16208 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16209 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 16210 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x44CC770ull |
|---|
| 16211 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16212 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 16213 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x44CC784ull |
|---|
| 16214 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16215 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 16216 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x44CC798ull |
|---|
| 16217 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16218 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 16219 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x44CC7ACull |
|---|
| 16220 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16221 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 16222 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x44CC7C0ull |
|---|
| 16223 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16224 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 16225 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x44CC7D4ull |
|---|
| 16226 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16227 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 16228 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x44CC7E8ull |
|---|
| 16229 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16230 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 16231 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x44CC7FCull |
|---|
| 16232 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16233 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 16234 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x44CC810ull |
|---|
| 16235 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16236 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 16237 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x44CC82Cull |
|---|
| 16238 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16239 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 16240 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x44CC840ull |
|---|
| 16241 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16242 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 16243 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x44CC854ull |
|---|
| 16244 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16245 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 16246 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x44CC868ull |
|---|
| 16247 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16248 | #define DCORE2_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 16249 | #define mmDCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x44CC880ull |
|---|
| 16250 | #define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 16251 | #define DCORE2_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 16252 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x44CC908ull |
|---|
| 16253 | #define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 16254 | #define DCORE2_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 |
|---|
| 16255 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x44CC928ull |
|---|
| 16256 | #define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 16257 | #define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 16258 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x44CC940ull |
|---|
| 16259 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 16260 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 |
|---|
| 16261 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x44CC998ull |
|---|
| 16262 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 16263 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 |
|---|
| 16264 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x44CC9F0ull |
|---|
| 16265 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 16266 | #define DCORE2_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 16267 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x44CCA5Cull |
|---|
| 16268 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16269 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 16270 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x44CCA70ull |
|---|
| 16271 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16272 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 16273 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x44CCA84ull |
|---|
| 16274 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16275 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 16276 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x44CCA98ull |
|---|
| 16277 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16278 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 16279 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x44CCAACull |
|---|
| 16280 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16281 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 16282 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x44CCAC0ull |
|---|
| 16283 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16284 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 16285 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x44CCAD4ull |
|---|
| 16286 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16287 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 16288 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x44CCAE8ull |
|---|
| 16289 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16290 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 16291 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x44CCAFCull |
|---|
| 16292 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16293 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 16294 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x44CCB10ull |
|---|
| 16295 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16296 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 16297 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x44CCB2Cull |
|---|
| 16298 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16299 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 16300 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x44CCB40ull |
|---|
| 16301 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16302 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 16303 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x44CCB54ull |
|---|
| 16304 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 16305 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 16306 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x44CCB68ull |
|---|
| 16307 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 16308 | #define DCORE2_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 16309 | #define mmDCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x44CCB80ull |
|---|
| 16310 | #define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 16311 | #define DCORE2_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 |
|---|
| 16312 | #define mmDCORE2_MME_CTRL_HI_SPECIAL_BASE 0x44CCE80ull |
|---|
| 16313 | #define DCORE2_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16314 | #define DCORE2_MME_CTRL_HI_SPECIAL_SECTION 0x1800 |
|---|
| 16315 | #define mmDCORE2_MME_EU_BIST_BASE 0x44CD000ull |
|---|
| 16316 | #define DCORE2_MME_EU_BIST_MAX_OFFSET 0x1000 |
|---|
| 16317 | #define DCORE2_MME_EU_BIST_SECTION 0xE800 |
|---|
| 16318 | #define mmDCORE2_MME_EU_BIST_SPECIAL_BASE 0x44CDE80ull |
|---|
| 16319 | #define DCORE2_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16320 | #define DCORE2_MME_EU_BIST_SPECIAL_SECTION 0x1800 |
|---|
| 16321 | #define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x44CE000ull |
|---|
| 16322 | #define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16323 | #define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16324 | #define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x44CE200ull |
|---|
| 16325 | #define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16326 | #define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16327 | #define mmDCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x44CE400ull |
|---|
| 16328 | #define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16329 | #define DCORE2_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16330 | #define mmDCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x44CE600ull |
|---|
| 16331 | #define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16332 | #define DCORE2_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16333 | #define mmDCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x44CE800ull |
|---|
| 16334 | #define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16335 | #define DCORE2_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16336 | #define mmDCORE2_MME_CTRL_MSTR_IF_AXUSER_BASE 0x44CEA80ull |
|---|
| 16337 | #define DCORE2_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16338 | #define DCORE2_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16339 | #define mmDCORE2_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x44CEB00ull |
|---|
| 16340 | #define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16341 | #define DCORE2_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16342 | #define mmDCORE2_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x44CEB80ull |
|---|
| 16343 | #define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16344 | #define DCORE2_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16345 | #define mmDCORE2_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x44CEC00ull |
|---|
| 16346 | #define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16347 | #define DCORE2_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16348 | #define mmDCORE2_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x44CED80ull |
|---|
| 16349 | #define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16350 | #define DCORE2_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16351 | #define mmDCORE2_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x44CEE80ull |
|---|
| 16352 | #define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16353 | #define DCORE2_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16354 | #define mmDCORE2_MME_QM_ARC_ACP_ENG_BASE 0x44CF000ull |
|---|
| 16355 | #define DCORE2_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 |
|---|
| 16356 | #define DCORE2_MME_QM_ARC_ACP_ENG_SECTION 0xE800 |
|---|
| 16357 | #define mmDCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x44CFE80ull |
|---|
| 16358 | #define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16359 | #define DCORE2_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 16360 | #define mmDCORE2_MME_SBTE0_BASE 0x44D0000ull |
|---|
| 16361 | #define DCORE2_MME_SBTE0_MAX_OFFSET 0x1000 |
|---|
| 16362 | #define DCORE2_MME_SBTE0_SECTION 0xE800 |
|---|
| 16363 | #define mmDCORE2_MME_SBTE0_SPECIAL_BASE 0x44D0E80ull |
|---|
| 16364 | #define DCORE2_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16365 | #define DCORE2_MME_SBTE0_SPECIAL_SECTION 0x1800 |
|---|
| 16366 | #define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x44D1000ull |
|---|
| 16367 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16368 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16369 | #define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x44D1200ull |
|---|
| 16370 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16371 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16372 | #define mmDCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x44D1400ull |
|---|
| 16373 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16374 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16375 | #define mmDCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x44D1600ull |
|---|
| 16376 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16377 | #define DCORE2_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16378 | #define mmDCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x44D1800ull |
|---|
| 16379 | #define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16380 | #define DCORE2_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16381 | #define mmDCORE2_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x44D1A80ull |
|---|
| 16382 | #define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16383 | #define DCORE2_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16384 | #define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x44D1B00ull |
|---|
| 16385 | #define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16386 | #define DCORE2_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16387 | #define mmDCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x44D1B80ull |
|---|
| 16388 | #define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16389 | #define DCORE2_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16390 | #define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x44D1C00ull |
|---|
| 16391 | #define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16392 | #define DCORE2_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16393 | #define mmDCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x44D1D80ull |
|---|
| 16394 | #define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16395 | #define DCORE2_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16396 | #define mmDCORE2_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x44D1E80ull |
|---|
| 16397 | #define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16398 | #define DCORE2_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 16399 | #define mmDCORE2_MME_SBTE1_BASE 0x44D8000ull |
|---|
| 16400 | #define DCORE2_MME_SBTE1_MAX_OFFSET 0x1000 |
|---|
| 16401 | #define DCORE2_MME_SBTE1_SECTION 0xE800 |
|---|
| 16402 | #define mmDCORE2_MME_SBTE1_SPECIAL_BASE 0x44D8E80ull |
|---|
| 16403 | #define DCORE2_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16404 | #define DCORE2_MME_SBTE1_SPECIAL_SECTION 0x1800 |
|---|
| 16405 | #define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x44D9000ull |
|---|
| 16406 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16407 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16408 | #define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x44D9200ull |
|---|
| 16409 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16410 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16411 | #define mmDCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x44D9400ull |
|---|
| 16412 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16413 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16414 | #define mmDCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x44D9600ull |
|---|
| 16415 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16416 | #define DCORE2_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16417 | #define mmDCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x44D9800ull |
|---|
| 16418 | #define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16419 | #define DCORE2_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16420 | #define mmDCORE2_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x44D9A80ull |
|---|
| 16421 | #define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16422 | #define DCORE2_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16423 | #define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x44D9B00ull |
|---|
| 16424 | #define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16425 | #define DCORE2_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16426 | #define mmDCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x44D9B80ull |
|---|
| 16427 | #define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16428 | #define DCORE2_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16429 | #define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x44D9C00ull |
|---|
| 16430 | #define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16431 | #define DCORE2_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16432 | #define mmDCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x44D9D80ull |
|---|
| 16433 | #define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16434 | #define DCORE2_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16435 | #define mmDCORE2_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x44D9E80ull |
|---|
| 16436 | #define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16437 | #define DCORE2_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 16438 | #define mmDCORE2_MME_SBTE2_BASE 0x44E0000ull |
|---|
| 16439 | #define DCORE2_MME_SBTE2_MAX_OFFSET 0x1000 |
|---|
| 16440 | #define DCORE2_MME_SBTE2_SECTION 0xE800 |
|---|
| 16441 | #define mmDCORE2_MME_SBTE2_SPECIAL_BASE 0x44E0E80ull |
|---|
| 16442 | #define DCORE2_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16443 | #define DCORE2_MME_SBTE2_SPECIAL_SECTION 0x1800 |
|---|
| 16444 | #define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x44E1000ull |
|---|
| 16445 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16446 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16447 | #define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x44E1200ull |
|---|
| 16448 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16449 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16450 | #define mmDCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x44E1400ull |
|---|
| 16451 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16452 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16453 | #define mmDCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x44E1600ull |
|---|
| 16454 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16455 | #define DCORE2_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16456 | #define mmDCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x44E1800ull |
|---|
| 16457 | #define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16458 | #define DCORE2_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16459 | #define mmDCORE2_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x44E1A80ull |
|---|
| 16460 | #define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16461 | #define DCORE2_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16462 | #define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x44E1B00ull |
|---|
| 16463 | #define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16464 | #define DCORE2_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16465 | #define mmDCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x44E1B80ull |
|---|
| 16466 | #define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16467 | #define DCORE2_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16468 | #define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x44E1C00ull |
|---|
| 16469 | #define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16470 | #define DCORE2_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16471 | #define mmDCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x44E1D80ull |
|---|
| 16472 | #define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16473 | #define DCORE2_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16474 | #define mmDCORE2_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x44E1E80ull |
|---|
| 16475 | #define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16476 | #define DCORE2_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 16477 | #define mmDCORE2_MME_SBTE3_BASE 0x44E8000ull |
|---|
| 16478 | #define DCORE2_MME_SBTE3_MAX_OFFSET 0x1000 |
|---|
| 16479 | #define DCORE2_MME_SBTE3_SECTION 0xE800 |
|---|
| 16480 | #define mmDCORE2_MME_SBTE3_SPECIAL_BASE 0x44E8E80ull |
|---|
| 16481 | #define DCORE2_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16482 | #define DCORE2_MME_SBTE3_SPECIAL_SECTION 0x1800 |
|---|
| 16483 | #define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x44E9000ull |
|---|
| 16484 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16485 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16486 | #define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x44E9200ull |
|---|
| 16487 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16488 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16489 | #define mmDCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x44E9400ull |
|---|
| 16490 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16491 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16492 | #define mmDCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x44E9600ull |
|---|
| 16493 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16494 | #define DCORE2_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16495 | #define mmDCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x44E9800ull |
|---|
| 16496 | #define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16497 | #define DCORE2_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16498 | #define mmDCORE2_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x44E9A80ull |
|---|
| 16499 | #define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16500 | #define DCORE2_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16501 | #define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x44E9B00ull |
|---|
| 16502 | #define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16503 | #define DCORE2_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16504 | #define mmDCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x44E9B80ull |
|---|
| 16505 | #define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16506 | #define DCORE2_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16507 | #define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x44E9C00ull |
|---|
| 16508 | #define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16509 | #define DCORE2_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16510 | #define mmDCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x44E9D80ull |
|---|
| 16511 | #define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16512 | #define DCORE2_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16513 | #define mmDCORE2_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x44E9E80ull |
|---|
| 16514 | #define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16515 | #define DCORE2_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 16516 | #define mmDCORE2_MME_SBTE4_BASE 0x44F0000ull |
|---|
| 16517 | #define DCORE2_MME_SBTE4_MAX_OFFSET 0x1000 |
|---|
| 16518 | #define DCORE2_MME_SBTE4_SECTION 0xE800 |
|---|
| 16519 | #define mmDCORE2_MME_SBTE4_SPECIAL_BASE 0x44F0E80ull |
|---|
| 16520 | #define DCORE2_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16521 | #define DCORE2_MME_SBTE4_SPECIAL_SECTION 0x1800 |
|---|
| 16522 | #define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x44F1000ull |
|---|
| 16523 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16524 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16525 | #define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x44F1200ull |
|---|
| 16526 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16527 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16528 | #define mmDCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x44F1400ull |
|---|
| 16529 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16530 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16531 | #define mmDCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x44F1600ull |
|---|
| 16532 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16533 | #define DCORE2_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16534 | #define mmDCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x44F1800ull |
|---|
| 16535 | #define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16536 | #define DCORE2_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16537 | #define mmDCORE2_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x44F1A80ull |
|---|
| 16538 | #define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16539 | #define DCORE2_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16540 | #define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x44F1B00ull |
|---|
| 16541 | #define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16542 | #define DCORE2_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16543 | #define mmDCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x44F1B80ull |
|---|
| 16544 | #define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16545 | #define DCORE2_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16546 | #define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x44F1C00ull |
|---|
| 16547 | #define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16548 | #define DCORE2_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16549 | #define mmDCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x44F1D80ull |
|---|
| 16550 | #define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16551 | #define DCORE2_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16552 | #define mmDCORE2_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x44F1E80ull |
|---|
| 16553 | #define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16554 | #define DCORE2_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 16555 | #define mmDCORE2_MME_ACC_BASE 0x44F8000ull |
|---|
| 16556 | #define DCORE2_MME_ACC_MAX_OFFSET 0x1000 |
|---|
| 16557 | #define DCORE2_MME_ACC_SECTION 0xE800 |
|---|
| 16558 | #define mmDCORE2_MME_ACC_SPECIAL_BASE 0x44F8E80ull |
|---|
| 16559 | #define DCORE2_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16560 | #define DCORE2_MME_ACC_SPECIAL_SECTION 0x1800 |
|---|
| 16561 | #define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x44F9000ull |
|---|
| 16562 | #define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16563 | #define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16564 | #define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x44F9200ull |
|---|
| 16565 | #define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16566 | #define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16567 | #define mmDCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x44F9400ull |
|---|
| 16568 | #define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16569 | #define DCORE2_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16570 | #define mmDCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x44F9600ull |
|---|
| 16571 | #define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16572 | #define DCORE2_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16573 | #define mmDCORE2_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x44F9800ull |
|---|
| 16574 | #define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16575 | #define DCORE2_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16576 | #define mmDCORE2_MME_WB0_MSTR_IF_AXUSER_BASE 0x44F9A80ull |
|---|
| 16577 | #define DCORE2_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16578 | #define DCORE2_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16579 | #define mmDCORE2_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x44F9B00ull |
|---|
| 16580 | #define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16581 | #define DCORE2_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16582 | #define mmDCORE2_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x44F9B80ull |
|---|
| 16583 | #define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16584 | #define DCORE2_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16585 | #define mmDCORE2_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x44F9C00ull |
|---|
| 16586 | #define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16587 | #define DCORE2_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16588 | #define mmDCORE2_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x44F9D80ull |
|---|
| 16589 | #define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16590 | #define DCORE2_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16591 | #define mmDCORE2_MME_WB0_MSTR_IF_SPECIAL_BASE 0x44F9E80ull |
|---|
| 16592 | #define DCORE2_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16593 | #define DCORE2_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16594 | #define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x44FA000ull |
|---|
| 16595 | #define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16596 | #define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16597 | #define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x44FA200ull |
|---|
| 16598 | #define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16599 | #define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16600 | #define mmDCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x44FA400ull |
|---|
| 16601 | #define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16602 | #define DCORE2_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16603 | #define mmDCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x44FA600ull |
|---|
| 16604 | #define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16605 | #define DCORE2_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16606 | #define mmDCORE2_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x44FA800ull |
|---|
| 16607 | #define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16608 | #define DCORE2_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16609 | #define mmDCORE2_MME_WB1_MSTR_IF_AXUSER_BASE 0x44FAA80ull |
|---|
| 16610 | #define DCORE2_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16611 | #define DCORE2_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16612 | #define mmDCORE2_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x44FAB00ull |
|---|
| 16613 | #define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16614 | #define DCORE2_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16615 | #define mmDCORE2_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x44FAB80ull |
|---|
| 16616 | #define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16617 | #define DCORE2_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16618 | #define mmDCORE2_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x44FAC00ull |
|---|
| 16619 | #define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16620 | #define DCORE2_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16621 | #define mmDCORE2_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x44FAD80ull |
|---|
| 16622 | #define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16623 | #define DCORE2_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16624 | #define mmDCORE2_MME_WB1_MSTR_IF_SPECIAL_BASE 0x44FAE80ull |
|---|
| 16625 | #define DCORE2_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16626 | #define DCORE2_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 |
|---|
| 16627 | #define mmDCORE2_SYNC_MNGR_OBJS_BASE 0x4500000ull |
|---|
| 16628 | #define DCORE2_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 |
|---|
| 16629 | #define DCORE2_SYNC_MNGR_OBJS_SECTION 0x1E000 |
|---|
| 16630 | #define mmDCORE2_SYNC_MNGR_GLBL_BASE 0x451E000ull |
|---|
| 16631 | #define DCORE2_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 |
|---|
| 16632 | #define DCORE2_SYNC_MNGR_GLBL_SECTION 0xE800 |
|---|
| 16633 | #define mmDCORE2_SYNC_MNGR_GLBL_SPECIAL_BASE 0x451EE80ull |
|---|
| 16634 | #define DCORE2_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16635 | #define DCORE2_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 |
|---|
| 16636 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x451F000ull |
|---|
| 16637 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16638 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16639 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x451F200ull |
|---|
| 16640 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16641 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16642 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x451F400ull |
|---|
| 16643 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16644 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16645 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x451F600ull |
|---|
| 16646 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16647 | #define DCORE2_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16648 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x451F800ull |
|---|
| 16649 | #define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16650 | #define DCORE2_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16651 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x451FA80ull |
|---|
| 16652 | #define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16653 | #define DCORE2_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16654 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x451FB00ull |
|---|
| 16655 | #define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16656 | #define DCORE2_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16657 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x451FB80ull |
|---|
| 16658 | #define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16659 | #define DCORE2_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16660 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x451FC00ull |
|---|
| 16661 | #define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16662 | #define DCORE2_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16663 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x451FD80ull |
|---|
| 16664 | #define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16665 | #define DCORE2_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16666 | #define mmDCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x451FE80ull |
|---|
| 16667 | #define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16668 | #define DCORE2_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16669 | #define mmDCORE2_HIF0_BASE 0x4520000ull |
|---|
| 16670 | #define DCORE2_HIF0_MAX_OFFSET 0x1000 |
|---|
| 16671 | #define DCORE2_HIF0_SECTION 0xE800 |
|---|
| 16672 | #define mmDCORE2_HIF0_SPECIAL_BASE 0x4520E80ull |
|---|
| 16673 | #define DCORE2_HIF0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16674 | #define DCORE2_HIF0_SPECIAL_SECTION 0x3180 |
|---|
| 16675 | #define mmDCORE2_HIF1_BASE 0x4524000ull |
|---|
| 16676 | #define DCORE2_HIF1_MAX_OFFSET 0x1000 |
|---|
| 16677 | #define DCORE2_HIF1_SECTION 0xE800 |
|---|
| 16678 | #define mmDCORE2_HIF1_SPECIAL_BASE 0x4524E80ull |
|---|
| 16679 | #define DCORE2_HIF1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16680 | #define DCORE2_HIF1_SPECIAL_SECTION 0x3180 |
|---|
| 16681 | #define mmDCORE2_HIF2_BASE 0x4528000ull |
|---|
| 16682 | #define DCORE2_HIF2_MAX_OFFSET 0x1000 |
|---|
| 16683 | #define DCORE2_HIF2_SECTION 0xE800 |
|---|
| 16684 | #define mmDCORE2_HIF2_SPECIAL_BASE 0x4528E80ull |
|---|
| 16685 | #define DCORE2_HIF2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16686 | #define DCORE2_HIF2_SPECIAL_SECTION 0x3180 |
|---|
| 16687 | #define mmDCORE2_HIF3_BASE 0x452C000ull |
|---|
| 16688 | #define DCORE2_HIF3_MAX_OFFSET 0x1000 |
|---|
| 16689 | #define DCORE2_HIF3_SECTION 0xE800 |
|---|
| 16690 | #define mmDCORE2_HIF3_SPECIAL_BASE 0x452CE80ull |
|---|
| 16691 | #define DCORE2_HIF3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16692 | #define DCORE2_HIF3_SPECIAL_SECTION 0x13180 |
|---|
| 16693 | #define mmDCORE2_RTR0_CTRL_BASE 0x4540000ull |
|---|
| 16694 | #define DCORE2_RTR0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 16695 | #define DCORE2_RTR0_CTRL_SECTION 0xE800 |
|---|
| 16696 | #define mmDCORE2_RTR0_CTRL_SPECIAL_BASE 0x4540E80ull |
|---|
| 16697 | #define DCORE2_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16698 | #define DCORE2_RTR0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 16699 | #define mmDCORE2_RTR0_H3_BASE 0x4541000ull |
|---|
| 16700 | #define DCORE2_RTR0_H3_MAX_OFFSET 0x1000 |
|---|
| 16701 | #define DCORE2_RTR0_H3_SECTION 0xE800 |
|---|
| 16702 | #define mmDCORE2_RTR0_H3_SPECIAL_BASE 0x4541E80ull |
|---|
| 16703 | #define DCORE2_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16704 | #define DCORE2_RTR0_H3_SPECIAL_SECTION 0x1800 |
|---|
| 16705 | #define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4542000ull |
|---|
| 16706 | #define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16707 | #define DCORE2_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16708 | #define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4542200ull |
|---|
| 16709 | #define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16710 | #define DCORE2_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16711 | #define mmDCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4542400ull |
|---|
| 16712 | #define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16713 | #define DCORE2_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16714 | #define mmDCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4542600ull |
|---|
| 16715 | #define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16716 | #define DCORE2_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16717 | #define mmDCORE2_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4542800ull |
|---|
| 16718 | #define DCORE2_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16719 | #define DCORE2_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16720 | #define mmDCORE2_RTR0_MSTR_IF_AXUSER_BASE 0x4542A80ull |
|---|
| 16721 | #define DCORE2_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16722 | #define DCORE2_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16723 | #define mmDCORE2_RTR0_MSTR_IF_DBG_HBW_BASE 0x4542B00ull |
|---|
| 16724 | #define DCORE2_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16725 | #define DCORE2_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16726 | #define mmDCORE2_RTR0_MSTR_IF_DBG_LBW_BASE 0x4542B80ull |
|---|
| 16727 | #define DCORE2_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16728 | #define DCORE2_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16729 | #define mmDCORE2_RTR0_MSTR_IF_CORE_HBW_BASE 0x4542C00ull |
|---|
| 16730 | #define DCORE2_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16731 | #define DCORE2_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16732 | #define mmDCORE2_RTR0_MSTR_IF_CORE_LBW_BASE 0x4542D80ull |
|---|
| 16733 | #define DCORE2_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16734 | #define DCORE2_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16735 | #define mmDCORE2_RTR0_MSTR_IF_SPECIAL_BASE 0x4542E80ull |
|---|
| 16736 | #define DCORE2_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16737 | #define DCORE2_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16738 | #define mmDCORE2_RTR0_ADD_DEC_HBW_BASE 0x4543000ull |
|---|
| 16739 | #define DCORE2_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 16740 | #define DCORE2_RTR0_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 16741 | #define mmDCORE2_RTR0_ADD_DEC_LBW_BASE 0x4543400ull |
|---|
| 16742 | #define DCORE2_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 16743 | #define DCORE2_RTR0_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 16744 | #define mmDCORE2_RTR0_ADD_DEC_SPECIAL_BASE 0x4543E80ull |
|---|
| 16745 | #define DCORE2_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16746 | #define DCORE2_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 16747 | #define mmDCORE2_RTR0_BASE 0x4544000ull |
|---|
| 16748 | #define DCORE2_RTR0_MAX_OFFSET 0x1000 |
|---|
| 16749 | #define DCORE2_RTR0_SECTION 0x3000 |
|---|
| 16750 | #define mmDCORE2_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4544300ull |
|---|
| 16751 | #define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16752 | #define DCORE2_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16753 | #define mmDCORE2_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4544340ull |
|---|
| 16754 | #define DCORE2_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16755 | #define DCORE2_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16756 | #define mmDCORE2_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4544380ull |
|---|
| 16757 | #define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16758 | #define DCORE2_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16759 | #define mmDCORE2_RTR0_HBW_WR_RS_LL_STAT_BASE 0x45443C0ull |
|---|
| 16760 | #define DCORE2_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16761 | #define DCORE2_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16762 | #define mmDCORE2_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4544400ull |
|---|
| 16763 | #define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16764 | #define DCORE2_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16765 | #define mmDCORE2_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4544440ull |
|---|
| 16766 | #define DCORE2_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16767 | #define DCORE2_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16768 | #define mmDCORE2_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4544480ull |
|---|
| 16769 | #define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16770 | #define DCORE2_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16771 | #define mmDCORE2_RTR0_LBW_WR_RS_LL_STAT_BASE 0x45444C0ull |
|---|
| 16772 | #define DCORE2_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16773 | #define DCORE2_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16774 | #define mmDCORE2_RTR0_HBW_MFIFO_BASE 0x4544500ull |
|---|
| 16775 | #define DCORE2_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 16776 | #define DCORE2_RTR0_HBW_MFIFO_SECTION 0x4000 |
|---|
| 16777 | #define mmDCORE2_RTR0_E2E_RD_LL_STAT_BASE 0x4544540ull |
|---|
| 16778 | #define DCORE2_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16779 | #define DCORE2_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 16780 | #define mmDCORE2_RTR0_E2E_WR_LL_STAT_BASE 0x4544580ull |
|---|
| 16781 | #define DCORE2_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16782 | #define DCORE2_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 16783 | #define mmDCORE2_RTR0_RTR_HBW_XACT_STAT_BASE 0x4544600ull |
|---|
| 16784 | #define DCORE2_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16785 | #define DCORE2_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 16786 | #define mmDCORE2_RTR0_RTR_LBW_XACT_STAT_BASE 0x4544680ull |
|---|
| 16787 | #define DCORE2_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16788 | #define DCORE2_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 16789 | #define mmDCORE2_RTR0_RTR_E2E_XACT_STAT_BASE 0x4544700ull |
|---|
| 16790 | #define DCORE2_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16791 | #define DCORE2_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 16792 | #define mmDCORE2_RTR0_SPECIAL_BASE 0x4544E80ull |
|---|
| 16793 | #define DCORE2_RTR0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16794 | #define DCORE2_RTR0_SPECIAL_SECTION 0x1800 |
|---|
| 16795 | #define mmDCORE2_RTR0_DBG_ADDR_BASE 0x4545000ull |
|---|
| 16796 | #define DCORE2_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 16797 | #define DCORE2_RTR0_DBG_ADDR_SECTION 0xE800 |
|---|
| 16798 | #define mmDCORE2_RTR0_DBG_ADDR_SPECIAL_BASE 0x4545E80ull |
|---|
| 16799 | #define DCORE2_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16800 | #define DCORE2_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 16801 | #define mmDCORE2_RTR1_CTRL_BASE 0x4548000ull |
|---|
| 16802 | #define DCORE2_RTR1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 16803 | #define DCORE2_RTR1_CTRL_SECTION 0xE800 |
|---|
| 16804 | #define mmDCORE2_RTR1_CTRL_SPECIAL_BASE 0x4548E80ull |
|---|
| 16805 | #define DCORE2_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16806 | #define DCORE2_RTR1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 16807 | #define mmDCORE2_RTR1_H3_BASE 0x4549000ull |
|---|
| 16808 | #define DCORE2_RTR1_H3_MAX_OFFSET 0x1000 |
|---|
| 16809 | #define DCORE2_RTR1_H3_SECTION 0xE800 |
|---|
| 16810 | #define mmDCORE2_RTR1_H3_SPECIAL_BASE 0x4549E80ull |
|---|
| 16811 | #define DCORE2_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16812 | #define DCORE2_RTR1_H3_SPECIAL_SECTION 0x1800 |
|---|
| 16813 | #define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x454A000ull |
|---|
| 16814 | #define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16815 | #define DCORE2_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16816 | #define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x454A200ull |
|---|
| 16817 | #define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16818 | #define DCORE2_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16819 | #define mmDCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x454A400ull |
|---|
| 16820 | #define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16821 | #define DCORE2_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16822 | #define mmDCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x454A600ull |
|---|
| 16823 | #define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16824 | #define DCORE2_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16825 | #define mmDCORE2_RTR1_MSTR_IF_E2E_CRDT_BASE 0x454A800ull |
|---|
| 16826 | #define DCORE2_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16827 | #define DCORE2_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16828 | #define mmDCORE2_RTR1_MSTR_IF_AXUSER_BASE 0x454AA80ull |
|---|
| 16829 | #define DCORE2_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16830 | #define DCORE2_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16831 | #define mmDCORE2_RTR1_MSTR_IF_DBG_HBW_BASE 0x454AB00ull |
|---|
| 16832 | #define DCORE2_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16833 | #define DCORE2_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16834 | #define mmDCORE2_RTR1_MSTR_IF_DBG_LBW_BASE 0x454AB80ull |
|---|
| 16835 | #define DCORE2_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16836 | #define DCORE2_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16837 | #define mmDCORE2_RTR1_MSTR_IF_CORE_HBW_BASE 0x454AC00ull |
|---|
| 16838 | #define DCORE2_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16839 | #define DCORE2_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16840 | #define mmDCORE2_RTR1_MSTR_IF_CORE_LBW_BASE 0x454AD80ull |
|---|
| 16841 | #define DCORE2_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16842 | #define DCORE2_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16843 | #define mmDCORE2_RTR1_MSTR_IF_SPECIAL_BASE 0x454AE80ull |
|---|
| 16844 | #define DCORE2_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16845 | #define DCORE2_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16846 | #define mmDCORE2_RTR1_ADD_DEC_HBW_BASE 0x454B000ull |
|---|
| 16847 | #define DCORE2_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 16848 | #define DCORE2_RTR1_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 16849 | #define mmDCORE2_RTR1_ADD_DEC_LBW_BASE 0x454B400ull |
|---|
| 16850 | #define DCORE2_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 16851 | #define DCORE2_RTR1_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 16852 | #define mmDCORE2_RTR1_ADD_DEC_SPECIAL_BASE 0x454BE80ull |
|---|
| 16853 | #define DCORE2_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16854 | #define DCORE2_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 16855 | #define mmDCORE2_RTR1_BASE 0x454C000ull |
|---|
| 16856 | #define DCORE2_RTR1_MAX_OFFSET 0x1000 |
|---|
| 16857 | #define DCORE2_RTR1_SECTION 0x3000 |
|---|
| 16858 | #define mmDCORE2_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x454C300ull |
|---|
| 16859 | #define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16860 | #define DCORE2_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16861 | #define mmDCORE2_RTR1_HBW_RD_RS_LL_STAT_BASE 0x454C340ull |
|---|
| 16862 | #define DCORE2_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16863 | #define DCORE2_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16864 | #define mmDCORE2_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x454C380ull |
|---|
| 16865 | #define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16866 | #define DCORE2_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16867 | #define mmDCORE2_RTR1_HBW_WR_RS_LL_STAT_BASE 0x454C3C0ull |
|---|
| 16868 | #define DCORE2_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16869 | #define DCORE2_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16870 | #define mmDCORE2_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x454C400ull |
|---|
| 16871 | #define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16872 | #define DCORE2_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16873 | #define mmDCORE2_RTR1_LBW_RD_RS_LL_STAT_BASE 0x454C440ull |
|---|
| 16874 | #define DCORE2_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16875 | #define DCORE2_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16876 | #define mmDCORE2_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x454C480ull |
|---|
| 16877 | #define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16878 | #define DCORE2_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16879 | #define mmDCORE2_RTR1_LBW_WR_RS_LL_STAT_BASE 0x454C4C0ull |
|---|
| 16880 | #define DCORE2_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16881 | #define DCORE2_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16882 | #define mmDCORE2_RTR1_HBW_MFIFO_BASE 0x454C500ull |
|---|
| 16883 | #define DCORE2_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 16884 | #define DCORE2_RTR1_HBW_MFIFO_SECTION 0x4000 |
|---|
| 16885 | #define mmDCORE2_RTR1_E2E_RD_LL_STAT_BASE 0x454C540ull |
|---|
| 16886 | #define DCORE2_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16887 | #define DCORE2_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 16888 | #define mmDCORE2_RTR1_E2E_WR_LL_STAT_BASE 0x454C580ull |
|---|
| 16889 | #define DCORE2_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16890 | #define DCORE2_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 16891 | #define mmDCORE2_RTR1_RTR_HBW_XACT_STAT_BASE 0x454C600ull |
|---|
| 16892 | #define DCORE2_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16893 | #define DCORE2_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 16894 | #define mmDCORE2_RTR1_RTR_LBW_XACT_STAT_BASE 0x454C680ull |
|---|
| 16895 | #define DCORE2_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16896 | #define DCORE2_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 16897 | #define mmDCORE2_RTR1_RTR_E2E_XACT_STAT_BASE 0x454C700ull |
|---|
| 16898 | #define DCORE2_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 16899 | #define DCORE2_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 16900 | #define mmDCORE2_RTR1_SPECIAL_BASE 0x454CE80ull |
|---|
| 16901 | #define DCORE2_RTR1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16902 | #define DCORE2_RTR1_SPECIAL_SECTION 0x1800 |
|---|
| 16903 | #define mmDCORE2_RTR1_DBG_ADDR_BASE 0x454D000ull |
|---|
| 16904 | #define DCORE2_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 16905 | #define DCORE2_RTR1_DBG_ADDR_SECTION 0xE800 |
|---|
| 16906 | #define mmDCORE2_RTR1_DBG_ADDR_SPECIAL_BASE 0x454DE80ull |
|---|
| 16907 | #define DCORE2_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16908 | #define DCORE2_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 16909 | #define mmDCORE2_RTR2_CTRL_BASE 0x4550000ull |
|---|
| 16910 | #define DCORE2_RTR2_CTRL_MAX_OFFSET 0x1000 |
|---|
| 16911 | #define DCORE2_RTR2_CTRL_SECTION 0xE800 |
|---|
| 16912 | #define mmDCORE2_RTR2_CTRL_SPECIAL_BASE 0x4550E80ull |
|---|
| 16913 | #define DCORE2_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16914 | #define DCORE2_RTR2_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 16915 | #define mmDCORE2_RTR2_H3_BASE 0x4551000ull |
|---|
| 16916 | #define DCORE2_RTR2_H3_MAX_OFFSET 0x1000 |
|---|
| 16917 | #define DCORE2_RTR2_H3_SECTION 0xE800 |
|---|
| 16918 | #define mmDCORE2_RTR2_H3_SPECIAL_BASE 0x4551E80ull |
|---|
| 16919 | #define DCORE2_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16920 | #define DCORE2_RTR2_H3_SPECIAL_SECTION 0x1800 |
|---|
| 16921 | #define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4552000ull |
|---|
| 16922 | #define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16923 | #define DCORE2_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 16924 | #define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4552200ull |
|---|
| 16925 | #define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 16926 | #define DCORE2_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 16927 | #define mmDCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4552400ull |
|---|
| 16928 | #define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16929 | #define DCORE2_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 16930 | #define mmDCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4552600ull |
|---|
| 16931 | #define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 16932 | #define DCORE2_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 16933 | #define mmDCORE2_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4552800ull |
|---|
| 16934 | #define DCORE2_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 16935 | #define DCORE2_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 16936 | #define mmDCORE2_RTR2_MSTR_IF_AXUSER_BASE 0x4552A80ull |
|---|
| 16937 | #define DCORE2_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 16938 | #define DCORE2_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 16939 | #define mmDCORE2_RTR2_MSTR_IF_DBG_HBW_BASE 0x4552B00ull |
|---|
| 16940 | #define DCORE2_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 16941 | #define DCORE2_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 16942 | #define mmDCORE2_RTR2_MSTR_IF_DBG_LBW_BASE 0x4552B80ull |
|---|
| 16943 | #define DCORE2_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 16944 | #define DCORE2_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 16945 | #define mmDCORE2_RTR2_MSTR_IF_CORE_HBW_BASE 0x4552C00ull |
|---|
| 16946 | #define DCORE2_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 16947 | #define DCORE2_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 16948 | #define mmDCORE2_RTR2_MSTR_IF_CORE_LBW_BASE 0x4552D80ull |
|---|
| 16949 | #define DCORE2_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 16950 | #define DCORE2_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 16951 | #define mmDCORE2_RTR2_MSTR_IF_SPECIAL_BASE 0x4552E80ull |
|---|
| 16952 | #define DCORE2_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16953 | #define DCORE2_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 16954 | #define mmDCORE2_RTR2_ADD_DEC_HBW_BASE 0x4553000ull |
|---|
| 16955 | #define DCORE2_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 16956 | #define DCORE2_RTR2_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 16957 | #define mmDCORE2_RTR2_ADD_DEC_LBW_BASE 0x4553400ull |
|---|
| 16958 | #define DCORE2_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 16959 | #define DCORE2_RTR2_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 16960 | #define mmDCORE2_RTR2_ADD_DEC_SPECIAL_BASE 0x4553E80ull |
|---|
| 16961 | #define DCORE2_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 16962 | #define DCORE2_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 16963 | #define mmDCORE2_RTR2_BASE 0x4554000ull |
|---|
| 16964 | #define DCORE2_RTR2_MAX_OFFSET 0x1000 |
|---|
| 16965 | #define DCORE2_RTR2_SECTION 0x3000 |
|---|
| 16966 | #define mmDCORE2_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4554300ull |
|---|
| 16967 | #define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16968 | #define DCORE2_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16969 | #define mmDCORE2_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4554340ull |
|---|
| 16970 | #define DCORE2_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16971 | #define DCORE2_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16972 | #define mmDCORE2_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4554380ull |
|---|
| 16973 | #define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16974 | #define DCORE2_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16975 | #define mmDCORE2_RTR2_HBW_WR_RS_LL_STAT_BASE 0x45543C0ull |
|---|
| 16976 | #define DCORE2_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16977 | #define DCORE2_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16978 | #define mmDCORE2_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4554400ull |
|---|
| 16979 | #define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16980 | #define DCORE2_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16981 | #define mmDCORE2_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4554440ull |
|---|
| 16982 | #define DCORE2_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16983 | #define DCORE2_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16984 | #define mmDCORE2_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4554480ull |
|---|
| 16985 | #define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16986 | #define DCORE2_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 16987 | #define mmDCORE2_RTR2_LBW_WR_RS_LL_STAT_BASE 0x45544C0ull |
|---|
| 16988 | #define DCORE2_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16989 | #define DCORE2_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 16990 | #define mmDCORE2_RTR2_HBW_MFIFO_BASE 0x4554500ull |
|---|
| 16991 | #define DCORE2_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 16992 | #define DCORE2_RTR2_HBW_MFIFO_SECTION 0x4000 |
|---|
| 16993 | #define mmDCORE2_RTR2_E2E_RD_LL_STAT_BASE 0x4554540ull |
|---|
| 16994 | #define DCORE2_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16995 | #define DCORE2_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 16996 | #define mmDCORE2_RTR2_E2E_WR_LL_STAT_BASE 0x4554580ull |
|---|
| 16997 | #define DCORE2_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 16998 | #define DCORE2_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 16999 | #define mmDCORE2_RTR2_RTR_HBW_XACT_STAT_BASE 0x4554600ull |
|---|
| 17000 | #define DCORE2_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17001 | #define DCORE2_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17002 | #define mmDCORE2_RTR2_RTR_LBW_XACT_STAT_BASE 0x4554680ull |
|---|
| 17003 | #define DCORE2_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17004 | #define DCORE2_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17005 | #define mmDCORE2_RTR2_RTR_E2E_XACT_STAT_BASE 0x4554700ull |
|---|
| 17006 | #define DCORE2_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17007 | #define DCORE2_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17008 | #define mmDCORE2_RTR2_SPECIAL_BASE 0x4554E80ull |
|---|
| 17009 | #define DCORE2_RTR2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17010 | #define DCORE2_RTR2_SPECIAL_SECTION 0x1800 |
|---|
| 17011 | #define mmDCORE2_RTR2_DBG_ADDR_BASE 0x4555000ull |
|---|
| 17012 | #define DCORE2_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17013 | #define DCORE2_RTR2_DBG_ADDR_SECTION 0xE800 |
|---|
| 17014 | #define mmDCORE2_RTR2_DBG_ADDR_SPECIAL_BASE 0x4555E80ull |
|---|
| 17015 | #define DCORE2_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17016 | #define DCORE2_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17017 | #define mmDCORE2_RTR3_CTRL_BASE 0x4558000ull |
|---|
| 17018 | #define DCORE2_RTR3_CTRL_MAX_OFFSET 0x1000 |
|---|
| 17019 | #define DCORE2_RTR3_CTRL_SECTION 0xE800 |
|---|
| 17020 | #define mmDCORE2_RTR3_CTRL_SPECIAL_BASE 0x4558E80ull |
|---|
| 17021 | #define DCORE2_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17022 | #define DCORE2_RTR3_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 17023 | #define mmDCORE2_RTR3_H3_BASE 0x4559000ull |
|---|
| 17024 | #define DCORE2_RTR3_H3_MAX_OFFSET 0x1000 |
|---|
| 17025 | #define DCORE2_RTR3_H3_SECTION 0xE800 |
|---|
| 17026 | #define mmDCORE2_RTR3_H3_SPECIAL_BASE 0x4559E80ull |
|---|
| 17027 | #define DCORE2_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17028 | #define DCORE2_RTR3_H3_SPECIAL_SECTION 0x1800 |
|---|
| 17029 | #define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x455A000ull |
|---|
| 17030 | #define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17031 | #define DCORE2_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 17032 | #define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x455A200ull |
|---|
| 17033 | #define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17034 | #define DCORE2_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 17035 | #define mmDCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x455A400ull |
|---|
| 17036 | #define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17037 | #define DCORE2_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 17038 | #define mmDCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x455A600ull |
|---|
| 17039 | #define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17040 | #define DCORE2_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 17041 | #define mmDCORE2_RTR3_MSTR_IF_E2E_CRDT_BASE 0x455A800ull |
|---|
| 17042 | #define DCORE2_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 17043 | #define DCORE2_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 17044 | #define mmDCORE2_RTR3_MSTR_IF_AXUSER_BASE 0x455AA80ull |
|---|
| 17045 | #define DCORE2_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 17046 | #define DCORE2_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 17047 | #define mmDCORE2_RTR3_MSTR_IF_DBG_HBW_BASE 0x455AB00ull |
|---|
| 17048 | #define DCORE2_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 17049 | #define DCORE2_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 17050 | #define mmDCORE2_RTR3_MSTR_IF_DBG_LBW_BASE 0x455AB80ull |
|---|
| 17051 | #define DCORE2_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 17052 | #define DCORE2_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 17053 | #define mmDCORE2_RTR3_MSTR_IF_CORE_HBW_BASE 0x455AC00ull |
|---|
| 17054 | #define DCORE2_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 17055 | #define DCORE2_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 17056 | #define mmDCORE2_RTR3_MSTR_IF_CORE_LBW_BASE 0x455AD80ull |
|---|
| 17057 | #define DCORE2_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 17058 | #define DCORE2_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 17059 | #define mmDCORE2_RTR3_MSTR_IF_SPECIAL_BASE 0x455AE80ull |
|---|
| 17060 | #define DCORE2_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17061 | #define DCORE2_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 17062 | #define mmDCORE2_RTR3_ADD_DEC_HBW_BASE 0x455B000ull |
|---|
| 17063 | #define DCORE2_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 17064 | #define DCORE2_RTR3_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 17065 | #define mmDCORE2_RTR3_ADD_DEC_LBW_BASE 0x455B400ull |
|---|
| 17066 | #define DCORE2_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 17067 | #define DCORE2_RTR3_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 17068 | #define mmDCORE2_RTR3_ADD_DEC_SPECIAL_BASE 0x455BE80ull |
|---|
| 17069 | #define DCORE2_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17070 | #define DCORE2_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 17071 | #define mmDCORE2_RTR3_BASE 0x455C000ull |
|---|
| 17072 | #define DCORE2_RTR3_MAX_OFFSET 0x1000 |
|---|
| 17073 | #define DCORE2_RTR3_SECTION 0x3000 |
|---|
| 17074 | #define mmDCORE2_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x455C300ull |
|---|
| 17075 | #define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17076 | #define DCORE2_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17077 | #define mmDCORE2_RTR3_HBW_RD_RS_LL_STAT_BASE 0x455C340ull |
|---|
| 17078 | #define DCORE2_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17079 | #define DCORE2_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17080 | #define mmDCORE2_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x455C380ull |
|---|
| 17081 | #define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17082 | #define DCORE2_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17083 | #define mmDCORE2_RTR3_HBW_WR_RS_LL_STAT_BASE 0x455C3C0ull |
|---|
| 17084 | #define DCORE2_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17085 | #define DCORE2_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17086 | #define mmDCORE2_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x455C400ull |
|---|
| 17087 | #define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17088 | #define DCORE2_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17089 | #define mmDCORE2_RTR3_LBW_RD_RS_LL_STAT_BASE 0x455C440ull |
|---|
| 17090 | #define DCORE2_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17091 | #define DCORE2_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17092 | #define mmDCORE2_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x455C480ull |
|---|
| 17093 | #define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17094 | #define DCORE2_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17095 | #define mmDCORE2_RTR3_LBW_WR_RS_LL_STAT_BASE 0x455C4C0ull |
|---|
| 17096 | #define DCORE2_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17097 | #define DCORE2_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17098 | #define mmDCORE2_RTR3_HBW_MFIFO_BASE 0x455C500ull |
|---|
| 17099 | #define DCORE2_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 17100 | #define DCORE2_RTR3_HBW_MFIFO_SECTION 0x4000 |
|---|
| 17101 | #define mmDCORE2_RTR3_E2E_RD_LL_STAT_BASE 0x455C540ull |
|---|
| 17102 | #define DCORE2_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17103 | #define DCORE2_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 17104 | #define mmDCORE2_RTR3_E2E_WR_LL_STAT_BASE 0x455C580ull |
|---|
| 17105 | #define DCORE2_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17106 | #define DCORE2_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 17107 | #define mmDCORE2_RTR3_RTR_HBW_XACT_STAT_BASE 0x455C600ull |
|---|
| 17108 | #define DCORE2_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17109 | #define DCORE2_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17110 | #define mmDCORE2_RTR3_RTR_LBW_XACT_STAT_BASE 0x455C680ull |
|---|
| 17111 | #define DCORE2_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17112 | #define DCORE2_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17113 | #define mmDCORE2_RTR3_RTR_E2E_XACT_STAT_BASE 0x455C700ull |
|---|
| 17114 | #define DCORE2_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17115 | #define DCORE2_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17116 | #define mmDCORE2_RTR3_SPECIAL_BASE 0x455CE80ull |
|---|
| 17117 | #define DCORE2_RTR3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17118 | #define DCORE2_RTR3_SPECIAL_SECTION 0x1800 |
|---|
| 17119 | #define mmDCORE2_RTR3_DBG_ADDR_BASE 0x455D000ull |
|---|
| 17120 | #define DCORE2_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17121 | #define DCORE2_RTR3_DBG_ADDR_SECTION 0xE800 |
|---|
| 17122 | #define mmDCORE2_RTR3_DBG_ADDR_SPECIAL_BASE 0x455DE80ull |
|---|
| 17123 | #define DCORE2_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17124 | #define DCORE2_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17125 | #define mmDCORE2_RTR4_CTRL_BASE 0x4560000ull |
|---|
| 17126 | #define DCORE2_RTR4_CTRL_MAX_OFFSET 0x1000 |
|---|
| 17127 | #define DCORE2_RTR4_CTRL_SECTION 0xE800 |
|---|
| 17128 | #define mmDCORE2_RTR4_CTRL_SPECIAL_BASE 0x4560E80ull |
|---|
| 17129 | #define DCORE2_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17130 | #define DCORE2_RTR4_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 17131 | #define mmDCORE2_RTR4_H3_BASE 0x4561000ull |
|---|
| 17132 | #define DCORE2_RTR4_H3_MAX_OFFSET 0x1000 |
|---|
| 17133 | #define DCORE2_RTR4_H3_SECTION 0xE800 |
|---|
| 17134 | #define mmDCORE2_RTR4_H3_SPECIAL_BASE 0x4561E80ull |
|---|
| 17135 | #define DCORE2_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17136 | #define DCORE2_RTR4_H3_SPECIAL_SECTION 0x1800 |
|---|
| 17137 | #define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4562000ull |
|---|
| 17138 | #define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17139 | #define DCORE2_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 17140 | #define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4562200ull |
|---|
| 17141 | #define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17142 | #define DCORE2_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 17143 | #define mmDCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4562400ull |
|---|
| 17144 | #define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17145 | #define DCORE2_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 17146 | #define mmDCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4562600ull |
|---|
| 17147 | #define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17148 | #define DCORE2_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 17149 | #define mmDCORE2_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4562800ull |
|---|
| 17150 | #define DCORE2_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 17151 | #define DCORE2_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 17152 | #define mmDCORE2_RTR4_MSTR_IF_AXUSER_BASE 0x4562A80ull |
|---|
| 17153 | #define DCORE2_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 17154 | #define DCORE2_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 17155 | #define mmDCORE2_RTR4_MSTR_IF_DBG_HBW_BASE 0x4562B00ull |
|---|
| 17156 | #define DCORE2_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 17157 | #define DCORE2_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 17158 | #define mmDCORE2_RTR4_MSTR_IF_DBG_LBW_BASE 0x4562B80ull |
|---|
| 17159 | #define DCORE2_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 17160 | #define DCORE2_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 17161 | #define mmDCORE2_RTR4_MSTR_IF_CORE_HBW_BASE 0x4562C00ull |
|---|
| 17162 | #define DCORE2_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 17163 | #define DCORE2_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 17164 | #define mmDCORE2_RTR4_MSTR_IF_CORE_LBW_BASE 0x4562D80ull |
|---|
| 17165 | #define DCORE2_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 17166 | #define DCORE2_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 17167 | #define mmDCORE2_RTR4_MSTR_IF_SPECIAL_BASE 0x4562E80ull |
|---|
| 17168 | #define DCORE2_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17169 | #define DCORE2_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 17170 | #define mmDCORE2_RTR4_ADD_DEC_HBW_BASE 0x4563000ull |
|---|
| 17171 | #define DCORE2_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 17172 | #define DCORE2_RTR4_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 17173 | #define mmDCORE2_RTR4_ADD_DEC_LBW_BASE 0x4563400ull |
|---|
| 17174 | #define DCORE2_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 17175 | #define DCORE2_RTR4_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 17176 | #define mmDCORE2_RTR4_ADD_DEC_SPECIAL_BASE 0x4563E80ull |
|---|
| 17177 | #define DCORE2_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17178 | #define DCORE2_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 17179 | #define mmDCORE2_RTR4_BASE 0x4564000ull |
|---|
| 17180 | #define DCORE2_RTR4_MAX_OFFSET 0x1000 |
|---|
| 17181 | #define DCORE2_RTR4_SECTION 0x3000 |
|---|
| 17182 | #define mmDCORE2_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4564300ull |
|---|
| 17183 | #define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17184 | #define DCORE2_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17185 | #define mmDCORE2_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4564340ull |
|---|
| 17186 | #define DCORE2_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17187 | #define DCORE2_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17188 | #define mmDCORE2_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4564380ull |
|---|
| 17189 | #define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17190 | #define DCORE2_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17191 | #define mmDCORE2_RTR4_HBW_WR_RS_LL_STAT_BASE 0x45643C0ull |
|---|
| 17192 | #define DCORE2_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17193 | #define DCORE2_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17194 | #define mmDCORE2_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4564400ull |
|---|
| 17195 | #define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17196 | #define DCORE2_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17197 | #define mmDCORE2_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4564440ull |
|---|
| 17198 | #define DCORE2_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17199 | #define DCORE2_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17200 | #define mmDCORE2_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4564480ull |
|---|
| 17201 | #define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17202 | #define DCORE2_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17203 | #define mmDCORE2_RTR4_LBW_WR_RS_LL_STAT_BASE 0x45644C0ull |
|---|
| 17204 | #define DCORE2_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17205 | #define DCORE2_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17206 | #define mmDCORE2_RTR4_HBW_MFIFO_BASE 0x4564500ull |
|---|
| 17207 | #define DCORE2_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 17208 | #define DCORE2_RTR4_HBW_MFIFO_SECTION 0x4000 |
|---|
| 17209 | #define mmDCORE2_RTR4_E2E_RD_LL_STAT_BASE 0x4564540ull |
|---|
| 17210 | #define DCORE2_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17211 | #define DCORE2_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 17212 | #define mmDCORE2_RTR4_E2E_WR_LL_STAT_BASE 0x4564580ull |
|---|
| 17213 | #define DCORE2_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17214 | #define DCORE2_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 17215 | #define mmDCORE2_RTR4_RTR_HBW_XACT_STAT_BASE 0x4564600ull |
|---|
| 17216 | #define DCORE2_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17217 | #define DCORE2_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17218 | #define mmDCORE2_RTR4_RTR_LBW_XACT_STAT_BASE 0x4564680ull |
|---|
| 17219 | #define DCORE2_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17220 | #define DCORE2_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17221 | #define mmDCORE2_RTR4_RTR_E2E_XACT_STAT_BASE 0x4564700ull |
|---|
| 17222 | #define DCORE2_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17223 | #define DCORE2_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17224 | #define mmDCORE2_RTR4_SPECIAL_BASE 0x4564E80ull |
|---|
| 17225 | #define DCORE2_RTR4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17226 | #define DCORE2_RTR4_SPECIAL_SECTION 0x1800 |
|---|
| 17227 | #define mmDCORE2_RTR4_DBG_ADDR_BASE 0x4565000ull |
|---|
| 17228 | #define DCORE2_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17229 | #define DCORE2_RTR4_DBG_ADDR_SECTION 0xE800 |
|---|
| 17230 | #define mmDCORE2_RTR4_DBG_ADDR_SPECIAL_BASE 0x4565E80ull |
|---|
| 17231 | #define DCORE2_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17232 | #define DCORE2_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17233 | #define mmDCORE2_RTR5_CTRL_BASE 0x4568000ull |
|---|
| 17234 | #define DCORE2_RTR5_CTRL_MAX_OFFSET 0x1000 |
|---|
| 17235 | #define DCORE2_RTR5_CTRL_SECTION 0xE800 |
|---|
| 17236 | #define mmDCORE2_RTR5_CTRL_SPECIAL_BASE 0x4568E80ull |
|---|
| 17237 | #define DCORE2_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17238 | #define DCORE2_RTR5_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 17239 | #define mmDCORE2_RTR5_H3_BASE 0x4569000ull |
|---|
| 17240 | #define DCORE2_RTR5_H3_MAX_OFFSET 0x1000 |
|---|
| 17241 | #define DCORE2_RTR5_H3_SECTION 0xE800 |
|---|
| 17242 | #define mmDCORE2_RTR5_H3_SPECIAL_BASE 0x4569E80ull |
|---|
| 17243 | #define DCORE2_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17244 | #define DCORE2_RTR5_H3_SPECIAL_SECTION 0x1800 |
|---|
| 17245 | #define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x456A000ull |
|---|
| 17246 | #define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17247 | #define DCORE2_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 17248 | #define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x456A200ull |
|---|
| 17249 | #define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17250 | #define DCORE2_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 17251 | #define mmDCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x456A400ull |
|---|
| 17252 | #define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17253 | #define DCORE2_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 17254 | #define mmDCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x456A600ull |
|---|
| 17255 | #define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17256 | #define DCORE2_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 17257 | #define mmDCORE2_RTR5_MSTR_IF_E2E_CRDT_BASE 0x456A800ull |
|---|
| 17258 | #define DCORE2_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 17259 | #define DCORE2_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 17260 | #define mmDCORE2_RTR5_MSTR_IF_AXUSER_BASE 0x456AA80ull |
|---|
| 17261 | #define DCORE2_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 17262 | #define DCORE2_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 17263 | #define mmDCORE2_RTR5_MSTR_IF_DBG_HBW_BASE 0x456AB00ull |
|---|
| 17264 | #define DCORE2_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 17265 | #define DCORE2_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 17266 | #define mmDCORE2_RTR5_MSTR_IF_DBG_LBW_BASE 0x456AB80ull |
|---|
| 17267 | #define DCORE2_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 17268 | #define DCORE2_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 17269 | #define mmDCORE2_RTR5_MSTR_IF_CORE_HBW_BASE 0x456AC00ull |
|---|
| 17270 | #define DCORE2_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 17271 | #define DCORE2_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 17272 | #define mmDCORE2_RTR5_MSTR_IF_CORE_LBW_BASE 0x456AD80ull |
|---|
| 17273 | #define DCORE2_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 17274 | #define DCORE2_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 17275 | #define mmDCORE2_RTR5_MSTR_IF_SPECIAL_BASE 0x456AE80ull |
|---|
| 17276 | #define DCORE2_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17277 | #define DCORE2_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 17278 | #define mmDCORE2_RTR5_ADD_DEC_HBW_BASE 0x456B000ull |
|---|
| 17279 | #define DCORE2_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 17280 | #define DCORE2_RTR5_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 17281 | #define mmDCORE2_RTR5_ADD_DEC_LBW_BASE 0x456B400ull |
|---|
| 17282 | #define DCORE2_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 17283 | #define DCORE2_RTR5_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 17284 | #define mmDCORE2_RTR5_ADD_DEC_SPECIAL_BASE 0x456BE80ull |
|---|
| 17285 | #define DCORE2_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17286 | #define DCORE2_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 17287 | #define mmDCORE2_RTR5_BASE 0x456C000ull |
|---|
| 17288 | #define DCORE2_RTR5_MAX_OFFSET 0x1000 |
|---|
| 17289 | #define DCORE2_RTR5_SECTION 0x3000 |
|---|
| 17290 | #define mmDCORE2_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x456C300ull |
|---|
| 17291 | #define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17292 | #define DCORE2_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17293 | #define mmDCORE2_RTR5_HBW_RD_RS_LL_STAT_BASE 0x456C340ull |
|---|
| 17294 | #define DCORE2_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17295 | #define DCORE2_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17296 | #define mmDCORE2_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x456C380ull |
|---|
| 17297 | #define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17298 | #define DCORE2_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17299 | #define mmDCORE2_RTR5_HBW_WR_RS_LL_STAT_BASE 0x456C3C0ull |
|---|
| 17300 | #define DCORE2_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17301 | #define DCORE2_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17302 | #define mmDCORE2_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x456C400ull |
|---|
| 17303 | #define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17304 | #define DCORE2_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17305 | #define mmDCORE2_RTR5_LBW_RD_RS_LL_STAT_BASE 0x456C440ull |
|---|
| 17306 | #define DCORE2_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17307 | #define DCORE2_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17308 | #define mmDCORE2_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x456C480ull |
|---|
| 17309 | #define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17310 | #define DCORE2_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17311 | #define mmDCORE2_RTR5_LBW_WR_RS_LL_STAT_BASE 0x456C4C0ull |
|---|
| 17312 | #define DCORE2_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17313 | #define DCORE2_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17314 | #define mmDCORE2_RTR5_HBW_MFIFO_BASE 0x456C500ull |
|---|
| 17315 | #define DCORE2_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 17316 | #define DCORE2_RTR5_HBW_MFIFO_SECTION 0x4000 |
|---|
| 17317 | #define mmDCORE2_RTR5_E2E_RD_LL_STAT_BASE 0x456C540ull |
|---|
| 17318 | #define DCORE2_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17319 | #define DCORE2_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 17320 | #define mmDCORE2_RTR5_E2E_WR_LL_STAT_BASE 0x456C580ull |
|---|
| 17321 | #define DCORE2_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17322 | #define DCORE2_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 17323 | #define mmDCORE2_RTR5_RTR_HBW_XACT_STAT_BASE 0x456C600ull |
|---|
| 17324 | #define DCORE2_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17325 | #define DCORE2_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17326 | #define mmDCORE2_RTR5_RTR_LBW_XACT_STAT_BASE 0x456C680ull |
|---|
| 17327 | #define DCORE2_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17328 | #define DCORE2_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17329 | #define mmDCORE2_RTR5_RTR_E2E_XACT_STAT_BASE 0x456C700ull |
|---|
| 17330 | #define DCORE2_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17331 | #define DCORE2_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17332 | #define mmDCORE2_RTR5_SPECIAL_BASE 0x456CE80ull |
|---|
| 17333 | #define DCORE2_RTR5_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17334 | #define DCORE2_RTR5_SPECIAL_SECTION 0x1800 |
|---|
| 17335 | #define mmDCORE2_RTR5_DBG_ADDR_BASE 0x456D000ull |
|---|
| 17336 | #define DCORE2_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17337 | #define DCORE2_RTR5_DBG_ADDR_SECTION 0xE800 |
|---|
| 17338 | #define mmDCORE2_RTR5_DBG_ADDR_SPECIAL_BASE 0x456DE80ull |
|---|
| 17339 | #define DCORE2_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17340 | #define DCORE2_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17341 | #define mmDCORE2_RTR6_CTRL_BASE 0x4570000ull |
|---|
| 17342 | #define DCORE2_RTR6_CTRL_MAX_OFFSET 0x1000 |
|---|
| 17343 | #define DCORE2_RTR6_CTRL_SECTION 0xE800 |
|---|
| 17344 | #define mmDCORE2_RTR6_CTRL_SPECIAL_BASE 0x4570E80ull |
|---|
| 17345 | #define DCORE2_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17346 | #define DCORE2_RTR6_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 17347 | #define mmDCORE2_RTR6_H3_BASE 0x4571000ull |
|---|
| 17348 | #define DCORE2_RTR6_H3_MAX_OFFSET 0x1000 |
|---|
| 17349 | #define DCORE2_RTR6_H3_SECTION 0xE800 |
|---|
| 17350 | #define mmDCORE2_RTR6_H3_SPECIAL_BASE 0x4571E80ull |
|---|
| 17351 | #define DCORE2_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17352 | #define DCORE2_RTR6_H3_SPECIAL_SECTION 0x1800 |
|---|
| 17353 | #define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4572000ull |
|---|
| 17354 | #define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17355 | #define DCORE2_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 17356 | #define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4572200ull |
|---|
| 17357 | #define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17358 | #define DCORE2_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 17359 | #define mmDCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4572400ull |
|---|
| 17360 | #define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17361 | #define DCORE2_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 17362 | #define mmDCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4572600ull |
|---|
| 17363 | #define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17364 | #define DCORE2_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 17365 | #define mmDCORE2_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4572800ull |
|---|
| 17366 | #define DCORE2_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 17367 | #define DCORE2_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 17368 | #define mmDCORE2_RTR6_MSTR_IF_AXUSER_BASE 0x4572A80ull |
|---|
| 17369 | #define DCORE2_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 17370 | #define DCORE2_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 17371 | #define mmDCORE2_RTR6_MSTR_IF_DBG_HBW_BASE 0x4572B00ull |
|---|
| 17372 | #define DCORE2_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 17373 | #define DCORE2_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 17374 | #define mmDCORE2_RTR6_MSTR_IF_DBG_LBW_BASE 0x4572B80ull |
|---|
| 17375 | #define DCORE2_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 17376 | #define DCORE2_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 17377 | #define mmDCORE2_RTR6_MSTR_IF_CORE_HBW_BASE 0x4572C00ull |
|---|
| 17378 | #define DCORE2_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 17379 | #define DCORE2_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 17380 | #define mmDCORE2_RTR6_MSTR_IF_CORE_LBW_BASE 0x4572D80ull |
|---|
| 17381 | #define DCORE2_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 17382 | #define DCORE2_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 17383 | #define mmDCORE2_RTR6_MSTR_IF_SPECIAL_BASE 0x4572E80ull |
|---|
| 17384 | #define DCORE2_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17385 | #define DCORE2_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 17386 | #define mmDCORE2_RTR6_ADD_DEC_HBW_BASE 0x4573000ull |
|---|
| 17387 | #define DCORE2_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 17388 | #define DCORE2_RTR6_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 17389 | #define mmDCORE2_RTR6_ADD_DEC_LBW_BASE 0x4573400ull |
|---|
| 17390 | #define DCORE2_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 17391 | #define DCORE2_RTR6_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 17392 | #define mmDCORE2_RTR6_ADD_DEC_SPECIAL_BASE 0x4573E80ull |
|---|
| 17393 | #define DCORE2_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17394 | #define DCORE2_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 17395 | #define mmDCORE2_RTR6_BASE 0x4574000ull |
|---|
| 17396 | #define DCORE2_RTR6_MAX_OFFSET 0x1000 |
|---|
| 17397 | #define DCORE2_RTR6_SECTION 0x3000 |
|---|
| 17398 | #define mmDCORE2_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4574300ull |
|---|
| 17399 | #define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17400 | #define DCORE2_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17401 | #define mmDCORE2_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4574340ull |
|---|
| 17402 | #define DCORE2_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17403 | #define DCORE2_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17404 | #define mmDCORE2_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4574380ull |
|---|
| 17405 | #define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17406 | #define DCORE2_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17407 | #define mmDCORE2_RTR6_HBW_WR_RS_LL_STAT_BASE 0x45743C0ull |
|---|
| 17408 | #define DCORE2_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17409 | #define DCORE2_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17410 | #define mmDCORE2_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4574400ull |
|---|
| 17411 | #define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17412 | #define DCORE2_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17413 | #define mmDCORE2_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4574440ull |
|---|
| 17414 | #define DCORE2_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17415 | #define DCORE2_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17416 | #define mmDCORE2_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4574480ull |
|---|
| 17417 | #define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17418 | #define DCORE2_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17419 | #define mmDCORE2_RTR6_LBW_WR_RS_LL_STAT_BASE 0x45744C0ull |
|---|
| 17420 | #define DCORE2_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17421 | #define DCORE2_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17422 | #define mmDCORE2_RTR6_HBW_MFIFO_BASE 0x4574500ull |
|---|
| 17423 | #define DCORE2_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 17424 | #define DCORE2_RTR6_HBW_MFIFO_SECTION 0x4000 |
|---|
| 17425 | #define mmDCORE2_RTR6_E2E_RD_LL_STAT_BASE 0x4574540ull |
|---|
| 17426 | #define DCORE2_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17427 | #define DCORE2_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 17428 | #define mmDCORE2_RTR6_E2E_WR_LL_STAT_BASE 0x4574580ull |
|---|
| 17429 | #define DCORE2_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17430 | #define DCORE2_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 17431 | #define mmDCORE2_RTR6_RTR_HBW_XACT_STAT_BASE 0x4574600ull |
|---|
| 17432 | #define DCORE2_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17433 | #define DCORE2_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17434 | #define mmDCORE2_RTR6_RTR_LBW_XACT_STAT_BASE 0x4574680ull |
|---|
| 17435 | #define DCORE2_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17436 | #define DCORE2_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17437 | #define mmDCORE2_RTR6_RTR_E2E_XACT_STAT_BASE 0x4574700ull |
|---|
| 17438 | #define DCORE2_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17439 | #define DCORE2_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17440 | #define mmDCORE2_RTR6_SPECIAL_BASE 0x4574E80ull |
|---|
| 17441 | #define DCORE2_RTR6_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17442 | #define DCORE2_RTR6_SPECIAL_SECTION 0x1800 |
|---|
| 17443 | #define mmDCORE2_RTR6_DBG_ADDR_BASE 0x4575000ull |
|---|
| 17444 | #define DCORE2_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17445 | #define DCORE2_RTR6_DBG_ADDR_SECTION 0xE800 |
|---|
| 17446 | #define mmDCORE2_RTR6_DBG_ADDR_SPECIAL_BASE 0x4575E80ull |
|---|
| 17447 | #define DCORE2_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17448 | #define DCORE2_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17449 | #define mmDCORE2_RTR7_CTRL_BASE 0x4578000ull |
|---|
| 17450 | #define DCORE2_RTR7_CTRL_MAX_OFFSET 0x1000 |
|---|
| 17451 | #define DCORE2_RTR7_CTRL_SECTION 0xE800 |
|---|
| 17452 | #define mmDCORE2_RTR7_CTRL_SPECIAL_BASE 0x4578E80ull |
|---|
| 17453 | #define DCORE2_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17454 | #define DCORE2_RTR7_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 17455 | #define mmDCORE2_RTR7_H3_BASE 0x4579000ull |
|---|
| 17456 | #define DCORE2_RTR7_H3_MAX_OFFSET 0x1000 |
|---|
| 17457 | #define DCORE2_RTR7_H3_SECTION 0xE800 |
|---|
| 17458 | #define mmDCORE2_RTR7_H3_SPECIAL_BASE 0x4579E80ull |
|---|
| 17459 | #define DCORE2_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17460 | #define DCORE2_RTR7_H3_SPECIAL_SECTION 0x1800 |
|---|
| 17461 | #define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x457A000ull |
|---|
| 17462 | #define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17463 | #define DCORE2_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 17464 | #define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x457A200ull |
|---|
| 17465 | #define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 17466 | #define DCORE2_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 17467 | #define mmDCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x457A400ull |
|---|
| 17468 | #define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17469 | #define DCORE2_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 17470 | #define mmDCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x457A600ull |
|---|
| 17471 | #define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 17472 | #define DCORE2_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 17473 | #define mmDCORE2_RTR7_MSTR_IF_E2E_CRDT_BASE 0x457A800ull |
|---|
| 17474 | #define DCORE2_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 17475 | #define DCORE2_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 17476 | #define mmDCORE2_RTR7_MSTR_IF_AXUSER_BASE 0x457AA80ull |
|---|
| 17477 | #define DCORE2_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 17478 | #define DCORE2_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 17479 | #define mmDCORE2_RTR7_MSTR_IF_DBG_HBW_BASE 0x457AB00ull |
|---|
| 17480 | #define DCORE2_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 17481 | #define DCORE2_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 17482 | #define mmDCORE2_RTR7_MSTR_IF_DBG_LBW_BASE 0x457AB80ull |
|---|
| 17483 | #define DCORE2_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 17484 | #define DCORE2_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 17485 | #define mmDCORE2_RTR7_MSTR_IF_CORE_HBW_BASE 0x457AC00ull |
|---|
| 17486 | #define DCORE2_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 17487 | #define DCORE2_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 17488 | #define mmDCORE2_RTR7_MSTR_IF_CORE_LBW_BASE 0x457AD80ull |
|---|
| 17489 | #define DCORE2_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 17490 | #define DCORE2_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 17491 | #define mmDCORE2_RTR7_MSTR_IF_SPECIAL_BASE 0x457AE80ull |
|---|
| 17492 | #define DCORE2_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17493 | #define DCORE2_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 17494 | #define mmDCORE2_RTR7_ADD_DEC_HBW_BASE 0x457B000ull |
|---|
| 17495 | #define DCORE2_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 17496 | #define DCORE2_RTR7_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 17497 | #define mmDCORE2_RTR7_ADD_DEC_LBW_BASE 0x457B400ull |
|---|
| 17498 | #define DCORE2_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 17499 | #define DCORE2_RTR7_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 17500 | #define mmDCORE2_RTR7_ADD_DEC_SPECIAL_BASE 0x457BE80ull |
|---|
| 17501 | #define DCORE2_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17502 | #define DCORE2_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 17503 | #define mmDCORE2_RTR7_BASE 0x457C000ull |
|---|
| 17504 | #define DCORE2_RTR7_MAX_OFFSET 0x1000 |
|---|
| 17505 | #define DCORE2_RTR7_SECTION 0x3000 |
|---|
| 17506 | #define mmDCORE2_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x457C300ull |
|---|
| 17507 | #define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17508 | #define DCORE2_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17509 | #define mmDCORE2_RTR7_HBW_RD_RS_LL_STAT_BASE 0x457C340ull |
|---|
| 17510 | #define DCORE2_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17511 | #define DCORE2_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17512 | #define mmDCORE2_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x457C380ull |
|---|
| 17513 | #define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17514 | #define DCORE2_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17515 | #define mmDCORE2_RTR7_HBW_WR_RS_LL_STAT_BASE 0x457C3C0ull |
|---|
| 17516 | #define DCORE2_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17517 | #define DCORE2_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17518 | #define mmDCORE2_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x457C400ull |
|---|
| 17519 | #define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17520 | #define DCORE2_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17521 | #define mmDCORE2_RTR7_LBW_RD_RS_LL_STAT_BASE 0x457C440ull |
|---|
| 17522 | #define DCORE2_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17523 | #define DCORE2_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17524 | #define mmDCORE2_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x457C480ull |
|---|
| 17525 | #define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17526 | #define DCORE2_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 17527 | #define mmDCORE2_RTR7_LBW_WR_RS_LL_STAT_BASE 0x457C4C0ull |
|---|
| 17528 | #define DCORE2_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17529 | #define DCORE2_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 17530 | #define mmDCORE2_RTR7_HBW_MFIFO_BASE 0x457C500ull |
|---|
| 17531 | #define DCORE2_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 17532 | #define DCORE2_RTR7_HBW_MFIFO_SECTION 0x4000 |
|---|
| 17533 | #define mmDCORE2_RTR7_E2E_RD_LL_STAT_BASE 0x457C540ull |
|---|
| 17534 | #define DCORE2_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17535 | #define DCORE2_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 17536 | #define mmDCORE2_RTR7_E2E_WR_LL_STAT_BASE 0x457C580ull |
|---|
| 17537 | #define DCORE2_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 17538 | #define DCORE2_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 17539 | #define mmDCORE2_RTR7_RTR_HBW_XACT_STAT_BASE 0x457C600ull |
|---|
| 17540 | #define DCORE2_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17541 | #define DCORE2_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17542 | #define mmDCORE2_RTR7_RTR_LBW_XACT_STAT_BASE 0x457C680ull |
|---|
| 17543 | #define DCORE2_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17544 | #define DCORE2_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 17545 | #define mmDCORE2_RTR7_RTR_E2E_XACT_STAT_BASE 0x457C700ull |
|---|
| 17546 | #define DCORE2_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 17547 | #define DCORE2_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 17548 | #define mmDCORE2_RTR7_SPECIAL_BASE 0x457CE80ull |
|---|
| 17549 | #define DCORE2_RTR7_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17550 | #define DCORE2_RTR7_SPECIAL_SECTION 0x1800 |
|---|
| 17551 | #define mmDCORE2_RTR7_DBG_ADDR_BASE 0x457D000ull |
|---|
| 17552 | #define DCORE2_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 17553 | #define DCORE2_RTR7_DBG_ADDR_SECTION 0xE800 |
|---|
| 17554 | #define mmDCORE2_RTR7_DBG_ADDR_SPECIAL_BASE 0x457DE80ull |
|---|
| 17555 | #define DCORE2_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17556 | #define DCORE2_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 17557 | #define mmDCORE2_SRAM0_BANK_BASE 0x4580000ull |
|---|
| 17558 | #define DCORE2_SRAM0_BANK_MAX_OFFSET 0x1000 |
|---|
| 17559 | #define DCORE2_SRAM0_BANK_SECTION 0xE800 |
|---|
| 17560 | #define mmDCORE2_SRAM0_BANK_SPECIAL_BASE 0x4580E80ull |
|---|
| 17561 | #define DCORE2_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17562 | #define DCORE2_SRAM0_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17563 | #define mmDCORE2_SRAM0_RTR_BASE 0x4581000ull |
|---|
| 17564 | #define DCORE2_SRAM0_RTR_MAX_OFFSET 0x1000 |
|---|
| 17565 | #define DCORE2_SRAM0_RTR_SECTION 0xE800 |
|---|
| 17566 | #define mmDCORE2_SRAM0_RTR_SPECIAL_BASE 0x4581E80ull |
|---|
| 17567 | #define DCORE2_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17568 | #define DCORE2_SRAM0_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17569 | #define mmDCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4582000ull |
|---|
| 17570 | #define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17571 | #define DCORE2_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17572 | #define mmDCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4582100ull |
|---|
| 17573 | #define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17574 | #define DCORE2_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17575 | #define mmDCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4582200ull |
|---|
| 17576 | #define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17577 | #define DCORE2_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17578 | #define mmDCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4582300ull |
|---|
| 17579 | #define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17580 | #define DCORE2_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17581 | #define mmDCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4582400ull |
|---|
| 17582 | #define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17583 | #define DCORE2_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17584 | #define mmDCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4582500ull |
|---|
| 17585 | #define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17586 | #define DCORE2_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17587 | #define mmDCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4582600ull |
|---|
| 17588 | #define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17589 | #define DCORE2_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17590 | #define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4582700ull |
|---|
| 17591 | #define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17592 | #define DCORE2_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17593 | #define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4582780ull |
|---|
| 17594 | #define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17595 | #define DCORE2_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17596 | #define mmDCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4582800ull |
|---|
| 17597 | #define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17598 | #define DCORE2_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17599 | #define mmDCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4582880ull |
|---|
| 17600 | #define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17601 | #define DCORE2_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17602 | #define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4582900ull |
|---|
| 17603 | #define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17604 | #define DCORE2_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17605 | #define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4582980ull |
|---|
| 17606 | #define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17607 | #define DCORE2_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17608 | #define mmDCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4582A00ull |
|---|
| 17609 | #define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17610 | #define DCORE2_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17611 | #define mmDCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4582A80ull |
|---|
| 17612 | #define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17613 | #define DCORE2_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17614 | #define mmDCORE2_SRAM0_DBG_CNT_SPECIAL_BASE 0x4582E80ull |
|---|
| 17615 | #define DCORE2_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17616 | #define DCORE2_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17617 | #define mmDCORE2_SRAM1_BANK_BASE 0x4588000ull |
|---|
| 17618 | #define DCORE2_SRAM1_BANK_MAX_OFFSET 0x1000 |
|---|
| 17619 | #define DCORE2_SRAM1_BANK_SECTION 0xE800 |
|---|
| 17620 | #define mmDCORE2_SRAM1_BANK_SPECIAL_BASE 0x4588E80ull |
|---|
| 17621 | #define DCORE2_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17622 | #define DCORE2_SRAM1_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17623 | #define mmDCORE2_SRAM1_RTR_BASE 0x4589000ull |
|---|
| 17624 | #define DCORE2_SRAM1_RTR_MAX_OFFSET 0x1000 |
|---|
| 17625 | #define DCORE2_SRAM1_RTR_SECTION 0xE800 |
|---|
| 17626 | #define mmDCORE2_SRAM1_RTR_SPECIAL_BASE 0x4589E80ull |
|---|
| 17627 | #define DCORE2_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17628 | #define DCORE2_SRAM1_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17629 | #define mmDCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x458A000ull |
|---|
| 17630 | #define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17631 | #define DCORE2_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17632 | #define mmDCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x458A100ull |
|---|
| 17633 | #define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17634 | #define DCORE2_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17635 | #define mmDCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x458A200ull |
|---|
| 17636 | #define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17637 | #define DCORE2_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17638 | #define mmDCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x458A300ull |
|---|
| 17639 | #define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17640 | #define DCORE2_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17641 | #define mmDCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x458A400ull |
|---|
| 17642 | #define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17643 | #define DCORE2_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17644 | #define mmDCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x458A500ull |
|---|
| 17645 | #define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17646 | #define DCORE2_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17647 | #define mmDCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x458A600ull |
|---|
| 17648 | #define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17649 | #define DCORE2_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17650 | #define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x458A700ull |
|---|
| 17651 | #define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17652 | #define DCORE2_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17653 | #define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x458A780ull |
|---|
| 17654 | #define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17655 | #define DCORE2_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17656 | #define mmDCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x458A800ull |
|---|
| 17657 | #define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17658 | #define DCORE2_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17659 | #define mmDCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x458A880ull |
|---|
| 17660 | #define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17661 | #define DCORE2_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17662 | #define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x458A900ull |
|---|
| 17663 | #define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17664 | #define DCORE2_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17665 | #define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x458A980ull |
|---|
| 17666 | #define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17667 | #define DCORE2_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17668 | #define mmDCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x458AA00ull |
|---|
| 17669 | #define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17670 | #define DCORE2_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17671 | #define mmDCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x458AA80ull |
|---|
| 17672 | #define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17673 | #define DCORE2_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17674 | #define mmDCORE2_SRAM1_DBG_CNT_SPECIAL_BASE 0x458AE80ull |
|---|
| 17675 | #define DCORE2_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17676 | #define DCORE2_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17677 | #define mmDCORE2_SRAM2_BANK_BASE 0x4590000ull |
|---|
| 17678 | #define DCORE2_SRAM2_BANK_MAX_OFFSET 0x1000 |
|---|
| 17679 | #define DCORE2_SRAM2_BANK_SECTION 0xE800 |
|---|
| 17680 | #define mmDCORE2_SRAM2_BANK_SPECIAL_BASE 0x4590E80ull |
|---|
| 17681 | #define DCORE2_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17682 | #define DCORE2_SRAM2_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17683 | #define mmDCORE2_SRAM2_RTR_BASE 0x4591000ull |
|---|
| 17684 | #define DCORE2_SRAM2_RTR_MAX_OFFSET 0x1000 |
|---|
| 17685 | #define DCORE2_SRAM2_RTR_SECTION 0xE800 |
|---|
| 17686 | #define mmDCORE2_SRAM2_RTR_SPECIAL_BASE 0x4591E80ull |
|---|
| 17687 | #define DCORE2_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17688 | #define DCORE2_SRAM2_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17689 | #define mmDCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4592000ull |
|---|
| 17690 | #define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17691 | #define DCORE2_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17692 | #define mmDCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4592100ull |
|---|
| 17693 | #define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17694 | #define DCORE2_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17695 | #define mmDCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4592200ull |
|---|
| 17696 | #define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17697 | #define DCORE2_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17698 | #define mmDCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4592300ull |
|---|
| 17699 | #define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17700 | #define DCORE2_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17701 | #define mmDCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4592400ull |
|---|
| 17702 | #define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17703 | #define DCORE2_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17704 | #define mmDCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4592500ull |
|---|
| 17705 | #define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17706 | #define DCORE2_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17707 | #define mmDCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4592600ull |
|---|
| 17708 | #define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17709 | #define DCORE2_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17710 | #define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4592700ull |
|---|
| 17711 | #define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17712 | #define DCORE2_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17713 | #define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4592780ull |
|---|
| 17714 | #define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17715 | #define DCORE2_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17716 | #define mmDCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4592800ull |
|---|
| 17717 | #define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17718 | #define DCORE2_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17719 | #define mmDCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4592880ull |
|---|
| 17720 | #define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17721 | #define DCORE2_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17722 | #define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4592900ull |
|---|
| 17723 | #define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17724 | #define DCORE2_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17725 | #define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4592980ull |
|---|
| 17726 | #define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17727 | #define DCORE2_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17728 | #define mmDCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4592A00ull |
|---|
| 17729 | #define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17730 | #define DCORE2_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17731 | #define mmDCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4592A80ull |
|---|
| 17732 | #define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17733 | #define DCORE2_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17734 | #define mmDCORE2_SRAM2_DBG_CNT_SPECIAL_BASE 0x4592E80ull |
|---|
| 17735 | #define DCORE2_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17736 | #define DCORE2_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17737 | #define mmDCORE2_SRAM3_BANK_BASE 0x4598000ull |
|---|
| 17738 | #define DCORE2_SRAM3_BANK_MAX_OFFSET 0x1000 |
|---|
| 17739 | #define DCORE2_SRAM3_BANK_SECTION 0xE800 |
|---|
| 17740 | #define mmDCORE2_SRAM3_BANK_SPECIAL_BASE 0x4598E80ull |
|---|
| 17741 | #define DCORE2_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17742 | #define DCORE2_SRAM3_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17743 | #define mmDCORE2_SRAM3_RTR_BASE 0x4599000ull |
|---|
| 17744 | #define DCORE2_SRAM3_RTR_MAX_OFFSET 0x1000 |
|---|
| 17745 | #define DCORE2_SRAM3_RTR_SECTION 0xE800 |
|---|
| 17746 | #define mmDCORE2_SRAM3_RTR_SPECIAL_BASE 0x4599E80ull |
|---|
| 17747 | #define DCORE2_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17748 | #define DCORE2_SRAM3_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17749 | #define mmDCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x459A000ull |
|---|
| 17750 | #define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17751 | #define DCORE2_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17752 | #define mmDCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x459A100ull |
|---|
| 17753 | #define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17754 | #define DCORE2_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17755 | #define mmDCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x459A200ull |
|---|
| 17756 | #define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17757 | #define DCORE2_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17758 | #define mmDCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x459A300ull |
|---|
| 17759 | #define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17760 | #define DCORE2_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17761 | #define mmDCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x459A400ull |
|---|
| 17762 | #define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17763 | #define DCORE2_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17764 | #define mmDCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x459A500ull |
|---|
| 17765 | #define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17766 | #define DCORE2_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17767 | #define mmDCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x459A600ull |
|---|
| 17768 | #define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17769 | #define DCORE2_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17770 | #define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x459A700ull |
|---|
| 17771 | #define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17772 | #define DCORE2_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17773 | #define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x459A780ull |
|---|
| 17774 | #define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17775 | #define DCORE2_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17776 | #define mmDCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x459A800ull |
|---|
| 17777 | #define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17778 | #define DCORE2_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17779 | #define mmDCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x459A880ull |
|---|
| 17780 | #define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17781 | #define DCORE2_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17782 | #define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x459A900ull |
|---|
| 17783 | #define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17784 | #define DCORE2_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17785 | #define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x459A980ull |
|---|
| 17786 | #define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17787 | #define DCORE2_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17788 | #define mmDCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x459AA00ull |
|---|
| 17789 | #define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17790 | #define DCORE2_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17791 | #define mmDCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x459AA80ull |
|---|
| 17792 | #define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17793 | #define DCORE2_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17794 | #define mmDCORE2_SRAM3_DBG_CNT_SPECIAL_BASE 0x459AE80ull |
|---|
| 17795 | #define DCORE2_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17796 | #define DCORE2_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17797 | #define mmDCORE2_SRAM4_BANK_BASE 0x45A0000ull |
|---|
| 17798 | #define DCORE2_SRAM4_BANK_MAX_OFFSET 0x1000 |
|---|
| 17799 | #define DCORE2_SRAM4_BANK_SECTION 0xE800 |
|---|
| 17800 | #define mmDCORE2_SRAM4_BANK_SPECIAL_BASE 0x45A0E80ull |
|---|
| 17801 | #define DCORE2_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17802 | #define DCORE2_SRAM4_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17803 | #define mmDCORE2_SRAM4_RTR_BASE 0x45A1000ull |
|---|
| 17804 | #define DCORE2_SRAM4_RTR_MAX_OFFSET 0x1000 |
|---|
| 17805 | #define DCORE2_SRAM4_RTR_SECTION 0xE800 |
|---|
| 17806 | #define mmDCORE2_SRAM4_RTR_SPECIAL_BASE 0x45A1E80ull |
|---|
| 17807 | #define DCORE2_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17808 | #define DCORE2_SRAM4_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17809 | #define mmDCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45A2000ull |
|---|
| 17810 | #define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17811 | #define DCORE2_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17812 | #define mmDCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45A2100ull |
|---|
| 17813 | #define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17814 | #define DCORE2_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17815 | #define mmDCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45A2200ull |
|---|
| 17816 | #define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17817 | #define DCORE2_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17818 | #define mmDCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45A2300ull |
|---|
| 17819 | #define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17820 | #define DCORE2_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17821 | #define mmDCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45A2400ull |
|---|
| 17822 | #define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17823 | #define DCORE2_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17824 | #define mmDCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45A2500ull |
|---|
| 17825 | #define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17826 | #define DCORE2_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17827 | #define mmDCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45A2600ull |
|---|
| 17828 | #define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17829 | #define DCORE2_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17830 | #define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2700ull |
|---|
| 17831 | #define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17832 | #define DCORE2_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17833 | #define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2780ull |
|---|
| 17834 | #define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17835 | #define DCORE2_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17836 | #define mmDCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45A2800ull |
|---|
| 17837 | #define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17838 | #define DCORE2_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17839 | #define mmDCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45A2880ull |
|---|
| 17840 | #define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17841 | #define DCORE2_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17842 | #define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45A2900ull |
|---|
| 17843 | #define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17844 | #define DCORE2_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17845 | #define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45A2980ull |
|---|
| 17846 | #define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17847 | #define DCORE2_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17848 | #define mmDCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45A2A00ull |
|---|
| 17849 | #define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17850 | #define DCORE2_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17851 | #define mmDCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45A2A80ull |
|---|
| 17852 | #define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17853 | #define DCORE2_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17854 | #define mmDCORE2_SRAM4_DBG_CNT_SPECIAL_BASE 0x45A2E80ull |
|---|
| 17855 | #define DCORE2_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17856 | #define DCORE2_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17857 | #define mmDCORE2_SRAM5_BANK_BASE 0x45A8000ull |
|---|
| 17858 | #define DCORE2_SRAM5_BANK_MAX_OFFSET 0x1000 |
|---|
| 17859 | #define DCORE2_SRAM5_BANK_SECTION 0xE800 |
|---|
| 17860 | #define mmDCORE2_SRAM5_BANK_SPECIAL_BASE 0x45A8E80ull |
|---|
| 17861 | #define DCORE2_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17862 | #define DCORE2_SRAM5_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17863 | #define mmDCORE2_SRAM5_RTR_BASE 0x45A9000ull |
|---|
| 17864 | #define DCORE2_SRAM5_RTR_MAX_OFFSET 0x1000 |
|---|
| 17865 | #define DCORE2_SRAM5_RTR_SECTION 0xE800 |
|---|
| 17866 | #define mmDCORE2_SRAM5_RTR_SPECIAL_BASE 0x45A9E80ull |
|---|
| 17867 | #define DCORE2_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17868 | #define DCORE2_SRAM5_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17869 | #define mmDCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45AA000ull |
|---|
| 17870 | #define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17871 | #define DCORE2_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17872 | #define mmDCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45AA100ull |
|---|
| 17873 | #define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17874 | #define DCORE2_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17875 | #define mmDCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45AA200ull |
|---|
| 17876 | #define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17877 | #define DCORE2_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17878 | #define mmDCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45AA300ull |
|---|
| 17879 | #define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17880 | #define DCORE2_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17881 | #define mmDCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45AA400ull |
|---|
| 17882 | #define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17883 | #define DCORE2_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17884 | #define mmDCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45AA500ull |
|---|
| 17885 | #define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17886 | #define DCORE2_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17887 | #define mmDCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45AA600ull |
|---|
| 17888 | #define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17889 | #define DCORE2_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17890 | #define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA700ull |
|---|
| 17891 | #define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17892 | #define DCORE2_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17893 | #define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA780ull |
|---|
| 17894 | #define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17895 | #define DCORE2_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17896 | #define mmDCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45AA800ull |
|---|
| 17897 | #define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17898 | #define DCORE2_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17899 | #define mmDCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45AA880ull |
|---|
| 17900 | #define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17901 | #define DCORE2_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17902 | #define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45AA900ull |
|---|
| 17903 | #define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17904 | #define DCORE2_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17905 | #define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45AA980ull |
|---|
| 17906 | #define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17907 | #define DCORE2_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17908 | #define mmDCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45AAA00ull |
|---|
| 17909 | #define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17910 | #define DCORE2_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17911 | #define mmDCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45AAA80ull |
|---|
| 17912 | #define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17913 | #define DCORE2_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17914 | #define mmDCORE2_SRAM5_DBG_CNT_SPECIAL_BASE 0x45AAE80ull |
|---|
| 17915 | #define DCORE2_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17916 | #define DCORE2_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17917 | #define mmDCORE2_SRAM6_BANK_BASE 0x45B0000ull |
|---|
| 17918 | #define DCORE2_SRAM6_BANK_MAX_OFFSET 0x1000 |
|---|
| 17919 | #define DCORE2_SRAM6_BANK_SECTION 0xE800 |
|---|
| 17920 | #define mmDCORE2_SRAM6_BANK_SPECIAL_BASE 0x45B0E80ull |
|---|
| 17921 | #define DCORE2_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17922 | #define DCORE2_SRAM6_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17923 | #define mmDCORE2_SRAM6_RTR_BASE 0x45B1000ull |
|---|
| 17924 | #define DCORE2_SRAM6_RTR_MAX_OFFSET 0x1000 |
|---|
| 17925 | #define DCORE2_SRAM6_RTR_SECTION 0xE800 |
|---|
| 17926 | #define mmDCORE2_SRAM6_RTR_SPECIAL_BASE 0x45B1E80ull |
|---|
| 17927 | #define DCORE2_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17928 | #define DCORE2_SRAM6_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17929 | #define mmDCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45B2000ull |
|---|
| 17930 | #define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17931 | #define DCORE2_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17932 | #define mmDCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45B2100ull |
|---|
| 17933 | #define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17934 | #define DCORE2_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17935 | #define mmDCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45B2200ull |
|---|
| 17936 | #define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17937 | #define DCORE2_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17938 | #define mmDCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45B2300ull |
|---|
| 17939 | #define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17940 | #define DCORE2_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17941 | #define mmDCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45B2400ull |
|---|
| 17942 | #define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17943 | #define DCORE2_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17944 | #define mmDCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45B2500ull |
|---|
| 17945 | #define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17946 | #define DCORE2_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17947 | #define mmDCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45B2600ull |
|---|
| 17948 | #define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17949 | #define DCORE2_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17950 | #define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2700ull |
|---|
| 17951 | #define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17952 | #define DCORE2_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17953 | #define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2780ull |
|---|
| 17954 | #define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17955 | #define DCORE2_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17956 | #define mmDCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45B2800ull |
|---|
| 17957 | #define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17958 | #define DCORE2_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17959 | #define mmDCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45B2880ull |
|---|
| 17960 | #define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17961 | #define DCORE2_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17962 | #define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45B2900ull |
|---|
| 17963 | #define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17964 | #define DCORE2_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17965 | #define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45B2980ull |
|---|
| 17966 | #define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17967 | #define DCORE2_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17968 | #define mmDCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45B2A00ull |
|---|
| 17969 | #define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17970 | #define DCORE2_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 17971 | #define mmDCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45B2A80ull |
|---|
| 17972 | #define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 17973 | #define DCORE2_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 17974 | #define mmDCORE2_SRAM6_DBG_CNT_SPECIAL_BASE 0x45B2E80ull |
|---|
| 17975 | #define DCORE2_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17976 | #define DCORE2_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 17977 | #define mmDCORE2_SRAM7_BANK_BASE 0x45B8000ull |
|---|
| 17978 | #define DCORE2_SRAM7_BANK_MAX_OFFSET 0x1000 |
|---|
| 17979 | #define DCORE2_SRAM7_BANK_SECTION 0xE800 |
|---|
| 17980 | #define mmDCORE2_SRAM7_BANK_SPECIAL_BASE 0x45B8E80ull |
|---|
| 17981 | #define DCORE2_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17982 | #define DCORE2_SRAM7_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 17983 | #define mmDCORE2_SRAM7_RTR_BASE 0x45B9000ull |
|---|
| 17984 | #define DCORE2_SRAM7_RTR_MAX_OFFSET 0x1000 |
|---|
| 17985 | #define DCORE2_SRAM7_RTR_SECTION 0xE800 |
|---|
| 17986 | #define mmDCORE2_SRAM7_RTR_SPECIAL_BASE 0x45B9E80ull |
|---|
| 17987 | #define DCORE2_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 17988 | #define DCORE2_SRAM7_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 17989 | #define mmDCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x45BA000ull |
|---|
| 17990 | #define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17991 | #define DCORE2_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17992 | #define mmDCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x45BA100ull |
|---|
| 17993 | #define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17994 | #define DCORE2_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17995 | #define mmDCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x45BA200ull |
|---|
| 17996 | #define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 17997 | #define DCORE2_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 17998 | #define mmDCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x45BA300ull |
|---|
| 17999 | #define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 18000 | #define DCORE2_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 18001 | #define mmDCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x45BA400ull |
|---|
| 18002 | #define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 18003 | #define DCORE2_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 18004 | #define mmDCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x45BA500ull |
|---|
| 18005 | #define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 18006 | #define DCORE2_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 18007 | #define mmDCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x45BA600ull |
|---|
| 18008 | #define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 18009 | #define DCORE2_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 18010 | #define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA700ull |
|---|
| 18011 | #define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18012 | #define DCORE2_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18013 | #define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA780ull |
|---|
| 18014 | #define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18015 | #define DCORE2_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18016 | #define mmDCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x45BA800ull |
|---|
| 18017 | #define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18018 | #define DCORE2_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18019 | #define mmDCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x45BA880ull |
|---|
| 18020 | #define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18021 | #define DCORE2_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18022 | #define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x45BA900ull |
|---|
| 18023 | #define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18024 | #define DCORE2_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18025 | #define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x45BA980ull |
|---|
| 18026 | #define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18027 | #define DCORE2_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18028 | #define mmDCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x45BAA00ull |
|---|
| 18029 | #define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18030 | #define DCORE2_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 18031 | #define mmDCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x45BAA80ull |
|---|
| 18032 | #define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 18033 | #define DCORE2_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 18034 | #define mmDCORE2_SRAM7_DBG_CNT_SPECIAL_BASE 0x45BAE80ull |
|---|
| 18035 | #define DCORE2_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18036 | #define DCORE2_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 18037 | #define mmDCORE2_EDMA0_QM_DCCM_BASE 0x45C0000ull |
|---|
| 18038 | #define DCORE2_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 18039 | #define DCORE2_EDMA0_QM_DCCM_SECTION 0x8000 |
|---|
| 18040 | #define mmDCORE2_EDMA0_QM_ARC_AUX_BASE 0x45C8000ull |
|---|
| 18041 | #define DCORE2_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 18042 | #define DCORE2_EDMA0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 18043 | #define mmDCORE2_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x45C8E80ull |
|---|
| 18044 | #define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18045 | #define DCORE2_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 18046 | #define mmDCORE2_EDMA0_QM_BASE 0x45CA000ull |
|---|
| 18047 | #define DCORE2_EDMA0_QM_MAX_OFFSET 0x1000 |
|---|
| 18048 | #define DCORE2_EDMA0_QM_SECTION 0x9000 |
|---|
| 18049 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45CA900ull |
|---|
| 18050 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 18051 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 18052 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45CA908ull |
|---|
| 18053 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 18054 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 18055 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45CA910ull |
|---|
| 18056 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 18057 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 18058 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45CA918ull |
|---|
| 18059 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 18060 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 18061 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45CA920ull |
|---|
| 18062 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 18063 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 18064 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45CA928ull |
|---|
| 18065 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 18066 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 18067 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45CA930ull |
|---|
| 18068 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 18069 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 18070 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45CA938ull |
|---|
| 18071 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 18072 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 18073 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45CA940ull |
|---|
| 18074 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 18075 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 18076 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45CA948ull |
|---|
| 18077 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 18078 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 18079 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45CA950ull |
|---|
| 18080 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 18081 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 18082 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45CA958ull |
|---|
| 18083 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 18084 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 18085 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45CA960ull |
|---|
| 18086 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 18087 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 18088 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45CA968ull |
|---|
| 18089 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 18090 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 18091 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45CA970ull |
|---|
| 18092 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 18093 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 18094 | #define mmDCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45CA978ull |
|---|
| 18095 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 18096 | #define DCORE2_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 18097 | #define mmDCORE2_EDMA0_QM_AXUSER_SECURED_BASE 0x45CAB00ull |
|---|
| 18098 | #define DCORE2_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 18099 | #define DCORE2_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 18100 | #define mmDCORE2_EDMA0_QM_AXUSER_NONSECURED_BASE 0x45CAB80ull |
|---|
| 18101 | #define DCORE2_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 18102 | #define DCORE2_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 18103 | #define mmDCORE2_EDMA0_QM_DBG_HBW_BASE 0x45CAC00ull |
|---|
| 18104 | #define DCORE2_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18105 | #define DCORE2_EDMA0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 18106 | #define mmDCORE2_EDMA0_QM_DBG_LBW_BASE 0x45CAC80ull |
|---|
| 18107 | #define DCORE2_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18108 | #define DCORE2_EDMA0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 18109 | #define mmDCORE2_EDMA0_QM_CGM_BASE 0x45CAD80ull |
|---|
| 18110 | #define DCORE2_EDMA0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 18111 | #define DCORE2_EDMA0_QM_CGM_SECTION 0x1000 |
|---|
| 18112 | #define mmDCORE2_EDMA0_QM_SPECIAL_BASE 0x45CAE80ull |
|---|
| 18113 | #define DCORE2_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18114 | #define DCORE2_EDMA0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18115 | #define mmDCORE2_EDMA0_CORE_BASE 0x45CB000ull |
|---|
| 18116 | #define DCORE2_EDMA0_CORE_MAX_OFFSET 0x1000 |
|---|
| 18117 | #define DCORE2_EDMA0_CORE_SECTION 0x8000 |
|---|
| 18118 | #define mmDCORE2_EDMA0_CORE_CTX_AXUSER_BASE 0x45CB800ull |
|---|
| 18119 | #define DCORE2_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18120 | #define DCORE2_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 18121 | #define mmDCORE2_EDMA0_CORE_CTX_BASE 0x45CB860ull |
|---|
| 18122 | #define DCORE2_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 18123 | #define DCORE2_EDMA0_CORE_CTX_SECTION 0x5A00 |
|---|
| 18124 | #define mmDCORE2_EDMA0_CORE_KDMA_CGM_BASE 0x45CBE00ull |
|---|
| 18125 | #define DCORE2_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 18126 | #define DCORE2_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 18127 | #define mmDCORE2_EDMA0_CORE_SPECIAL_BASE 0x45CBE80ull |
|---|
| 18128 | #define DCORE2_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18129 | #define DCORE2_EDMA0_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 18130 | #define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x45CC000ull |
|---|
| 18131 | #define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18132 | #define DCORE2_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18133 | #define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x45CC200ull |
|---|
| 18134 | #define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18135 | #define DCORE2_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18136 | #define mmDCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x45CC400ull |
|---|
| 18137 | #define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18138 | #define DCORE2_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18139 | #define mmDCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x45CC600ull |
|---|
| 18140 | #define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18141 | #define DCORE2_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18142 | #define mmDCORE2_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x45CC800ull |
|---|
| 18143 | #define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18144 | #define DCORE2_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18145 | #define mmDCORE2_EDMA0_MSTR_IF_AXUSER_BASE 0x45CCA80ull |
|---|
| 18146 | #define DCORE2_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18147 | #define DCORE2_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18148 | #define mmDCORE2_EDMA0_MSTR_IF_DBG_HBW_BASE 0x45CCB00ull |
|---|
| 18149 | #define DCORE2_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18150 | #define DCORE2_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18151 | #define mmDCORE2_EDMA0_MSTR_IF_DBG_LBW_BASE 0x45CCB80ull |
|---|
| 18152 | #define DCORE2_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18153 | #define DCORE2_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18154 | #define mmDCORE2_EDMA0_MSTR_IF_CORE_HBW_BASE 0x45CCC00ull |
|---|
| 18155 | #define DCORE2_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18156 | #define DCORE2_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18157 | #define mmDCORE2_EDMA0_MSTR_IF_CORE_LBW_BASE 0x45CCD80ull |
|---|
| 18158 | #define DCORE2_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18159 | #define DCORE2_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18160 | #define mmDCORE2_EDMA0_MSTR_IF_SPECIAL_BASE 0x45CCE80ull |
|---|
| 18161 | #define DCORE2_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18162 | #define DCORE2_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 18163 | #define mmDCORE2_EDMA1_QM_DCCM_BASE 0x45D0000ull |
|---|
| 18164 | #define DCORE2_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 18165 | #define DCORE2_EDMA1_QM_DCCM_SECTION 0x8000 |
|---|
| 18166 | #define mmDCORE2_EDMA1_QM_ARC_AUX_BASE 0x45D8000ull |
|---|
| 18167 | #define DCORE2_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 18168 | #define DCORE2_EDMA1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 18169 | #define mmDCORE2_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x45D8E80ull |
|---|
| 18170 | #define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18171 | #define DCORE2_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 18172 | #define mmDCORE2_EDMA1_QM_BASE 0x45DA000ull |
|---|
| 18173 | #define DCORE2_EDMA1_QM_MAX_OFFSET 0x1000 |
|---|
| 18174 | #define DCORE2_EDMA1_QM_SECTION 0x9000 |
|---|
| 18175 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x45DA900ull |
|---|
| 18176 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 18177 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 18178 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x45DA908ull |
|---|
| 18179 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 18180 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 18181 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x45DA910ull |
|---|
| 18182 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 18183 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 18184 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x45DA918ull |
|---|
| 18185 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 18186 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 18187 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x45DA920ull |
|---|
| 18188 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 18189 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 18190 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x45DA928ull |
|---|
| 18191 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 18192 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 18193 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x45DA930ull |
|---|
| 18194 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 18195 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 18196 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x45DA938ull |
|---|
| 18197 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 18198 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 18199 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x45DA940ull |
|---|
| 18200 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 18201 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 18202 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x45DA948ull |
|---|
| 18203 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 18204 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 18205 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x45DA950ull |
|---|
| 18206 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 18207 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 18208 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x45DA958ull |
|---|
| 18209 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 18210 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 18211 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x45DA960ull |
|---|
| 18212 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 18213 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 18214 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x45DA968ull |
|---|
| 18215 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 18216 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 18217 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x45DA970ull |
|---|
| 18218 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 18219 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 18220 | #define mmDCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x45DA978ull |
|---|
| 18221 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 18222 | #define DCORE2_EDMA1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 18223 | #define mmDCORE2_EDMA1_QM_AXUSER_SECURED_BASE 0x45DAB00ull |
|---|
| 18224 | #define DCORE2_EDMA1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 18225 | #define DCORE2_EDMA1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 18226 | #define mmDCORE2_EDMA1_QM_AXUSER_NONSECURED_BASE 0x45DAB80ull |
|---|
| 18227 | #define DCORE2_EDMA1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 18228 | #define DCORE2_EDMA1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 18229 | #define mmDCORE2_EDMA1_QM_DBG_HBW_BASE 0x45DAC00ull |
|---|
| 18230 | #define DCORE2_EDMA1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18231 | #define DCORE2_EDMA1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 18232 | #define mmDCORE2_EDMA1_QM_DBG_LBW_BASE 0x45DAC80ull |
|---|
| 18233 | #define DCORE2_EDMA1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18234 | #define DCORE2_EDMA1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 18235 | #define mmDCORE2_EDMA1_QM_CGM_BASE 0x45DAD80ull |
|---|
| 18236 | #define DCORE2_EDMA1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 18237 | #define DCORE2_EDMA1_QM_CGM_SECTION 0x1000 |
|---|
| 18238 | #define mmDCORE2_EDMA1_QM_SPECIAL_BASE 0x45DAE80ull |
|---|
| 18239 | #define DCORE2_EDMA1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18240 | #define DCORE2_EDMA1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18241 | #define mmDCORE2_EDMA1_CORE_BASE 0x45DB000ull |
|---|
| 18242 | #define DCORE2_EDMA1_CORE_MAX_OFFSET 0x1000 |
|---|
| 18243 | #define DCORE2_EDMA1_CORE_SECTION 0x8000 |
|---|
| 18244 | #define mmDCORE2_EDMA1_CORE_CTX_AXUSER_BASE 0x45DB800ull |
|---|
| 18245 | #define DCORE2_EDMA1_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18246 | #define DCORE2_EDMA1_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 18247 | #define mmDCORE2_EDMA1_CORE_CTX_BASE 0x45DB860ull |
|---|
| 18248 | #define DCORE2_EDMA1_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 18249 | #define DCORE2_EDMA1_CORE_CTX_SECTION 0x5A00 |
|---|
| 18250 | #define mmDCORE2_EDMA1_CORE_KDMA_CGM_BASE 0x45DBE00ull |
|---|
| 18251 | #define DCORE2_EDMA1_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 18252 | #define DCORE2_EDMA1_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 18253 | #define mmDCORE2_EDMA1_CORE_SPECIAL_BASE 0x45DBE80ull |
|---|
| 18254 | #define DCORE2_EDMA1_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18255 | #define DCORE2_EDMA1_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 18256 | #define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_BASE 0x45DC000ull |
|---|
| 18257 | #define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18258 | #define DCORE2_EDMA1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18259 | #define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_BASE 0x45DC200ull |
|---|
| 18260 | #define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18261 | #define DCORE2_EDMA1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18262 | #define mmDCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_BASE 0x45DC400ull |
|---|
| 18263 | #define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18264 | #define DCORE2_EDMA1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18265 | #define mmDCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_BASE 0x45DC600ull |
|---|
| 18266 | #define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18267 | #define DCORE2_EDMA1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18268 | #define mmDCORE2_EDMA1_MSTR_IF_E2E_CRDT_BASE 0x45DC800ull |
|---|
| 18269 | #define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18270 | #define DCORE2_EDMA1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18271 | #define mmDCORE2_EDMA1_MSTR_IF_AXUSER_BASE 0x45DCA80ull |
|---|
| 18272 | #define DCORE2_EDMA1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18273 | #define DCORE2_EDMA1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18274 | #define mmDCORE2_EDMA1_MSTR_IF_DBG_HBW_BASE 0x45DCB00ull |
|---|
| 18275 | #define DCORE2_EDMA1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18276 | #define DCORE2_EDMA1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18277 | #define mmDCORE2_EDMA1_MSTR_IF_DBG_LBW_BASE 0x45DCB80ull |
|---|
| 18278 | #define DCORE2_EDMA1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18279 | #define DCORE2_EDMA1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18280 | #define mmDCORE2_EDMA1_MSTR_IF_CORE_HBW_BASE 0x45DCC00ull |
|---|
| 18281 | #define DCORE2_EDMA1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18282 | #define DCORE2_EDMA1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18283 | #define mmDCORE2_EDMA1_MSTR_IF_CORE_LBW_BASE 0x45DCD80ull |
|---|
| 18284 | #define DCORE2_EDMA1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18285 | #define DCORE2_EDMA1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18286 | #define mmDCORE2_EDMA1_MSTR_IF_SPECIAL_BASE 0x45DCE80ull |
|---|
| 18287 | #define DCORE2_EDMA1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18288 | #define DCORE2_EDMA1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 18289 | #define mmDCORE2_DEC0_CMD_BASE 0x45E0000ull |
|---|
| 18290 | #define DCORE2_DEC0_CMD_MAX_OFFSET 0x1100 |
|---|
| 18291 | #define DCORE2_DEC0_CMD_SECTION 0x1000 |
|---|
| 18292 | #define mmDCORE2_DEC0_VSI_BASE 0x45E1000ull |
|---|
| 18293 | #define DCORE2_DEC0_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 18294 | #define DCORE2_DEC0_VSI_SECTION 0x1000 |
|---|
| 18295 | #define mmDCORE2_DEC0_L2C_BASE 0x45E2000ull |
|---|
| 18296 | #define DCORE2_DEC0_L2C_MAX_OFFSET 0x39C0 |
|---|
| 18297 | #define DCORE2_DEC0_L2C_SECTION 0x1000 |
|---|
| 18298 | #define mmDCORE2_VDEC0_BRDG_CTRL_BASE 0x45E3000ull |
|---|
| 18299 | #define DCORE2_VDEC0_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 18300 | #define DCORE2_VDEC0_BRDG_CTRL_SECTION 0x8000 |
|---|
| 18301 | #define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45E3800ull |
|---|
| 18302 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 18303 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 18304 | #define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45E3900ull |
|---|
| 18305 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 18306 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 18307 | #define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45E3A00ull |
|---|
| 18308 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 18309 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 18310 | #define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45E3B00ull |
|---|
| 18311 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 18312 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 18313 | #define mmDCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_BASE 0x45E3C00ull |
|---|
| 18314 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 18315 | #define DCORE2_VDEC0_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 18316 | #define mmDCORE2_VDEC0_BRDG_CTRL_SPECIAL_BASE 0x45E3E80ull |
|---|
| 18317 | #define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18318 | #define DCORE2_VDEC0_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 18319 | #define mmDCORE2_VDEC0_CTRL_BASE 0x45E4000ull |
|---|
| 18320 | #define DCORE2_VDEC0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 18321 | #define DCORE2_VDEC0_CTRL_SECTION 0xE800 |
|---|
| 18322 | #define mmDCORE2_VDEC0_CTRL_SPECIAL_BASE 0x45E4E80ull |
|---|
| 18323 | #define DCORE2_VDEC0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18324 | #define DCORE2_VDEC0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 18325 | #define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_BASE 0x45E5000ull |
|---|
| 18326 | #define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18327 | #define DCORE2_VDEC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18328 | #define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_BASE 0x45E5200ull |
|---|
| 18329 | #define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18330 | #define DCORE2_VDEC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18331 | #define mmDCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_BASE 0x45E5400ull |
|---|
| 18332 | #define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18333 | #define DCORE2_VDEC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18334 | #define mmDCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_BASE 0x45E5600ull |
|---|
| 18335 | #define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18336 | #define DCORE2_VDEC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18337 | #define mmDCORE2_VDEC0_MSTR_IF_E2E_CRDT_BASE 0x45E5800ull |
|---|
| 18338 | #define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18339 | #define DCORE2_VDEC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18340 | #define mmDCORE2_VDEC0_MSTR_IF_AXUSER_BASE 0x45E5A80ull |
|---|
| 18341 | #define DCORE2_VDEC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18342 | #define DCORE2_VDEC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18343 | #define mmDCORE2_VDEC0_MSTR_IF_DBG_HBW_BASE 0x45E5B00ull |
|---|
| 18344 | #define DCORE2_VDEC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18345 | #define DCORE2_VDEC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18346 | #define mmDCORE2_VDEC0_MSTR_IF_DBG_LBW_BASE 0x45E5B80ull |
|---|
| 18347 | #define DCORE2_VDEC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18348 | #define DCORE2_VDEC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18349 | #define mmDCORE2_VDEC0_MSTR_IF_CORE_HBW_BASE 0x45E5C00ull |
|---|
| 18350 | #define DCORE2_VDEC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18351 | #define DCORE2_VDEC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18352 | #define mmDCORE2_VDEC0_MSTR_IF_CORE_LBW_BASE 0x45E5D80ull |
|---|
| 18353 | #define DCORE2_VDEC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18354 | #define DCORE2_VDEC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18355 | #define mmDCORE2_VDEC0_MSTR_IF_SPECIAL_BASE 0x45E5E80ull |
|---|
| 18356 | #define DCORE2_VDEC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18357 | #define DCORE2_VDEC0_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 18358 | #define mmDCORE2_DEC1_CMD_BASE 0x45F0000ull |
|---|
| 18359 | #define DCORE2_DEC1_CMD_MAX_OFFSET 0x1100 |
|---|
| 18360 | #define DCORE2_DEC1_CMD_SECTION 0x1000 |
|---|
| 18361 | #define mmDCORE2_DEC1_VSI_BASE 0x45F1000ull |
|---|
| 18362 | #define DCORE2_DEC1_VSI_MAX_OFFSET 0x6FC0 |
|---|
| 18363 | #define DCORE2_DEC1_VSI_SECTION 0x1000 |
|---|
| 18364 | #define mmDCORE2_DEC1_L2C_BASE 0x45F2000ull |
|---|
| 18365 | #define DCORE2_DEC1_L2C_MAX_OFFSET 0x39C0 |
|---|
| 18366 | #define DCORE2_DEC1_L2C_SECTION 0x1000 |
|---|
| 18367 | #define mmDCORE2_VDEC1_BRDG_CTRL_BASE 0x45F3000ull |
|---|
| 18368 | #define DCORE2_VDEC1_BRDG_CTRL_MAX_OFFSET 0x1000 |
|---|
| 18369 | #define DCORE2_VDEC1_BRDG_CTRL_SECTION 0x8000 |
|---|
| 18370 | #define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_BASE 0x45F3800ull |
|---|
| 18371 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_MAX_OFFSET 0x5000 |
|---|
| 18372 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_VCD_SECTION 0x1000 |
|---|
| 18373 | #define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_BASE 0x45F3900ull |
|---|
| 18374 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_MAX_OFFSET 0x5000 |
|---|
| 18375 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_L2C_SECTION 0x1000 |
|---|
| 18376 | #define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_BASE 0x45F3A00ull |
|---|
| 18377 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_MAX_OFFSET 0x5000 |
|---|
| 18378 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_NRM_SECTION 0x1000 |
|---|
| 18379 | #define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_BASE 0x45F3B00ull |
|---|
| 18380 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_MAX_OFFSET 0x5000 |
|---|
| 18381 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_MSIX_ABNRM_SECTION 0x1000 |
|---|
| 18382 | #define mmDCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_BASE 0x45F3C00ull |
|---|
| 18383 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_MAX_OFFSET 0x5000 |
|---|
| 18384 | #define DCORE2_VDEC1_BRDG_CTRL_AXUSER_DEC_SECTION 0x2800 |
|---|
| 18385 | #define mmDCORE2_VDEC1_BRDG_CTRL_SPECIAL_BASE 0x45F3E80ull |
|---|
| 18386 | #define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18387 | #define DCORE2_VDEC1_BRDG_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 18388 | #define mmDCORE2_VDEC1_CTRL_BASE 0x45F4000ull |
|---|
| 18389 | #define DCORE2_VDEC1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 18390 | #define DCORE2_VDEC1_CTRL_SECTION 0xE800 |
|---|
| 18391 | #define mmDCORE2_VDEC1_CTRL_SPECIAL_BASE 0x45F4E80ull |
|---|
| 18392 | #define DCORE2_VDEC1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18393 | #define DCORE2_VDEC1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 18394 | #define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_BASE 0x45F5000ull |
|---|
| 18395 | #define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18396 | #define DCORE2_VDEC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18397 | #define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_BASE 0x45F5200ull |
|---|
| 18398 | #define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18399 | #define DCORE2_VDEC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18400 | #define mmDCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_BASE 0x45F5400ull |
|---|
| 18401 | #define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18402 | #define DCORE2_VDEC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18403 | #define mmDCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_BASE 0x45F5600ull |
|---|
| 18404 | #define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18405 | #define DCORE2_VDEC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18406 | #define mmDCORE2_VDEC1_MSTR_IF_E2E_CRDT_BASE 0x45F5800ull |
|---|
| 18407 | #define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18408 | #define DCORE2_VDEC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18409 | #define mmDCORE2_VDEC1_MSTR_IF_AXUSER_BASE 0x45F5A80ull |
|---|
| 18410 | #define DCORE2_VDEC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18411 | #define DCORE2_VDEC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18412 | #define mmDCORE2_VDEC1_MSTR_IF_DBG_HBW_BASE 0x45F5B00ull |
|---|
| 18413 | #define DCORE2_VDEC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18414 | #define DCORE2_VDEC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18415 | #define mmDCORE2_VDEC1_MSTR_IF_DBG_LBW_BASE 0x45F5B80ull |
|---|
| 18416 | #define DCORE2_VDEC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18417 | #define DCORE2_VDEC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18418 | #define mmDCORE2_VDEC1_MSTR_IF_CORE_HBW_BASE 0x45F5C00ull |
|---|
| 18419 | #define DCORE2_VDEC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18420 | #define DCORE2_VDEC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18421 | #define mmDCORE2_VDEC1_MSTR_IF_CORE_LBW_BASE 0x45F5D80ull |
|---|
| 18422 | #define DCORE2_VDEC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18423 | #define DCORE2_VDEC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18424 | #define mmDCORE2_VDEC1_MSTR_IF_SPECIAL_BASE 0x45F5E80ull |
|---|
| 18425 | #define DCORE2_VDEC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18426 | #define DCORE2_VDEC1_MSTR_IF_SPECIAL_SECTION 0xA180 |
|---|
| 18427 | #define mmDCORE3_TPC0_QM_DCCM_BASE 0x4600000ull |
|---|
| 18428 | #define DCORE3_TPC0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 18429 | #define DCORE3_TPC0_QM_DCCM_SECTION 0x8000 |
|---|
| 18430 | #define mmDCORE3_TPC0_QM_ARC_AUX_BASE 0x4608000ull |
|---|
| 18431 | #define DCORE3_TPC0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 18432 | #define DCORE3_TPC0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 18433 | #define mmDCORE3_TPC0_QM_ARC_AUX_SPECIAL_BASE 0x4608E80ull |
|---|
| 18434 | #define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18435 | #define DCORE3_TPC0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 18436 | #define mmDCORE3_TPC0_QM_BASE 0x460A000ull |
|---|
| 18437 | #define DCORE3_TPC0_QM_MAX_OFFSET 0x1000 |
|---|
| 18438 | #define DCORE3_TPC0_QM_SECTION 0x9000 |
|---|
| 18439 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x460A900ull |
|---|
| 18440 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 18441 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 18442 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x460A908ull |
|---|
| 18443 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 18444 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 18445 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x460A910ull |
|---|
| 18446 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 18447 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 18448 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x460A918ull |
|---|
| 18449 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 18450 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 18451 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x460A920ull |
|---|
| 18452 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 18453 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 18454 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x460A928ull |
|---|
| 18455 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 18456 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 18457 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x460A930ull |
|---|
| 18458 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 18459 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 18460 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x460A938ull |
|---|
| 18461 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 18462 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 18463 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x460A940ull |
|---|
| 18464 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 18465 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 18466 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x460A948ull |
|---|
| 18467 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 18468 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 18469 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x460A950ull |
|---|
| 18470 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 18471 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 18472 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x460A958ull |
|---|
| 18473 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 18474 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 18475 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x460A960ull |
|---|
| 18476 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 18477 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 18478 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x460A968ull |
|---|
| 18479 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 18480 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 18481 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x460A970ull |
|---|
| 18482 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 18483 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 18484 | #define mmDCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x460A978ull |
|---|
| 18485 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 18486 | #define DCORE3_TPC0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 18487 | #define mmDCORE3_TPC0_QM_AXUSER_SECURED_BASE 0x460AB00ull |
|---|
| 18488 | #define DCORE3_TPC0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 18489 | #define DCORE3_TPC0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 18490 | #define mmDCORE3_TPC0_QM_AXUSER_NONSECURED_BASE 0x460AB80ull |
|---|
| 18491 | #define DCORE3_TPC0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 18492 | #define DCORE3_TPC0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 18493 | #define mmDCORE3_TPC0_QM_DBG_HBW_BASE 0x460AC00ull |
|---|
| 18494 | #define DCORE3_TPC0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18495 | #define DCORE3_TPC0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 18496 | #define mmDCORE3_TPC0_QM_DBG_LBW_BASE 0x460AC80ull |
|---|
| 18497 | #define DCORE3_TPC0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18498 | #define DCORE3_TPC0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 18499 | #define mmDCORE3_TPC0_QM_CGM_BASE 0x460AD80ull |
|---|
| 18500 | #define DCORE3_TPC0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 18501 | #define DCORE3_TPC0_QM_CGM_SECTION 0x1000 |
|---|
| 18502 | #define mmDCORE3_TPC0_QM_SPECIAL_BASE 0x460AE80ull |
|---|
| 18503 | #define DCORE3_TPC0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18504 | #define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18505 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_0_BASE 0x460B000ull |
|---|
| 18506 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 18507 | #define DCORE3_TPC0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18508 | #define mmDCORE3_TPC0_CFG_BASE 0x460B000ull |
|---|
| 18509 | #define DCORE3_TPC0_CFG_MAX_OFFSET 0x1000 |
|---|
| 18510 | #define DCORE3_TPC0_CFG_SECTION 0x5000 |
|---|
| 18511 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_1_BASE 0x460B050ull |
|---|
| 18512 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 18513 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 18514 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_2_BASE 0x460B0A0ull |
|---|
| 18515 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 18516 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 18517 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_3_BASE 0x460B0F0ull |
|---|
| 18518 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 18519 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 18520 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_4_BASE 0x460B140ull |
|---|
| 18521 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 18522 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 18523 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_5_BASE 0x460B190ull |
|---|
| 18524 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 18525 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 18526 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_6_BASE 0x460B1E0ull |
|---|
| 18527 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 18528 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 18529 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_7_BASE 0x460B230ull |
|---|
| 18530 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 18531 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 18532 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_8_BASE 0x460B280ull |
|---|
| 18533 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 18534 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 18535 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_9_BASE 0x460B2D0ull |
|---|
| 18536 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 18537 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 18538 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_10_BASE 0x460B320ull |
|---|
| 18539 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 18540 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 18541 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_11_BASE 0x460B370ull |
|---|
| 18542 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 18543 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 18544 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_12_BASE 0x460B3C0ull |
|---|
| 18545 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 18546 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 18547 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_13_BASE 0x460B410ull |
|---|
| 18548 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 18549 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 18550 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_14_BASE 0x460B460ull |
|---|
| 18551 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 18552 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 18553 | #define mmDCORE3_TPC0_CFG_KERNEL_TENSOR_15_BASE 0x460B4B0ull |
|---|
| 18554 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 18555 | #define DCORE3_TPC0_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 18556 | #define mmDCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_BASE 0x460B500ull |
|---|
| 18557 | #define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 18558 | #define DCORE3_TPC0_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 18559 | #define mmDCORE3_TPC0_CFG_KERNEL_BASE 0x460B508ull |
|---|
| 18560 | #define DCORE3_TPC0_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 18561 | #define DCORE3_TPC0_CFG_KERNEL_SECTION 0xD400 |
|---|
| 18562 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_0_BASE 0x460B5DCull |
|---|
| 18563 | #define DCORE3_TPC0_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 18564 | #define DCORE3_TPC0_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 18565 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_1_BASE 0x460B62Cull |
|---|
| 18566 | #define DCORE3_TPC0_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 18567 | #define DCORE3_TPC0_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 18568 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_2_BASE 0x460B67Cull |
|---|
| 18569 | #define DCORE3_TPC0_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 18570 | #define DCORE3_TPC0_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 18571 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_3_BASE 0x460B6CCull |
|---|
| 18572 | #define DCORE3_TPC0_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 18573 | #define DCORE3_TPC0_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 18574 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_4_BASE 0x460B71Cull |
|---|
| 18575 | #define DCORE3_TPC0_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 18576 | #define DCORE3_TPC0_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 18577 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_5_BASE 0x460B76Cull |
|---|
| 18578 | #define DCORE3_TPC0_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 18579 | #define DCORE3_TPC0_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 18580 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_6_BASE 0x460B7BCull |
|---|
| 18581 | #define DCORE3_TPC0_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 18582 | #define DCORE3_TPC0_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 18583 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_7_BASE 0x460B80Cull |
|---|
| 18584 | #define DCORE3_TPC0_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 18585 | #define DCORE3_TPC0_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 18586 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_8_BASE 0x460B85Cull |
|---|
| 18587 | #define DCORE3_TPC0_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 18588 | #define DCORE3_TPC0_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 18589 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_9_BASE 0x460B8ACull |
|---|
| 18590 | #define DCORE3_TPC0_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 18591 | #define DCORE3_TPC0_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 18592 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_10_BASE 0x460B8FCull |
|---|
| 18593 | #define DCORE3_TPC0_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 18594 | #define DCORE3_TPC0_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 18595 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_11_BASE 0x460B94Cull |
|---|
| 18596 | #define DCORE3_TPC0_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 18597 | #define DCORE3_TPC0_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 18598 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_12_BASE 0x460B99Cull |
|---|
| 18599 | #define DCORE3_TPC0_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 18600 | #define DCORE3_TPC0_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 18601 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_13_BASE 0x460B9ECull |
|---|
| 18602 | #define DCORE3_TPC0_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 18603 | #define DCORE3_TPC0_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 18604 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_14_BASE 0x460BA3Cull |
|---|
| 18605 | #define DCORE3_TPC0_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 18606 | #define DCORE3_TPC0_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 18607 | #define mmDCORE3_TPC0_CFG_QM_TENSOR_15_BASE 0x460BA8Cull |
|---|
| 18608 | #define DCORE3_TPC0_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 18609 | #define DCORE3_TPC0_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 18610 | #define mmDCORE3_TPC0_CFG_QM_SYNC_OBJECT_BASE 0x460BADCull |
|---|
| 18611 | #define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 18612 | #define DCORE3_TPC0_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 18613 | #define mmDCORE3_TPC0_CFG_QM_BASE 0x460BAE4ull |
|---|
| 18614 | #define DCORE3_TPC0_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 18615 | #define DCORE3_TPC0_CFG_QM_SECTION 0x31C0 |
|---|
| 18616 | #define mmDCORE3_TPC0_CFG_AXUSER_BASE 0x460BE00ull |
|---|
| 18617 | #define DCORE3_TPC0_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18618 | #define DCORE3_TPC0_CFG_AXUSER_SECTION 0x8000 |
|---|
| 18619 | #define mmDCORE3_TPC0_CFG_SPECIAL_BASE 0x460BE80ull |
|---|
| 18620 | #define DCORE3_TPC0_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18621 | #define DCORE3_TPC0_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 18622 | #define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_BASE 0x460C000ull |
|---|
| 18623 | #define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18624 | #define DCORE3_TPC0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18625 | #define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_BASE 0x460C200ull |
|---|
| 18626 | #define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18627 | #define DCORE3_TPC0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18628 | #define mmDCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_BASE 0x460C400ull |
|---|
| 18629 | #define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18630 | #define DCORE3_TPC0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18631 | #define mmDCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_BASE 0x460C600ull |
|---|
| 18632 | #define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18633 | #define DCORE3_TPC0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18634 | #define mmDCORE3_TPC0_MSTR_IF_E2E_CRDT_BASE 0x460C800ull |
|---|
| 18635 | #define DCORE3_TPC0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18636 | #define DCORE3_TPC0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18637 | #define mmDCORE3_TPC0_MSTR_IF_AXUSER_BASE 0x460CA80ull |
|---|
| 18638 | #define DCORE3_TPC0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18639 | #define DCORE3_TPC0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18640 | #define mmDCORE3_TPC0_MSTR_IF_DBG_HBW_BASE 0x460CB00ull |
|---|
| 18641 | #define DCORE3_TPC0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18642 | #define DCORE3_TPC0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18643 | #define mmDCORE3_TPC0_MSTR_IF_DBG_LBW_BASE 0x460CB80ull |
|---|
| 18644 | #define DCORE3_TPC0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18645 | #define DCORE3_TPC0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18646 | #define mmDCORE3_TPC0_MSTR_IF_CORE_HBW_BASE 0x460CC00ull |
|---|
| 18647 | #define DCORE3_TPC0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18648 | #define DCORE3_TPC0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18649 | #define mmDCORE3_TPC0_MSTR_IF_CORE_LBW_BASE 0x460CD80ull |
|---|
| 18650 | #define DCORE3_TPC0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18651 | #define DCORE3_TPC0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18652 | #define mmDCORE3_TPC0_MSTR_IF_SPECIAL_BASE 0x460CE80ull |
|---|
| 18653 | #define DCORE3_TPC0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18654 | #define DCORE3_TPC0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 18655 | #define mmDCORE3_TPC1_QM_DCCM_BASE 0x4610000ull |
|---|
| 18656 | #define DCORE3_TPC1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 18657 | #define DCORE3_TPC1_QM_DCCM_SECTION 0x8000 |
|---|
| 18658 | #define mmDCORE3_TPC1_QM_ARC_AUX_BASE 0x4618000ull |
|---|
| 18659 | #define DCORE3_TPC1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 18660 | #define DCORE3_TPC1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 18661 | #define mmDCORE3_TPC1_QM_ARC_AUX_SPECIAL_BASE 0x4618E80ull |
|---|
| 18662 | #define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18663 | #define DCORE3_TPC1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 18664 | #define mmDCORE3_TPC1_QM_BASE 0x461A000ull |
|---|
| 18665 | #define DCORE3_TPC1_QM_MAX_OFFSET 0x1000 |
|---|
| 18666 | #define DCORE3_TPC1_QM_SECTION 0x9000 |
|---|
| 18667 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x461A900ull |
|---|
| 18668 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 18669 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 18670 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x461A908ull |
|---|
| 18671 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 18672 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 18673 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x461A910ull |
|---|
| 18674 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 18675 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 18676 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x461A918ull |
|---|
| 18677 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 18678 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 18679 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x461A920ull |
|---|
| 18680 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 18681 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 18682 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x461A928ull |
|---|
| 18683 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 18684 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 18685 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x461A930ull |
|---|
| 18686 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 18687 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 18688 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x461A938ull |
|---|
| 18689 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 18690 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 18691 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_BASE 0x461A940ull |
|---|
| 18692 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 18693 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 18694 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_BASE 0x461A948ull |
|---|
| 18695 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 18696 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 18697 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_BASE 0x461A950ull |
|---|
| 18698 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 18699 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 18700 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_BASE 0x461A958ull |
|---|
| 18701 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 18702 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 18703 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_BASE 0x461A960ull |
|---|
| 18704 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 18705 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 18706 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_BASE 0x461A968ull |
|---|
| 18707 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 18708 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 18709 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_BASE 0x461A970ull |
|---|
| 18710 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 18711 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 18712 | #define mmDCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_BASE 0x461A978ull |
|---|
| 18713 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 18714 | #define DCORE3_TPC1_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 18715 | #define mmDCORE3_TPC1_QM_AXUSER_SECURED_BASE 0x461AB00ull |
|---|
| 18716 | #define DCORE3_TPC1_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 18717 | #define DCORE3_TPC1_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 18718 | #define mmDCORE3_TPC1_QM_AXUSER_NONSECURED_BASE 0x461AB80ull |
|---|
| 18719 | #define DCORE3_TPC1_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 18720 | #define DCORE3_TPC1_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 18721 | #define mmDCORE3_TPC1_QM_DBG_HBW_BASE 0x461AC00ull |
|---|
| 18722 | #define DCORE3_TPC1_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18723 | #define DCORE3_TPC1_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 18724 | #define mmDCORE3_TPC1_QM_DBG_LBW_BASE 0x461AC80ull |
|---|
| 18725 | #define DCORE3_TPC1_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18726 | #define DCORE3_TPC1_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 18727 | #define mmDCORE3_TPC1_QM_CGM_BASE 0x461AD80ull |
|---|
| 18728 | #define DCORE3_TPC1_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 18729 | #define DCORE3_TPC1_QM_CGM_SECTION 0x1000 |
|---|
| 18730 | #define mmDCORE3_TPC1_QM_SPECIAL_BASE 0x461AE80ull |
|---|
| 18731 | #define DCORE3_TPC1_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18732 | #define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18733 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_0_BASE 0x461B000ull |
|---|
| 18734 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 18735 | #define DCORE3_TPC1_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18736 | #define mmDCORE3_TPC1_CFG_BASE 0x461B000ull |
|---|
| 18737 | #define DCORE3_TPC1_CFG_MAX_OFFSET 0x1000 |
|---|
| 18738 | #define DCORE3_TPC1_CFG_SECTION 0x5000 |
|---|
| 18739 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_1_BASE 0x461B050ull |
|---|
| 18740 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 18741 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 18742 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_2_BASE 0x461B0A0ull |
|---|
| 18743 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 18744 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 18745 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_3_BASE 0x461B0F0ull |
|---|
| 18746 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 18747 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 18748 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_4_BASE 0x461B140ull |
|---|
| 18749 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 18750 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 18751 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_5_BASE 0x461B190ull |
|---|
| 18752 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 18753 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 18754 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_6_BASE 0x461B1E0ull |
|---|
| 18755 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 18756 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 18757 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_7_BASE 0x461B230ull |
|---|
| 18758 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 18759 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 18760 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_8_BASE 0x461B280ull |
|---|
| 18761 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 18762 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 18763 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_9_BASE 0x461B2D0ull |
|---|
| 18764 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 18765 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 18766 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_10_BASE 0x461B320ull |
|---|
| 18767 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 18768 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 18769 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_11_BASE 0x461B370ull |
|---|
| 18770 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 18771 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 18772 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_12_BASE 0x461B3C0ull |
|---|
| 18773 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 18774 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 18775 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_13_BASE 0x461B410ull |
|---|
| 18776 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 18777 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 18778 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_14_BASE 0x461B460ull |
|---|
| 18779 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 18780 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 18781 | #define mmDCORE3_TPC1_CFG_KERNEL_TENSOR_15_BASE 0x461B4B0ull |
|---|
| 18782 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 18783 | #define DCORE3_TPC1_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 18784 | #define mmDCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_BASE 0x461B500ull |
|---|
| 18785 | #define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 18786 | #define DCORE3_TPC1_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 18787 | #define mmDCORE3_TPC1_CFG_KERNEL_BASE 0x461B508ull |
|---|
| 18788 | #define DCORE3_TPC1_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 18789 | #define DCORE3_TPC1_CFG_KERNEL_SECTION 0xD400 |
|---|
| 18790 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_0_BASE 0x461B5DCull |
|---|
| 18791 | #define DCORE3_TPC1_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 18792 | #define DCORE3_TPC1_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 18793 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_1_BASE 0x461B62Cull |
|---|
| 18794 | #define DCORE3_TPC1_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 18795 | #define DCORE3_TPC1_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 18796 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_2_BASE 0x461B67Cull |
|---|
| 18797 | #define DCORE3_TPC1_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 18798 | #define DCORE3_TPC1_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 18799 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_3_BASE 0x461B6CCull |
|---|
| 18800 | #define DCORE3_TPC1_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 18801 | #define DCORE3_TPC1_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 18802 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_4_BASE 0x461B71Cull |
|---|
| 18803 | #define DCORE3_TPC1_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 18804 | #define DCORE3_TPC1_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 18805 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_5_BASE 0x461B76Cull |
|---|
| 18806 | #define DCORE3_TPC1_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 18807 | #define DCORE3_TPC1_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 18808 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_6_BASE 0x461B7BCull |
|---|
| 18809 | #define DCORE3_TPC1_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 18810 | #define DCORE3_TPC1_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 18811 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_7_BASE 0x461B80Cull |
|---|
| 18812 | #define DCORE3_TPC1_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 18813 | #define DCORE3_TPC1_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 18814 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_8_BASE 0x461B85Cull |
|---|
| 18815 | #define DCORE3_TPC1_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 18816 | #define DCORE3_TPC1_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 18817 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_9_BASE 0x461B8ACull |
|---|
| 18818 | #define DCORE3_TPC1_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 18819 | #define DCORE3_TPC1_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 18820 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_10_BASE 0x461B8FCull |
|---|
| 18821 | #define DCORE3_TPC1_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 18822 | #define DCORE3_TPC1_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 18823 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_11_BASE 0x461B94Cull |
|---|
| 18824 | #define DCORE3_TPC1_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 18825 | #define DCORE3_TPC1_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 18826 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_12_BASE 0x461B99Cull |
|---|
| 18827 | #define DCORE3_TPC1_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 18828 | #define DCORE3_TPC1_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 18829 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_13_BASE 0x461B9ECull |
|---|
| 18830 | #define DCORE3_TPC1_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 18831 | #define DCORE3_TPC1_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 18832 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_14_BASE 0x461BA3Cull |
|---|
| 18833 | #define DCORE3_TPC1_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 18834 | #define DCORE3_TPC1_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 18835 | #define mmDCORE3_TPC1_CFG_QM_TENSOR_15_BASE 0x461BA8Cull |
|---|
| 18836 | #define DCORE3_TPC1_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 18837 | #define DCORE3_TPC1_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 18838 | #define mmDCORE3_TPC1_CFG_QM_SYNC_OBJECT_BASE 0x461BADCull |
|---|
| 18839 | #define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 18840 | #define DCORE3_TPC1_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 18841 | #define mmDCORE3_TPC1_CFG_QM_BASE 0x461BAE4ull |
|---|
| 18842 | #define DCORE3_TPC1_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 18843 | #define DCORE3_TPC1_CFG_QM_SECTION 0x31C0 |
|---|
| 18844 | #define mmDCORE3_TPC1_CFG_AXUSER_BASE 0x461BE00ull |
|---|
| 18845 | #define DCORE3_TPC1_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18846 | #define DCORE3_TPC1_CFG_AXUSER_SECTION 0x8000 |
|---|
| 18847 | #define mmDCORE3_TPC1_CFG_SPECIAL_BASE 0x461BE80ull |
|---|
| 18848 | #define DCORE3_TPC1_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18849 | #define DCORE3_TPC1_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 18850 | #define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_BASE 0x461C000ull |
|---|
| 18851 | #define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18852 | #define DCORE3_TPC1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 18853 | #define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_BASE 0x461C200ull |
|---|
| 18854 | #define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 18855 | #define DCORE3_TPC1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 18856 | #define mmDCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_BASE 0x461C400ull |
|---|
| 18857 | #define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18858 | #define DCORE3_TPC1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 18859 | #define mmDCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_BASE 0x461C600ull |
|---|
| 18860 | #define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 18861 | #define DCORE3_TPC1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 18862 | #define mmDCORE3_TPC1_MSTR_IF_E2E_CRDT_BASE 0x461C800ull |
|---|
| 18863 | #define DCORE3_TPC1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 18864 | #define DCORE3_TPC1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 18865 | #define mmDCORE3_TPC1_MSTR_IF_AXUSER_BASE 0x461CA80ull |
|---|
| 18866 | #define DCORE3_TPC1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 18867 | #define DCORE3_TPC1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 18868 | #define mmDCORE3_TPC1_MSTR_IF_DBG_HBW_BASE 0x461CB00ull |
|---|
| 18869 | #define DCORE3_TPC1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18870 | #define DCORE3_TPC1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 18871 | #define mmDCORE3_TPC1_MSTR_IF_DBG_LBW_BASE 0x461CB80ull |
|---|
| 18872 | #define DCORE3_TPC1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18873 | #define DCORE3_TPC1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 18874 | #define mmDCORE3_TPC1_MSTR_IF_CORE_HBW_BASE 0x461CC00ull |
|---|
| 18875 | #define DCORE3_TPC1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 18876 | #define DCORE3_TPC1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 18877 | #define mmDCORE3_TPC1_MSTR_IF_CORE_LBW_BASE 0x461CD80ull |
|---|
| 18878 | #define DCORE3_TPC1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 18879 | #define DCORE3_TPC1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 18880 | #define mmDCORE3_TPC1_MSTR_IF_SPECIAL_BASE 0x461CE80ull |
|---|
| 18881 | #define DCORE3_TPC1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18882 | #define DCORE3_TPC1_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 18883 | #define mmDCORE3_TPC2_QM_DCCM_BASE 0x4620000ull |
|---|
| 18884 | #define DCORE3_TPC2_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 18885 | #define DCORE3_TPC2_QM_DCCM_SECTION 0x8000 |
|---|
| 18886 | #define mmDCORE3_TPC2_QM_ARC_AUX_BASE 0x4628000ull |
|---|
| 18887 | #define DCORE3_TPC2_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 18888 | #define DCORE3_TPC2_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 18889 | #define mmDCORE3_TPC2_QM_ARC_AUX_SPECIAL_BASE 0x4628E80ull |
|---|
| 18890 | #define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18891 | #define DCORE3_TPC2_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 18892 | #define mmDCORE3_TPC2_QM_BASE 0x462A000ull |
|---|
| 18893 | #define DCORE3_TPC2_QM_MAX_OFFSET 0x1000 |
|---|
| 18894 | #define DCORE3_TPC2_QM_SECTION 0x9000 |
|---|
| 18895 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_BASE 0x462A900ull |
|---|
| 18896 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 18897 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 18898 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_BASE 0x462A908ull |
|---|
| 18899 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 18900 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 18901 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_BASE 0x462A910ull |
|---|
| 18902 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 18903 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 18904 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_BASE 0x462A918ull |
|---|
| 18905 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 18906 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 18907 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_BASE 0x462A920ull |
|---|
| 18908 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 18909 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 18910 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_BASE 0x462A928ull |
|---|
| 18911 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 18912 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 18913 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_BASE 0x462A930ull |
|---|
| 18914 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 18915 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 18916 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_BASE 0x462A938ull |
|---|
| 18917 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 18918 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 18919 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_BASE 0x462A940ull |
|---|
| 18920 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 18921 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 18922 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_BASE 0x462A948ull |
|---|
| 18923 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 18924 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 18925 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_BASE 0x462A950ull |
|---|
| 18926 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 18927 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 18928 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_BASE 0x462A958ull |
|---|
| 18929 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 18930 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 18931 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_BASE 0x462A960ull |
|---|
| 18932 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 18933 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 18934 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_BASE 0x462A968ull |
|---|
| 18935 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 18936 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 18937 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_BASE 0x462A970ull |
|---|
| 18938 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 18939 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 18940 | #define mmDCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_BASE 0x462A978ull |
|---|
| 18941 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 18942 | #define DCORE3_TPC2_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 18943 | #define mmDCORE3_TPC2_QM_AXUSER_SECURED_BASE 0x462AB00ull |
|---|
| 18944 | #define DCORE3_TPC2_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 18945 | #define DCORE3_TPC2_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 18946 | #define mmDCORE3_TPC2_QM_AXUSER_NONSECURED_BASE 0x462AB80ull |
|---|
| 18947 | #define DCORE3_TPC2_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 18948 | #define DCORE3_TPC2_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 18949 | #define mmDCORE3_TPC2_QM_DBG_HBW_BASE 0x462AC00ull |
|---|
| 18950 | #define DCORE3_TPC2_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 18951 | #define DCORE3_TPC2_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 18952 | #define mmDCORE3_TPC2_QM_DBG_LBW_BASE 0x462AC80ull |
|---|
| 18953 | #define DCORE3_TPC2_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 18954 | #define DCORE3_TPC2_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 18955 | #define mmDCORE3_TPC2_QM_CGM_BASE 0x462AD80ull |
|---|
| 18956 | #define DCORE3_TPC2_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 18957 | #define DCORE3_TPC2_QM_CGM_SECTION 0x1000 |
|---|
| 18958 | #define mmDCORE3_TPC2_QM_SPECIAL_BASE 0x462AE80ull |
|---|
| 18959 | #define DCORE3_TPC2_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 18960 | #define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18961 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_0_BASE 0x462B000ull |
|---|
| 18962 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 18963 | #define DCORE3_TPC2_QM_SPECIAL_SECTION 0x1800 |
|---|
| 18964 | #define mmDCORE3_TPC2_CFG_BASE 0x462B000ull |
|---|
| 18965 | #define DCORE3_TPC2_CFG_MAX_OFFSET 0x1000 |
|---|
| 18966 | #define DCORE3_TPC2_CFG_SECTION 0x5000 |
|---|
| 18967 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_1_BASE 0x462B050ull |
|---|
| 18968 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 18969 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 18970 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_2_BASE 0x462B0A0ull |
|---|
| 18971 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 18972 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 18973 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_3_BASE 0x462B0F0ull |
|---|
| 18974 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 18975 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 18976 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_4_BASE 0x462B140ull |
|---|
| 18977 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 18978 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 18979 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_5_BASE 0x462B190ull |
|---|
| 18980 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 18981 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 18982 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_6_BASE 0x462B1E0ull |
|---|
| 18983 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 18984 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 18985 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_7_BASE 0x462B230ull |
|---|
| 18986 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 18987 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 18988 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_8_BASE 0x462B280ull |
|---|
| 18989 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 18990 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 18991 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_9_BASE 0x462B2D0ull |
|---|
| 18992 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 18993 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 18994 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_10_BASE 0x462B320ull |
|---|
| 18995 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 18996 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 18997 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_11_BASE 0x462B370ull |
|---|
| 18998 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 18999 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 19000 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_12_BASE 0x462B3C0ull |
|---|
| 19001 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19002 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 19003 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_13_BASE 0x462B410ull |
|---|
| 19004 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19005 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 19006 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_14_BASE 0x462B460ull |
|---|
| 19007 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19008 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 19009 | #define mmDCORE3_TPC2_CFG_KERNEL_TENSOR_15_BASE 0x462B4B0ull |
|---|
| 19010 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19011 | #define DCORE3_TPC2_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 19012 | #define mmDCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_BASE 0x462B500ull |
|---|
| 19013 | #define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19014 | #define DCORE3_TPC2_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19015 | #define mmDCORE3_TPC2_CFG_KERNEL_BASE 0x462B508ull |
|---|
| 19016 | #define DCORE3_TPC2_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 19017 | #define DCORE3_TPC2_CFG_KERNEL_SECTION 0xD400 |
|---|
| 19018 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_0_BASE 0x462B5DCull |
|---|
| 19019 | #define DCORE3_TPC2_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19020 | #define DCORE3_TPC2_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 19021 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_1_BASE 0x462B62Cull |
|---|
| 19022 | #define DCORE3_TPC2_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19023 | #define DCORE3_TPC2_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 19024 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_2_BASE 0x462B67Cull |
|---|
| 19025 | #define DCORE3_TPC2_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19026 | #define DCORE3_TPC2_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 19027 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_3_BASE 0x462B6CCull |
|---|
| 19028 | #define DCORE3_TPC2_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19029 | #define DCORE3_TPC2_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 19030 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_4_BASE 0x462B71Cull |
|---|
| 19031 | #define DCORE3_TPC2_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19032 | #define DCORE3_TPC2_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 19033 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_5_BASE 0x462B76Cull |
|---|
| 19034 | #define DCORE3_TPC2_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19035 | #define DCORE3_TPC2_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 19036 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_6_BASE 0x462B7BCull |
|---|
| 19037 | #define DCORE3_TPC2_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19038 | #define DCORE3_TPC2_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 19039 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_7_BASE 0x462B80Cull |
|---|
| 19040 | #define DCORE3_TPC2_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19041 | #define DCORE3_TPC2_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 19042 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_8_BASE 0x462B85Cull |
|---|
| 19043 | #define DCORE3_TPC2_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19044 | #define DCORE3_TPC2_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 19045 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_9_BASE 0x462B8ACull |
|---|
| 19046 | #define DCORE3_TPC2_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19047 | #define DCORE3_TPC2_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 19048 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_10_BASE 0x462B8FCull |
|---|
| 19049 | #define DCORE3_TPC2_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19050 | #define DCORE3_TPC2_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 19051 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_11_BASE 0x462B94Cull |
|---|
| 19052 | #define DCORE3_TPC2_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19053 | #define DCORE3_TPC2_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 19054 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_12_BASE 0x462B99Cull |
|---|
| 19055 | #define DCORE3_TPC2_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19056 | #define DCORE3_TPC2_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 19057 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_13_BASE 0x462B9ECull |
|---|
| 19058 | #define DCORE3_TPC2_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19059 | #define DCORE3_TPC2_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 19060 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_14_BASE 0x462BA3Cull |
|---|
| 19061 | #define DCORE3_TPC2_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19062 | #define DCORE3_TPC2_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 19063 | #define mmDCORE3_TPC2_CFG_QM_TENSOR_15_BASE 0x462BA8Cull |
|---|
| 19064 | #define DCORE3_TPC2_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19065 | #define DCORE3_TPC2_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 19066 | #define mmDCORE3_TPC2_CFG_QM_SYNC_OBJECT_BASE 0x462BADCull |
|---|
| 19067 | #define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19068 | #define DCORE3_TPC2_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19069 | #define mmDCORE3_TPC2_CFG_QM_BASE 0x462BAE4ull |
|---|
| 19070 | #define DCORE3_TPC2_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 19071 | #define DCORE3_TPC2_CFG_QM_SECTION 0x31C0 |
|---|
| 19072 | #define mmDCORE3_TPC2_CFG_AXUSER_BASE 0x462BE00ull |
|---|
| 19073 | #define DCORE3_TPC2_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19074 | #define DCORE3_TPC2_CFG_AXUSER_SECTION 0x8000 |
|---|
| 19075 | #define mmDCORE3_TPC2_CFG_SPECIAL_BASE 0x462BE80ull |
|---|
| 19076 | #define DCORE3_TPC2_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19077 | #define DCORE3_TPC2_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 19078 | #define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_BASE 0x462C000ull |
|---|
| 19079 | #define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19080 | #define DCORE3_TPC2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19081 | #define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_BASE 0x462C200ull |
|---|
| 19082 | #define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19083 | #define DCORE3_TPC2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19084 | #define mmDCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_BASE 0x462C400ull |
|---|
| 19085 | #define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19086 | #define DCORE3_TPC2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19087 | #define mmDCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_BASE 0x462C600ull |
|---|
| 19088 | #define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19089 | #define DCORE3_TPC2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19090 | #define mmDCORE3_TPC2_MSTR_IF_E2E_CRDT_BASE 0x462C800ull |
|---|
| 19091 | #define DCORE3_TPC2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19092 | #define DCORE3_TPC2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19093 | #define mmDCORE3_TPC2_MSTR_IF_AXUSER_BASE 0x462CA80ull |
|---|
| 19094 | #define DCORE3_TPC2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19095 | #define DCORE3_TPC2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19096 | #define mmDCORE3_TPC2_MSTR_IF_DBG_HBW_BASE 0x462CB00ull |
|---|
| 19097 | #define DCORE3_TPC2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19098 | #define DCORE3_TPC2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19099 | #define mmDCORE3_TPC2_MSTR_IF_DBG_LBW_BASE 0x462CB80ull |
|---|
| 19100 | #define DCORE3_TPC2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19101 | #define DCORE3_TPC2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19102 | #define mmDCORE3_TPC2_MSTR_IF_CORE_HBW_BASE 0x462CC00ull |
|---|
| 19103 | #define DCORE3_TPC2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19104 | #define DCORE3_TPC2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19105 | #define mmDCORE3_TPC2_MSTR_IF_CORE_LBW_BASE 0x462CD80ull |
|---|
| 19106 | #define DCORE3_TPC2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19107 | #define DCORE3_TPC2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19108 | #define mmDCORE3_TPC2_MSTR_IF_SPECIAL_BASE 0x462CE80ull |
|---|
| 19109 | #define DCORE3_TPC2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19110 | #define DCORE3_TPC2_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 19111 | #define mmDCORE3_TPC3_QM_DCCM_BASE 0x4630000ull |
|---|
| 19112 | #define DCORE3_TPC3_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 19113 | #define DCORE3_TPC3_QM_DCCM_SECTION 0x8000 |
|---|
| 19114 | #define mmDCORE3_TPC3_QM_ARC_AUX_BASE 0x4638000ull |
|---|
| 19115 | #define DCORE3_TPC3_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 19116 | #define DCORE3_TPC3_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 19117 | #define mmDCORE3_TPC3_QM_ARC_AUX_SPECIAL_BASE 0x4638E80ull |
|---|
| 19118 | #define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19119 | #define DCORE3_TPC3_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 19120 | #define mmDCORE3_TPC3_QM_BASE 0x463A000ull |
|---|
| 19121 | #define DCORE3_TPC3_QM_MAX_OFFSET 0x1000 |
|---|
| 19122 | #define DCORE3_TPC3_QM_SECTION 0x9000 |
|---|
| 19123 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_BASE 0x463A900ull |
|---|
| 19124 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 19125 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 19126 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_BASE 0x463A908ull |
|---|
| 19127 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 19128 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 19129 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_BASE 0x463A910ull |
|---|
| 19130 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 19131 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 19132 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_BASE 0x463A918ull |
|---|
| 19133 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 19134 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 19135 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_BASE 0x463A920ull |
|---|
| 19136 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 19137 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 19138 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_BASE 0x463A928ull |
|---|
| 19139 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 19140 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 19141 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_BASE 0x463A930ull |
|---|
| 19142 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 19143 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 19144 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_BASE 0x463A938ull |
|---|
| 19145 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 19146 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 19147 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_BASE 0x463A940ull |
|---|
| 19148 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 19149 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 19150 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_BASE 0x463A948ull |
|---|
| 19151 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 19152 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 19153 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_BASE 0x463A950ull |
|---|
| 19154 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 19155 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 19156 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_BASE 0x463A958ull |
|---|
| 19157 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 19158 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 19159 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_BASE 0x463A960ull |
|---|
| 19160 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 19161 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 19162 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_BASE 0x463A968ull |
|---|
| 19163 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 19164 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 19165 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_BASE 0x463A970ull |
|---|
| 19166 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 19167 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 19168 | #define mmDCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_BASE 0x463A978ull |
|---|
| 19169 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 19170 | #define DCORE3_TPC3_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 19171 | #define mmDCORE3_TPC3_QM_AXUSER_SECURED_BASE 0x463AB00ull |
|---|
| 19172 | #define DCORE3_TPC3_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 19173 | #define DCORE3_TPC3_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 19174 | #define mmDCORE3_TPC3_QM_AXUSER_NONSECURED_BASE 0x463AB80ull |
|---|
| 19175 | #define DCORE3_TPC3_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 19176 | #define DCORE3_TPC3_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 19177 | #define mmDCORE3_TPC3_QM_DBG_HBW_BASE 0x463AC00ull |
|---|
| 19178 | #define DCORE3_TPC3_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19179 | #define DCORE3_TPC3_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 19180 | #define mmDCORE3_TPC3_QM_DBG_LBW_BASE 0x463AC80ull |
|---|
| 19181 | #define DCORE3_TPC3_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19182 | #define DCORE3_TPC3_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 19183 | #define mmDCORE3_TPC3_QM_CGM_BASE 0x463AD80ull |
|---|
| 19184 | #define DCORE3_TPC3_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 19185 | #define DCORE3_TPC3_QM_CGM_SECTION 0x1000 |
|---|
| 19186 | #define mmDCORE3_TPC3_QM_SPECIAL_BASE 0x463AE80ull |
|---|
| 19187 | #define DCORE3_TPC3_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19188 | #define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19189 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_0_BASE 0x463B000ull |
|---|
| 19190 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19191 | #define DCORE3_TPC3_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19192 | #define mmDCORE3_TPC3_CFG_BASE 0x463B000ull |
|---|
| 19193 | #define DCORE3_TPC3_CFG_MAX_OFFSET 0x1000 |
|---|
| 19194 | #define DCORE3_TPC3_CFG_SECTION 0x5000 |
|---|
| 19195 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_1_BASE 0x463B050ull |
|---|
| 19196 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19197 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 19198 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_2_BASE 0x463B0A0ull |
|---|
| 19199 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19200 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 19201 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_3_BASE 0x463B0F0ull |
|---|
| 19202 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19203 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 19204 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_4_BASE 0x463B140ull |
|---|
| 19205 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19206 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 19207 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_5_BASE 0x463B190ull |
|---|
| 19208 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19209 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 19210 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_6_BASE 0x463B1E0ull |
|---|
| 19211 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19212 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 19213 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_7_BASE 0x463B230ull |
|---|
| 19214 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19215 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 19216 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_8_BASE 0x463B280ull |
|---|
| 19217 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19218 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 19219 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_9_BASE 0x463B2D0ull |
|---|
| 19220 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19221 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 19222 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_10_BASE 0x463B320ull |
|---|
| 19223 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19224 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 19225 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_11_BASE 0x463B370ull |
|---|
| 19226 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19227 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 19228 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_12_BASE 0x463B3C0ull |
|---|
| 19229 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19230 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 19231 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_13_BASE 0x463B410ull |
|---|
| 19232 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19233 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 19234 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_14_BASE 0x463B460ull |
|---|
| 19235 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19236 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 19237 | #define mmDCORE3_TPC3_CFG_KERNEL_TENSOR_15_BASE 0x463B4B0ull |
|---|
| 19238 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19239 | #define DCORE3_TPC3_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 19240 | #define mmDCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_BASE 0x463B500ull |
|---|
| 19241 | #define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19242 | #define DCORE3_TPC3_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19243 | #define mmDCORE3_TPC3_CFG_KERNEL_BASE 0x463B508ull |
|---|
| 19244 | #define DCORE3_TPC3_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 19245 | #define DCORE3_TPC3_CFG_KERNEL_SECTION 0xD400 |
|---|
| 19246 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_0_BASE 0x463B5DCull |
|---|
| 19247 | #define DCORE3_TPC3_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19248 | #define DCORE3_TPC3_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 19249 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_1_BASE 0x463B62Cull |
|---|
| 19250 | #define DCORE3_TPC3_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19251 | #define DCORE3_TPC3_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 19252 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_2_BASE 0x463B67Cull |
|---|
| 19253 | #define DCORE3_TPC3_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19254 | #define DCORE3_TPC3_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 19255 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_3_BASE 0x463B6CCull |
|---|
| 19256 | #define DCORE3_TPC3_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19257 | #define DCORE3_TPC3_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 19258 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_4_BASE 0x463B71Cull |
|---|
| 19259 | #define DCORE3_TPC3_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19260 | #define DCORE3_TPC3_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 19261 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_5_BASE 0x463B76Cull |
|---|
| 19262 | #define DCORE3_TPC3_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19263 | #define DCORE3_TPC3_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 19264 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_6_BASE 0x463B7BCull |
|---|
| 19265 | #define DCORE3_TPC3_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19266 | #define DCORE3_TPC3_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 19267 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_7_BASE 0x463B80Cull |
|---|
| 19268 | #define DCORE3_TPC3_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19269 | #define DCORE3_TPC3_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 19270 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_8_BASE 0x463B85Cull |
|---|
| 19271 | #define DCORE3_TPC3_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19272 | #define DCORE3_TPC3_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 19273 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_9_BASE 0x463B8ACull |
|---|
| 19274 | #define DCORE3_TPC3_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19275 | #define DCORE3_TPC3_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 19276 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_10_BASE 0x463B8FCull |
|---|
| 19277 | #define DCORE3_TPC3_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19278 | #define DCORE3_TPC3_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 19279 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_11_BASE 0x463B94Cull |
|---|
| 19280 | #define DCORE3_TPC3_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19281 | #define DCORE3_TPC3_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 19282 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_12_BASE 0x463B99Cull |
|---|
| 19283 | #define DCORE3_TPC3_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19284 | #define DCORE3_TPC3_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 19285 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_13_BASE 0x463B9ECull |
|---|
| 19286 | #define DCORE3_TPC3_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19287 | #define DCORE3_TPC3_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 19288 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_14_BASE 0x463BA3Cull |
|---|
| 19289 | #define DCORE3_TPC3_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19290 | #define DCORE3_TPC3_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 19291 | #define mmDCORE3_TPC3_CFG_QM_TENSOR_15_BASE 0x463BA8Cull |
|---|
| 19292 | #define DCORE3_TPC3_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19293 | #define DCORE3_TPC3_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 19294 | #define mmDCORE3_TPC3_CFG_QM_SYNC_OBJECT_BASE 0x463BADCull |
|---|
| 19295 | #define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19296 | #define DCORE3_TPC3_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19297 | #define mmDCORE3_TPC3_CFG_QM_BASE 0x463BAE4ull |
|---|
| 19298 | #define DCORE3_TPC3_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 19299 | #define DCORE3_TPC3_CFG_QM_SECTION 0x31C0 |
|---|
| 19300 | #define mmDCORE3_TPC3_CFG_AXUSER_BASE 0x463BE00ull |
|---|
| 19301 | #define DCORE3_TPC3_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19302 | #define DCORE3_TPC3_CFG_AXUSER_SECTION 0x8000 |
|---|
| 19303 | #define mmDCORE3_TPC3_CFG_SPECIAL_BASE 0x463BE80ull |
|---|
| 19304 | #define DCORE3_TPC3_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19305 | #define DCORE3_TPC3_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 19306 | #define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_BASE 0x463C000ull |
|---|
| 19307 | #define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19308 | #define DCORE3_TPC3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19309 | #define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_BASE 0x463C200ull |
|---|
| 19310 | #define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19311 | #define DCORE3_TPC3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19312 | #define mmDCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_BASE 0x463C400ull |
|---|
| 19313 | #define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19314 | #define DCORE3_TPC3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19315 | #define mmDCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_BASE 0x463C600ull |
|---|
| 19316 | #define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19317 | #define DCORE3_TPC3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19318 | #define mmDCORE3_TPC3_MSTR_IF_E2E_CRDT_BASE 0x463C800ull |
|---|
| 19319 | #define DCORE3_TPC3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19320 | #define DCORE3_TPC3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19321 | #define mmDCORE3_TPC3_MSTR_IF_AXUSER_BASE 0x463CA80ull |
|---|
| 19322 | #define DCORE3_TPC3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19323 | #define DCORE3_TPC3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19324 | #define mmDCORE3_TPC3_MSTR_IF_DBG_HBW_BASE 0x463CB00ull |
|---|
| 19325 | #define DCORE3_TPC3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19326 | #define DCORE3_TPC3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19327 | #define mmDCORE3_TPC3_MSTR_IF_DBG_LBW_BASE 0x463CB80ull |
|---|
| 19328 | #define DCORE3_TPC3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19329 | #define DCORE3_TPC3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19330 | #define mmDCORE3_TPC3_MSTR_IF_CORE_HBW_BASE 0x463CC00ull |
|---|
| 19331 | #define DCORE3_TPC3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19332 | #define DCORE3_TPC3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19333 | #define mmDCORE3_TPC3_MSTR_IF_CORE_LBW_BASE 0x463CD80ull |
|---|
| 19334 | #define DCORE3_TPC3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19335 | #define DCORE3_TPC3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19336 | #define mmDCORE3_TPC3_MSTR_IF_SPECIAL_BASE 0x463CE80ull |
|---|
| 19337 | #define DCORE3_TPC3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19338 | #define DCORE3_TPC3_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 19339 | #define mmDCORE3_TPC4_QM_DCCM_BASE 0x4640000ull |
|---|
| 19340 | #define DCORE3_TPC4_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 19341 | #define DCORE3_TPC4_QM_DCCM_SECTION 0x8000 |
|---|
| 19342 | #define mmDCORE3_TPC4_QM_ARC_AUX_BASE 0x4648000ull |
|---|
| 19343 | #define DCORE3_TPC4_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 19344 | #define DCORE3_TPC4_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 19345 | #define mmDCORE3_TPC4_QM_ARC_AUX_SPECIAL_BASE 0x4648E80ull |
|---|
| 19346 | #define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19347 | #define DCORE3_TPC4_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 19348 | #define mmDCORE3_TPC4_QM_BASE 0x464A000ull |
|---|
| 19349 | #define DCORE3_TPC4_QM_MAX_OFFSET 0x1000 |
|---|
| 19350 | #define DCORE3_TPC4_QM_SECTION 0x9000 |
|---|
| 19351 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_BASE 0x464A900ull |
|---|
| 19352 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 19353 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 19354 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_BASE 0x464A908ull |
|---|
| 19355 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 19356 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 19357 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_BASE 0x464A910ull |
|---|
| 19358 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 19359 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 19360 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_BASE 0x464A918ull |
|---|
| 19361 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 19362 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 19363 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_BASE 0x464A920ull |
|---|
| 19364 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 19365 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 19366 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_BASE 0x464A928ull |
|---|
| 19367 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 19368 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 19369 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_BASE 0x464A930ull |
|---|
| 19370 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 19371 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 19372 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_BASE 0x464A938ull |
|---|
| 19373 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 19374 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 19375 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_BASE 0x464A940ull |
|---|
| 19376 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 19377 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 19378 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_BASE 0x464A948ull |
|---|
| 19379 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 19380 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 19381 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_BASE 0x464A950ull |
|---|
| 19382 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 19383 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 19384 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_BASE 0x464A958ull |
|---|
| 19385 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 19386 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 19387 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_BASE 0x464A960ull |
|---|
| 19388 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 19389 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 19390 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_BASE 0x464A968ull |
|---|
| 19391 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 19392 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 19393 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_BASE 0x464A970ull |
|---|
| 19394 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 19395 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 19396 | #define mmDCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_BASE 0x464A978ull |
|---|
| 19397 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 19398 | #define DCORE3_TPC4_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 19399 | #define mmDCORE3_TPC4_QM_AXUSER_SECURED_BASE 0x464AB00ull |
|---|
| 19400 | #define DCORE3_TPC4_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 19401 | #define DCORE3_TPC4_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 19402 | #define mmDCORE3_TPC4_QM_AXUSER_NONSECURED_BASE 0x464AB80ull |
|---|
| 19403 | #define DCORE3_TPC4_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 19404 | #define DCORE3_TPC4_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 19405 | #define mmDCORE3_TPC4_QM_DBG_HBW_BASE 0x464AC00ull |
|---|
| 19406 | #define DCORE3_TPC4_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19407 | #define DCORE3_TPC4_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 19408 | #define mmDCORE3_TPC4_QM_DBG_LBW_BASE 0x464AC80ull |
|---|
| 19409 | #define DCORE3_TPC4_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19410 | #define DCORE3_TPC4_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 19411 | #define mmDCORE3_TPC4_QM_CGM_BASE 0x464AD80ull |
|---|
| 19412 | #define DCORE3_TPC4_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 19413 | #define DCORE3_TPC4_QM_CGM_SECTION 0x1000 |
|---|
| 19414 | #define mmDCORE3_TPC4_QM_SPECIAL_BASE 0x464AE80ull |
|---|
| 19415 | #define DCORE3_TPC4_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19416 | #define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19417 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_0_BASE 0x464B000ull |
|---|
| 19418 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19419 | #define DCORE3_TPC4_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19420 | #define mmDCORE3_TPC4_CFG_BASE 0x464B000ull |
|---|
| 19421 | #define DCORE3_TPC4_CFG_MAX_OFFSET 0x1000 |
|---|
| 19422 | #define DCORE3_TPC4_CFG_SECTION 0x5000 |
|---|
| 19423 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_1_BASE 0x464B050ull |
|---|
| 19424 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19425 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 19426 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_2_BASE 0x464B0A0ull |
|---|
| 19427 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19428 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 19429 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_3_BASE 0x464B0F0ull |
|---|
| 19430 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19431 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 19432 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_4_BASE 0x464B140ull |
|---|
| 19433 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19434 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 19435 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_5_BASE 0x464B190ull |
|---|
| 19436 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19437 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 19438 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_6_BASE 0x464B1E0ull |
|---|
| 19439 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19440 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 19441 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_7_BASE 0x464B230ull |
|---|
| 19442 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19443 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 19444 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_8_BASE 0x464B280ull |
|---|
| 19445 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19446 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 19447 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_9_BASE 0x464B2D0ull |
|---|
| 19448 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19449 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 19450 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_10_BASE 0x464B320ull |
|---|
| 19451 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19452 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 19453 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_11_BASE 0x464B370ull |
|---|
| 19454 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19455 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 19456 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_12_BASE 0x464B3C0ull |
|---|
| 19457 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19458 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 19459 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_13_BASE 0x464B410ull |
|---|
| 19460 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19461 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 19462 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_14_BASE 0x464B460ull |
|---|
| 19463 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19464 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 19465 | #define mmDCORE3_TPC4_CFG_KERNEL_TENSOR_15_BASE 0x464B4B0ull |
|---|
| 19466 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19467 | #define DCORE3_TPC4_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 19468 | #define mmDCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_BASE 0x464B500ull |
|---|
| 19469 | #define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19470 | #define DCORE3_TPC4_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19471 | #define mmDCORE3_TPC4_CFG_KERNEL_BASE 0x464B508ull |
|---|
| 19472 | #define DCORE3_TPC4_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 19473 | #define DCORE3_TPC4_CFG_KERNEL_SECTION 0xD400 |
|---|
| 19474 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_0_BASE 0x464B5DCull |
|---|
| 19475 | #define DCORE3_TPC4_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19476 | #define DCORE3_TPC4_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 19477 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_1_BASE 0x464B62Cull |
|---|
| 19478 | #define DCORE3_TPC4_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19479 | #define DCORE3_TPC4_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 19480 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_2_BASE 0x464B67Cull |
|---|
| 19481 | #define DCORE3_TPC4_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19482 | #define DCORE3_TPC4_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 19483 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_3_BASE 0x464B6CCull |
|---|
| 19484 | #define DCORE3_TPC4_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19485 | #define DCORE3_TPC4_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 19486 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_4_BASE 0x464B71Cull |
|---|
| 19487 | #define DCORE3_TPC4_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19488 | #define DCORE3_TPC4_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 19489 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_5_BASE 0x464B76Cull |
|---|
| 19490 | #define DCORE3_TPC4_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19491 | #define DCORE3_TPC4_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 19492 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_6_BASE 0x464B7BCull |
|---|
| 19493 | #define DCORE3_TPC4_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19494 | #define DCORE3_TPC4_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 19495 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_7_BASE 0x464B80Cull |
|---|
| 19496 | #define DCORE3_TPC4_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19497 | #define DCORE3_TPC4_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 19498 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_8_BASE 0x464B85Cull |
|---|
| 19499 | #define DCORE3_TPC4_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19500 | #define DCORE3_TPC4_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 19501 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_9_BASE 0x464B8ACull |
|---|
| 19502 | #define DCORE3_TPC4_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19503 | #define DCORE3_TPC4_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 19504 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_10_BASE 0x464B8FCull |
|---|
| 19505 | #define DCORE3_TPC4_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19506 | #define DCORE3_TPC4_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 19507 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_11_BASE 0x464B94Cull |
|---|
| 19508 | #define DCORE3_TPC4_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19509 | #define DCORE3_TPC4_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 19510 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_12_BASE 0x464B99Cull |
|---|
| 19511 | #define DCORE3_TPC4_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19512 | #define DCORE3_TPC4_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 19513 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_13_BASE 0x464B9ECull |
|---|
| 19514 | #define DCORE3_TPC4_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19515 | #define DCORE3_TPC4_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 19516 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_14_BASE 0x464BA3Cull |
|---|
| 19517 | #define DCORE3_TPC4_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19518 | #define DCORE3_TPC4_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 19519 | #define mmDCORE3_TPC4_CFG_QM_TENSOR_15_BASE 0x464BA8Cull |
|---|
| 19520 | #define DCORE3_TPC4_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19521 | #define DCORE3_TPC4_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 19522 | #define mmDCORE3_TPC4_CFG_QM_SYNC_OBJECT_BASE 0x464BADCull |
|---|
| 19523 | #define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19524 | #define DCORE3_TPC4_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19525 | #define mmDCORE3_TPC4_CFG_QM_BASE 0x464BAE4ull |
|---|
| 19526 | #define DCORE3_TPC4_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 19527 | #define DCORE3_TPC4_CFG_QM_SECTION 0x31C0 |
|---|
| 19528 | #define mmDCORE3_TPC4_CFG_AXUSER_BASE 0x464BE00ull |
|---|
| 19529 | #define DCORE3_TPC4_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19530 | #define DCORE3_TPC4_CFG_AXUSER_SECTION 0x8000 |
|---|
| 19531 | #define mmDCORE3_TPC4_CFG_SPECIAL_BASE 0x464BE80ull |
|---|
| 19532 | #define DCORE3_TPC4_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19533 | #define DCORE3_TPC4_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 19534 | #define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_BASE 0x464C000ull |
|---|
| 19535 | #define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19536 | #define DCORE3_TPC4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19537 | #define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_BASE 0x464C200ull |
|---|
| 19538 | #define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19539 | #define DCORE3_TPC4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19540 | #define mmDCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_BASE 0x464C400ull |
|---|
| 19541 | #define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19542 | #define DCORE3_TPC4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19543 | #define mmDCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_BASE 0x464C600ull |
|---|
| 19544 | #define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19545 | #define DCORE3_TPC4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19546 | #define mmDCORE3_TPC4_MSTR_IF_E2E_CRDT_BASE 0x464C800ull |
|---|
| 19547 | #define DCORE3_TPC4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19548 | #define DCORE3_TPC4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19549 | #define mmDCORE3_TPC4_MSTR_IF_AXUSER_BASE 0x464CA80ull |
|---|
| 19550 | #define DCORE3_TPC4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19551 | #define DCORE3_TPC4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19552 | #define mmDCORE3_TPC4_MSTR_IF_DBG_HBW_BASE 0x464CB00ull |
|---|
| 19553 | #define DCORE3_TPC4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19554 | #define DCORE3_TPC4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19555 | #define mmDCORE3_TPC4_MSTR_IF_DBG_LBW_BASE 0x464CB80ull |
|---|
| 19556 | #define DCORE3_TPC4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19557 | #define DCORE3_TPC4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19558 | #define mmDCORE3_TPC4_MSTR_IF_CORE_HBW_BASE 0x464CC00ull |
|---|
| 19559 | #define DCORE3_TPC4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19560 | #define DCORE3_TPC4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19561 | #define mmDCORE3_TPC4_MSTR_IF_CORE_LBW_BASE 0x464CD80ull |
|---|
| 19562 | #define DCORE3_TPC4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19563 | #define DCORE3_TPC4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19564 | #define mmDCORE3_TPC4_MSTR_IF_SPECIAL_BASE 0x464CE80ull |
|---|
| 19565 | #define DCORE3_TPC4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19566 | #define DCORE3_TPC4_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 19567 | #define mmDCORE3_TPC5_QM_DCCM_BASE 0x4650000ull |
|---|
| 19568 | #define DCORE3_TPC5_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 19569 | #define DCORE3_TPC5_QM_DCCM_SECTION 0x8000 |
|---|
| 19570 | #define mmDCORE3_TPC5_QM_ARC_AUX_BASE 0x4658000ull |
|---|
| 19571 | #define DCORE3_TPC5_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 19572 | #define DCORE3_TPC5_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 19573 | #define mmDCORE3_TPC5_QM_ARC_AUX_SPECIAL_BASE 0x4658E80ull |
|---|
| 19574 | #define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19575 | #define DCORE3_TPC5_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 19576 | #define mmDCORE3_TPC5_QM_BASE 0x465A000ull |
|---|
| 19577 | #define DCORE3_TPC5_QM_MAX_OFFSET 0x1000 |
|---|
| 19578 | #define DCORE3_TPC5_QM_SECTION 0x9000 |
|---|
| 19579 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_BASE 0x465A900ull |
|---|
| 19580 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 19581 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 19582 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_BASE 0x465A908ull |
|---|
| 19583 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 19584 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 19585 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_BASE 0x465A910ull |
|---|
| 19586 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 19587 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 19588 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_BASE 0x465A918ull |
|---|
| 19589 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 19590 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 19591 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_BASE 0x465A920ull |
|---|
| 19592 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 19593 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 19594 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_BASE 0x465A928ull |
|---|
| 19595 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 19596 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 19597 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_BASE 0x465A930ull |
|---|
| 19598 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 19599 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 19600 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_BASE 0x465A938ull |
|---|
| 19601 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 19602 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 19603 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_BASE 0x465A940ull |
|---|
| 19604 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 19605 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 19606 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_BASE 0x465A948ull |
|---|
| 19607 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 19608 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 19609 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_BASE 0x465A950ull |
|---|
| 19610 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 19611 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 19612 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_BASE 0x465A958ull |
|---|
| 19613 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 19614 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 19615 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_BASE 0x465A960ull |
|---|
| 19616 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 19617 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 19618 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_BASE 0x465A968ull |
|---|
| 19619 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 19620 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 19621 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_BASE 0x465A970ull |
|---|
| 19622 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 19623 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 19624 | #define mmDCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_BASE 0x465A978ull |
|---|
| 19625 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 19626 | #define DCORE3_TPC5_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 19627 | #define mmDCORE3_TPC5_QM_AXUSER_SECURED_BASE 0x465AB00ull |
|---|
| 19628 | #define DCORE3_TPC5_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 19629 | #define DCORE3_TPC5_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 19630 | #define mmDCORE3_TPC5_QM_AXUSER_NONSECURED_BASE 0x465AB80ull |
|---|
| 19631 | #define DCORE3_TPC5_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 19632 | #define DCORE3_TPC5_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 19633 | #define mmDCORE3_TPC5_QM_DBG_HBW_BASE 0x465AC00ull |
|---|
| 19634 | #define DCORE3_TPC5_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19635 | #define DCORE3_TPC5_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 19636 | #define mmDCORE3_TPC5_QM_DBG_LBW_BASE 0x465AC80ull |
|---|
| 19637 | #define DCORE3_TPC5_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19638 | #define DCORE3_TPC5_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 19639 | #define mmDCORE3_TPC5_QM_CGM_BASE 0x465AD80ull |
|---|
| 19640 | #define DCORE3_TPC5_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 19641 | #define DCORE3_TPC5_QM_CGM_SECTION 0x1000 |
|---|
| 19642 | #define mmDCORE3_TPC5_QM_SPECIAL_BASE 0x465AE80ull |
|---|
| 19643 | #define DCORE3_TPC5_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19644 | #define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19645 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_0_BASE 0x465B000ull |
|---|
| 19646 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19647 | #define DCORE3_TPC5_QM_SPECIAL_SECTION 0x1800 |
|---|
| 19648 | #define mmDCORE3_TPC5_CFG_BASE 0x465B000ull |
|---|
| 19649 | #define DCORE3_TPC5_CFG_MAX_OFFSET 0x1000 |
|---|
| 19650 | #define DCORE3_TPC5_CFG_SECTION 0x5000 |
|---|
| 19651 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_1_BASE 0x465B050ull |
|---|
| 19652 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19653 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_1_SECTION 0x5000 |
|---|
| 19654 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_2_BASE 0x465B0A0ull |
|---|
| 19655 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19656 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_2_SECTION 0x5000 |
|---|
| 19657 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_3_BASE 0x465B0F0ull |
|---|
| 19658 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19659 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_3_SECTION 0x5000 |
|---|
| 19660 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_4_BASE 0x465B140ull |
|---|
| 19661 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19662 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_4_SECTION 0x5000 |
|---|
| 19663 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_5_BASE 0x465B190ull |
|---|
| 19664 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19665 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_5_SECTION 0x5000 |
|---|
| 19666 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_6_BASE 0x465B1E0ull |
|---|
| 19667 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19668 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_6_SECTION 0x5000 |
|---|
| 19669 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_7_BASE 0x465B230ull |
|---|
| 19670 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19671 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_7_SECTION 0x5000 |
|---|
| 19672 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_8_BASE 0x465B280ull |
|---|
| 19673 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19674 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_8_SECTION 0x5000 |
|---|
| 19675 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_9_BASE 0x465B2D0ull |
|---|
| 19676 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19677 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_9_SECTION 0x5000 |
|---|
| 19678 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_10_BASE 0x465B320ull |
|---|
| 19679 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19680 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_10_SECTION 0x5000 |
|---|
| 19681 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_11_BASE 0x465B370ull |
|---|
| 19682 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19683 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_11_SECTION 0x5000 |
|---|
| 19684 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_12_BASE 0x465B3C0ull |
|---|
| 19685 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19686 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_12_SECTION 0x5000 |
|---|
| 19687 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_13_BASE 0x465B410ull |
|---|
| 19688 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19689 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_13_SECTION 0x5000 |
|---|
| 19690 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_14_BASE 0x465B460ull |
|---|
| 19691 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19692 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_14_SECTION 0x5000 |
|---|
| 19693 | #define mmDCORE3_TPC5_CFG_KERNEL_TENSOR_15_BASE 0x465B4B0ull |
|---|
| 19694 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19695 | #define DCORE3_TPC5_CFG_KERNEL_TENSOR_15_SECTION 0x5000 |
|---|
| 19696 | #define mmDCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_BASE 0x465B500ull |
|---|
| 19697 | #define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19698 | #define DCORE3_TPC5_CFG_KERNEL_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19699 | #define mmDCORE3_TPC5_CFG_KERNEL_BASE 0x465B508ull |
|---|
| 19700 | #define DCORE3_TPC5_CFG_KERNEL_MAX_OFFSET 0xD400 |
|---|
| 19701 | #define DCORE3_TPC5_CFG_KERNEL_SECTION 0xD400 |
|---|
| 19702 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_0_BASE 0x465B5DCull |
|---|
| 19703 | #define DCORE3_TPC5_CFG_QM_TENSOR_0_MAX_OFFSET 0x5000 |
|---|
| 19704 | #define DCORE3_TPC5_CFG_QM_TENSOR_0_SECTION 0x5000 |
|---|
| 19705 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_1_BASE 0x465B62Cull |
|---|
| 19706 | #define DCORE3_TPC5_CFG_QM_TENSOR_1_MAX_OFFSET 0x5000 |
|---|
| 19707 | #define DCORE3_TPC5_CFG_QM_TENSOR_1_SECTION 0x5000 |
|---|
| 19708 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_2_BASE 0x465B67Cull |
|---|
| 19709 | #define DCORE3_TPC5_CFG_QM_TENSOR_2_MAX_OFFSET 0x5000 |
|---|
| 19710 | #define DCORE3_TPC5_CFG_QM_TENSOR_2_SECTION 0x5000 |
|---|
| 19711 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_3_BASE 0x465B6CCull |
|---|
| 19712 | #define DCORE3_TPC5_CFG_QM_TENSOR_3_MAX_OFFSET 0x5000 |
|---|
| 19713 | #define DCORE3_TPC5_CFG_QM_TENSOR_3_SECTION 0x5000 |
|---|
| 19714 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_4_BASE 0x465B71Cull |
|---|
| 19715 | #define DCORE3_TPC5_CFG_QM_TENSOR_4_MAX_OFFSET 0x5000 |
|---|
| 19716 | #define DCORE3_TPC5_CFG_QM_TENSOR_4_SECTION 0x5000 |
|---|
| 19717 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_5_BASE 0x465B76Cull |
|---|
| 19718 | #define DCORE3_TPC5_CFG_QM_TENSOR_5_MAX_OFFSET 0x5000 |
|---|
| 19719 | #define DCORE3_TPC5_CFG_QM_TENSOR_5_SECTION 0x5000 |
|---|
| 19720 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_6_BASE 0x465B7BCull |
|---|
| 19721 | #define DCORE3_TPC5_CFG_QM_TENSOR_6_MAX_OFFSET 0x5000 |
|---|
| 19722 | #define DCORE3_TPC5_CFG_QM_TENSOR_6_SECTION 0x5000 |
|---|
| 19723 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_7_BASE 0x465B80Cull |
|---|
| 19724 | #define DCORE3_TPC5_CFG_QM_TENSOR_7_MAX_OFFSET 0x5000 |
|---|
| 19725 | #define DCORE3_TPC5_CFG_QM_TENSOR_7_SECTION 0x5000 |
|---|
| 19726 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_8_BASE 0x465B85Cull |
|---|
| 19727 | #define DCORE3_TPC5_CFG_QM_TENSOR_8_MAX_OFFSET 0x5000 |
|---|
| 19728 | #define DCORE3_TPC5_CFG_QM_TENSOR_8_SECTION 0x5000 |
|---|
| 19729 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_9_BASE 0x465B8ACull |
|---|
| 19730 | #define DCORE3_TPC5_CFG_QM_TENSOR_9_MAX_OFFSET 0x5000 |
|---|
| 19731 | #define DCORE3_TPC5_CFG_QM_TENSOR_9_SECTION 0x5000 |
|---|
| 19732 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_10_BASE 0x465B8FCull |
|---|
| 19733 | #define DCORE3_TPC5_CFG_QM_TENSOR_10_MAX_OFFSET 0x5000 |
|---|
| 19734 | #define DCORE3_TPC5_CFG_QM_TENSOR_10_SECTION 0x5000 |
|---|
| 19735 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_11_BASE 0x465B94Cull |
|---|
| 19736 | #define DCORE3_TPC5_CFG_QM_TENSOR_11_MAX_OFFSET 0x5000 |
|---|
| 19737 | #define DCORE3_TPC5_CFG_QM_TENSOR_11_SECTION 0x5000 |
|---|
| 19738 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_12_BASE 0x465B99Cull |
|---|
| 19739 | #define DCORE3_TPC5_CFG_QM_TENSOR_12_MAX_OFFSET 0x5000 |
|---|
| 19740 | #define DCORE3_TPC5_CFG_QM_TENSOR_12_SECTION 0x5000 |
|---|
| 19741 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_13_BASE 0x465B9ECull |
|---|
| 19742 | #define DCORE3_TPC5_CFG_QM_TENSOR_13_MAX_OFFSET 0x5000 |
|---|
| 19743 | #define DCORE3_TPC5_CFG_QM_TENSOR_13_SECTION 0x5000 |
|---|
| 19744 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_14_BASE 0x465BA3Cull |
|---|
| 19745 | #define DCORE3_TPC5_CFG_QM_TENSOR_14_MAX_OFFSET 0x5000 |
|---|
| 19746 | #define DCORE3_TPC5_CFG_QM_TENSOR_14_SECTION 0x5000 |
|---|
| 19747 | #define mmDCORE3_TPC5_CFG_QM_TENSOR_15_BASE 0x465BA8Cull |
|---|
| 19748 | #define DCORE3_TPC5_CFG_QM_TENSOR_15_MAX_OFFSET 0x5000 |
|---|
| 19749 | #define DCORE3_TPC5_CFG_QM_TENSOR_15_SECTION 0x5000 |
|---|
| 19750 | #define mmDCORE3_TPC5_CFG_QM_SYNC_OBJECT_BASE 0x465BADCull |
|---|
| 19751 | #define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_MAX_OFFSET 0x8000 |
|---|
| 19752 | #define DCORE3_TPC5_CFG_QM_SYNC_OBJECT_SECTION 0x8000 |
|---|
| 19753 | #define mmDCORE3_TPC5_CFG_QM_BASE 0x465BAE4ull |
|---|
| 19754 | #define DCORE3_TPC5_CFG_QM_MAX_OFFSET 0xD400 |
|---|
| 19755 | #define DCORE3_TPC5_CFG_QM_SECTION 0x31C0 |
|---|
| 19756 | #define mmDCORE3_TPC5_CFG_AXUSER_BASE 0x465BE00ull |
|---|
| 19757 | #define DCORE3_TPC5_CFG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19758 | #define DCORE3_TPC5_CFG_AXUSER_SECTION 0x8000 |
|---|
| 19759 | #define mmDCORE3_TPC5_CFG_SPECIAL_BASE 0x465BE80ull |
|---|
| 19760 | #define DCORE3_TPC5_CFG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19761 | #define DCORE3_TPC5_CFG_SPECIAL_SECTION 0x1800 |
|---|
| 19762 | #define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_BASE 0x465C000ull |
|---|
| 19763 | #define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19764 | #define DCORE3_TPC5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19765 | #define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_BASE 0x465C200ull |
|---|
| 19766 | #define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19767 | #define DCORE3_TPC5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19768 | #define mmDCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_BASE 0x465C400ull |
|---|
| 19769 | #define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19770 | #define DCORE3_TPC5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19771 | #define mmDCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_BASE 0x465C600ull |
|---|
| 19772 | #define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19773 | #define DCORE3_TPC5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19774 | #define mmDCORE3_TPC5_MSTR_IF_E2E_CRDT_BASE 0x465C800ull |
|---|
| 19775 | #define DCORE3_TPC5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19776 | #define DCORE3_TPC5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19777 | #define mmDCORE3_TPC5_MSTR_IF_AXUSER_BASE 0x465CA80ull |
|---|
| 19778 | #define DCORE3_TPC5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19779 | #define DCORE3_TPC5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19780 | #define mmDCORE3_TPC5_MSTR_IF_DBG_HBW_BASE 0x465CB00ull |
|---|
| 19781 | #define DCORE3_TPC5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19782 | #define DCORE3_TPC5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19783 | #define mmDCORE3_TPC5_MSTR_IF_DBG_LBW_BASE 0x465CB80ull |
|---|
| 19784 | #define DCORE3_TPC5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19785 | #define DCORE3_TPC5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19786 | #define mmDCORE3_TPC5_MSTR_IF_CORE_HBW_BASE 0x465CC00ull |
|---|
| 19787 | #define DCORE3_TPC5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19788 | #define DCORE3_TPC5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19789 | #define mmDCORE3_TPC5_MSTR_IF_CORE_LBW_BASE 0x465CD80ull |
|---|
| 19790 | #define DCORE3_TPC5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19791 | #define DCORE3_TPC5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19792 | #define mmDCORE3_TPC5_MSTR_IF_SPECIAL_BASE 0x465CE80ull |
|---|
| 19793 | #define DCORE3_TPC5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19794 | #define DCORE3_TPC5_MSTR_IF_SPECIAL_SECTION 0x23180 |
|---|
| 19795 | #define mmDCORE3_HMMU0_MMU_BASE 0x4680000ull |
|---|
| 19796 | #define DCORE3_HMMU0_MMU_MAX_OFFSET 0x1000 |
|---|
| 19797 | #define DCORE3_HMMU0_MMU_SECTION 0xE800 |
|---|
| 19798 | #define mmDCORE3_HMMU0_MMU_SPECIAL_BASE 0x4680E80ull |
|---|
| 19799 | #define DCORE3_HMMU0_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19800 | #define DCORE3_HMMU0_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 19801 | #define mmDCORE3_HMMU0_STLB_BASE 0x4681000ull |
|---|
| 19802 | #define DCORE3_HMMU0_STLB_MAX_OFFSET 0x1000 |
|---|
| 19803 | #define DCORE3_HMMU0_STLB_SECTION 0xE800 |
|---|
| 19804 | #define mmDCORE3_HMMU0_STLB_SPECIAL_BASE 0x4681E80ull |
|---|
| 19805 | #define DCORE3_HMMU0_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19806 | #define DCORE3_HMMU0_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 19807 | #define mmDCORE3_HMMU0_SCRAMB_OUT_BASE 0x4683000ull |
|---|
| 19808 | #define DCORE3_HMMU0_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 19809 | #define DCORE3_HMMU0_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 19810 | #define mmDCORE3_HMMU0_SCRAMB_OUT_SPECIAL_BASE 0x4683E80ull |
|---|
| 19811 | #define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19812 | #define DCORE3_HMMU0_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 19813 | #define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE 0x4684000ull |
|---|
| 19814 | #define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19815 | #define DCORE3_HMMU0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19816 | #define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_BASE 0x4684200ull |
|---|
| 19817 | #define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19818 | #define DCORE3_HMMU0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19819 | #define mmDCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_BASE 0x4684400ull |
|---|
| 19820 | #define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19821 | #define DCORE3_HMMU0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19822 | #define mmDCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_BASE 0x4684600ull |
|---|
| 19823 | #define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19824 | #define DCORE3_HMMU0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19825 | #define mmDCORE3_HMMU0_MSTR_IF_E2E_CRDT_BASE 0x4684800ull |
|---|
| 19826 | #define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19827 | #define DCORE3_HMMU0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19828 | #define mmDCORE3_HMMU0_MSTR_IF_AXUSER_BASE 0x4684A80ull |
|---|
| 19829 | #define DCORE3_HMMU0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19830 | #define DCORE3_HMMU0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19831 | #define mmDCORE3_HMMU0_MSTR_IF_DBG_HBW_BASE 0x4684B00ull |
|---|
| 19832 | #define DCORE3_HMMU0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19833 | #define DCORE3_HMMU0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19834 | #define mmDCORE3_HMMU0_MSTR_IF_DBG_LBW_BASE 0x4684B80ull |
|---|
| 19835 | #define DCORE3_HMMU0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19836 | #define DCORE3_HMMU0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19837 | #define mmDCORE3_HMMU0_MSTR_IF_CORE_HBW_BASE 0x4684C00ull |
|---|
| 19838 | #define DCORE3_HMMU0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19839 | #define DCORE3_HMMU0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19840 | #define mmDCORE3_HMMU0_MSTR_IF_CORE_LBW_BASE 0x4684D80ull |
|---|
| 19841 | #define DCORE3_HMMU0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19842 | #define DCORE3_HMMU0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19843 | #define mmDCORE3_HMMU0_MSTR_IF_SPECIAL_BASE 0x4684E80ull |
|---|
| 19844 | #define DCORE3_HMMU0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19845 | #define DCORE3_HMMU0_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 19846 | #define mmDCORE3_HMMU1_MMU_BASE 0x4690000ull |
|---|
| 19847 | #define DCORE3_HMMU1_MMU_MAX_OFFSET 0x1000 |
|---|
| 19848 | #define DCORE3_HMMU1_MMU_SECTION 0xE800 |
|---|
| 19849 | #define mmDCORE3_HMMU1_MMU_SPECIAL_BASE 0x4690E80ull |
|---|
| 19850 | #define DCORE3_HMMU1_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19851 | #define DCORE3_HMMU1_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 19852 | #define mmDCORE3_HMMU1_STLB_BASE 0x4691000ull |
|---|
| 19853 | #define DCORE3_HMMU1_STLB_MAX_OFFSET 0x1000 |
|---|
| 19854 | #define DCORE3_HMMU1_STLB_SECTION 0xE800 |
|---|
| 19855 | #define mmDCORE3_HMMU1_STLB_SPECIAL_BASE 0x4691E80ull |
|---|
| 19856 | #define DCORE3_HMMU1_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19857 | #define DCORE3_HMMU1_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 19858 | #define mmDCORE3_HMMU1_SCRAMB_OUT_BASE 0x4693000ull |
|---|
| 19859 | #define DCORE3_HMMU1_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 19860 | #define DCORE3_HMMU1_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 19861 | #define mmDCORE3_HMMU1_SCRAMB_OUT_SPECIAL_BASE 0x4693E80ull |
|---|
| 19862 | #define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19863 | #define DCORE3_HMMU1_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 19864 | #define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_BASE 0x4694000ull |
|---|
| 19865 | #define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19866 | #define DCORE3_HMMU1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19867 | #define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_BASE 0x4694200ull |
|---|
| 19868 | #define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19869 | #define DCORE3_HMMU1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19870 | #define mmDCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_BASE 0x4694400ull |
|---|
| 19871 | #define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19872 | #define DCORE3_HMMU1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19873 | #define mmDCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_BASE 0x4694600ull |
|---|
| 19874 | #define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19875 | #define DCORE3_HMMU1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19876 | #define mmDCORE3_HMMU1_MSTR_IF_E2E_CRDT_BASE 0x4694800ull |
|---|
| 19877 | #define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19878 | #define DCORE3_HMMU1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19879 | #define mmDCORE3_HMMU1_MSTR_IF_AXUSER_BASE 0x4694A80ull |
|---|
| 19880 | #define DCORE3_HMMU1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19881 | #define DCORE3_HMMU1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19882 | #define mmDCORE3_HMMU1_MSTR_IF_DBG_HBW_BASE 0x4694B00ull |
|---|
| 19883 | #define DCORE3_HMMU1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19884 | #define DCORE3_HMMU1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19885 | #define mmDCORE3_HMMU1_MSTR_IF_DBG_LBW_BASE 0x4694B80ull |
|---|
| 19886 | #define DCORE3_HMMU1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19887 | #define DCORE3_HMMU1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19888 | #define mmDCORE3_HMMU1_MSTR_IF_CORE_HBW_BASE 0x4694C00ull |
|---|
| 19889 | #define DCORE3_HMMU1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19890 | #define DCORE3_HMMU1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19891 | #define mmDCORE3_HMMU1_MSTR_IF_CORE_LBW_BASE 0x4694D80ull |
|---|
| 19892 | #define DCORE3_HMMU1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19893 | #define DCORE3_HMMU1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19894 | #define mmDCORE3_HMMU1_MSTR_IF_SPECIAL_BASE 0x4694E80ull |
|---|
| 19895 | #define DCORE3_HMMU1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19896 | #define DCORE3_HMMU1_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 19897 | #define mmDCORE3_HMMU2_MMU_BASE 0x46A0000ull |
|---|
| 19898 | #define DCORE3_HMMU2_MMU_MAX_OFFSET 0x1000 |
|---|
| 19899 | #define DCORE3_HMMU2_MMU_SECTION 0xE800 |
|---|
| 19900 | #define mmDCORE3_HMMU2_MMU_SPECIAL_BASE 0x46A0E80ull |
|---|
| 19901 | #define DCORE3_HMMU2_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19902 | #define DCORE3_HMMU2_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 19903 | #define mmDCORE3_HMMU2_STLB_BASE 0x46A1000ull |
|---|
| 19904 | #define DCORE3_HMMU2_STLB_MAX_OFFSET 0x1000 |
|---|
| 19905 | #define DCORE3_HMMU2_STLB_SECTION 0xE800 |
|---|
| 19906 | #define mmDCORE3_HMMU2_STLB_SPECIAL_BASE 0x46A1E80ull |
|---|
| 19907 | #define DCORE3_HMMU2_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19908 | #define DCORE3_HMMU2_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 19909 | #define mmDCORE3_HMMU2_SCRAMB_OUT_BASE 0x46A3000ull |
|---|
| 19910 | #define DCORE3_HMMU2_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 19911 | #define DCORE3_HMMU2_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 19912 | #define mmDCORE3_HMMU2_SCRAMB_OUT_SPECIAL_BASE 0x46A3E80ull |
|---|
| 19913 | #define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19914 | #define DCORE3_HMMU2_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 19915 | #define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_BASE 0x46A4000ull |
|---|
| 19916 | #define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19917 | #define DCORE3_HMMU2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19918 | #define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_BASE 0x46A4200ull |
|---|
| 19919 | #define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19920 | #define DCORE3_HMMU2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19921 | #define mmDCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_BASE 0x46A4400ull |
|---|
| 19922 | #define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19923 | #define DCORE3_HMMU2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19924 | #define mmDCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_BASE 0x46A4600ull |
|---|
| 19925 | #define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19926 | #define DCORE3_HMMU2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19927 | #define mmDCORE3_HMMU2_MSTR_IF_E2E_CRDT_BASE 0x46A4800ull |
|---|
| 19928 | #define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19929 | #define DCORE3_HMMU2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19930 | #define mmDCORE3_HMMU2_MSTR_IF_AXUSER_BASE 0x46A4A80ull |
|---|
| 19931 | #define DCORE3_HMMU2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19932 | #define DCORE3_HMMU2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19933 | #define mmDCORE3_HMMU2_MSTR_IF_DBG_HBW_BASE 0x46A4B00ull |
|---|
| 19934 | #define DCORE3_HMMU2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19935 | #define DCORE3_HMMU2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19936 | #define mmDCORE3_HMMU2_MSTR_IF_DBG_LBW_BASE 0x46A4B80ull |
|---|
| 19937 | #define DCORE3_HMMU2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19938 | #define DCORE3_HMMU2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19939 | #define mmDCORE3_HMMU2_MSTR_IF_CORE_HBW_BASE 0x46A4C00ull |
|---|
| 19940 | #define DCORE3_HMMU2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19941 | #define DCORE3_HMMU2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19942 | #define mmDCORE3_HMMU2_MSTR_IF_CORE_LBW_BASE 0x46A4D80ull |
|---|
| 19943 | #define DCORE3_HMMU2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19944 | #define DCORE3_HMMU2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19945 | #define mmDCORE3_HMMU2_MSTR_IF_SPECIAL_BASE 0x46A4E80ull |
|---|
| 19946 | #define DCORE3_HMMU2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19947 | #define DCORE3_HMMU2_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 19948 | #define mmDCORE3_HMMU3_MMU_BASE 0x46B0000ull |
|---|
| 19949 | #define DCORE3_HMMU3_MMU_MAX_OFFSET 0x1000 |
|---|
| 19950 | #define DCORE3_HMMU3_MMU_SECTION 0xE800 |
|---|
| 19951 | #define mmDCORE3_HMMU3_MMU_SPECIAL_BASE 0x46B0E80ull |
|---|
| 19952 | #define DCORE3_HMMU3_MMU_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19953 | #define DCORE3_HMMU3_MMU_SPECIAL_SECTION 0x1800 |
|---|
| 19954 | #define mmDCORE3_HMMU3_STLB_BASE 0x46B1000ull |
|---|
| 19955 | #define DCORE3_HMMU3_STLB_MAX_OFFSET 0x1000 |
|---|
| 19956 | #define DCORE3_HMMU3_STLB_SECTION 0xE800 |
|---|
| 19957 | #define mmDCORE3_HMMU3_STLB_SPECIAL_BASE 0x46B1E80ull |
|---|
| 19958 | #define DCORE3_HMMU3_STLB_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19959 | #define DCORE3_HMMU3_STLB_SPECIAL_SECTION 0x1180 |
|---|
| 19960 | #define mmDCORE3_HMMU3_SCRAMB_OUT_BASE 0x46B3000ull |
|---|
| 19961 | #define DCORE3_HMMU3_SCRAMB_OUT_MAX_OFFSET 0x1000 |
|---|
| 19962 | #define DCORE3_HMMU3_SCRAMB_OUT_SECTION 0xE800 |
|---|
| 19963 | #define mmDCORE3_HMMU3_SCRAMB_OUT_SPECIAL_BASE 0x46B3E80ull |
|---|
| 19964 | #define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19965 | #define DCORE3_HMMU3_SCRAMB_OUT_SPECIAL_SECTION 0x1800 |
|---|
| 19966 | #define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_BASE 0x46B4000ull |
|---|
| 19967 | #define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19968 | #define DCORE3_HMMU3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 19969 | #define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_BASE 0x46B4200ull |
|---|
| 19970 | #define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 19971 | #define DCORE3_HMMU3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 19972 | #define mmDCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_BASE 0x46B4400ull |
|---|
| 19973 | #define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19974 | #define DCORE3_HMMU3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 19975 | #define mmDCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_BASE 0x46B4600ull |
|---|
| 19976 | #define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 19977 | #define DCORE3_HMMU3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 19978 | #define mmDCORE3_HMMU3_MSTR_IF_E2E_CRDT_BASE 0x46B4800ull |
|---|
| 19979 | #define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 19980 | #define DCORE3_HMMU3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 19981 | #define mmDCORE3_HMMU3_MSTR_IF_AXUSER_BASE 0x46B4A80ull |
|---|
| 19982 | #define DCORE3_HMMU3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 19983 | #define DCORE3_HMMU3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 19984 | #define mmDCORE3_HMMU3_MSTR_IF_DBG_HBW_BASE 0x46B4B00ull |
|---|
| 19985 | #define DCORE3_HMMU3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 19986 | #define DCORE3_HMMU3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 19987 | #define mmDCORE3_HMMU3_MSTR_IF_DBG_LBW_BASE 0x46B4B80ull |
|---|
| 19988 | #define DCORE3_HMMU3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 19989 | #define DCORE3_HMMU3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 19990 | #define mmDCORE3_HMMU3_MSTR_IF_CORE_HBW_BASE 0x46B4C00ull |
|---|
| 19991 | #define DCORE3_HMMU3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 19992 | #define DCORE3_HMMU3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 19993 | #define mmDCORE3_HMMU3_MSTR_IF_CORE_LBW_BASE 0x46B4D80ull |
|---|
| 19994 | #define DCORE3_HMMU3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 19995 | #define DCORE3_HMMU3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 19996 | #define mmDCORE3_HMMU3_MSTR_IF_SPECIAL_BASE 0x46B4E80ull |
|---|
| 19997 | #define DCORE3_HMMU3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 19998 | #define DCORE3_HMMU3_MSTR_IF_SPECIAL_SECTION 0xB180 |
|---|
| 19999 | #define mmDCORE3_MME_QM_ARC_DCCM_BASE 0x46C0000ull |
|---|
| 20000 | #define DCORE3_MME_QM_ARC_DCCM_MAX_OFFSET 0x4000 |
|---|
| 20001 | #define DCORE3_MME_QM_ARC_DCCM_SECTION 0x8000 |
|---|
| 20002 | #define mmDCORE3_MME_QM_ARC_AUX_BASE 0x46C8000ull |
|---|
| 20003 | #define DCORE3_MME_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 20004 | #define DCORE3_MME_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 20005 | #define mmDCORE3_MME_QM_ARC_AUX_SPECIAL_BASE 0x46C8E80ull |
|---|
| 20006 | #define DCORE3_MME_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20007 | #define DCORE3_MME_QM_ARC_AUX_SPECIAL_SECTION 0x1800 |
|---|
| 20008 | #define mmDCORE3_MME_QM_ARC_DUP_ENG_BASE 0x46C9000ull |
|---|
| 20009 | #define DCORE3_MME_QM_ARC_DUP_ENG_MAX_OFFSET 0x1000 |
|---|
| 20010 | #define DCORE3_MME_QM_ARC_DUP_ENG_SECTION 0x9000 |
|---|
| 20011 | #define mmDCORE3_MME_QM_ARC_DUP_ENG_AXUSER_BASE 0x46C9900ull |
|---|
| 20012 | #define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20013 | #define DCORE3_MME_QM_ARC_DUP_ENG_AXUSER_SECTION 0x5800 |
|---|
| 20014 | #define mmDCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_BASE 0x46C9E80ull |
|---|
| 20015 | #define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20016 | #define DCORE3_MME_QM_ARC_DUP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 20017 | #define mmDCORE3_MME_QM_BASE 0x46CA000ull |
|---|
| 20018 | #define DCORE3_MME_QM_MAX_OFFSET 0x1000 |
|---|
| 20019 | #define DCORE3_MME_QM_SECTION 0x9000 |
|---|
| 20020 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_BASE 0x46CA900ull |
|---|
| 20021 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 20022 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 20023 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_BASE 0x46CA908ull |
|---|
| 20024 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 20025 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 20026 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_BASE 0x46CA910ull |
|---|
| 20027 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 20028 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 20029 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_BASE 0x46CA918ull |
|---|
| 20030 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 20031 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 20032 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_BASE 0x46CA920ull |
|---|
| 20033 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 20034 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 20035 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_BASE 0x46CA928ull |
|---|
| 20036 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 20037 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 20038 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_BASE 0x46CA930ull |
|---|
| 20039 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 20040 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 20041 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_BASE 0x46CA938ull |
|---|
| 20042 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 20043 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 20044 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_BASE 0x46CA940ull |
|---|
| 20045 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 20046 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 20047 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_BASE 0x46CA948ull |
|---|
| 20048 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 20049 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 20050 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_BASE 0x46CA950ull |
|---|
| 20051 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 20052 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 20053 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_BASE 0x46CA958ull |
|---|
| 20054 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 20055 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 20056 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_BASE 0x46CA960ull |
|---|
| 20057 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 20058 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 20059 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_BASE 0x46CA968ull |
|---|
| 20060 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 20061 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 20062 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_BASE 0x46CA970ull |
|---|
| 20063 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 20064 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 20065 | #define mmDCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_BASE 0x46CA978ull |
|---|
| 20066 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 20067 | #define DCORE3_MME_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 20068 | #define mmDCORE3_MME_QM_AXUSER_SECURED_BASE 0x46CAB00ull |
|---|
| 20069 | #define DCORE3_MME_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 20070 | #define DCORE3_MME_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 20071 | #define mmDCORE3_MME_QM_AXUSER_NONSECURED_BASE 0x46CAB80ull |
|---|
| 20072 | #define DCORE3_MME_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 20073 | #define DCORE3_MME_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 20074 | #define mmDCORE3_MME_QM_DBG_HBW_BASE 0x46CAC00ull |
|---|
| 20075 | #define DCORE3_MME_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20076 | #define DCORE3_MME_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 20077 | #define mmDCORE3_MME_QM_DBG_LBW_BASE 0x46CAC80ull |
|---|
| 20078 | #define DCORE3_MME_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20079 | #define DCORE3_MME_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 20080 | #define mmDCORE3_MME_QM_CGM_BASE 0x46CAD80ull |
|---|
| 20081 | #define DCORE3_MME_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 20082 | #define DCORE3_MME_QM_CGM_SECTION 0x1000 |
|---|
| 20083 | #define mmDCORE3_MME_QM_SPECIAL_BASE 0x46CAE80ull |
|---|
| 20084 | #define DCORE3_MME_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20085 | #define DCORE3_MME_QM_SPECIAL_SECTION 0x1800 |
|---|
| 20086 | #define mmDCORE3_MME_CTRL_LO_BASE 0x46CB000ull |
|---|
| 20087 | #define DCORE3_MME_CTRL_LO_MAX_OFFSET 0x1000 |
|---|
| 20088 | #define DCORE3_MME_CTRL_LO_SECTION 0x8000 |
|---|
| 20089 | #define mmDCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_BASE 0x46CB008ull |
|---|
| 20090 | #define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 20091 | #define DCORE3_MME_CTRL_LO_ARCH_BASE_ADDR_SECTION 0x2000 |
|---|
| 20092 | #define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE 0x46CB028ull |
|---|
| 20093 | #define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 20094 | #define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 20095 | #define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_A_BASE 0x46CB040ull |
|---|
| 20096 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 20097 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_A_SECTION 0x5800 |
|---|
| 20098 | #define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_B_BASE 0x46CB098ull |
|---|
| 20099 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 20100 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_B_SECTION 0x5800 |
|---|
| 20101 | #define mmDCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE 0x46CB0F0ull |
|---|
| 20102 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 20103 | #define DCORE3_MME_CTRL_LO_ARCH_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 20104 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE 0x46CB15Cull |
|---|
| 20105 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20106 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 20107 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE 0x46CB170ull |
|---|
| 20108 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20109 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 20110 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE 0x46CB184ull |
|---|
| 20111 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20112 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 20113 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE 0x46CB198ull |
|---|
| 20114 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20115 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 20116 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE 0x46CB1ACull |
|---|
| 20117 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20118 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 20119 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE 0x46CB1C0ull |
|---|
| 20120 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20121 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 20122 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE 0x46CB1D4ull |
|---|
| 20123 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20124 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 20125 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE 0x46CB1E8ull |
|---|
| 20126 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20127 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 20128 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE 0x46CB1FCull |
|---|
| 20129 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20130 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 20131 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE 0x46CB210ull |
|---|
| 20132 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20133 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 20134 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE 0x46CB22Cull |
|---|
| 20135 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20136 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 20137 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE 0x46CB240ull |
|---|
| 20138 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20139 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 20140 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE 0x46CB254ull |
|---|
| 20141 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20142 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 20143 | #define mmDCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE 0x46CB268ull |
|---|
| 20144 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20145 | #define DCORE3_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 20146 | #define mmDCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE 0x46CB280ull |
|---|
| 20147 | #define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 20148 | #define DCORE3_MME_CTRL_LO_ARCH_NON_TENSOR_END_SECTION 0xB800 |
|---|
| 20149 | #define mmDCORE3_MME_CTRL_LO_MME_AXUSER_BASE 0x46CBE00ull |
|---|
| 20150 | #define DCORE3_MME_CTRL_LO_MME_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20151 | #define DCORE3_MME_CTRL_LO_MME_AXUSER_SECTION 0x8000 |
|---|
| 20152 | #define mmDCORE3_MME_CTRL_LO_SPECIAL_BASE 0x46CBE80ull |
|---|
| 20153 | #define DCORE3_MME_CTRL_LO_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20154 | #define DCORE3_MME_CTRL_LO_SPECIAL_SECTION 0x1800 |
|---|
| 20155 | #define mmDCORE3_MME_CTRL_HI_BASE 0x46CC000ull |
|---|
| 20156 | #define DCORE3_MME_CTRL_HI_MAX_OFFSET 0x1000 |
|---|
| 20157 | #define DCORE3_MME_CTRL_HI_SECTION 0x8000 |
|---|
| 20158 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_BASE 0x46CC008ull |
|---|
| 20159 | #define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 20160 | #define DCORE3_MME_CTRL_HI_SHADOW_0_BASE_ADDR_SECTION 0x2000 |
|---|
| 20161 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_BASE 0x46CC028ull |
|---|
| 20162 | #define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 20163 | #define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 20164 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_BASE 0x46CC040ull |
|---|
| 20165 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 20166 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_A_SECTION 0x5800 |
|---|
| 20167 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_BASE 0x46CC098ull |
|---|
| 20168 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 20169 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_B_SECTION 0x5800 |
|---|
| 20170 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_BASE 0x46CC0F0ull |
|---|
| 20171 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 20172 | #define DCORE3_MME_CTRL_HI_SHADOW_0_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 20173 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_BASE 0x46CC15Cull |
|---|
| 20174 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20175 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 20176 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_BASE 0x46CC170ull |
|---|
| 20177 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20178 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 20179 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_BASE 0x46CC184ull |
|---|
| 20180 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20181 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 20182 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_BASE 0x46CC198ull |
|---|
| 20183 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20184 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 20185 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_BASE 0x46CC1ACull |
|---|
| 20186 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20187 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 20188 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_BASE 0x46CC1C0ull |
|---|
| 20189 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20190 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 20191 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_BASE 0x46CC1D4ull |
|---|
| 20192 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20193 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 20194 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_BASE 0x46CC1E8ull |
|---|
| 20195 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20196 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 20197 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_BASE 0x46CC1FCull |
|---|
| 20198 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20199 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 20200 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_BASE 0x46CC210ull |
|---|
| 20201 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20202 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 20203 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_BASE 0x46CC22Cull |
|---|
| 20204 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20205 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 20206 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_BASE 0x46CC240ull |
|---|
| 20207 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20208 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 20209 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_BASE 0x46CC254ull |
|---|
| 20210 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20211 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 20212 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_BASE 0x46CC268ull |
|---|
| 20213 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20214 | #define DCORE3_MME_CTRL_HI_SHADOW_0_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 20215 | #define mmDCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_BASE 0x46CC280ull |
|---|
| 20216 | #define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 20217 | #define DCORE3_MME_CTRL_HI_SHADOW_0_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 20218 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_BASE 0x46CC308ull |
|---|
| 20219 | #define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 20220 | #define DCORE3_MME_CTRL_HI_SHADOW_1_BASE_ADDR_SECTION 0x2000 |
|---|
| 20221 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_BASE 0x46CC328ull |
|---|
| 20222 | #define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 20223 | #define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 20224 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_BASE 0x46CC340ull |
|---|
| 20225 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 20226 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_A_SECTION 0x5800 |
|---|
| 20227 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_BASE 0x46CC398ull |
|---|
| 20228 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 20229 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_B_SECTION 0x5800 |
|---|
| 20230 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_BASE 0x46CC3F0ull |
|---|
| 20231 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 20232 | #define DCORE3_MME_CTRL_HI_SHADOW_1_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 20233 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_BASE 0x46CC45Cull |
|---|
| 20234 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20235 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 20236 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_BASE 0x46CC470ull |
|---|
| 20237 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20238 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 20239 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_BASE 0x46CC484ull |
|---|
| 20240 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20241 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 20242 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_BASE 0x46CC498ull |
|---|
| 20243 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20244 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 20245 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_BASE 0x46CC4ACull |
|---|
| 20246 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20247 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 20248 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_BASE 0x46CC4C0ull |
|---|
| 20249 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20250 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 20251 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_BASE 0x46CC4D4ull |
|---|
| 20252 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20253 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 20254 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_BASE 0x46CC4E8ull |
|---|
| 20255 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20256 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 20257 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_BASE 0x46CC4FCull |
|---|
| 20258 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20259 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 20260 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_BASE 0x46CC510ull |
|---|
| 20261 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20262 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 20263 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_BASE 0x46CC52Cull |
|---|
| 20264 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20265 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 20266 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_BASE 0x46CC540ull |
|---|
| 20267 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20268 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 20269 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_BASE 0x46CC554ull |
|---|
| 20270 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20271 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 20272 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_BASE 0x46CC568ull |
|---|
| 20273 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20274 | #define DCORE3_MME_CTRL_HI_SHADOW_1_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 20275 | #define mmDCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_BASE 0x46CC580ull |
|---|
| 20276 | #define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 20277 | #define DCORE3_MME_CTRL_HI_SHADOW_1_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 20278 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_BASE 0x46CC608ull |
|---|
| 20279 | #define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 20280 | #define DCORE3_MME_CTRL_HI_SHADOW_2_BASE_ADDR_SECTION 0x2000 |
|---|
| 20281 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_BASE 0x46CC628ull |
|---|
| 20282 | #define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 20283 | #define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 20284 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_BASE 0x46CC640ull |
|---|
| 20285 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 20286 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_A_SECTION 0x5800 |
|---|
| 20287 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_BASE 0x46CC698ull |
|---|
| 20288 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 20289 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_B_SECTION 0x5800 |
|---|
| 20290 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_BASE 0x46CC6F0ull |
|---|
| 20291 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 20292 | #define DCORE3_MME_CTRL_HI_SHADOW_2_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 20293 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_BASE 0x46CC75Cull |
|---|
| 20294 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20295 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 20296 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_BASE 0x46CC770ull |
|---|
| 20297 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20298 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 20299 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_BASE 0x46CC784ull |
|---|
| 20300 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20301 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 20302 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_BASE 0x46CC798ull |
|---|
| 20303 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20304 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 20305 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_BASE 0x46CC7ACull |
|---|
| 20306 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20307 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 20308 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_BASE 0x46CC7C0ull |
|---|
| 20309 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20310 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 20311 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_BASE 0x46CC7D4ull |
|---|
| 20312 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20313 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 20314 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_BASE 0x46CC7E8ull |
|---|
| 20315 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20316 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 20317 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_BASE 0x46CC7FCull |
|---|
| 20318 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20319 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 20320 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_BASE 0x46CC810ull |
|---|
| 20321 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20322 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 20323 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_BASE 0x46CC82Cull |
|---|
| 20324 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20325 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 20326 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_BASE 0x46CC840ull |
|---|
| 20327 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20328 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 20329 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_BASE 0x46CC854ull |
|---|
| 20330 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20331 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 20332 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_BASE 0x46CC868ull |
|---|
| 20333 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20334 | #define DCORE3_MME_CTRL_HI_SHADOW_2_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 20335 | #define mmDCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_BASE 0x46CC880ull |
|---|
| 20336 | #define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 20337 | #define DCORE3_MME_CTRL_HI_SHADOW_2_NON_TENSOR_END_SECTION 0x8800 |
|---|
| 20338 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_BASE 0x46CC908ull |
|---|
| 20339 | #define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_MAX_OFFSET 0x2000 |
|---|
| 20340 | #define DCORE3_MME_CTRL_HI_SHADOW_3_BASE_ADDR_SECTION 0x2000 |
|---|
| 20341 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_BASE 0x46CC928ull |
|---|
| 20342 | #define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_MAX_OFFSET 0x1800 |
|---|
| 20343 | #define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_START_SECTION 0x1800 |
|---|
| 20344 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_BASE 0x46CC940ull |
|---|
| 20345 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_MAX_OFFSET 0x5800 |
|---|
| 20346 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_A_SECTION 0x5800 |
|---|
| 20347 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_BASE 0x46CC998ull |
|---|
| 20348 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_MAX_OFFSET 0x5800 |
|---|
| 20349 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_B_SECTION 0x5800 |
|---|
| 20350 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_BASE 0x46CC9F0ull |
|---|
| 20351 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_MAX_OFFSET 0x5800 |
|---|
| 20352 | #define DCORE3_MME_CTRL_HI_SHADOW_3_TENSOR_COUT_SECTION 0x6C00 |
|---|
| 20353 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_BASE 0x46CCA5Cull |
|---|
| 20354 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20355 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_MASTER_SECTION 0x1400 |
|---|
| 20356 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_BASE 0x46CCA70ull |
|---|
| 20357 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20358 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN0_SLAVE_SECTION 0x1400 |
|---|
| 20359 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_BASE 0x46CCA84ull |
|---|
| 20360 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20361 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_MASTER_SECTION 0x1400 |
|---|
| 20362 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_BASE 0x46CCA98ull |
|---|
| 20363 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20364 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN1_SLAVE_SECTION 0x1400 |
|---|
| 20365 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_BASE 0x46CCAACull |
|---|
| 20366 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20367 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_MASTER_SECTION 0x1400 |
|---|
| 20368 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_BASE 0x46CCAC0ull |
|---|
| 20369 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20370 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN2_SLAVE_SECTION 0x1400 |
|---|
| 20371 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_BASE 0x46CCAD4ull |
|---|
| 20372 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20373 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_MASTER_SECTION 0x1400 |
|---|
| 20374 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_BASE 0x46CCAE8ull |
|---|
| 20375 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20376 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN3_SLAVE_SECTION 0x1400 |
|---|
| 20377 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_BASE 0x46CCAFCull |
|---|
| 20378 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20379 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_MASTER_SECTION 0x1400 |
|---|
| 20380 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_BASE 0x46CCB10ull |
|---|
| 20381 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20382 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_IN4_SLAVE_SECTION 0x1C00 |
|---|
| 20383 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_BASE 0x46CCB2Cull |
|---|
| 20384 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20385 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_MASTER_SECTION 0x1400 |
|---|
| 20386 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_BASE 0x46CCB40ull |
|---|
| 20387 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20388 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT0_SLAVE_SECTION 0x1400 |
|---|
| 20389 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_BASE 0x46CCB54ull |
|---|
| 20390 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_MAX_OFFSET 0x1400 |
|---|
| 20391 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_MASTER_SECTION 0x1400 |
|---|
| 20392 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_BASE 0x46CCB68ull |
|---|
| 20393 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_MAX_OFFSET 0x1400 |
|---|
| 20394 | #define DCORE3_MME_CTRL_HI_SHADOW_3_AGU_COUT1_SLAVE_SECTION 0x1800 |
|---|
| 20395 | #define mmDCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_BASE 0x46CCB80ull |
|---|
| 20396 | #define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_MAX_OFFSET 0x6000 |
|---|
| 20397 | #define DCORE3_MME_CTRL_HI_SHADOW_3_NON_TENSOR_END_SECTION 0x3000 |
|---|
| 20398 | #define mmDCORE3_MME_CTRL_HI_SPECIAL_BASE 0x46CCE80ull |
|---|
| 20399 | #define DCORE3_MME_CTRL_HI_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20400 | #define DCORE3_MME_CTRL_HI_SPECIAL_SECTION 0x1800 |
|---|
| 20401 | #define mmDCORE3_MME_EU_BIST_BASE 0x46CD000ull |
|---|
| 20402 | #define DCORE3_MME_EU_BIST_MAX_OFFSET 0x1000 |
|---|
| 20403 | #define DCORE3_MME_EU_BIST_SECTION 0xE800 |
|---|
| 20404 | #define mmDCORE3_MME_EU_BIST_SPECIAL_BASE 0x46CDE80ull |
|---|
| 20405 | #define DCORE3_MME_EU_BIST_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20406 | #define DCORE3_MME_EU_BIST_SPECIAL_SECTION 0x1800 |
|---|
| 20407 | #define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE 0x46CE000ull |
|---|
| 20408 | #define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20409 | #define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20410 | #define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_BASE 0x46CE200ull |
|---|
| 20411 | #define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20412 | #define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20413 | #define mmDCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_BASE 0x46CE400ull |
|---|
| 20414 | #define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20415 | #define DCORE3_MME_CTRL_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20416 | #define mmDCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_BASE 0x46CE600ull |
|---|
| 20417 | #define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20418 | #define DCORE3_MME_CTRL_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20419 | #define mmDCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_BASE 0x46CE800ull |
|---|
| 20420 | #define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20421 | #define DCORE3_MME_CTRL_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20422 | #define mmDCORE3_MME_CTRL_MSTR_IF_AXUSER_BASE 0x46CEA80ull |
|---|
| 20423 | #define DCORE3_MME_CTRL_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20424 | #define DCORE3_MME_CTRL_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20425 | #define mmDCORE3_MME_CTRL_MSTR_IF_DBG_HBW_BASE 0x46CEB00ull |
|---|
| 20426 | #define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20427 | #define DCORE3_MME_CTRL_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20428 | #define mmDCORE3_MME_CTRL_MSTR_IF_DBG_LBW_BASE 0x46CEB80ull |
|---|
| 20429 | #define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20430 | #define DCORE3_MME_CTRL_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20431 | #define mmDCORE3_MME_CTRL_MSTR_IF_CORE_HBW_BASE 0x46CEC00ull |
|---|
| 20432 | #define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20433 | #define DCORE3_MME_CTRL_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20434 | #define mmDCORE3_MME_CTRL_MSTR_IF_CORE_LBW_BASE 0x46CED80ull |
|---|
| 20435 | #define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20436 | #define DCORE3_MME_CTRL_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20437 | #define mmDCORE3_MME_CTRL_MSTR_IF_SPECIAL_BASE 0x46CEE80ull |
|---|
| 20438 | #define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20439 | #define DCORE3_MME_CTRL_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 20440 | #define mmDCORE3_MME_QM_ARC_ACP_ENG_BASE 0x46CF000ull |
|---|
| 20441 | #define DCORE3_MME_QM_ARC_ACP_ENG_MAX_OFFSET 0x1000 |
|---|
| 20442 | #define DCORE3_MME_QM_ARC_ACP_ENG_SECTION 0xE800 |
|---|
| 20443 | #define mmDCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_BASE 0x46CFE80ull |
|---|
| 20444 | #define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20445 | #define DCORE3_MME_QM_ARC_ACP_ENG_SPECIAL_SECTION 0x1800 |
|---|
| 20446 | #define mmDCORE3_MME_SBTE0_BASE 0x46D0000ull |
|---|
| 20447 | #define DCORE3_MME_SBTE0_MAX_OFFSET 0x1000 |
|---|
| 20448 | #define DCORE3_MME_SBTE0_SECTION 0xE800 |
|---|
| 20449 | #define mmDCORE3_MME_SBTE0_SPECIAL_BASE 0x46D0E80ull |
|---|
| 20450 | #define DCORE3_MME_SBTE0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20451 | #define DCORE3_MME_SBTE0_SPECIAL_SECTION 0x1800 |
|---|
| 20452 | #define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE 0x46D1000ull |
|---|
| 20453 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20454 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20455 | #define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_BASE 0x46D1200ull |
|---|
| 20456 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20457 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20458 | #define mmDCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_BASE 0x46D1400ull |
|---|
| 20459 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20460 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20461 | #define mmDCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_BASE 0x46D1600ull |
|---|
| 20462 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20463 | #define DCORE3_MME_SBTE0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20464 | #define mmDCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_BASE 0x46D1800ull |
|---|
| 20465 | #define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20466 | #define DCORE3_MME_SBTE0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20467 | #define mmDCORE3_MME_SBTE0_MSTR_IF_AXUSER_BASE 0x46D1A80ull |
|---|
| 20468 | #define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20469 | #define DCORE3_MME_SBTE0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20470 | #define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_BASE 0x46D1B00ull |
|---|
| 20471 | #define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20472 | #define DCORE3_MME_SBTE0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20473 | #define mmDCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_BASE 0x46D1B80ull |
|---|
| 20474 | #define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20475 | #define DCORE3_MME_SBTE0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20476 | #define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_BASE 0x46D1C00ull |
|---|
| 20477 | #define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20478 | #define DCORE3_MME_SBTE0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20479 | #define mmDCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_BASE 0x46D1D80ull |
|---|
| 20480 | #define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20481 | #define DCORE3_MME_SBTE0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20482 | #define mmDCORE3_MME_SBTE0_MSTR_IF_SPECIAL_BASE 0x46D1E80ull |
|---|
| 20483 | #define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20484 | #define DCORE3_MME_SBTE0_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 20485 | #define mmDCORE3_MME_SBTE1_BASE 0x46D8000ull |
|---|
| 20486 | #define DCORE3_MME_SBTE1_MAX_OFFSET 0x1000 |
|---|
| 20487 | #define DCORE3_MME_SBTE1_SECTION 0xE800 |
|---|
| 20488 | #define mmDCORE3_MME_SBTE1_SPECIAL_BASE 0x46D8E80ull |
|---|
| 20489 | #define DCORE3_MME_SBTE1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20490 | #define DCORE3_MME_SBTE1_SPECIAL_SECTION 0x1800 |
|---|
| 20491 | #define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_BASE 0x46D9000ull |
|---|
| 20492 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20493 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20494 | #define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_BASE 0x46D9200ull |
|---|
| 20495 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20496 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20497 | #define mmDCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_BASE 0x46D9400ull |
|---|
| 20498 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20499 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20500 | #define mmDCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_BASE 0x46D9600ull |
|---|
| 20501 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20502 | #define DCORE3_MME_SBTE1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20503 | #define mmDCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_BASE 0x46D9800ull |
|---|
| 20504 | #define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20505 | #define DCORE3_MME_SBTE1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20506 | #define mmDCORE3_MME_SBTE1_MSTR_IF_AXUSER_BASE 0x46D9A80ull |
|---|
| 20507 | #define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20508 | #define DCORE3_MME_SBTE1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20509 | #define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_BASE 0x46D9B00ull |
|---|
| 20510 | #define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20511 | #define DCORE3_MME_SBTE1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20512 | #define mmDCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_BASE 0x46D9B80ull |
|---|
| 20513 | #define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20514 | #define DCORE3_MME_SBTE1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20515 | #define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_BASE 0x46D9C00ull |
|---|
| 20516 | #define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20517 | #define DCORE3_MME_SBTE1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20518 | #define mmDCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_BASE 0x46D9D80ull |
|---|
| 20519 | #define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20520 | #define DCORE3_MME_SBTE1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20521 | #define mmDCORE3_MME_SBTE1_MSTR_IF_SPECIAL_BASE 0x46D9E80ull |
|---|
| 20522 | #define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20523 | #define DCORE3_MME_SBTE1_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 20524 | #define mmDCORE3_MME_SBTE2_BASE 0x46E0000ull |
|---|
| 20525 | #define DCORE3_MME_SBTE2_MAX_OFFSET 0x1000 |
|---|
| 20526 | #define DCORE3_MME_SBTE2_SECTION 0xE800 |
|---|
| 20527 | #define mmDCORE3_MME_SBTE2_SPECIAL_BASE 0x46E0E80ull |
|---|
| 20528 | #define DCORE3_MME_SBTE2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20529 | #define DCORE3_MME_SBTE2_SPECIAL_SECTION 0x1800 |
|---|
| 20530 | #define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_BASE 0x46E1000ull |
|---|
| 20531 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20532 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20533 | #define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_BASE 0x46E1200ull |
|---|
| 20534 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20535 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20536 | #define mmDCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_BASE 0x46E1400ull |
|---|
| 20537 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20538 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20539 | #define mmDCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_BASE 0x46E1600ull |
|---|
| 20540 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20541 | #define DCORE3_MME_SBTE2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20542 | #define mmDCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_BASE 0x46E1800ull |
|---|
| 20543 | #define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20544 | #define DCORE3_MME_SBTE2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20545 | #define mmDCORE3_MME_SBTE2_MSTR_IF_AXUSER_BASE 0x46E1A80ull |
|---|
| 20546 | #define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20547 | #define DCORE3_MME_SBTE2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20548 | #define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_BASE 0x46E1B00ull |
|---|
| 20549 | #define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20550 | #define DCORE3_MME_SBTE2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20551 | #define mmDCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_BASE 0x46E1B80ull |
|---|
| 20552 | #define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20553 | #define DCORE3_MME_SBTE2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20554 | #define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_BASE 0x46E1C00ull |
|---|
| 20555 | #define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20556 | #define DCORE3_MME_SBTE2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20557 | #define mmDCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_BASE 0x46E1D80ull |
|---|
| 20558 | #define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20559 | #define DCORE3_MME_SBTE2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20560 | #define mmDCORE3_MME_SBTE2_MSTR_IF_SPECIAL_BASE 0x46E1E80ull |
|---|
| 20561 | #define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20562 | #define DCORE3_MME_SBTE2_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 20563 | #define mmDCORE3_MME_SBTE3_BASE 0x46E8000ull |
|---|
| 20564 | #define DCORE3_MME_SBTE3_MAX_OFFSET 0x1000 |
|---|
| 20565 | #define DCORE3_MME_SBTE3_SECTION 0xE800 |
|---|
| 20566 | #define mmDCORE3_MME_SBTE3_SPECIAL_BASE 0x46E8E80ull |
|---|
| 20567 | #define DCORE3_MME_SBTE3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20568 | #define DCORE3_MME_SBTE3_SPECIAL_SECTION 0x1800 |
|---|
| 20569 | #define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_BASE 0x46E9000ull |
|---|
| 20570 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20571 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20572 | #define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_BASE 0x46E9200ull |
|---|
| 20573 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20574 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20575 | #define mmDCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_BASE 0x46E9400ull |
|---|
| 20576 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20577 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20578 | #define mmDCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_BASE 0x46E9600ull |
|---|
| 20579 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20580 | #define DCORE3_MME_SBTE3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20581 | #define mmDCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_BASE 0x46E9800ull |
|---|
| 20582 | #define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20583 | #define DCORE3_MME_SBTE3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20584 | #define mmDCORE3_MME_SBTE3_MSTR_IF_AXUSER_BASE 0x46E9A80ull |
|---|
| 20585 | #define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20586 | #define DCORE3_MME_SBTE3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20587 | #define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_BASE 0x46E9B00ull |
|---|
| 20588 | #define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20589 | #define DCORE3_MME_SBTE3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20590 | #define mmDCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_BASE 0x46E9B80ull |
|---|
| 20591 | #define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20592 | #define DCORE3_MME_SBTE3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20593 | #define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_BASE 0x46E9C00ull |
|---|
| 20594 | #define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20595 | #define DCORE3_MME_SBTE3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20596 | #define mmDCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_BASE 0x46E9D80ull |
|---|
| 20597 | #define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20598 | #define DCORE3_MME_SBTE3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20599 | #define mmDCORE3_MME_SBTE3_MSTR_IF_SPECIAL_BASE 0x46E9E80ull |
|---|
| 20600 | #define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20601 | #define DCORE3_MME_SBTE3_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 20602 | #define mmDCORE3_MME_SBTE4_BASE 0x46F0000ull |
|---|
| 20603 | #define DCORE3_MME_SBTE4_MAX_OFFSET 0x1000 |
|---|
| 20604 | #define DCORE3_MME_SBTE4_SECTION 0xE800 |
|---|
| 20605 | #define mmDCORE3_MME_SBTE4_SPECIAL_BASE 0x46F0E80ull |
|---|
| 20606 | #define DCORE3_MME_SBTE4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20607 | #define DCORE3_MME_SBTE4_SPECIAL_SECTION 0x1800 |
|---|
| 20608 | #define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_BASE 0x46F1000ull |
|---|
| 20609 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20610 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20611 | #define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_BASE 0x46F1200ull |
|---|
| 20612 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20613 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20614 | #define mmDCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_BASE 0x46F1400ull |
|---|
| 20615 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20616 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20617 | #define mmDCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_BASE 0x46F1600ull |
|---|
| 20618 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20619 | #define DCORE3_MME_SBTE4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20620 | #define mmDCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_BASE 0x46F1800ull |
|---|
| 20621 | #define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20622 | #define DCORE3_MME_SBTE4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20623 | #define mmDCORE3_MME_SBTE4_MSTR_IF_AXUSER_BASE 0x46F1A80ull |
|---|
| 20624 | #define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20625 | #define DCORE3_MME_SBTE4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20626 | #define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_BASE 0x46F1B00ull |
|---|
| 20627 | #define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20628 | #define DCORE3_MME_SBTE4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20629 | #define mmDCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_BASE 0x46F1B80ull |
|---|
| 20630 | #define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20631 | #define DCORE3_MME_SBTE4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20632 | #define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_BASE 0x46F1C00ull |
|---|
| 20633 | #define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20634 | #define DCORE3_MME_SBTE4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20635 | #define mmDCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_BASE 0x46F1D80ull |
|---|
| 20636 | #define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20637 | #define DCORE3_MME_SBTE4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20638 | #define mmDCORE3_MME_SBTE4_MSTR_IF_SPECIAL_BASE 0x46F1E80ull |
|---|
| 20639 | #define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20640 | #define DCORE3_MME_SBTE4_MSTR_IF_SPECIAL_SECTION 0x6180 |
|---|
| 20641 | #define mmDCORE3_MME_ACC_BASE 0x46F8000ull |
|---|
| 20642 | #define DCORE3_MME_ACC_MAX_OFFSET 0x1000 |
|---|
| 20643 | #define DCORE3_MME_ACC_SECTION 0xE800 |
|---|
| 20644 | #define mmDCORE3_MME_ACC_SPECIAL_BASE 0x46F8E80ull |
|---|
| 20645 | #define DCORE3_MME_ACC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20646 | #define DCORE3_MME_ACC_SPECIAL_SECTION 0x1800 |
|---|
| 20647 | #define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE 0x46F9000ull |
|---|
| 20648 | #define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20649 | #define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20650 | #define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_BASE 0x46F9200ull |
|---|
| 20651 | #define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20652 | #define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20653 | #define mmDCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_BASE 0x46F9400ull |
|---|
| 20654 | #define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20655 | #define DCORE3_MME_WB0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20656 | #define mmDCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_BASE 0x46F9600ull |
|---|
| 20657 | #define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20658 | #define DCORE3_MME_WB0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20659 | #define mmDCORE3_MME_WB0_MSTR_IF_E2E_CRDT_BASE 0x46F9800ull |
|---|
| 20660 | #define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20661 | #define DCORE3_MME_WB0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20662 | #define mmDCORE3_MME_WB0_MSTR_IF_AXUSER_BASE 0x46F9A80ull |
|---|
| 20663 | #define DCORE3_MME_WB0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20664 | #define DCORE3_MME_WB0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20665 | #define mmDCORE3_MME_WB0_MSTR_IF_DBG_HBW_BASE 0x46F9B00ull |
|---|
| 20666 | #define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20667 | #define DCORE3_MME_WB0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20668 | #define mmDCORE3_MME_WB0_MSTR_IF_DBG_LBW_BASE 0x46F9B80ull |
|---|
| 20669 | #define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20670 | #define DCORE3_MME_WB0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20671 | #define mmDCORE3_MME_WB0_MSTR_IF_CORE_HBW_BASE 0x46F9C00ull |
|---|
| 20672 | #define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20673 | #define DCORE3_MME_WB0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20674 | #define mmDCORE3_MME_WB0_MSTR_IF_CORE_LBW_BASE 0x46F9D80ull |
|---|
| 20675 | #define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20676 | #define DCORE3_MME_WB0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20677 | #define mmDCORE3_MME_WB0_MSTR_IF_SPECIAL_BASE 0x46F9E80ull |
|---|
| 20678 | #define DCORE3_MME_WB0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20679 | #define DCORE3_MME_WB0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 20680 | #define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE 0x46FA000ull |
|---|
| 20681 | #define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20682 | #define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20683 | #define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_BASE 0x46FA200ull |
|---|
| 20684 | #define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20685 | #define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20686 | #define mmDCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_BASE 0x46FA400ull |
|---|
| 20687 | #define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20688 | #define DCORE3_MME_WB1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20689 | #define mmDCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_BASE 0x46FA600ull |
|---|
| 20690 | #define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20691 | #define DCORE3_MME_WB1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20692 | #define mmDCORE3_MME_WB1_MSTR_IF_E2E_CRDT_BASE 0x46FA800ull |
|---|
| 20693 | #define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20694 | #define DCORE3_MME_WB1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20695 | #define mmDCORE3_MME_WB1_MSTR_IF_AXUSER_BASE 0x46FAA80ull |
|---|
| 20696 | #define DCORE3_MME_WB1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20697 | #define DCORE3_MME_WB1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20698 | #define mmDCORE3_MME_WB1_MSTR_IF_DBG_HBW_BASE 0x46FAB00ull |
|---|
| 20699 | #define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20700 | #define DCORE3_MME_WB1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20701 | #define mmDCORE3_MME_WB1_MSTR_IF_DBG_LBW_BASE 0x46FAB80ull |
|---|
| 20702 | #define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20703 | #define DCORE3_MME_WB1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20704 | #define mmDCORE3_MME_WB1_MSTR_IF_CORE_HBW_BASE 0x46FAC00ull |
|---|
| 20705 | #define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20706 | #define DCORE3_MME_WB1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20707 | #define mmDCORE3_MME_WB1_MSTR_IF_CORE_LBW_BASE 0x46FAD80ull |
|---|
| 20708 | #define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20709 | #define DCORE3_MME_WB1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20710 | #define mmDCORE3_MME_WB1_MSTR_IF_SPECIAL_BASE 0x46FAE80ull |
|---|
| 20711 | #define DCORE3_MME_WB1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20712 | #define DCORE3_MME_WB1_MSTR_IF_SPECIAL_SECTION 0x5180 |
|---|
| 20713 | #define mmDCORE3_SYNC_MNGR_OBJS_BASE 0x4700000ull |
|---|
| 20714 | #define DCORE3_SYNC_MNGR_OBJS_MAX_OFFSET 0x15A00 |
|---|
| 20715 | #define DCORE3_SYNC_MNGR_OBJS_SECTION 0x1E000 |
|---|
| 20716 | #define mmDCORE3_SYNC_MNGR_GLBL_BASE 0x471E000ull |
|---|
| 20717 | #define DCORE3_SYNC_MNGR_GLBL_MAX_OFFSET 0x1000 |
|---|
| 20718 | #define DCORE3_SYNC_MNGR_GLBL_SECTION 0xE800 |
|---|
| 20719 | #define mmDCORE3_SYNC_MNGR_GLBL_SPECIAL_BASE 0x471EE80ull |
|---|
| 20720 | #define DCORE3_SYNC_MNGR_GLBL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20721 | #define DCORE3_SYNC_MNGR_GLBL_SPECIAL_SECTION 0x1800 |
|---|
| 20722 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE 0x471F000ull |
|---|
| 20723 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20724 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20725 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_BASE 0x471F200ull |
|---|
| 20726 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20727 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20728 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_BASE 0x471F400ull |
|---|
| 20729 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20730 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20731 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_BASE 0x471F600ull |
|---|
| 20732 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20733 | #define DCORE3_SYNC_MNGR_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20734 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_BASE 0x471F800ull |
|---|
| 20735 | #define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20736 | #define DCORE3_SYNC_MNGR_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20737 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_AXUSER_BASE 0x471FA80ull |
|---|
| 20738 | #define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20739 | #define DCORE3_SYNC_MNGR_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20740 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_BASE 0x471FB00ull |
|---|
| 20741 | #define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20742 | #define DCORE3_SYNC_MNGR_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20743 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_BASE 0x471FB80ull |
|---|
| 20744 | #define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20745 | #define DCORE3_SYNC_MNGR_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20746 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_BASE 0x471FC00ull |
|---|
| 20747 | #define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20748 | #define DCORE3_SYNC_MNGR_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20749 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_BASE 0x471FD80ull |
|---|
| 20750 | #define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20751 | #define DCORE3_SYNC_MNGR_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20752 | #define mmDCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_BASE 0x471FE80ull |
|---|
| 20753 | #define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20754 | #define DCORE3_SYNC_MNGR_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 20755 | #define mmDCORE3_HIF0_BASE 0x4720000ull |
|---|
| 20756 | #define DCORE3_HIF0_MAX_OFFSET 0x1000 |
|---|
| 20757 | #define DCORE3_HIF0_SECTION 0xE800 |
|---|
| 20758 | #define mmDCORE3_HIF0_SPECIAL_BASE 0x4720E80ull |
|---|
| 20759 | #define DCORE3_HIF0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20760 | #define DCORE3_HIF0_SPECIAL_SECTION 0x3180 |
|---|
| 20761 | #define mmDCORE3_HIF1_BASE 0x4724000ull |
|---|
| 20762 | #define DCORE3_HIF1_MAX_OFFSET 0x1000 |
|---|
| 20763 | #define DCORE3_HIF1_SECTION 0xE800 |
|---|
| 20764 | #define mmDCORE3_HIF1_SPECIAL_BASE 0x4724E80ull |
|---|
| 20765 | #define DCORE3_HIF1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20766 | #define DCORE3_HIF1_SPECIAL_SECTION 0x3180 |
|---|
| 20767 | #define mmDCORE3_HIF2_BASE 0x4728000ull |
|---|
| 20768 | #define DCORE3_HIF2_MAX_OFFSET 0x1000 |
|---|
| 20769 | #define DCORE3_HIF2_SECTION 0xE800 |
|---|
| 20770 | #define mmDCORE3_HIF2_SPECIAL_BASE 0x4728E80ull |
|---|
| 20771 | #define DCORE3_HIF2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20772 | #define DCORE3_HIF2_SPECIAL_SECTION 0x3180 |
|---|
| 20773 | #define mmDCORE3_HIF3_BASE 0x472C000ull |
|---|
| 20774 | #define DCORE3_HIF3_MAX_OFFSET 0x1000 |
|---|
| 20775 | #define DCORE3_HIF3_SECTION 0xE800 |
|---|
| 20776 | #define mmDCORE3_HIF3_SPECIAL_BASE 0x472CE80ull |
|---|
| 20777 | #define DCORE3_HIF3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20778 | #define DCORE3_HIF3_SPECIAL_SECTION 0x13180 |
|---|
| 20779 | #define mmDCORE3_RTR0_CTRL_BASE 0x4740000ull |
|---|
| 20780 | #define DCORE3_RTR0_CTRL_MAX_OFFSET 0x1000 |
|---|
| 20781 | #define DCORE3_RTR0_CTRL_SECTION 0xE800 |
|---|
| 20782 | #define mmDCORE3_RTR0_CTRL_SPECIAL_BASE 0x4740E80ull |
|---|
| 20783 | #define DCORE3_RTR0_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20784 | #define DCORE3_RTR0_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 20785 | #define mmDCORE3_RTR0_H3_BASE 0x4741000ull |
|---|
| 20786 | #define DCORE3_RTR0_H3_MAX_OFFSET 0x1000 |
|---|
| 20787 | #define DCORE3_RTR0_H3_SECTION 0xE800 |
|---|
| 20788 | #define mmDCORE3_RTR0_H3_SPECIAL_BASE 0x4741E80ull |
|---|
| 20789 | #define DCORE3_RTR0_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20790 | #define DCORE3_RTR0_H3_SPECIAL_SECTION 0x1800 |
|---|
| 20791 | #define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_BASE 0x4742000ull |
|---|
| 20792 | #define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20793 | #define DCORE3_RTR0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20794 | #define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_BASE 0x4742200ull |
|---|
| 20795 | #define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20796 | #define DCORE3_RTR0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20797 | #define mmDCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_BASE 0x4742400ull |
|---|
| 20798 | #define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20799 | #define DCORE3_RTR0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20800 | #define mmDCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_BASE 0x4742600ull |
|---|
| 20801 | #define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20802 | #define DCORE3_RTR0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20803 | #define mmDCORE3_RTR0_MSTR_IF_E2E_CRDT_BASE 0x4742800ull |
|---|
| 20804 | #define DCORE3_RTR0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20805 | #define DCORE3_RTR0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20806 | #define mmDCORE3_RTR0_MSTR_IF_AXUSER_BASE 0x4742A80ull |
|---|
| 20807 | #define DCORE3_RTR0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20808 | #define DCORE3_RTR0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20809 | #define mmDCORE3_RTR0_MSTR_IF_DBG_HBW_BASE 0x4742B00ull |
|---|
| 20810 | #define DCORE3_RTR0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20811 | #define DCORE3_RTR0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20812 | #define mmDCORE3_RTR0_MSTR_IF_DBG_LBW_BASE 0x4742B80ull |
|---|
| 20813 | #define DCORE3_RTR0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20814 | #define DCORE3_RTR0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20815 | #define mmDCORE3_RTR0_MSTR_IF_CORE_HBW_BASE 0x4742C00ull |
|---|
| 20816 | #define DCORE3_RTR0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20817 | #define DCORE3_RTR0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20818 | #define mmDCORE3_RTR0_MSTR_IF_CORE_LBW_BASE 0x4742D80ull |
|---|
| 20819 | #define DCORE3_RTR0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20820 | #define DCORE3_RTR0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20821 | #define mmDCORE3_RTR0_MSTR_IF_SPECIAL_BASE 0x4742E80ull |
|---|
| 20822 | #define DCORE3_RTR0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20823 | #define DCORE3_RTR0_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 20824 | #define mmDCORE3_RTR0_ADD_DEC_HBW_BASE 0x4743000ull |
|---|
| 20825 | #define DCORE3_RTR0_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 20826 | #define DCORE3_RTR0_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 20827 | #define mmDCORE3_RTR0_ADD_DEC_LBW_BASE 0x4743400ull |
|---|
| 20828 | #define DCORE3_RTR0_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 20829 | #define DCORE3_RTR0_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 20830 | #define mmDCORE3_RTR0_ADD_DEC_SPECIAL_BASE 0x4743E80ull |
|---|
| 20831 | #define DCORE3_RTR0_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20832 | #define DCORE3_RTR0_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 20833 | #define mmDCORE3_RTR0_BASE 0x4744000ull |
|---|
| 20834 | #define DCORE3_RTR0_MAX_OFFSET 0x1000 |
|---|
| 20835 | #define DCORE3_RTR0_SECTION 0x3000 |
|---|
| 20836 | #define mmDCORE3_RTR0_HBW_RD_RQ_LL_STAT_BASE 0x4744300ull |
|---|
| 20837 | #define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20838 | #define DCORE3_RTR0_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20839 | #define mmDCORE3_RTR0_HBW_RD_RS_LL_STAT_BASE 0x4744340ull |
|---|
| 20840 | #define DCORE3_RTR0_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20841 | #define DCORE3_RTR0_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20842 | #define mmDCORE3_RTR0_HBW_WR_RQ_LL_STAT_BASE 0x4744380ull |
|---|
| 20843 | #define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20844 | #define DCORE3_RTR0_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20845 | #define mmDCORE3_RTR0_HBW_WR_RS_LL_STAT_BASE 0x47443C0ull |
|---|
| 20846 | #define DCORE3_RTR0_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20847 | #define DCORE3_RTR0_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20848 | #define mmDCORE3_RTR0_LBW_RD_RQ_LL_STAT_BASE 0x4744400ull |
|---|
| 20849 | #define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20850 | #define DCORE3_RTR0_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20851 | #define mmDCORE3_RTR0_LBW_RD_RS_LL_STAT_BASE 0x4744440ull |
|---|
| 20852 | #define DCORE3_RTR0_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20853 | #define DCORE3_RTR0_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20854 | #define mmDCORE3_RTR0_LBW_WR_RQ_LL_STAT_BASE 0x4744480ull |
|---|
| 20855 | #define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20856 | #define DCORE3_RTR0_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20857 | #define mmDCORE3_RTR0_LBW_WR_RS_LL_STAT_BASE 0x47444C0ull |
|---|
| 20858 | #define DCORE3_RTR0_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20859 | #define DCORE3_RTR0_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20860 | #define mmDCORE3_RTR0_HBW_MFIFO_BASE 0x4744500ull |
|---|
| 20861 | #define DCORE3_RTR0_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 20862 | #define DCORE3_RTR0_HBW_MFIFO_SECTION 0x4000 |
|---|
| 20863 | #define mmDCORE3_RTR0_E2E_RD_LL_STAT_BASE 0x4744540ull |
|---|
| 20864 | #define DCORE3_RTR0_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20865 | #define DCORE3_RTR0_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 20866 | #define mmDCORE3_RTR0_E2E_WR_LL_STAT_BASE 0x4744580ull |
|---|
| 20867 | #define DCORE3_RTR0_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20868 | #define DCORE3_RTR0_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 20869 | #define mmDCORE3_RTR0_RTR_HBW_XACT_STAT_BASE 0x4744600ull |
|---|
| 20870 | #define DCORE3_RTR0_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20871 | #define DCORE3_RTR0_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 20872 | #define mmDCORE3_RTR0_RTR_LBW_XACT_STAT_BASE 0x4744680ull |
|---|
| 20873 | #define DCORE3_RTR0_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20874 | #define DCORE3_RTR0_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 20875 | #define mmDCORE3_RTR0_RTR_E2E_XACT_STAT_BASE 0x4744700ull |
|---|
| 20876 | #define DCORE3_RTR0_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20877 | #define DCORE3_RTR0_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 20878 | #define mmDCORE3_RTR0_SPECIAL_BASE 0x4744E80ull |
|---|
| 20879 | #define DCORE3_RTR0_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20880 | #define DCORE3_RTR0_SPECIAL_SECTION 0x1800 |
|---|
| 20881 | #define mmDCORE3_RTR0_DBG_ADDR_BASE 0x4745000ull |
|---|
| 20882 | #define DCORE3_RTR0_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 20883 | #define DCORE3_RTR0_DBG_ADDR_SECTION 0xE800 |
|---|
| 20884 | #define mmDCORE3_RTR0_DBG_ADDR_SPECIAL_BASE 0x4745E80ull |
|---|
| 20885 | #define DCORE3_RTR0_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20886 | #define DCORE3_RTR0_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 20887 | #define mmDCORE3_RTR1_CTRL_BASE 0x4748000ull |
|---|
| 20888 | #define DCORE3_RTR1_CTRL_MAX_OFFSET 0x1000 |
|---|
| 20889 | #define DCORE3_RTR1_CTRL_SECTION 0xE800 |
|---|
| 20890 | #define mmDCORE3_RTR1_CTRL_SPECIAL_BASE 0x4748E80ull |
|---|
| 20891 | #define DCORE3_RTR1_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20892 | #define DCORE3_RTR1_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 20893 | #define mmDCORE3_RTR1_H3_BASE 0x4749000ull |
|---|
| 20894 | #define DCORE3_RTR1_H3_MAX_OFFSET 0x1000 |
|---|
| 20895 | #define DCORE3_RTR1_H3_SECTION 0xE800 |
|---|
| 20896 | #define mmDCORE3_RTR1_H3_SPECIAL_BASE 0x4749E80ull |
|---|
| 20897 | #define DCORE3_RTR1_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20898 | #define DCORE3_RTR1_H3_SPECIAL_SECTION 0x1800 |
|---|
| 20899 | #define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_BASE 0x474A000ull |
|---|
| 20900 | #define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20901 | #define DCORE3_RTR1_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 20902 | #define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_BASE 0x474A200ull |
|---|
| 20903 | #define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 20904 | #define DCORE3_RTR1_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 20905 | #define mmDCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_BASE 0x474A400ull |
|---|
| 20906 | #define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20907 | #define DCORE3_RTR1_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 20908 | #define mmDCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_BASE 0x474A600ull |
|---|
| 20909 | #define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 20910 | #define DCORE3_RTR1_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 20911 | #define mmDCORE3_RTR1_MSTR_IF_E2E_CRDT_BASE 0x474A800ull |
|---|
| 20912 | #define DCORE3_RTR1_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 20913 | #define DCORE3_RTR1_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 20914 | #define mmDCORE3_RTR1_MSTR_IF_AXUSER_BASE 0x474AA80ull |
|---|
| 20915 | #define DCORE3_RTR1_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 20916 | #define DCORE3_RTR1_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 20917 | #define mmDCORE3_RTR1_MSTR_IF_DBG_HBW_BASE 0x474AB00ull |
|---|
| 20918 | #define DCORE3_RTR1_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 20919 | #define DCORE3_RTR1_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 20920 | #define mmDCORE3_RTR1_MSTR_IF_DBG_LBW_BASE 0x474AB80ull |
|---|
| 20921 | #define DCORE3_RTR1_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 20922 | #define DCORE3_RTR1_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 20923 | #define mmDCORE3_RTR1_MSTR_IF_CORE_HBW_BASE 0x474AC00ull |
|---|
| 20924 | #define DCORE3_RTR1_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 20925 | #define DCORE3_RTR1_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 20926 | #define mmDCORE3_RTR1_MSTR_IF_CORE_LBW_BASE 0x474AD80ull |
|---|
| 20927 | #define DCORE3_RTR1_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 20928 | #define DCORE3_RTR1_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 20929 | #define mmDCORE3_RTR1_MSTR_IF_SPECIAL_BASE 0x474AE80ull |
|---|
| 20930 | #define DCORE3_RTR1_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20931 | #define DCORE3_RTR1_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 20932 | #define mmDCORE3_RTR1_ADD_DEC_HBW_BASE 0x474B000ull |
|---|
| 20933 | #define DCORE3_RTR1_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 20934 | #define DCORE3_RTR1_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 20935 | #define mmDCORE3_RTR1_ADD_DEC_LBW_BASE 0x474B400ull |
|---|
| 20936 | #define DCORE3_RTR1_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 20937 | #define DCORE3_RTR1_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 20938 | #define mmDCORE3_RTR1_ADD_DEC_SPECIAL_BASE 0x474BE80ull |
|---|
| 20939 | #define DCORE3_RTR1_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20940 | #define DCORE3_RTR1_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 20941 | #define mmDCORE3_RTR1_BASE 0x474C000ull |
|---|
| 20942 | #define DCORE3_RTR1_MAX_OFFSET 0x1000 |
|---|
| 20943 | #define DCORE3_RTR1_SECTION 0x3000 |
|---|
| 20944 | #define mmDCORE3_RTR1_HBW_RD_RQ_LL_STAT_BASE 0x474C300ull |
|---|
| 20945 | #define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20946 | #define DCORE3_RTR1_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20947 | #define mmDCORE3_RTR1_HBW_RD_RS_LL_STAT_BASE 0x474C340ull |
|---|
| 20948 | #define DCORE3_RTR1_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20949 | #define DCORE3_RTR1_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20950 | #define mmDCORE3_RTR1_HBW_WR_RQ_LL_STAT_BASE 0x474C380ull |
|---|
| 20951 | #define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20952 | #define DCORE3_RTR1_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20953 | #define mmDCORE3_RTR1_HBW_WR_RS_LL_STAT_BASE 0x474C3C0ull |
|---|
| 20954 | #define DCORE3_RTR1_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20955 | #define DCORE3_RTR1_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20956 | #define mmDCORE3_RTR1_LBW_RD_RQ_LL_STAT_BASE 0x474C400ull |
|---|
| 20957 | #define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20958 | #define DCORE3_RTR1_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20959 | #define mmDCORE3_RTR1_LBW_RD_RS_LL_STAT_BASE 0x474C440ull |
|---|
| 20960 | #define DCORE3_RTR1_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20961 | #define DCORE3_RTR1_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20962 | #define mmDCORE3_RTR1_LBW_WR_RQ_LL_STAT_BASE 0x474C480ull |
|---|
| 20963 | #define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20964 | #define DCORE3_RTR1_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 20965 | #define mmDCORE3_RTR1_LBW_WR_RS_LL_STAT_BASE 0x474C4C0ull |
|---|
| 20966 | #define DCORE3_RTR1_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20967 | #define DCORE3_RTR1_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 20968 | #define mmDCORE3_RTR1_HBW_MFIFO_BASE 0x474C500ull |
|---|
| 20969 | #define DCORE3_RTR1_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 20970 | #define DCORE3_RTR1_HBW_MFIFO_SECTION 0x4000 |
|---|
| 20971 | #define mmDCORE3_RTR1_E2E_RD_LL_STAT_BASE 0x474C540ull |
|---|
| 20972 | #define DCORE3_RTR1_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20973 | #define DCORE3_RTR1_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 20974 | #define mmDCORE3_RTR1_E2E_WR_LL_STAT_BASE 0x474C580ull |
|---|
| 20975 | #define DCORE3_RTR1_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 20976 | #define DCORE3_RTR1_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 20977 | #define mmDCORE3_RTR1_RTR_HBW_XACT_STAT_BASE 0x474C600ull |
|---|
| 20978 | #define DCORE3_RTR1_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20979 | #define DCORE3_RTR1_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 20980 | #define mmDCORE3_RTR1_RTR_LBW_XACT_STAT_BASE 0x474C680ull |
|---|
| 20981 | #define DCORE3_RTR1_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20982 | #define DCORE3_RTR1_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 20983 | #define mmDCORE3_RTR1_RTR_E2E_XACT_STAT_BASE 0x474C700ull |
|---|
| 20984 | #define DCORE3_RTR1_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 20985 | #define DCORE3_RTR1_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 20986 | #define mmDCORE3_RTR1_SPECIAL_BASE 0x474CE80ull |
|---|
| 20987 | #define DCORE3_RTR1_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20988 | #define DCORE3_RTR1_SPECIAL_SECTION 0x1800 |
|---|
| 20989 | #define mmDCORE3_RTR1_DBG_ADDR_BASE 0x474D000ull |
|---|
| 20990 | #define DCORE3_RTR1_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 20991 | #define DCORE3_RTR1_DBG_ADDR_SECTION 0xE800 |
|---|
| 20992 | #define mmDCORE3_RTR1_DBG_ADDR_SPECIAL_BASE 0x474DE80ull |
|---|
| 20993 | #define DCORE3_RTR1_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 20994 | #define DCORE3_RTR1_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 20995 | #define mmDCORE3_RTR2_CTRL_BASE 0x4750000ull |
|---|
| 20996 | #define DCORE3_RTR2_CTRL_MAX_OFFSET 0x1000 |
|---|
| 20997 | #define DCORE3_RTR2_CTRL_SECTION 0xE800 |
|---|
| 20998 | #define mmDCORE3_RTR2_CTRL_SPECIAL_BASE 0x4750E80ull |
|---|
| 20999 | #define DCORE3_RTR2_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21000 | #define DCORE3_RTR2_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21001 | #define mmDCORE3_RTR2_H3_BASE 0x4751000ull |
|---|
| 21002 | #define DCORE3_RTR2_H3_MAX_OFFSET 0x1000 |
|---|
| 21003 | #define DCORE3_RTR2_H3_SECTION 0xE800 |
|---|
| 21004 | #define mmDCORE3_RTR2_H3_SPECIAL_BASE 0x4751E80ull |
|---|
| 21005 | #define DCORE3_RTR2_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21006 | #define DCORE3_RTR2_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21007 | #define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_BASE 0x4752000ull |
|---|
| 21008 | #define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21009 | #define DCORE3_RTR2_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21010 | #define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_BASE 0x4752200ull |
|---|
| 21011 | #define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21012 | #define DCORE3_RTR2_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21013 | #define mmDCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_BASE 0x4752400ull |
|---|
| 21014 | #define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21015 | #define DCORE3_RTR2_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21016 | #define mmDCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_BASE 0x4752600ull |
|---|
| 21017 | #define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21018 | #define DCORE3_RTR2_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21019 | #define mmDCORE3_RTR2_MSTR_IF_E2E_CRDT_BASE 0x4752800ull |
|---|
| 21020 | #define DCORE3_RTR2_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21021 | #define DCORE3_RTR2_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21022 | #define mmDCORE3_RTR2_MSTR_IF_AXUSER_BASE 0x4752A80ull |
|---|
| 21023 | #define DCORE3_RTR2_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21024 | #define DCORE3_RTR2_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21025 | #define mmDCORE3_RTR2_MSTR_IF_DBG_HBW_BASE 0x4752B00ull |
|---|
| 21026 | #define DCORE3_RTR2_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21027 | #define DCORE3_RTR2_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21028 | #define mmDCORE3_RTR2_MSTR_IF_DBG_LBW_BASE 0x4752B80ull |
|---|
| 21029 | #define DCORE3_RTR2_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21030 | #define DCORE3_RTR2_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21031 | #define mmDCORE3_RTR2_MSTR_IF_CORE_HBW_BASE 0x4752C00ull |
|---|
| 21032 | #define DCORE3_RTR2_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21033 | #define DCORE3_RTR2_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21034 | #define mmDCORE3_RTR2_MSTR_IF_CORE_LBW_BASE 0x4752D80ull |
|---|
| 21035 | #define DCORE3_RTR2_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21036 | #define DCORE3_RTR2_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21037 | #define mmDCORE3_RTR2_MSTR_IF_SPECIAL_BASE 0x4752E80ull |
|---|
| 21038 | #define DCORE3_RTR2_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21039 | #define DCORE3_RTR2_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21040 | #define mmDCORE3_RTR2_ADD_DEC_HBW_BASE 0x4753000ull |
|---|
| 21041 | #define DCORE3_RTR2_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21042 | #define DCORE3_RTR2_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21043 | #define mmDCORE3_RTR2_ADD_DEC_LBW_BASE 0x4753400ull |
|---|
| 21044 | #define DCORE3_RTR2_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21045 | #define DCORE3_RTR2_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21046 | #define mmDCORE3_RTR2_ADD_DEC_SPECIAL_BASE 0x4753E80ull |
|---|
| 21047 | #define DCORE3_RTR2_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21048 | #define DCORE3_RTR2_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21049 | #define mmDCORE3_RTR2_BASE 0x4754000ull |
|---|
| 21050 | #define DCORE3_RTR2_MAX_OFFSET 0x1000 |
|---|
| 21051 | #define DCORE3_RTR2_SECTION 0x3000 |
|---|
| 21052 | #define mmDCORE3_RTR2_HBW_RD_RQ_LL_STAT_BASE 0x4754300ull |
|---|
| 21053 | #define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21054 | #define DCORE3_RTR2_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21055 | #define mmDCORE3_RTR2_HBW_RD_RS_LL_STAT_BASE 0x4754340ull |
|---|
| 21056 | #define DCORE3_RTR2_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21057 | #define DCORE3_RTR2_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21058 | #define mmDCORE3_RTR2_HBW_WR_RQ_LL_STAT_BASE 0x4754380ull |
|---|
| 21059 | #define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21060 | #define DCORE3_RTR2_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21061 | #define mmDCORE3_RTR2_HBW_WR_RS_LL_STAT_BASE 0x47543C0ull |
|---|
| 21062 | #define DCORE3_RTR2_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21063 | #define DCORE3_RTR2_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21064 | #define mmDCORE3_RTR2_LBW_RD_RQ_LL_STAT_BASE 0x4754400ull |
|---|
| 21065 | #define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21066 | #define DCORE3_RTR2_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21067 | #define mmDCORE3_RTR2_LBW_RD_RS_LL_STAT_BASE 0x4754440ull |
|---|
| 21068 | #define DCORE3_RTR2_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21069 | #define DCORE3_RTR2_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21070 | #define mmDCORE3_RTR2_LBW_WR_RQ_LL_STAT_BASE 0x4754480ull |
|---|
| 21071 | #define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21072 | #define DCORE3_RTR2_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21073 | #define mmDCORE3_RTR2_LBW_WR_RS_LL_STAT_BASE 0x47544C0ull |
|---|
| 21074 | #define DCORE3_RTR2_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21075 | #define DCORE3_RTR2_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21076 | #define mmDCORE3_RTR2_HBW_MFIFO_BASE 0x4754500ull |
|---|
| 21077 | #define DCORE3_RTR2_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21078 | #define DCORE3_RTR2_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21079 | #define mmDCORE3_RTR2_E2E_RD_LL_STAT_BASE 0x4754540ull |
|---|
| 21080 | #define DCORE3_RTR2_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21081 | #define DCORE3_RTR2_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21082 | #define mmDCORE3_RTR2_E2E_WR_LL_STAT_BASE 0x4754580ull |
|---|
| 21083 | #define DCORE3_RTR2_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21084 | #define DCORE3_RTR2_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21085 | #define mmDCORE3_RTR2_RTR_HBW_XACT_STAT_BASE 0x4754600ull |
|---|
| 21086 | #define DCORE3_RTR2_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21087 | #define DCORE3_RTR2_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21088 | #define mmDCORE3_RTR2_RTR_LBW_XACT_STAT_BASE 0x4754680ull |
|---|
| 21089 | #define DCORE3_RTR2_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21090 | #define DCORE3_RTR2_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21091 | #define mmDCORE3_RTR2_RTR_E2E_XACT_STAT_BASE 0x4754700ull |
|---|
| 21092 | #define DCORE3_RTR2_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21093 | #define DCORE3_RTR2_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21094 | #define mmDCORE3_RTR2_SPECIAL_BASE 0x4754E80ull |
|---|
| 21095 | #define DCORE3_RTR2_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21096 | #define DCORE3_RTR2_SPECIAL_SECTION 0x1800 |
|---|
| 21097 | #define mmDCORE3_RTR2_DBG_ADDR_BASE 0x4755000ull |
|---|
| 21098 | #define DCORE3_RTR2_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21099 | #define DCORE3_RTR2_DBG_ADDR_SECTION 0xE800 |
|---|
| 21100 | #define mmDCORE3_RTR2_DBG_ADDR_SPECIAL_BASE 0x4755E80ull |
|---|
| 21101 | #define DCORE3_RTR2_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21102 | #define DCORE3_RTR2_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21103 | #define mmDCORE3_RTR3_CTRL_BASE 0x4758000ull |
|---|
| 21104 | #define DCORE3_RTR3_CTRL_MAX_OFFSET 0x1000 |
|---|
| 21105 | #define DCORE3_RTR3_CTRL_SECTION 0xE800 |
|---|
| 21106 | #define mmDCORE3_RTR3_CTRL_SPECIAL_BASE 0x4758E80ull |
|---|
| 21107 | #define DCORE3_RTR3_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21108 | #define DCORE3_RTR3_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21109 | #define mmDCORE3_RTR3_H3_BASE 0x4759000ull |
|---|
| 21110 | #define DCORE3_RTR3_H3_MAX_OFFSET 0x1000 |
|---|
| 21111 | #define DCORE3_RTR3_H3_SECTION 0xE800 |
|---|
| 21112 | #define mmDCORE3_RTR3_H3_SPECIAL_BASE 0x4759E80ull |
|---|
| 21113 | #define DCORE3_RTR3_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21114 | #define DCORE3_RTR3_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21115 | #define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_BASE 0x475A000ull |
|---|
| 21116 | #define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21117 | #define DCORE3_RTR3_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21118 | #define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_BASE 0x475A200ull |
|---|
| 21119 | #define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21120 | #define DCORE3_RTR3_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21121 | #define mmDCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_BASE 0x475A400ull |
|---|
| 21122 | #define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21123 | #define DCORE3_RTR3_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21124 | #define mmDCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_BASE 0x475A600ull |
|---|
| 21125 | #define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21126 | #define DCORE3_RTR3_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21127 | #define mmDCORE3_RTR3_MSTR_IF_E2E_CRDT_BASE 0x475A800ull |
|---|
| 21128 | #define DCORE3_RTR3_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21129 | #define DCORE3_RTR3_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21130 | #define mmDCORE3_RTR3_MSTR_IF_AXUSER_BASE 0x475AA80ull |
|---|
| 21131 | #define DCORE3_RTR3_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21132 | #define DCORE3_RTR3_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21133 | #define mmDCORE3_RTR3_MSTR_IF_DBG_HBW_BASE 0x475AB00ull |
|---|
| 21134 | #define DCORE3_RTR3_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21135 | #define DCORE3_RTR3_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21136 | #define mmDCORE3_RTR3_MSTR_IF_DBG_LBW_BASE 0x475AB80ull |
|---|
| 21137 | #define DCORE3_RTR3_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21138 | #define DCORE3_RTR3_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21139 | #define mmDCORE3_RTR3_MSTR_IF_CORE_HBW_BASE 0x475AC00ull |
|---|
| 21140 | #define DCORE3_RTR3_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21141 | #define DCORE3_RTR3_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21142 | #define mmDCORE3_RTR3_MSTR_IF_CORE_LBW_BASE 0x475AD80ull |
|---|
| 21143 | #define DCORE3_RTR3_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21144 | #define DCORE3_RTR3_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21145 | #define mmDCORE3_RTR3_MSTR_IF_SPECIAL_BASE 0x475AE80ull |
|---|
| 21146 | #define DCORE3_RTR3_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21147 | #define DCORE3_RTR3_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21148 | #define mmDCORE3_RTR3_ADD_DEC_HBW_BASE 0x475B000ull |
|---|
| 21149 | #define DCORE3_RTR3_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21150 | #define DCORE3_RTR3_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21151 | #define mmDCORE3_RTR3_ADD_DEC_LBW_BASE 0x475B400ull |
|---|
| 21152 | #define DCORE3_RTR3_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21153 | #define DCORE3_RTR3_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21154 | #define mmDCORE3_RTR3_ADD_DEC_SPECIAL_BASE 0x475BE80ull |
|---|
| 21155 | #define DCORE3_RTR3_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21156 | #define DCORE3_RTR3_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21157 | #define mmDCORE3_RTR3_BASE 0x475C000ull |
|---|
| 21158 | #define DCORE3_RTR3_MAX_OFFSET 0x1000 |
|---|
| 21159 | #define DCORE3_RTR3_SECTION 0x3000 |
|---|
| 21160 | #define mmDCORE3_RTR3_HBW_RD_RQ_LL_STAT_BASE 0x475C300ull |
|---|
| 21161 | #define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21162 | #define DCORE3_RTR3_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21163 | #define mmDCORE3_RTR3_HBW_RD_RS_LL_STAT_BASE 0x475C340ull |
|---|
| 21164 | #define DCORE3_RTR3_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21165 | #define DCORE3_RTR3_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21166 | #define mmDCORE3_RTR3_HBW_WR_RQ_LL_STAT_BASE 0x475C380ull |
|---|
| 21167 | #define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21168 | #define DCORE3_RTR3_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21169 | #define mmDCORE3_RTR3_HBW_WR_RS_LL_STAT_BASE 0x475C3C0ull |
|---|
| 21170 | #define DCORE3_RTR3_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21171 | #define DCORE3_RTR3_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21172 | #define mmDCORE3_RTR3_LBW_RD_RQ_LL_STAT_BASE 0x475C400ull |
|---|
| 21173 | #define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21174 | #define DCORE3_RTR3_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21175 | #define mmDCORE3_RTR3_LBW_RD_RS_LL_STAT_BASE 0x475C440ull |
|---|
| 21176 | #define DCORE3_RTR3_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21177 | #define DCORE3_RTR3_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21178 | #define mmDCORE3_RTR3_LBW_WR_RQ_LL_STAT_BASE 0x475C480ull |
|---|
| 21179 | #define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21180 | #define DCORE3_RTR3_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21181 | #define mmDCORE3_RTR3_LBW_WR_RS_LL_STAT_BASE 0x475C4C0ull |
|---|
| 21182 | #define DCORE3_RTR3_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21183 | #define DCORE3_RTR3_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21184 | #define mmDCORE3_RTR3_HBW_MFIFO_BASE 0x475C500ull |
|---|
| 21185 | #define DCORE3_RTR3_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21186 | #define DCORE3_RTR3_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21187 | #define mmDCORE3_RTR3_E2E_RD_LL_STAT_BASE 0x475C540ull |
|---|
| 21188 | #define DCORE3_RTR3_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21189 | #define DCORE3_RTR3_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21190 | #define mmDCORE3_RTR3_E2E_WR_LL_STAT_BASE 0x475C580ull |
|---|
| 21191 | #define DCORE3_RTR3_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21192 | #define DCORE3_RTR3_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21193 | #define mmDCORE3_RTR3_RTR_HBW_XACT_STAT_BASE 0x475C600ull |
|---|
| 21194 | #define DCORE3_RTR3_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21195 | #define DCORE3_RTR3_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21196 | #define mmDCORE3_RTR3_RTR_LBW_XACT_STAT_BASE 0x475C680ull |
|---|
| 21197 | #define DCORE3_RTR3_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21198 | #define DCORE3_RTR3_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21199 | #define mmDCORE3_RTR3_RTR_E2E_XACT_STAT_BASE 0x475C700ull |
|---|
| 21200 | #define DCORE3_RTR3_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21201 | #define DCORE3_RTR3_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21202 | #define mmDCORE3_RTR3_SPECIAL_BASE 0x475CE80ull |
|---|
| 21203 | #define DCORE3_RTR3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21204 | #define DCORE3_RTR3_SPECIAL_SECTION 0x1800 |
|---|
| 21205 | #define mmDCORE3_RTR3_DBG_ADDR_BASE 0x475D000ull |
|---|
| 21206 | #define DCORE3_RTR3_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21207 | #define DCORE3_RTR3_DBG_ADDR_SECTION 0xE800 |
|---|
| 21208 | #define mmDCORE3_RTR3_DBG_ADDR_SPECIAL_BASE 0x475DE80ull |
|---|
| 21209 | #define DCORE3_RTR3_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21210 | #define DCORE3_RTR3_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21211 | #define mmDCORE3_RTR4_CTRL_BASE 0x4760000ull |
|---|
| 21212 | #define DCORE3_RTR4_CTRL_MAX_OFFSET 0x1000 |
|---|
| 21213 | #define DCORE3_RTR4_CTRL_SECTION 0xE800 |
|---|
| 21214 | #define mmDCORE3_RTR4_CTRL_SPECIAL_BASE 0x4760E80ull |
|---|
| 21215 | #define DCORE3_RTR4_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21216 | #define DCORE3_RTR4_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21217 | #define mmDCORE3_RTR4_H3_BASE 0x4761000ull |
|---|
| 21218 | #define DCORE3_RTR4_H3_MAX_OFFSET 0x1000 |
|---|
| 21219 | #define DCORE3_RTR4_H3_SECTION 0xE800 |
|---|
| 21220 | #define mmDCORE3_RTR4_H3_SPECIAL_BASE 0x4761E80ull |
|---|
| 21221 | #define DCORE3_RTR4_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21222 | #define DCORE3_RTR4_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21223 | #define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_BASE 0x4762000ull |
|---|
| 21224 | #define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21225 | #define DCORE3_RTR4_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21226 | #define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_BASE 0x4762200ull |
|---|
| 21227 | #define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21228 | #define DCORE3_RTR4_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21229 | #define mmDCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_BASE 0x4762400ull |
|---|
| 21230 | #define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21231 | #define DCORE3_RTR4_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21232 | #define mmDCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_BASE 0x4762600ull |
|---|
| 21233 | #define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21234 | #define DCORE3_RTR4_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21235 | #define mmDCORE3_RTR4_MSTR_IF_E2E_CRDT_BASE 0x4762800ull |
|---|
| 21236 | #define DCORE3_RTR4_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21237 | #define DCORE3_RTR4_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21238 | #define mmDCORE3_RTR4_MSTR_IF_AXUSER_BASE 0x4762A80ull |
|---|
| 21239 | #define DCORE3_RTR4_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21240 | #define DCORE3_RTR4_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21241 | #define mmDCORE3_RTR4_MSTR_IF_DBG_HBW_BASE 0x4762B00ull |
|---|
| 21242 | #define DCORE3_RTR4_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21243 | #define DCORE3_RTR4_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21244 | #define mmDCORE3_RTR4_MSTR_IF_DBG_LBW_BASE 0x4762B80ull |
|---|
| 21245 | #define DCORE3_RTR4_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21246 | #define DCORE3_RTR4_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21247 | #define mmDCORE3_RTR4_MSTR_IF_CORE_HBW_BASE 0x4762C00ull |
|---|
| 21248 | #define DCORE3_RTR4_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21249 | #define DCORE3_RTR4_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21250 | #define mmDCORE3_RTR4_MSTR_IF_CORE_LBW_BASE 0x4762D80ull |
|---|
| 21251 | #define DCORE3_RTR4_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21252 | #define DCORE3_RTR4_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21253 | #define mmDCORE3_RTR4_MSTR_IF_SPECIAL_BASE 0x4762E80ull |
|---|
| 21254 | #define DCORE3_RTR4_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21255 | #define DCORE3_RTR4_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21256 | #define mmDCORE3_RTR4_ADD_DEC_HBW_BASE 0x4763000ull |
|---|
| 21257 | #define DCORE3_RTR4_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21258 | #define DCORE3_RTR4_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21259 | #define mmDCORE3_RTR4_ADD_DEC_LBW_BASE 0x4763400ull |
|---|
| 21260 | #define DCORE3_RTR4_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21261 | #define DCORE3_RTR4_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21262 | #define mmDCORE3_RTR4_ADD_DEC_SPECIAL_BASE 0x4763E80ull |
|---|
| 21263 | #define DCORE3_RTR4_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21264 | #define DCORE3_RTR4_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21265 | #define mmDCORE3_RTR4_BASE 0x4764000ull |
|---|
| 21266 | #define DCORE3_RTR4_MAX_OFFSET 0x1000 |
|---|
| 21267 | #define DCORE3_RTR4_SECTION 0x3000 |
|---|
| 21268 | #define mmDCORE3_RTR4_HBW_RD_RQ_LL_STAT_BASE 0x4764300ull |
|---|
| 21269 | #define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21270 | #define DCORE3_RTR4_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21271 | #define mmDCORE3_RTR4_HBW_RD_RS_LL_STAT_BASE 0x4764340ull |
|---|
| 21272 | #define DCORE3_RTR4_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21273 | #define DCORE3_RTR4_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21274 | #define mmDCORE3_RTR4_HBW_WR_RQ_LL_STAT_BASE 0x4764380ull |
|---|
| 21275 | #define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21276 | #define DCORE3_RTR4_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21277 | #define mmDCORE3_RTR4_HBW_WR_RS_LL_STAT_BASE 0x47643C0ull |
|---|
| 21278 | #define DCORE3_RTR4_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21279 | #define DCORE3_RTR4_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21280 | #define mmDCORE3_RTR4_LBW_RD_RQ_LL_STAT_BASE 0x4764400ull |
|---|
| 21281 | #define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21282 | #define DCORE3_RTR4_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21283 | #define mmDCORE3_RTR4_LBW_RD_RS_LL_STAT_BASE 0x4764440ull |
|---|
| 21284 | #define DCORE3_RTR4_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21285 | #define DCORE3_RTR4_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21286 | #define mmDCORE3_RTR4_LBW_WR_RQ_LL_STAT_BASE 0x4764480ull |
|---|
| 21287 | #define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21288 | #define DCORE3_RTR4_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21289 | #define mmDCORE3_RTR4_LBW_WR_RS_LL_STAT_BASE 0x47644C0ull |
|---|
| 21290 | #define DCORE3_RTR4_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21291 | #define DCORE3_RTR4_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21292 | #define mmDCORE3_RTR4_HBW_MFIFO_BASE 0x4764500ull |
|---|
| 21293 | #define DCORE3_RTR4_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21294 | #define DCORE3_RTR4_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21295 | #define mmDCORE3_RTR4_E2E_RD_LL_STAT_BASE 0x4764540ull |
|---|
| 21296 | #define DCORE3_RTR4_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21297 | #define DCORE3_RTR4_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21298 | #define mmDCORE3_RTR4_E2E_WR_LL_STAT_BASE 0x4764580ull |
|---|
| 21299 | #define DCORE3_RTR4_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21300 | #define DCORE3_RTR4_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21301 | #define mmDCORE3_RTR4_RTR_HBW_XACT_STAT_BASE 0x4764600ull |
|---|
| 21302 | #define DCORE3_RTR4_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21303 | #define DCORE3_RTR4_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21304 | #define mmDCORE3_RTR4_RTR_LBW_XACT_STAT_BASE 0x4764680ull |
|---|
| 21305 | #define DCORE3_RTR4_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21306 | #define DCORE3_RTR4_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21307 | #define mmDCORE3_RTR4_RTR_E2E_XACT_STAT_BASE 0x4764700ull |
|---|
| 21308 | #define DCORE3_RTR4_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21309 | #define DCORE3_RTR4_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21310 | #define mmDCORE3_RTR4_SPECIAL_BASE 0x4764E80ull |
|---|
| 21311 | #define DCORE3_RTR4_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21312 | #define DCORE3_RTR4_SPECIAL_SECTION 0x1800 |
|---|
| 21313 | #define mmDCORE3_RTR4_DBG_ADDR_BASE 0x4765000ull |
|---|
| 21314 | #define DCORE3_RTR4_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21315 | #define DCORE3_RTR4_DBG_ADDR_SECTION 0xE800 |
|---|
| 21316 | #define mmDCORE3_RTR4_DBG_ADDR_SPECIAL_BASE 0x4765E80ull |
|---|
| 21317 | #define DCORE3_RTR4_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21318 | #define DCORE3_RTR4_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21319 | #define mmDCORE3_RTR5_CTRL_BASE 0x4768000ull |
|---|
| 21320 | #define DCORE3_RTR5_CTRL_MAX_OFFSET 0x1000 |
|---|
| 21321 | #define DCORE3_RTR5_CTRL_SECTION 0xE800 |
|---|
| 21322 | #define mmDCORE3_RTR5_CTRL_SPECIAL_BASE 0x4768E80ull |
|---|
| 21323 | #define DCORE3_RTR5_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21324 | #define DCORE3_RTR5_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21325 | #define mmDCORE3_RTR5_H3_BASE 0x4769000ull |
|---|
| 21326 | #define DCORE3_RTR5_H3_MAX_OFFSET 0x1000 |
|---|
| 21327 | #define DCORE3_RTR5_H3_SECTION 0xE800 |
|---|
| 21328 | #define mmDCORE3_RTR5_H3_SPECIAL_BASE 0x4769E80ull |
|---|
| 21329 | #define DCORE3_RTR5_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21330 | #define DCORE3_RTR5_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21331 | #define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_BASE 0x476A000ull |
|---|
| 21332 | #define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21333 | #define DCORE3_RTR5_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21334 | #define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_BASE 0x476A200ull |
|---|
| 21335 | #define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21336 | #define DCORE3_RTR5_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21337 | #define mmDCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_BASE 0x476A400ull |
|---|
| 21338 | #define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21339 | #define DCORE3_RTR5_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21340 | #define mmDCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_BASE 0x476A600ull |
|---|
| 21341 | #define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21342 | #define DCORE3_RTR5_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21343 | #define mmDCORE3_RTR5_MSTR_IF_E2E_CRDT_BASE 0x476A800ull |
|---|
| 21344 | #define DCORE3_RTR5_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21345 | #define DCORE3_RTR5_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21346 | #define mmDCORE3_RTR5_MSTR_IF_AXUSER_BASE 0x476AA80ull |
|---|
| 21347 | #define DCORE3_RTR5_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21348 | #define DCORE3_RTR5_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21349 | #define mmDCORE3_RTR5_MSTR_IF_DBG_HBW_BASE 0x476AB00ull |
|---|
| 21350 | #define DCORE3_RTR5_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21351 | #define DCORE3_RTR5_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21352 | #define mmDCORE3_RTR5_MSTR_IF_DBG_LBW_BASE 0x476AB80ull |
|---|
| 21353 | #define DCORE3_RTR5_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21354 | #define DCORE3_RTR5_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21355 | #define mmDCORE3_RTR5_MSTR_IF_CORE_HBW_BASE 0x476AC00ull |
|---|
| 21356 | #define DCORE3_RTR5_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21357 | #define DCORE3_RTR5_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21358 | #define mmDCORE3_RTR5_MSTR_IF_CORE_LBW_BASE 0x476AD80ull |
|---|
| 21359 | #define DCORE3_RTR5_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21360 | #define DCORE3_RTR5_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21361 | #define mmDCORE3_RTR5_MSTR_IF_SPECIAL_BASE 0x476AE80ull |
|---|
| 21362 | #define DCORE3_RTR5_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21363 | #define DCORE3_RTR5_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21364 | #define mmDCORE3_RTR5_ADD_DEC_HBW_BASE 0x476B000ull |
|---|
| 21365 | #define DCORE3_RTR5_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21366 | #define DCORE3_RTR5_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21367 | #define mmDCORE3_RTR5_ADD_DEC_LBW_BASE 0x476B400ull |
|---|
| 21368 | #define DCORE3_RTR5_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21369 | #define DCORE3_RTR5_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21370 | #define mmDCORE3_RTR5_ADD_DEC_SPECIAL_BASE 0x476BE80ull |
|---|
| 21371 | #define DCORE3_RTR5_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21372 | #define DCORE3_RTR5_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21373 | #define mmDCORE3_RTR5_BASE 0x476C000ull |
|---|
| 21374 | #define DCORE3_RTR5_MAX_OFFSET 0x1000 |
|---|
| 21375 | #define DCORE3_RTR5_SECTION 0x3000 |
|---|
| 21376 | #define mmDCORE3_RTR5_HBW_RD_RQ_LL_STAT_BASE 0x476C300ull |
|---|
| 21377 | #define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21378 | #define DCORE3_RTR5_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21379 | #define mmDCORE3_RTR5_HBW_RD_RS_LL_STAT_BASE 0x476C340ull |
|---|
| 21380 | #define DCORE3_RTR5_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21381 | #define DCORE3_RTR5_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21382 | #define mmDCORE3_RTR5_HBW_WR_RQ_LL_STAT_BASE 0x476C380ull |
|---|
| 21383 | #define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21384 | #define DCORE3_RTR5_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21385 | #define mmDCORE3_RTR5_HBW_WR_RS_LL_STAT_BASE 0x476C3C0ull |
|---|
| 21386 | #define DCORE3_RTR5_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21387 | #define DCORE3_RTR5_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21388 | #define mmDCORE3_RTR5_LBW_RD_RQ_LL_STAT_BASE 0x476C400ull |
|---|
| 21389 | #define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21390 | #define DCORE3_RTR5_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21391 | #define mmDCORE3_RTR5_LBW_RD_RS_LL_STAT_BASE 0x476C440ull |
|---|
| 21392 | #define DCORE3_RTR5_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21393 | #define DCORE3_RTR5_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21394 | #define mmDCORE3_RTR5_LBW_WR_RQ_LL_STAT_BASE 0x476C480ull |
|---|
| 21395 | #define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21396 | #define DCORE3_RTR5_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21397 | #define mmDCORE3_RTR5_LBW_WR_RS_LL_STAT_BASE 0x476C4C0ull |
|---|
| 21398 | #define DCORE3_RTR5_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21399 | #define DCORE3_RTR5_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21400 | #define mmDCORE3_RTR5_HBW_MFIFO_BASE 0x476C500ull |
|---|
| 21401 | #define DCORE3_RTR5_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21402 | #define DCORE3_RTR5_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21403 | #define mmDCORE3_RTR5_E2E_RD_LL_STAT_BASE 0x476C540ull |
|---|
| 21404 | #define DCORE3_RTR5_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21405 | #define DCORE3_RTR5_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21406 | #define mmDCORE3_RTR5_E2E_WR_LL_STAT_BASE 0x476C580ull |
|---|
| 21407 | #define DCORE3_RTR5_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21408 | #define DCORE3_RTR5_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21409 | #define mmDCORE3_RTR5_RTR_HBW_XACT_STAT_BASE 0x476C600ull |
|---|
| 21410 | #define DCORE3_RTR5_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21411 | #define DCORE3_RTR5_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21412 | #define mmDCORE3_RTR5_RTR_LBW_XACT_STAT_BASE 0x476C680ull |
|---|
| 21413 | #define DCORE3_RTR5_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21414 | #define DCORE3_RTR5_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21415 | #define mmDCORE3_RTR5_RTR_E2E_XACT_STAT_BASE 0x476C700ull |
|---|
| 21416 | #define DCORE3_RTR5_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21417 | #define DCORE3_RTR5_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21418 | #define mmDCORE3_RTR5_SPECIAL_BASE 0x476CE80ull |
|---|
| 21419 | #define DCORE3_RTR5_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21420 | #define DCORE3_RTR5_SPECIAL_SECTION 0x1800 |
|---|
| 21421 | #define mmDCORE3_RTR5_DBG_ADDR_BASE 0x476D000ull |
|---|
| 21422 | #define DCORE3_RTR5_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21423 | #define DCORE3_RTR5_DBG_ADDR_SECTION 0xE800 |
|---|
| 21424 | #define mmDCORE3_RTR5_DBG_ADDR_SPECIAL_BASE 0x476DE80ull |
|---|
| 21425 | #define DCORE3_RTR5_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21426 | #define DCORE3_RTR5_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21427 | #define mmDCORE3_RTR6_CTRL_BASE 0x4770000ull |
|---|
| 21428 | #define DCORE3_RTR6_CTRL_MAX_OFFSET 0x1000 |
|---|
| 21429 | #define DCORE3_RTR6_CTRL_SECTION 0xE800 |
|---|
| 21430 | #define mmDCORE3_RTR6_CTRL_SPECIAL_BASE 0x4770E80ull |
|---|
| 21431 | #define DCORE3_RTR6_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21432 | #define DCORE3_RTR6_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21433 | #define mmDCORE3_RTR6_H3_BASE 0x4771000ull |
|---|
| 21434 | #define DCORE3_RTR6_H3_MAX_OFFSET 0x1000 |
|---|
| 21435 | #define DCORE3_RTR6_H3_SECTION 0xE800 |
|---|
| 21436 | #define mmDCORE3_RTR6_H3_SPECIAL_BASE 0x4771E80ull |
|---|
| 21437 | #define DCORE3_RTR6_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21438 | #define DCORE3_RTR6_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21439 | #define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_BASE 0x4772000ull |
|---|
| 21440 | #define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21441 | #define DCORE3_RTR6_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21442 | #define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_BASE 0x4772200ull |
|---|
| 21443 | #define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21444 | #define DCORE3_RTR6_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21445 | #define mmDCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_BASE 0x4772400ull |
|---|
| 21446 | #define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21447 | #define DCORE3_RTR6_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21448 | #define mmDCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_BASE 0x4772600ull |
|---|
| 21449 | #define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21450 | #define DCORE3_RTR6_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21451 | #define mmDCORE3_RTR6_MSTR_IF_E2E_CRDT_BASE 0x4772800ull |
|---|
| 21452 | #define DCORE3_RTR6_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21453 | #define DCORE3_RTR6_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21454 | #define mmDCORE3_RTR6_MSTR_IF_AXUSER_BASE 0x4772A80ull |
|---|
| 21455 | #define DCORE3_RTR6_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21456 | #define DCORE3_RTR6_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21457 | #define mmDCORE3_RTR6_MSTR_IF_DBG_HBW_BASE 0x4772B00ull |
|---|
| 21458 | #define DCORE3_RTR6_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21459 | #define DCORE3_RTR6_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21460 | #define mmDCORE3_RTR6_MSTR_IF_DBG_LBW_BASE 0x4772B80ull |
|---|
| 21461 | #define DCORE3_RTR6_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21462 | #define DCORE3_RTR6_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21463 | #define mmDCORE3_RTR6_MSTR_IF_CORE_HBW_BASE 0x4772C00ull |
|---|
| 21464 | #define DCORE3_RTR6_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21465 | #define DCORE3_RTR6_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21466 | #define mmDCORE3_RTR6_MSTR_IF_CORE_LBW_BASE 0x4772D80ull |
|---|
| 21467 | #define DCORE3_RTR6_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21468 | #define DCORE3_RTR6_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21469 | #define mmDCORE3_RTR6_MSTR_IF_SPECIAL_BASE 0x4772E80ull |
|---|
| 21470 | #define DCORE3_RTR6_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21471 | #define DCORE3_RTR6_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21472 | #define mmDCORE3_RTR6_ADD_DEC_HBW_BASE 0x4773000ull |
|---|
| 21473 | #define DCORE3_RTR6_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21474 | #define DCORE3_RTR6_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21475 | #define mmDCORE3_RTR6_ADD_DEC_LBW_BASE 0x4773400ull |
|---|
| 21476 | #define DCORE3_RTR6_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21477 | #define DCORE3_RTR6_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21478 | #define mmDCORE3_RTR6_ADD_DEC_SPECIAL_BASE 0x4773E80ull |
|---|
| 21479 | #define DCORE3_RTR6_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21480 | #define DCORE3_RTR6_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21481 | #define mmDCORE3_RTR6_BASE 0x4774000ull |
|---|
| 21482 | #define DCORE3_RTR6_MAX_OFFSET 0x1000 |
|---|
| 21483 | #define DCORE3_RTR6_SECTION 0x3000 |
|---|
| 21484 | #define mmDCORE3_RTR6_HBW_RD_RQ_LL_STAT_BASE 0x4774300ull |
|---|
| 21485 | #define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21486 | #define DCORE3_RTR6_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21487 | #define mmDCORE3_RTR6_HBW_RD_RS_LL_STAT_BASE 0x4774340ull |
|---|
| 21488 | #define DCORE3_RTR6_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21489 | #define DCORE3_RTR6_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21490 | #define mmDCORE3_RTR6_HBW_WR_RQ_LL_STAT_BASE 0x4774380ull |
|---|
| 21491 | #define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21492 | #define DCORE3_RTR6_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21493 | #define mmDCORE3_RTR6_HBW_WR_RS_LL_STAT_BASE 0x47743C0ull |
|---|
| 21494 | #define DCORE3_RTR6_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21495 | #define DCORE3_RTR6_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21496 | #define mmDCORE3_RTR6_LBW_RD_RQ_LL_STAT_BASE 0x4774400ull |
|---|
| 21497 | #define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21498 | #define DCORE3_RTR6_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21499 | #define mmDCORE3_RTR6_LBW_RD_RS_LL_STAT_BASE 0x4774440ull |
|---|
| 21500 | #define DCORE3_RTR6_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21501 | #define DCORE3_RTR6_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21502 | #define mmDCORE3_RTR6_LBW_WR_RQ_LL_STAT_BASE 0x4774480ull |
|---|
| 21503 | #define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21504 | #define DCORE3_RTR6_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21505 | #define mmDCORE3_RTR6_LBW_WR_RS_LL_STAT_BASE 0x47744C0ull |
|---|
| 21506 | #define DCORE3_RTR6_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21507 | #define DCORE3_RTR6_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21508 | #define mmDCORE3_RTR6_HBW_MFIFO_BASE 0x4774500ull |
|---|
| 21509 | #define DCORE3_RTR6_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21510 | #define DCORE3_RTR6_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21511 | #define mmDCORE3_RTR6_E2E_RD_LL_STAT_BASE 0x4774540ull |
|---|
| 21512 | #define DCORE3_RTR6_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21513 | #define DCORE3_RTR6_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21514 | #define mmDCORE3_RTR6_E2E_WR_LL_STAT_BASE 0x4774580ull |
|---|
| 21515 | #define DCORE3_RTR6_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21516 | #define DCORE3_RTR6_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21517 | #define mmDCORE3_RTR6_RTR_HBW_XACT_STAT_BASE 0x4774600ull |
|---|
| 21518 | #define DCORE3_RTR6_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21519 | #define DCORE3_RTR6_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21520 | #define mmDCORE3_RTR6_RTR_LBW_XACT_STAT_BASE 0x4774680ull |
|---|
| 21521 | #define DCORE3_RTR6_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21522 | #define DCORE3_RTR6_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21523 | #define mmDCORE3_RTR6_RTR_E2E_XACT_STAT_BASE 0x4774700ull |
|---|
| 21524 | #define DCORE3_RTR6_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21525 | #define DCORE3_RTR6_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21526 | #define mmDCORE3_RTR6_SPECIAL_BASE 0x4774E80ull |
|---|
| 21527 | #define DCORE3_RTR6_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21528 | #define DCORE3_RTR6_SPECIAL_SECTION 0x1800 |
|---|
| 21529 | #define mmDCORE3_RTR6_DBG_ADDR_BASE 0x4775000ull |
|---|
| 21530 | #define DCORE3_RTR6_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21531 | #define DCORE3_RTR6_DBG_ADDR_SECTION 0xE800 |
|---|
| 21532 | #define mmDCORE3_RTR6_DBG_ADDR_SPECIAL_BASE 0x4775E80ull |
|---|
| 21533 | #define DCORE3_RTR6_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21534 | #define DCORE3_RTR6_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21535 | #define mmDCORE3_RTR7_CTRL_BASE 0x4778000ull |
|---|
| 21536 | #define DCORE3_RTR7_CTRL_MAX_OFFSET 0x1000 |
|---|
| 21537 | #define DCORE3_RTR7_CTRL_SECTION 0xE800 |
|---|
| 21538 | #define mmDCORE3_RTR7_CTRL_SPECIAL_BASE 0x4778E80ull |
|---|
| 21539 | #define DCORE3_RTR7_CTRL_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21540 | #define DCORE3_RTR7_CTRL_SPECIAL_SECTION 0x1800 |
|---|
| 21541 | #define mmDCORE3_RTR7_H3_BASE 0x4779000ull |
|---|
| 21542 | #define DCORE3_RTR7_H3_MAX_OFFSET 0x1000 |
|---|
| 21543 | #define DCORE3_RTR7_H3_SECTION 0xE800 |
|---|
| 21544 | #define mmDCORE3_RTR7_H3_SPECIAL_BASE 0x4779E80ull |
|---|
| 21545 | #define DCORE3_RTR7_H3_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21546 | #define DCORE3_RTR7_H3_SPECIAL_SECTION 0x1800 |
|---|
| 21547 | #define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_BASE 0x477A000ull |
|---|
| 21548 | #define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21549 | #define DCORE3_RTR7_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 21550 | #define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_BASE 0x477A200ull |
|---|
| 21551 | #define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 21552 | #define DCORE3_RTR7_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 21553 | #define mmDCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_BASE 0x477A400ull |
|---|
| 21554 | #define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21555 | #define DCORE3_RTR7_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 21556 | #define mmDCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_BASE 0x477A600ull |
|---|
| 21557 | #define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 21558 | #define DCORE3_RTR7_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 21559 | #define mmDCORE3_RTR7_MSTR_IF_E2E_CRDT_BASE 0x477A800ull |
|---|
| 21560 | #define DCORE3_RTR7_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 21561 | #define DCORE3_RTR7_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 21562 | #define mmDCORE3_RTR7_MSTR_IF_AXUSER_BASE 0x477AA80ull |
|---|
| 21563 | #define DCORE3_RTR7_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 21564 | #define DCORE3_RTR7_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 21565 | #define mmDCORE3_RTR7_MSTR_IF_DBG_HBW_BASE 0x477AB00ull |
|---|
| 21566 | #define DCORE3_RTR7_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 21567 | #define DCORE3_RTR7_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 21568 | #define mmDCORE3_RTR7_MSTR_IF_DBG_LBW_BASE 0x477AB80ull |
|---|
| 21569 | #define DCORE3_RTR7_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 21570 | #define DCORE3_RTR7_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 21571 | #define mmDCORE3_RTR7_MSTR_IF_CORE_HBW_BASE 0x477AC00ull |
|---|
| 21572 | #define DCORE3_RTR7_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 21573 | #define DCORE3_RTR7_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 21574 | #define mmDCORE3_RTR7_MSTR_IF_CORE_LBW_BASE 0x477AD80ull |
|---|
| 21575 | #define DCORE3_RTR7_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 21576 | #define DCORE3_RTR7_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 21577 | #define mmDCORE3_RTR7_MSTR_IF_SPECIAL_BASE 0x477AE80ull |
|---|
| 21578 | #define DCORE3_RTR7_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21579 | #define DCORE3_RTR7_MSTR_IF_SPECIAL_SECTION 0x1800 |
|---|
| 21580 | #define mmDCORE3_RTR7_ADD_DEC_HBW_BASE 0x477B000ull |
|---|
| 21581 | #define DCORE3_RTR7_ADD_DEC_HBW_MAX_OFFSET 0x4000 |
|---|
| 21582 | #define DCORE3_RTR7_ADD_DEC_HBW_SECTION 0x4000 |
|---|
| 21583 | #define mmDCORE3_RTR7_ADD_DEC_LBW_BASE 0x477B400ull |
|---|
| 21584 | #define DCORE3_RTR7_ADD_DEC_LBW_MAX_OFFSET 0xA600 |
|---|
| 21585 | #define DCORE3_RTR7_ADD_DEC_LBW_SECTION 0xA800 |
|---|
| 21586 | #define mmDCORE3_RTR7_ADD_DEC_SPECIAL_BASE 0x477BE80ull |
|---|
| 21587 | #define DCORE3_RTR7_ADD_DEC_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21588 | #define DCORE3_RTR7_ADD_DEC_SPECIAL_SECTION 0x1800 |
|---|
| 21589 | #define mmDCORE3_RTR7_BASE 0x477C000ull |
|---|
| 21590 | #define DCORE3_RTR7_MAX_OFFSET 0x1000 |
|---|
| 21591 | #define DCORE3_RTR7_SECTION 0x3000 |
|---|
| 21592 | #define mmDCORE3_RTR7_HBW_RD_RQ_LL_STAT_BASE 0x477C300ull |
|---|
| 21593 | #define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21594 | #define DCORE3_RTR7_HBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21595 | #define mmDCORE3_RTR7_HBW_RD_RS_LL_STAT_BASE 0x477C340ull |
|---|
| 21596 | #define DCORE3_RTR7_HBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21597 | #define DCORE3_RTR7_HBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21598 | #define mmDCORE3_RTR7_HBW_WR_RQ_LL_STAT_BASE 0x477C380ull |
|---|
| 21599 | #define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21600 | #define DCORE3_RTR7_HBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21601 | #define mmDCORE3_RTR7_HBW_WR_RS_LL_STAT_BASE 0x477C3C0ull |
|---|
| 21602 | #define DCORE3_RTR7_HBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21603 | #define DCORE3_RTR7_HBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21604 | #define mmDCORE3_RTR7_LBW_RD_RQ_LL_STAT_BASE 0x477C400ull |
|---|
| 21605 | #define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21606 | #define DCORE3_RTR7_LBW_RD_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21607 | #define mmDCORE3_RTR7_LBW_RD_RS_LL_STAT_BASE 0x477C440ull |
|---|
| 21608 | #define DCORE3_RTR7_LBW_RD_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21609 | #define DCORE3_RTR7_LBW_RD_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21610 | #define mmDCORE3_RTR7_LBW_WR_RQ_LL_STAT_BASE 0x477C480ull |
|---|
| 21611 | #define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21612 | #define DCORE3_RTR7_LBW_WR_RQ_LL_STAT_SECTION 0x4000 |
|---|
| 21613 | #define mmDCORE3_RTR7_LBW_WR_RS_LL_STAT_BASE 0x477C4C0ull |
|---|
| 21614 | #define DCORE3_RTR7_LBW_WR_RS_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21615 | #define DCORE3_RTR7_LBW_WR_RS_LL_STAT_SECTION 0x4000 |
|---|
| 21616 | #define mmDCORE3_RTR7_HBW_MFIFO_BASE 0x477C500ull |
|---|
| 21617 | #define DCORE3_RTR7_HBW_MFIFO_MAX_OFFSET 0x3000 |
|---|
| 21618 | #define DCORE3_RTR7_HBW_MFIFO_SECTION 0x4000 |
|---|
| 21619 | #define mmDCORE3_RTR7_E2E_RD_LL_STAT_BASE 0x477C540ull |
|---|
| 21620 | #define DCORE3_RTR7_E2E_RD_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21621 | #define DCORE3_RTR7_E2E_RD_LL_STAT_SECTION 0x4000 |
|---|
| 21622 | #define mmDCORE3_RTR7_E2E_WR_LL_STAT_BASE 0x477C580ull |
|---|
| 21623 | #define DCORE3_RTR7_E2E_WR_LL_STAT_MAX_OFFSET 0x3000 |
|---|
| 21624 | #define DCORE3_RTR7_E2E_WR_LL_STAT_SECTION 0x8000 |
|---|
| 21625 | #define mmDCORE3_RTR7_RTR_HBW_XACT_STAT_BASE 0x477C600ull |
|---|
| 21626 | #define DCORE3_RTR7_RTR_HBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21627 | #define DCORE3_RTR7_RTR_HBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21628 | #define mmDCORE3_RTR7_RTR_LBW_XACT_STAT_BASE 0x477C680ull |
|---|
| 21629 | #define DCORE3_RTR7_RTR_LBW_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21630 | #define DCORE3_RTR7_RTR_LBW_XACT_STAT_SECTION 0x8000 |
|---|
| 21631 | #define mmDCORE3_RTR7_RTR_E2E_XACT_STAT_BASE 0x477C700ull |
|---|
| 21632 | #define DCORE3_RTR7_RTR_E2E_XACT_STAT_MAX_OFFSET 0x5000 |
|---|
| 21633 | #define DCORE3_RTR7_RTR_E2E_XACT_STAT_SECTION 0x7800 |
|---|
| 21634 | #define mmDCORE3_RTR7_SPECIAL_BASE 0x477CE80ull |
|---|
| 21635 | #define DCORE3_RTR7_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21636 | #define DCORE3_RTR7_SPECIAL_SECTION 0x1800 |
|---|
| 21637 | #define mmDCORE3_RTR7_DBG_ADDR_BASE 0x477D000ull |
|---|
| 21638 | #define DCORE3_RTR7_DBG_ADDR_MAX_OFFSET 0x1000 |
|---|
| 21639 | #define DCORE3_RTR7_DBG_ADDR_SECTION 0xE800 |
|---|
| 21640 | #define mmDCORE3_RTR7_DBG_ADDR_SPECIAL_BASE 0x477DE80ull |
|---|
| 21641 | #define DCORE3_RTR7_DBG_ADDR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21642 | #define DCORE3_RTR7_DBG_ADDR_SPECIAL_SECTION 0x2180 |
|---|
| 21643 | #define mmDCORE3_SRAM0_BANK_BASE 0x4780000ull |
|---|
| 21644 | #define DCORE3_SRAM0_BANK_MAX_OFFSET 0x1000 |
|---|
| 21645 | #define DCORE3_SRAM0_BANK_SECTION 0xE800 |
|---|
| 21646 | #define mmDCORE3_SRAM0_BANK_SPECIAL_BASE 0x4780E80ull |
|---|
| 21647 | #define DCORE3_SRAM0_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21648 | #define DCORE3_SRAM0_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21649 | #define mmDCORE3_SRAM0_RTR_BASE 0x4781000ull |
|---|
| 21650 | #define DCORE3_SRAM0_RTR_MAX_OFFSET 0x1000 |
|---|
| 21651 | #define DCORE3_SRAM0_RTR_SECTION 0xE800 |
|---|
| 21652 | #define mmDCORE3_SRAM0_RTR_SPECIAL_BASE 0x4781E80ull |
|---|
| 21653 | #define DCORE3_SRAM0_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21654 | #define DCORE3_SRAM0_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21655 | #define mmDCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4782000ull |
|---|
| 21656 | #define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21657 | #define DCORE3_SRAM0_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21658 | #define mmDCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4782100ull |
|---|
| 21659 | #define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21660 | #define DCORE3_SRAM0_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21661 | #define mmDCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4782200ull |
|---|
| 21662 | #define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21663 | #define DCORE3_SRAM0_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21664 | #define mmDCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4782300ull |
|---|
| 21665 | #define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21666 | #define DCORE3_SRAM0_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21667 | #define mmDCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4782400ull |
|---|
| 21668 | #define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21669 | #define DCORE3_SRAM0_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21670 | #define mmDCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4782500ull |
|---|
| 21671 | #define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21672 | #define DCORE3_SRAM0_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21673 | #define mmDCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4782600ull |
|---|
| 21674 | #define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21675 | #define DCORE3_SRAM0_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21676 | #define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4782700ull |
|---|
| 21677 | #define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21678 | #define DCORE3_SRAM0_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21679 | #define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4782780ull |
|---|
| 21680 | #define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21681 | #define DCORE3_SRAM0_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21682 | #define mmDCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4782800ull |
|---|
| 21683 | #define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21684 | #define DCORE3_SRAM0_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21685 | #define mmDCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4782880ull |
|---|
| 21686 | #define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21687 | #define DCORE3_SRAM0_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21688 | #define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4782900ull |
|---|
| 21689 | #define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21690 | #define DCORE3_SRAM0_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21691 | #define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4782980ull |
|---|
| 21692 | #define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21693 | #define DCORE3_SRAM0_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21694 | #define mmDCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4782A00ull |
|---|
| 21695 | #define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21696 | #define DCORE3_SRAM0_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21697 | #define mmDCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4782A80ull |
|---|
| 21698 | #define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21699 | #define DCORE3_SRAM0_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 21700 | #define mmDCORE3_SRAM0_DBG_CNT_SPECIAL_BASE 0x4782E80ull |
|---|
| 21701 | #define DCORE3_SRAM0_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21702 | #define DCORE3_SRAM0_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 21703 | #define mmDCORE3_SRAM1_BANK_BASE 0x4788000ull |
|---|
| 21704 | #define DCORE3_SRAM1_BANK_MAX_OFFSET 0x1000 |
|---|
| 21705 | #define DCORE3_SRAM1_BANK_SECTION 0xE800 |
|---|
| 21706 | #define mmDCORE3_SRAM1_BANK_SPECIAL_BASE 0x4788E80ull |
|---|
| 21707 | #define DCORE3_SRAM1_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21708 | #define DCORE3_SRAM1_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21709 | #define mmDCORE3_SRAM1_RTR_BASE 0x4789000ull |
|---|
| 21710 | #define DCORE3_SRAM1_RTR_MAX_OFFSET 0x1000 |
|---|
| 21711 | #define DCORE3_SRAM1_RTR_SECTION 0xE800 |
|---|
| 21712 | #define mmDCORE3_SRAM1_RTR_SPECIAL_BASE 0x4789E80ull |
|---|
| 21713 | #define DCORE3_SRAM1_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21714 | #define DCORE3_SRAM1_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21715 | #define mmDCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_BASE 0x478A000ull |
|---|
| 21716 | #define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21717 | #define DCORE3_SRAM1_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21718 | #define mmDCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_BASE 0x478A100ull |
|---|
| 21719 | #define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21720 | #define DCORE3_SRAM1_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21721 | #define mmDCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x478A200ull |
|---|
| 21722 | #define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21723 | #define DCORE3_SRAM1_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21724 | #define mmDCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x478A300ull |
|---|
| 21725 | #define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21726 | #define DCORE3_SRAM1_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21727 | #define mmDCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_BASE 0x478A400ull |
|---|
| 21728 | #define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21729 | #define DCORE3_SRAM1_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21730 | #define mmDCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_BASE 0x478A500ull |
|---|
| 21731 | #define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21732 | #define DCORE3_SRAM1_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21733 | #define mmDCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_BASE 0x478A600ull |
|---|
| 21734 | #define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21735 | #define DCORE3_SRAM1_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21736 | #define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x478A700ull |
|---|
| 21737 | #define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21738 | #define DCORE3_SRAM1_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21739 | #define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x478A780ull |
|---|
| 21740 | #define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21741 | #define DCORE3_SRAM1_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21742 | #define mmDCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x478A800ull |
|---|
| 21743 | #define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21744 | #define DCORE3_SRAM1_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21745 | #define mmDCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x478A880ull |
|---|
| 21746 | #define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21747 | #define DCORE3_SRAM1_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21748 | #define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x478A900ull |
|---|
| 21749 | #define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21750 | #define DCORE3_SRAM1_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21751 | #define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x478A980ull |
|---|
| 21752 | #define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21753 | #define DCORE3_SRAM1_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21754 | #define mmDCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x478AA00ull |
|---|
| 21755 | #define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21756 | #define DCORE3_SRAM1_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21757 | #define mmDCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x478AA80ull |
|---|
| 21758 | #define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21759 | #define DCORE3_SRAM1_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 21760 | #define mmDCORE3_SRAM1_DBG_CNT_SPECIAL_BASE 0x478AE80ull |
|---|
| 21761 | #define DCORE3_SRAM1_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21762 | #define DCORE3_SRAM1_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 21763 | #define mmDCORE3_SRAM2_BANK_BASE 0x4790000ull |
|---|
| 21764 | #define DCORE3_SRAM2_BANK_MAX_OFFSET 0x1000 |
|---|
| 21765 | #define DCORE3_SRAM2_BANK_SECTION 0xE800 |
|---|
| 21766 | #define mmDCORE3_SRAM2_BANK_SPECIAL_BASE 0x4790E80ull |
|---|
| 21767 | #define DCORE3_SRAM2_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21768 | #define DCORE3_SRAM2_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21769 | #define mmDCORE3_SRAM2_RTR_BASE 0x4791000ull |
|---|
| 21770 | #define DCORE3_SRAM2_RTR_MAX_OFFSET 0x1000 |
|---|
| 21771 | #define DCORE3_SRAM2_RTR_SECTION 0xE800 |
|---|
| 21772 | #define mmDCORE3_SRAM2_RTR_SPECIAL_BASE 0x4791E80ull |
|---|
| 21773 | #define DCORE3_SRAM2_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21774 | #define DCORE3_SRAM2_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21775 | #define mmDCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_BASE 0x4792000ull |
|---|
| 21776 | #define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21777 | #define DCORE3_SRAM2_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21778 | #define mmDCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_BASE 0x4792100ull |
|---|
| 21779 | #define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21780 | #define DCORE3_SRAM2_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21781 | #define mmDCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x4792200ull |
|---|
| 21782 | #define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21783 | #define DCORE3_SRAM2_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21784 | #define mmDCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x4792300ull |
|---|
| 21785 | #define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21786 | #define DCORE3_SRAM2_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21787 | #define mmDCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_BASE 0x4792400ull |
|---|
| 21788 | #define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21789 | #define DCORE3_SRAM2_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21790 | #define mmDCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_BASE 0x4792500ull |
|---|
| 21791 | #define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21792 | #define DCORE3_SRAM2_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21793 | #define mmDCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_BASE 0x4792600ull |
|---|
| 21794 | #define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21795 | #define DCORE3_SRAM2_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21796 | #define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x4792700ull |
|---|
| 21797 | #define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21798 | #define DCORE3_SRAM2_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21799 | #define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x4792780ull |
|---|
| 21800 | #define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21801 | #define DCORE3_SRAM2_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21802 | #define mmDCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x4792800ull |
|---|
| 21803 | #define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21804 | #define DCORE3_SRAM2_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21805 | #define mmDCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x4792880ull |
|---|
| 21806 | #define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21807 | #define DCORE3_SRAM2_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21808 | #define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x4792900ull |
|---|
| 21809 | #define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21810 | #define DCORE3_SRAM2_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21811 | #define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x4792980ull |
|---|
| 21812 | #define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21813 | #define DCORE3_SRAM2_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21814 | #define mmDCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x4792A00ull |
|---|
| 21815 | #define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21816 | #define DCORE3_SRAM2_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21817 | #define mmDCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x4792A80ull |
|---|
| 21818 | #define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21819 | #define DCORE3_SRAM2_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 21820 | #define mmDCORE3_SRAM2_DBG_CNT_SPECIAL_BASE 0x4792E80ull |
|---|
| 21821 | #define DCORE3_SRAM2_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21822 | #define DCORE3_SRAM2_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 21823 | #define mmDCORE3_SRAM3_BANK_BASE 0x4798000ull |
|---|
| 21824 | #define DCORE3_SRAM3_BANK_MAX_OFFSET 0x1000 |
|---|
| 21825 | #define DCORE3_SRAM3_BANK_SECTION 0xE800 |
|---|
| 21826 | #define mmDCORE3_SRAM3_BANK_SPECIAL_BASE 0x4798E80ull |
|---|
| 21827 | #define DCORE3_SRAM3_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21828 | #define DCORE3_SRAM3_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21829 | #define mmDCORE3_SRAM3_RTR_BASE 0x4799000ull |
|---|
| 21830 | #define DCORE3_SRAM3_RTR_MAX_OFFSET 0x1000 |
|---|
| 21831 | #define DCORE3_SRAM3_RTR_SECTION 0xE800 |
|---|
| 21832 | #define mmDCORE3_SRAM3_RTR_SPECIAL_BASE 0x4799E80ull |
|---|
| 21833 | #define DCORE3_SRAM3_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21834 | #define DCORE3_SRAM3_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21835 | #define mmDCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_BASE 0x479A000ull |
|---|
| 21836 | #define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21837 | #define DCORE3_SRAM3_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21838 | #define mmDCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_BASE 0x479A100ull |
|---|
| 21839 | #define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21840 | #define DCORE3_SRAM3_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21841 | #define mmDCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x479A200ull |
|---|
| 21842 | #define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21843 | #define DCORE3_SRAM3_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21844 | #define mmDCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x479A300ull |
|---|
| 21845 | #define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21846 | #define DCORE3_SRAM3_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21847 | #define mmDCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_BASE 0x479A400ull |
|---|
| 21848 | #define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21849 | #define DCORE3_SRAM3_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21850 | #define mmDCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_BASE 0x479A500ull |
|---|
| 21851 | #define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21852 | #define DCORE3_SRAM3_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21853 | #define mmDCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_BASE 0x479A600ull |
|---|
| 21854 | #define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21855 | #define DCORE3_SRAM3_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21856 | #define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x479A700ull |
|---|
| 21857 | #define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21858 | #define DCORE3_SRAM3_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21859 | #define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x479A780ull |
|---|
| 21860 | #define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21861 | #define DCORE3_SRAM3_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21862 | #define mmDCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x479A800ull |
|---|
| 21863 | #define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21864 | #define DCORE3_SRAM3_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21865 | #define mmDCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x479A880ull |
|---|
| 21866 | #define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21867 | #define DCORE3_SRAM3_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21868 | #define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x479A900ull |
|---|
| 21869 | #define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21870 | #define DCORE3_SRAM3_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21871 | #define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x479A980ull |
|---|
| 21872 | #define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21873 | #define DCORE3_SRAM3_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21874 | #define mmDCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x479AA00ull |
|---|
| 21875 | #define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21876 | #define DCORE3_SRAM3_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21877 | #define mmDCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x479AA80ull |
|---|
| 21878 | #define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21879 | #define DCORE3_SRAM3_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 21880 | #define mmDCORE3_SRAM3_DBG_CNT_SPECIAL_BASE 0x479AE80ull |
|---|
| 21881 | #define DCORE3_SRAM3_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21882 | #define DCORE3_SRAM3_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 21883 | #define mmDCORE3_SRAM4_BANK_BASE 0x47A0000ull |
|---|
| 21884 | #define DCORE3_SRAM4_BANK_MAX_OFFSET 0x1000 |
|---|
| 21885 | #define DCORE3_SRAM4_BANK_SECTION 0xE800 |
|---|
| 21886 | #define mmDCORE3_SRAM4_BANK_SPECIAL_BASE 0x47A0E80ull |
|---|
| 21887 | #define DCORE3_SRAM4_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21888 | #define DCORE3_SRAM4_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21889 | #define mmDCORE3_SRAM4_RTR_BASE 0x47A1000ull |
|---|
| 21890 | #define DCORE3_SRAM4_RTR_MAX_OFFSET 0x1000 |
|---|
| 21891 | #define DCORE3_SRAM4_RTR_SECTION 0xE800 |
|---|
| 21892 | #define mmDCORE3_SRAM4_RTR_SPECIAL_BASE 0x47A1E80ull |
|---|
| 21893 | #define DCORE3_SRAM4_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21894 | #define DCORE3_SRAM4_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21895 | #define mmDCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47A2000ull |
|---|
| 21896 | #define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21897 | #define DCORE3_SRAM4_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21898 | #define mmDCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47A2100ull |
|---|
| 21899 | #define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21900 | #define DCORE3_SRAM4_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21901 | #define mmDCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47A2200ull |
|---|
| 21902 | #define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21903 | #define DCORE3_SRAM4_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21904 | #define mmDCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47A2300ull |
|---|
| 21905 | #define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21906 | #define DCORE3_SRAM4_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21907 | #define mmDCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47A2400ull |
|---|
| 21908 | #define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21909 | #define DCORE3_SRAM4_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21910 | #define mmDCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47A2500ull |
|---|
| 21911 | #define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21912 | #define DCORE3_SRAM4_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21913 | #define mmDCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47A2600ull |
|---|
| 21914 | #define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21915 | #define DCORE3_SRAM4_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21916 | #define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2700ull |
|---|
| 21917 | #define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21918 | #define DCORE3_SRAM4_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21919 | #define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2780ull |
|---|
| 21920 | #define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21921 | #define DCORE3_SRAM4_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21922 | #define mmDCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47A2800ull |
|---|
| 21923 | #define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21924 | #define DCORE3_SRAM4_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21925 | #define mmDCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47A2880ull |
|---|
| 21926 | #define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21927 | #define DCORE3_SRAM4_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21928 | #define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47A2900ull |
|---|
| 21929 | #define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21930 | #define DCORE3_SRAM4_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21931 | #define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47A2980ull |
|---|
| 21932 | #define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21933 | #define DCORE3_SRAM4_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21934 | #define mmDCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47A2A00ull |
|---|
| 21935 | #define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21936 | #define DCORE3_SRAM4_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21937 | #define mmDCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47A2A80ull |
|---|
| 21938 | #define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21939 | #define DCORE3_SRAM4_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 21940 | #define mmDCORE3_SRAM4_DBG_CNT_SPECIAL_BASE 0x47A2E80ull |
|---|
| 21941 | #define DCORE3_SRAM4_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21942 | #define DCORE3_SRAM4_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 21943 | #define mmDCORE3_SRAM5_BANK_BASE 0x47A8000ull |
|---|
| 21944 | #define DCORE3_SRAM5_BANK_MAX_OFFSET 0x1000 |
|---|
| 21945 | #define DCORE3_SRAM5_BANK_SECTION 0xE800 |
|---|
| 21946 | #define mmDCORE3_SRAM5_BANK_SPECIAL_BASE 0x47A8E80ull |
|---|
| 21947 | #define DCORE3_SRAM5_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21948 | #define DCORE3_SRAM5_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 21949 | #define mmDCORE3_SRAM5_RTR_BASE 0x47A9000ull |
|---|
| 21950 | #define DCORE3_SRAM5_RTR_MAX_OFFSET 0x1000 |
|---|
| 21951 | #define DCORE3_SRAM5_RTR_SECTION 0xE800 |
|---|
| 21952 | #define mmDCORE3_SRAM5_RTR_SPECIAL_BASE 0x47A9E80ull |
|---|
| 21953 | #define DCORE3_SRAM5_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 21954 | #define DCORE3_SRAM5_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 21955 | #define mmDCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47AA000ull |
|---|
| 21956 | #define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21957 | #define DCORE3_SRAM5_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21958 | #define mmDCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47AA100ull |
|---|
| 21959 | #define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21960 | #define DCORE3_SRAM5_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21961 | #define mmDCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47AA200ull |
|---|
| 21962 | #define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21963 | #define DCORE3_SRAM5_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21964 | #define mmDCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47AA300ull |
|---|
| 21965 | #define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21966 | #define DCORE3_SRAM5_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21967 | #define mmDCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47AA400ull |
|---|
| 21968 | #define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21969 | #define DCORE3_SRAM5_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21970 | #define mmDCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47AA500ull |
|---|
| 21971 | #define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21972 | #define DCORE3_SRAM5_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21973 | #define mmDCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47AA600ull |
|---|
| 21974 | #define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 21975 | #define DCORE3_SRAM5_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 21976 | #define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA700ull |
|---|
| 21977 | #define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21978 | #define DCORE3_SRAM5_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21979 | #define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA780ull |
|---|
| 21980 | #define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21981 | #define DCORE3_SRAM5_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21982 | #define mmDCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47AA800ull |
|---|
| 21983 | #define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21984 | #define DCORE3_SRAM5_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21985 | #define mmDCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47AA880ull |
|---|
| 21986 | #define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21987 | #define DCORE3_SRAM5_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21988 | #define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47AA900ull |
|---|
| 21989 | #define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21990 | #define DCORE3_SRAM5_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21991 | #define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47AA980ull |
|---|
| 21992 | #define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21993 | #define DCORE3_SRAM5_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21994 | #define mmDCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47AAA00ull |
|---|
| 21995 | #define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21996 | #define DCORE3_SRAM5_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 21997 | #define mmDCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47AAA80ull |
|---|
| 21998 | #define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 21999 | #define DCORE3_SRAM5_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 22000 | #define mmDCORE3_SRAM5_DBG_CNT_SPECIAL_BASE 0x47AAE80ull |
|---|
| 22001 | #define DCORE3_SRAM5_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22002 | #define DCORE3_SRAM5_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 22003 | #define mmDCORE3_SRAM6_BANK_BASE 0x47B0000ull |
|---|
| 22004 | #define DCORE3_SRAM6_BANK_MAX_OFFSET 0x1000 |
|---|
| 22005 | #define DCORE3_SRAM6_BANK_SECTION 0xE800 |
|---|
| 22006 | #define mmDCORE3_SRAM6_BANK_SPECIAL_BASE 0x47B0E80ull |
|---|
| 22007 | #define DCORE3_SRAM6_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22008 | #define DCORE3_SRAM6_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 22009 | #define mmDCORE3_SRAM6_RTR_BASE 0x47B1000ull |
|---|
| 22010 | #define DCORE3_SRAM6_RTR_MAX_OFFSET 0x1000 |
|---|
| 22011 | #define DCORE3_SRAM6_RTR_SECTION 0xE800 |
|---|
| 22012 | #define mmDCORE3_SRAM6_RTR_SPECIAL_BASE 0x47B1E80ull |
|---|
| 22013 | #define DCORE3_SRAM6_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22014 | #define DCORE3_SRAM6_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 22015 | #define mmDCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47B2000ull |
|---|
| 22016 | #define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22017 | #define DCORE3_SRAM6_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22018 | #define mmDCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47B2100ull |
|---|
| 22019 | #define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22020 | #define DCORE3_SRAM6_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22021 | #define mmDCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47B2200ull |
|---|
| 22022 | #define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22023 | #define DCORE3_SRAM6_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22024 | #define mmDCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47B2300ull |
|---|
| 22025 | #define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22026 | #define DCORE3_SRAM6_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22027 | #define mmDCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47B2400ull |
|---|
| 22028 | #define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22029 | #define DCORE3_SRAM6_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22030 | #define mmDCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47B2500ull |
|---|
| 22031 | #define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22032 | #define DCORE3_SRAM6_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22033 | #define mmDCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47B2600ull |
|---|
| 22034 | #define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22035 | #define DCORE3_SRAM6_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22036 | #define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2700ull |
|---|
| 22037 | #define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22038 | #define DCORE3_SRAM6_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22039 | #define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2780ull |
|---|
| 22040 | #define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22041 | #define DCORE3_SRAM6_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22042 | #define mmDCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47B2800ull |
|---|
| 22043 | #define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22044 | #define DCORE3_SRAM6_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22045 | #define mmDCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47B2880ull |
|---|
| 22046 | #define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22047 | #define DCORE3_SRAM6_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22048 | #define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47B2900ull |
|---|
| 22049 | #define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22050 | #define DCORE3_SRAM6_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22051 | #define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47B2980ull |
|---|
| 22052 | #define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22053 | #define DCORE3_SRAM6_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22054 | #define mmDCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47B2A00ull |
|---|
| 22055 | #define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22056 | #define DCORE3_SRAM6_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22057 | #define mmDCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47B2A80ull |
|---|
| 22058 | #define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22059 | #define DCORE3_SRAM6_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 22060 | #define mmDCORE3_SRAM6_DBG_CNT_SPECIAL_BASE 0x47B2E80ull |
|---|
| 22061 | #define DCORE3_SRAM6_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22062 | #define DCORE3_SRAM6_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 22063 | #define mmDCORE3_SRAM7_BANK_BASE 0x47B8000ull |
|---|
| 22064 | #define DCORE3_SRAM7_BANK_MAX_OFFSET 0x1000 |
|---|
| 22065 | #define DCORE3_SRAM7_BANK_SECTION 0xE800 |
|---|
| 22066 | #define mmDCORE3_SRAM7_BANK_SPECIAL_BASE 0x47B8E80ull |
|---|
| 22067 | #define DCORE3_SRAM7_BANK_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22068 | #define DCORE3_SRAM7_BANK_SPECIAL_SECTION 0x1800 |
|---|
| 22069 | #define mmDCORE3_SRAM7_RTR_BASE 0x47B9000ull |
|---|
| 22070 | #define DCORE3_SRAM7_RTR_MAX_OFFSET 0x1000 |
|---|
| 22071 | #define DCORE3_SRAM7_RTR_SECTION 0xE800 |
|---|
| 22072 | #define mmDCORE3_SRAM7_RTR_SPECIAL_BASE 0x47B9E80ull |
|---|
| 22073 | #define DCORE3_SRAM7_RTR_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22074 | #define DCORE3_SRAM7_RTR_SPECIAL_SECTION 0x1800 |
|---|
| 22075 | #define mmDCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_BASE 0x47BA000ull |
|---|
| 22076 | #define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22077 | #define DCORE3_SRAM7_DBG_CNT_N_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22078 | #define mmDCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_BASE 0x47BA100ull |
|---|
| 22079 | #define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22080 | #define DCORE3_SRAM7_DBG_CNT_S_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22081 | #define mmDCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_BASE 0x47BA200ull |
|---|
| 22082 | #define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22083 | #define DCORE3_SRAM7_DBG_CNT_L_BANK0_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22084 | #define mmDCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_BASE 0x47BA300ull |
|---|
| 22085 | #define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22086 | #define DCORE3_SRAM7_DBG_CNT_L_BANK1_HBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22087 | #define mmDCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_BASE 0x47BA400ull |
|---|
| 22088 | #define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22089 | #define DCORE3_SRAM7_DBG_CNT_N_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22090 | #define mmDCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_BASE 0x47BA500ull |
|---|
| 22091 | #define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22092 | #define DCORE3_SRAM7_DBG_CNT_S_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22093 | #define mmDCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_BASE 0x47BA600ull |
|---|
| 22094 | #define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_MAX_OFFSET 0x5800 |
|---|
| 22095 | #define DCORE3_SRAM7_DBG_CNT_L_LBW_DBG_CNT_SECTION 0x1000 |
|---|
| 22096 | #define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA700ull |
|---|
| 22097 | #define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22098 | #define DCORE3_SRAM7_DBG_CNT_HBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22099 | #define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA780ull |
|---|
| 22100 | #define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22101 | #define DCORE3_SRAM7_DBG_CNT_HBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22102 | #define mmDCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_BASE 0x47BA800ull |
|---|
| 22103 | #define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22104 | #define DCORE3_SRAM7_DBG_CNT_HBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22105 | #define mmDCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_BASE 0x47BA880ull |
|---|
| 22106 | #define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22107 | #define DCORE3_SRAM7_DBG_CNT_HBW_WR_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22108 | #define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_BASE 0x47BA900ull |
|---|
| 22109 | #define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22110 | #define DCORE3_SRAM7_DBG_CNT_LBW_RD_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22111 | #define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_BASE 0x47BA980ull |
|---|
| 22112 | #define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22113 | #define DCORE3_SRAM7_DBG_CNT_LBW_WR_RQ_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22114 | #define mmDCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_BASE 0x47BAA00ull |
|---|
| 22115 | #define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22116 | #define DCORE3_SRAM7_DBG_CNT_LBW_RD_RS_LL_STAT_CNT_SECTION 0x8000 |
|---|
| 22117 | #define mmDCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_BASE 0x47BAA80ull |
|---|
| 22118 | #define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_MAX_OFFSET 0x3000 |
|---|
| 22119 | #define DCORE3_SRAM7_DBG_CNT_LBW_WR_RS_LL_STAT_CNT_SECTION 0x4000 |
|---|
| 22120 | #define mmDCORE3_SRAM7_DBG_CNT_SPECIAL_BASE 0x47BAE80ull |
|---|
| 22121 | #define DCORE3_SRAM7_DBG_CNT_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22122 | #define DCORE3_SRAM7_DBG_CNT_SPECIAL_SECTION 0x5180 |
|---|
| 22123 | #define mmDCORE3_EDMA0_QM_DCCM_BASE 0x47C0000ull |
|---|
| 22124 | #define DCORE3_EDMA0_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 22125 | #define DCORE3_EDMA0_QM_DCCM_SECTION 0x8000 |
|---|
| 22126 | #define mmDCORE3_EDMA0_QM_ARC_AUX_BASE 0x47C8000ull |
|---|
| 22127 | #define DCORE3_EDMA0_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 22128 | #define DCORE3_EDMA0_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 22129 | #define mmDCORE3_EDMA0_QM_ARC_AUX_SPECIAL_BASE 0x47C8E80ull |
|---|
| 22130 | #define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22131 | #define DCORE3_EDMA0_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 22132 | #define mmDCORE3_EDMA0_QM_BASE 0x47CA000ull |
|---|
| 22133 | #define DCORE3_EDMA0_QM_MAX_OFFSET 0x1000 |
|---|
| 22134 | #define DCORE3_EDMA0_QM_SECTION 0x9000 |
|---|
| 22135 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47CA900ull |
|---|
| 22136 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 22137 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 22138 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47CA908ull |
|---|
| 22139 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 22140 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 22141 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47CA910ull |
|---|
| 22142 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 22143 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
|---|
| 22144 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47CA918ull |
|---|
| 22145 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
|---|
| 22146 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
|---|
| 22147 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47CA920ull |
|---|
| 22148 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
|---|
| 22149 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
|---|
| 22150 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47CA928ull |
|---|
| 22151 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
|---|
| 22152 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
|---|
| 22153 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47CA930ull |
|---|
| 22154 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
|---|
| 22155 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
|---|
| 22156 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47CA938ull |
|---|
| 22157 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_MAX_OFFSET 0x8000 |
|---|
| 22158 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR7_SECTION 0x8000 |
|---|
| 22159 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE 0x47CA940ull |
|---|
| 22160 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_MAX_OFFSET 0x8000 |
|---|
| 22161 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR8_SECTION 0x8000 |
|---|
| 22162 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE 0x47CA948ull |
|---|
| 22163 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_MAX_OFFSET 0x8000 |
|---|
| 22164 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR9_SECTION 0x8000 |
|---|
| 22165 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE 0x47CA950ull |
|---|
| 22166 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_MAX_OFFSET 0x8000 |
|---|
| 22167 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR10_SECTION 0x8000 |
|---|
| 22168 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE 0x47CA958ull |
|---|
| 22169 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_MAX_OFFSET 0x8000 |
|---|
| 22170 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR11_SECTION 0x8000 |
|---|
| 22171 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE 0x47CA960ull |
|---|
| 22172 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_MAX_OFFSET 0x8000 |
|---|
| 22173 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR12_SECTION 0x8000 |
|---|
| 22174 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE 0x47CA968ull |
|---|
| 22175 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_MAX_OFFSET 0x8000 |
|---|
| 22176 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR13_SECTION 0x8000 |
|---|
| 22177 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE 0x47CA970ull |
|---|
| 22178 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_MAX_OFFSET 0x8000 |
|---|
| 22179 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR14_SECTION 0x8000 |
|---|
| 22180 | #define mmDCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE 0x47CA978ull |
|---|
| 22181 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_MAX_OFFSET 0x8000 |
|---|
| 22182 | #define DCORE3_EDMA0_QM_QMAN_WR64_BASE_ADDR15_SECTION 0x1880 |
|---|
| 22183 | #define mmDCORE3_EDMA0_QM_AXUSER_SECURED_BASE 0x47CAB00ull |
|---|
| 22184 | #define DCORE3_EDMA0_QM_AXUSER_SECURED_MAX_OFFSET 0x5000 |
|---|
| 22185 | #define DCORE3_EDMA0_QM_AXUSER_SECURED_SECTION 0x8000 |
|---|
| 22186 | #define mmDCORE3_EDMA0_QM_AXUSER_NONSECURED_BASE 0x47CAB80ull |
|---|
| 22187 | #define DCORE3_EDMA0_QM_AXUSER_NONSECURED_MAX_OFFSET 0x5000 |
|---|
| 22188 | #define DCORE3_EDMA0_QM_AXUSER_NONSECURED_SECTION 0x8000 |
|---|
| 22189 | #define mmDCORE3_EDMA0_QM_DBG_HBW_BASE 0x47CAC00ull |
|---|
| 22190 | #define DCORE3_EDMA0_QM_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 22191 | #define DCORE3_EDMA0_QM_DBG_HBW_SECTION 0x8000 |
|---|
| 22192 | #define mmDCORE3_EDMA0_QM_DBG_LBW_BASE 0x47CAC80ull |
|---|
| 22193 | #define DCORE3_EDMA0_QM_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 22194 | #define DCORE3_EDMA0_QM_DBG_LBW_SECTION 0x1000 |
|---|
| 22195 | #define mmDCORE3_EDMA0_QM_CGM_BASE 0x47CAD80ull |
|---|
| 22196 | #define DCORE3_EDMA0_QM_CGM_MAX_OFFSET 0xC000 |
|---|
| 22197 | #define DCORE3_EDMA0_QM_CGM_SECTION 0x1000 |
|---|
| 22198 | #define mmDCORE3_EDMA0_QM_SPECIAL_BASE 0x47CAE80ull |
|---|
| 22199 | #define DCORE3_EDMA0_QM_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22200 | #define DCORE3_EDMA0_QM_SPECIAL_SECTION 0x1800 |
|---|
| 22201 | #define mmDCORE3_EDMA0_CORE_BASE 0x47CB000ull |
|---|
| 22202 | #define DCORE3_EDMA0_CORE_MAX_OFFSET 0x1000 |
|---|
| 22203 | #define DCORE3_EDMA0_CORE_SECTION 0x8000 |
|---|
| 22204 | #define mmDCORE3_EDMA0_CORE_CTX_AXUSER_BASE 0x47CB800ull |
|---|
| 22205 | #define DCORE3_EDMA0_CORE_CTX_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 22206 | #define DCORE3_EDMA0_CORE_CTX_AXUSER_SECTION 0x6000 |
|---|
| 22207 | #define mmDCORE3_EDMA0_CORE_CTX_BASE 0x47CB860ull |
|---|
| 22208 | #define DCORE3_EDMA0_CORE_CTX_MAX_OFFSET 0x9000 |
|---|
| 22209 | #define DCORE3_EDMA0_CORE_CTX_SECTION 0x5A00 |
|---|
| 22210 | #define mmDCORE3_EDMA0_CORE_KDMA_CGM_BASE 0x47CBE00ull |
|---|
| 22211 | #define DCORE3_EDMA0_CORE_KDMA_CGM_MAX_OFFSET 0xC000 |
|---|
| 22212 | #define DCORE3_EDMA0_CORE_KDMA_CGM_SECTION 0x8000 |
|---|
| 22213 | #define mmDCORE3_EDMA0_CORE_SPECIAL_BASE 0x47CBE80ull |
|---|
| 22214 | #define DCORE3_EDMA0_CORE_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22215 | #define DCORE3_EDMA0_CORE_SPECIAL_SECTION 0x1800 |
|---|
| 22216 | #define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE 0x47CC000ull |
|---|
| 22217 | #define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_MAX_OFFSET 0x17C0 |
|---|
| 22218 | #define DCORE3_EDMA0_MSTR_IF_RR_SHRD_HBW_SECTION 0x2000 |
|---|
| 22219 | #define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_BASE 0x47CC200ull |
|---|
| 22220 | #define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_MAX_OFFSET 0x17C0 |
|---|
| 22221 | #define DCORE3_EDMA0_MSTR_IF_RR_PRVT_HBW_SECTION 0x2000 |
|---|
| 22222 | #define mmDCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_BASE 0x47CC400ull |
|---|
| 22223 | #define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_MAX_OFFSET 0x14C0 |
|---|
| 22224 | #define DCORE3_EDMA0_MSTR_IF_RR_SHRD_LBW_SECTION 0x2000 |
|---|
| 22225 | #define mmDCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_BASE 0x47CC600ull |
|---|
| 22226 | #define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_MAX_OFFSET 0x14C0 |
|---|
| 22227 | #define DCORE3_EDMA0_MSTR_IF_RR_PRVT_LBW_SECTION 0x2000 |
|---|
| 22228 | #define mmDCORE3_EDMA0_MSTR_IF_E2E_CRDT_BASE 0x47CC800ull |
|---|
| 22229 | #define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_MAX_OFFSET 0x2400 |
|---|
| 22230 | #define DCORE3_EDMA0_MSTR_IF_E2E_CRDT_SECTION 0x2800 |
|---|
| 22231 | #define mmDCORE3_EDMA0_MSTR_IF_AXUSER_BASE 0x47CCA80ull |
|---|
| 22232 | #define DCORE3_EDMA0_MSTR_IF_AXUSER_MAX_OFFSET 0x5000 |
|---|
| 22233 | #define DCORE3_EDMA0_MSTR_IF_AXUSER_SECTION 0x8000 |
|---|
| 22234 | #define mmDCORE3_EDMA0_MSTR_IF_DBG_HBW_BASE 0x47CCB00ull |
|---|
| 22235 | #define DCORE3_EDMA0_MSTR_IF_DBG_HBW_MAX_OFFSET 0x5800 |
|---|
| 22236 | #define DCORE3_EDMA0_MSTR_IF_DBG_HBW_SECTION 0x8000 |
|---|
| 22237 | #define mmDCORE3_EDMA0_MSTR_IF_DBG_LBW_BASE 0x47CCB80ull |
|---|
| 22238 | #define DCORE3_EDMA0_MSTR_IF_DBG_LBW_MAX_OFFSET 0x5800 |
|---|
| 22239 | #define DCORE3_EDMA0_MSTR_IF_DBG_LBW_SECTION 0x8000 |
|---|
| 22240 | #define mmDCORE3_EDMA0_MSTR_IF_CORE_HBW_BASE 0x47CCC00ull |
|---|
| 22241 | #define DCORE3_EDMA0_MSTR_IF_CORE_HBW_MAX_OFFSET 0x1200 |
|---|
| 22242 | #define DCORE3_EDMA0_MSTR_IF_CORE_HBW_SECTION 0x1800 |
|---|
| 22243 | #define mmDCORE3_EDMA0_MSTR_IF_CORE_LBW_BASE 0x47CCD80ull |
|---|
| 22244 | #define DCORE3_EDMA0_MSTR_IF_CORE_LBW_MAX_OFFSET 0x8000 |
|---|
| 22245 | #define DCORE3_EDMA0_MSTR_IF_CORE_LBW_SECTION 0x1000 |
|---|
| 22246 | #define mmDCORE3_EDMA0_MSTR_IF_SPECIAL_BASE 0x47CCE80ull |
|---|
| 22247 | #define DCORE3_EDMA0_MSTR_IF_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22248 | #define DCORE3_EDMA0_MSTR_IF_SPECIAL_SECTION 0x3180 |
|---|
| 22249 | #define mmDCORE3_EDMA1_QM_DCCM_BASE 0x47D0000ull |
|---|
| 22250 | #define DCORE3_EDMA1_QM_DCCM_MAX_OFFSET 0x4000 |
|---|
| 22251 | #define DCORE3_EDMA1_QM_DCCM_SECTION 0x8000 |
|---|
| 22252 | #define mmDCORE3_EDMA1_QM_ARC_AUX_BASE 0x47D8000ull |
|---|
| 22253 | #define DCORE3_EDMA1_QM_ARC_AUX_MAX_OFFSET 0x1000 |
|---|
| 22254 | #define DCORE3_EDMA1_QM_ARC_AUX_SECTION 0xE800 |
|---|
| 22255 | #define mmDCORE3_EDMA1_QM_ARC_AUX_SPECIAL_BASE 0x47D8E80ull |
|---|
| 22256 | #define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_MAX_OFFSET 0x1800 |
|---|
| 22257 | #define DCORE3_EDMA1_QM_ARC_AUX_SPECIAL_SECTION 0x1180 |
|---|
| 22258 | #define mmDCORE3_EDMA1_QM_BASE 0x47DA000ull |
|---|
| 22259 | #define DCORE3_EDMA1_QM_MAX_OFFSET 0x1000 |
|---|
| 22260 | #define DCORE3_EDMA1_QM_SECTION 0x9000 |
|---|
| 22261 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_BASE 0x47DA900ull |
|---|
| 22262 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_MAX_OFFSET 0x8000 |
|---|
| 22263 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR0_SECTION 0x8000 |
|---|
| 22264 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_BASE 0x47DA908ull |
|---|
| 22265 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_MAX_OFFSET 0x8000 |
|---|
| 22266 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR1_SECTION 0x8000 |
|---|
| 22267 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_BASE 0x47DA910ull |
|---|
| 22268 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_MAX_OFFSET 0x8000 |
|---|
| 22269 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR2_SECTION 0x8000 |
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| 22270 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_BASE 0x47DA918ull |
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| 22271 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_MAX_OFFSET 0x8000 |
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| 22272 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR3_SECTION 0x8000 |
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| 22273 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_BASE 0x47DA920ull |
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| 22274 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_MAX_OFFSET 0x8000 |
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| 22275 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR4_SECTION 0x8000 |
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| 22276 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_BASE 0x47DA928ull |
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| 22277 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_MAX_OFFSET 0x8000 |
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| 22278 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR5_SECTION 0x8000 |
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| 22279 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_BASE 0x47DA930ull |
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| 22280 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_MAX_OFFSET 0x8000 |
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| 22281 | #define DCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR6_SECTION 0x8000 |
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| 22282 | #define mmDCORE3_EDMA1_QM_QMAN_WR64_BASE_ADDR7_BASE 0x47DA938ull |
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| 22283 | #define |
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