| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_PCIE_DEC0_CMD_REGS_H_ |
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| 14 | #define ASIC_REG_PCIE_DEC0_CMD_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * PCIE_DEC0_CMD |
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| 19 | * (Prototype: VSI_CMD) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmPCIE_DEC0_CMD_SWREG0 0x4F00000 |
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| 24 | |
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| 25 | #define mmPCIE_DEC0_CMD_SWREG1 0x4F00004 |
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| 26 | |
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| 27 | #define mmPCIE_DEC0_CMD_SWREG2 0x4F00008 |
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| 28 | |
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| 29 | #define mmPCIE_DEC0_CMD_SWREG3 0x4F0000C |
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| 30 | |
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| 31 | #define mmPCIE_DEC0_CMD_SWREG4 0x4F00010 |
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| 32 | |
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| 33 | #define mmPCIE_DEC0_CMD_SWREG5 0x4F00014 |
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| 34 | |
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| 35 | #define mmPCIE_DEC0_CMD_SWREG6 0x4F00018 |
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| 36 | |
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| 37 | #define mmPCIE_DEC0_CMD_SWREG7 0x4F0001C |
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| 38 | |
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| 39 | #define mmPCIE_DEC0_CMD_SWREG8 0x4F00020 |
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| 40 | |
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| 41 | #define mmPCIE_DEC0_CMD_SWREG9 0x4F00024 |
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| 42 | |
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| 43 | #define mmPCIE_DEC0_CMD_SWREG10 0x4F00028 |
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| 44 | |
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| 45 | #define mmPCIE_DEC0_CMD_SWREG11 0x4F0002C |
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| 46 | |
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| 47 | #define mmPCIE_DEC0_CMD_SWREG12 0x4F00030 |
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| 48 | |
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| 49 | #define mmPCIE_DEC0_CMD_SWREG13 0x4F00034 |
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| 50 | |
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| 51 | #define mmPCIE_DEC0_CMD_SWREG14 0x4F00038 |
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| 52 | |
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| 53 | #define mmPCIE_DEC0_CMD_SWREG15 0x4F0003C |
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| 54 | |
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| 55 | #define mmPCIE_DEC0_CMD_SWREG16 0x4F00040 |
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| 56 | |
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| 57 | #define mmPCIE_DEC0_CMD_SWREG17 0x4F00044 |
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| 58 | |
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| 59 | #define mmPCIE_DEC0_CMD_SWREG18 0x4F00048 |
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| 60 | |
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| 61 | #define mmPCIE_DEC0_CMD_SWREG19 0x4F0004C |
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| 62 | |
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| 63 | #define mmPCIE_DEC0_CMD_SWREG20 0x4F00050 |
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| 64 | |
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| 65 | #define mmPCIE_DEC0_CMD_SWREG21 0x4F00054 |
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| 66 | |
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| 67 | #define mmPCIE_DEC0_CMD_SWREG22 0x4F00058 |
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| 68 | |
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| 69 | #define mmPCIE_DEC0_CMD_SWREG23 0x4F0005C |
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| 70 | |
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| 71 | #define mmPCIE_DEC0_CMD_SWREG24 0x4F00060 |
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| 72 | |
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| 73 | #define mmPCIE_DEC0_CMD_SWREG25 0x4F00064 |
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| 74 | |
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| 75 | #define mmPCIE_DEC0_CMD_SWREG26 0x4F00068 |
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| 76 | |
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| 77 | #define mmPCIE_DEC0_CMD_SWREG64 0x4F00100 |
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| 78 | |
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| 79 | #define mmPCIE_DEC0_CMD_SWREG65 0x4F00104 |
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| 80 | |
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| 81 | #define mmPCIE_DEC0_CMD_SWREG66 0x4F00108 |
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| 82 | |
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| 83 | #define mmPCIE_DEC0_CMD_SWREG67 0x4F0010C |
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| 84 | |
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| 85 | #endif /* ASIC_REG_PCIE_DEC0_CMD_REGS_H_ */ |
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| 86 | |
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