| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2020 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_XBAR_MID_0_REGS_H_ |
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| 14 | #define ASIC_REG_XBAR_MID_0_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * XBAR_MID_0 |
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| 19 | * (Prototype: XBAR) |
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| 20 | ***************************************** |
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| 21 | */ |
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| 22 | |
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| 23 | #define mmXBAR_MID_0_LBW_HIF0_BASE_ADDR 0x4D40000 |
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| 24 | |
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| 25 | #define mmXBAR_MID_0_LBW_HIF0_ADDR_MASK 0x4D40004 |
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| 26 | |
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| 27 | #define mmXBAR_MID_0_LBW_HIF1_BASE_ADDR 0x4D40008 |
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| 28 | |
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| 29 | #define mmXBAR_MID_0_LBW_HIF1_ADDR_MASK 0x4D4000C |
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| 30 | |
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| 31 | #define mmXBAR_MID_0_LBW_HMMU0_BASE_ADDR 0x4D40010 |
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| 32 | |
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| 33 | #define mmXBAR_MID_0_LBW_HMMU0_ADDR_MASK 0x4D40014 |
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| 34 | |
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| 35 | #define mmXBAR_MID_0_LBW_HMMU1_BASE_ADDR 0x4D40018 |
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| 36 | |
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| 37 | #define mmXBAR_MID_0_LBW_HMMU1_ADDR_MASK 0x4D4001C |
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| 38 | |
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| 39 | #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR0 0x4D40020 |
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| 40 | |
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| 41 | #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK0 0x4D40024 |
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| 42 | |
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| 43 | #define mmXBAR_MID_0_LBW_EDMA_BASE_ADDR1 0x4D40028 |
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| 44 | |
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| 45 | #define mmXBAR_MID_0_LBW_EDMA_ADDR_MASK1 0x4D4002C |
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| 46 | |
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| 47 | #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR0 0x4D40030 |
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| 48 | |
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| 49 | #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK0 0x4D40034 |
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| 50 | |
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| 51 | #define mmXBAR_MID_0_LBW_HBM_BASE_ADDR1 0x4D40038 |
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| 52 | |
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| 53 | #define mmXBAR_MID_0_LBW_HBM_ADDR_MASK1 0x4D4003C |
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| 54 | |
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| 55 | #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR0 0x4D40040 |
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| 56 | |
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| 57 | #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK0 0x4D40044 |
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| 58 | |
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| 59 | #define mmXBAR_MID_0_LBW_XBAR_BASE_ADDR1 0x4D40048 |
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| 60 | |
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| 61 | #define mmXBAR_MID_0_LBW_XBAR_ADDR_MASK1 0x4D4004C |
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| 62 | |
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| 63 | #define mmXBAR_MID_0_DBG_HIF0_BASE_ADDR 0x4D40080 |
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| 64 | |
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| 65 | #define mmXBAR_MID_0_DBG_HIF0_ADDR_MASK 0x4D40084 |
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| 66 | |
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| 67 | #define mmXBAR_MID_0_DBG_HIF1_BASE_ADDR 0x4D40088 |
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| 68 | |
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| 69 | #define mmXBAR_MID_0_DBG_HIF1_ADDR_MASK 0x4D4008C |
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| 70 | |
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| 71 | #define mmXBAR_MID_0_DBG_HMMU0_BASE_ADDR 0x4D40090 |
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| 72 | |
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| 73 | #define mmXBAR_MID_0_DBG_HMMU0_ADDR_MASK 0x4D40094 |
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| 74 | |
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| 75 | #define mmXBAR_MID_0_DBG_HMMU1_BASE_ADDR 0x4D40098 |
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| 76 | |
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| 77 | #define mmXBAR_MID_0_DBG_HMMU1_ADDR_MASK 0x4D4009C |
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| 78 | |
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| 79 | #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR0 0x4D400A0 |
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| 80 | |
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| 81 | #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK0 0x4D400A4 |
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| 82 | |
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| 83 | #define mmXBAR_MID_0_DBG_EDMA_BASE_ADDR1 0x4D400A8 |
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| 84 | |
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| 85 | #define mmXBAR_MID_0_DBG_EDMA_ADDR_MASK1 0x4D400AC |
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| 86 | |
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| 87 | #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR0 0x4D400B0 |
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| 88 | |
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| 89 | #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK0 0x4D400B4 |
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| 90 | |
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| 91 | #define mmXBAR_MID_0_DBG_HBM_BASE_ADDR1 0x4D400B8 |
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| 92 | |
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| 93 | #define mmXBAR_MID_0_DBG_HBM_ADDR_MASK1 0x4D400BC |
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| 94 | |
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| 95 | #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR0 0x4D400C0 |
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| 96 | |
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| 97 | #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK0 0x4D400C4 |
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| 98 | |
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| 99 | #define mmXBAR_MID_0_DBG_XBAR_BASE_ADDR1 0x4D400C8 |
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| 100 | |
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| 101 | #define mmXBAR_MID_0_DBG_XBAR_ADDR_MASK1 0x4D400CC |
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| 102 | |
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| 103 | #define mmXBAR_MID_0_LBW_INTERNAL_ADDR_RGF 0x4D400D0 |
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| 104 | |
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| 105 | #define mmXBAR_MID_0_DBG_INTERNAL_ADDR_FUN 0x4D400D4 |
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| 106 | |
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| 107 | #define mmXBAR_MID_0_EMEM_HBM_BIT_LOCATION 0x4D40100 |
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| 108 | |
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| 109 | #define mmXBAR_MID_0_EMEM_PC_BIT_LOCATION 0x4D40104 |
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| 110 | |
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| 111 | #define mmXBAR_MID_0_HIF_WR_RS_CH_LOCATION 0x4D40108 |
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| 112 | |
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| 113 | #define mmXBAR_MID_0_HBW_MST_ARB_WEIGHT 0x4D4010C |
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| 114 | |
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| 115 | #define mmXBAR_MID_0_MMU_PC_IDX_MAP_0 0x4D40110 |
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| 116 | |
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| 117 | #define mmXBAR_MID_0_MMU_PC_IDX_MAP_1 0x4D40114 |
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| 118 | |
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| 119 | #define mmXBAR_MID_0_MMU_RD_LL_ARB_0 0x4D40120 |
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| 120 | |
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| 121 | #define mmXBAR_MID_0_MMU_RD_LL_ARB_1 0x4D40124 |
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| 122 | |
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| 123 | #define mmXBAR_MID_0_MMU_WR_LL_ARB_0 0x4D40128 |
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| 124 | |
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| 125 | #define mmXBAR_MID_0_MMU_WR_LL_ARB_1 0x4D4012C |
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| 126 | |
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| 127 | #define mmXBAR_MID_0_HBM_USER_RESP_OVR_0 0x4D40130 |
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| 128 | |
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| 129 | #define mmXBAR_MID_0_HBM_USER_RESP_OVR_1 0x4D40134 |
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| 130 | |
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| 131 | #define mmXBAR_MID_0_RL_RD_0 0x4D40140 |
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| 132 | |
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| 133 | #define mmXBAR_MID_0_RL_RD_1 0x4D40144 |
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| 134 | |
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| 135 | #define mmXBAR_MID_0_RL_RD_2 0x4D40148 |
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| 136 | |
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| 137 | #define mmXBAR_MID_0_RL_RD_3 0x4D4014C |
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| 138 | |
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| 139 | #define mmXBAR_MID_0_RL_RD_4 0x4D40150 |
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| 140 | |
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| 141 | #define mmXBAR_MID_0_RL_RD_5 0x4D40154 |
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| 142 | |
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| 143 | #define mmXBAR_MID_0_RL_RD_6 0x4D40158 |
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| 144 | |
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| 145 | #define mmXBAR_MID_0_RL_RD_7 0x4D4015C |
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| 146 | |
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| 147 | #define mmXBAR_MID_0_RL_RD_8 0x4D40160 |
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| 148 | |
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| 149 | #define mmXBAR_MID_0_RL_RD_9 0x4D40164 |
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| 150 | |
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| 151 | #define mmXBAR_MID_0_RL_RD_10 0x4D40168 |
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| 152 | |
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| 153 | #define mmXBAR_MID_0_RL_RD_11 0x4D4016C |
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| 154 | |
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| 155 | #define mmXBAR_MID_0_RL_WR_0 0x4D40180 |
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| 156 | |
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| 157 | #define mmXBAR_MID_0_RL_WR_1 0x4D40184 |
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| 158 | |
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| 159 | #define mmXBAR_MID_0_RL_WR_2 0x4D40188 |
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| 160 | |
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| 161 | #define mmXBAR_MID_0_RL_WR_3 0x4D4018C |
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| 162 | |
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| 163 | #define mmXBAR_MID_0_RL_WR_4 0x4D40190 |
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| 164 | |
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| 165 | #define mmXBAR_MID_0_RL_WR_5 0x4D40194 |
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| 166 | |
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| 167 | #define mmXBAR_MID_0_RL_WR_6 0x4D40198 |
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| 168 | |
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| 169 | #define mmXBAR_MID_0_RL_WR_7 0x4D4019C |
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| 170 | |
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| 171 | #define mmXBAR_MID_0_RL_WR_8 0x4D401A0 |
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| 172 | |
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| 173 | #define mmXBAR_MID_0_RL_WR_9 0x4D401A4 |
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| 174 | |
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| 175 | #define mmXBAR_MID_0_RL_WR_10 0x4D401A8 |
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| 176 | |
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| 177 | #define mmXBAR_MID_0_RL_WR_11 0x4D401AC |
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| 178 | |
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| 179 | #define mmXBAR_MID_0_E2E_CRDT_SLV_0 0x4D401B0 |
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| 180 | |
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| 181 | #define mmXBAR_MID_0_E2E_CRDT_SLV_1 0x4D401B4 |
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| 182 | |
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| 183 | #define mmXBAR_MID_0_E2E_CRDT_SLV_2 0x4D401B8 |
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| 184 | |
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| 185 | #define mmXBAR_MID_0_E2E_CRDT_DEBUG 0x4D401BC |
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| 186 | |
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| 187 | #define mmXBAR_MID_0_UPSCALE 0x4D401C0 |
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| 188 | |
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| 189 | #define mmXBAR_MID_0_DOWN_CONV 0x4D401C4 |
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| 190 | |
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| 191 | #define mmXBAR_MID_0_DOWN_CONV_LFSR_EN 0x4D401D0 |
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| 192 | |
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| 193 | #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD 0x4D401D4 |
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| 194 | |
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| 195 | #define mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE 0x4D401D8 |
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| 196 | |
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| 197 | #define mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY 0x4D401DC |
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| 198 | |
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| 199 | #endif /* ASIC_REG_XBAR_MID_0_REGS_H_ */ |
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| 200 | |
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