| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_CPU_CA53_CFG_MASKS_H_ |
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| 14 | #define ASIC_REG_CPU_CA53_CFG_MASKS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * CPU_CA53_CFG (Prototype: CA53_CFG) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | /* CPU_CA53_CFG_ARM_CFG */ |
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| 23 | #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_SHIFT 0 |
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| 24 | #define CPU_CA53_CFG_ARM_CFG_AA64NAA32_MASK 0x3 |
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| 25 | #define CPU_CA53_CFG_ARM_CFG_END_SHIFT 4 |
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| 26 | #define CPU_CA53_CFG_ARM_CFG_END_MASK 0x30 |
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| 27 | #define CPU_CA53_CFG_ARM_CFG_TE_SHIFT 8 |
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| 28 | #define CPU_CA53_CFG_ARM_CFG_TE_MASK 0x300 |
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| 29 | #define CPU_CA53_CFG_ARM_CFG_VINITHI_SHIFT 12 |
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| 30 | #define CPU_CA53_CFG_ARM_CFG_VINITHI_MASK 0x3000 |
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| 31 | |
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| 32 | /* CPU_CA53_CFG_RST_ADDR_LSB */ |
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| 33 | #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_SHIFT 0 |
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| 34 | #define CPU_CA53_CFG_RST_ADDR_LSB_VECTOR_MASK 0xFFFFFFFF |
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| 35 | |
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| 36 | /* CPU_CA53_CFG_RST_ADDR_MSB */ |
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| 37 | #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_SHIFT 0 |
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| 38 | #define CPU_CA53_CFG_RST_ADDR_MSB_VECTOR_MASK 0xFF |
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| 39 | |
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| 40 | /* CPU_CA53_CFG_ARM_RST_CONTROL */ |
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| 41 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT 0 |
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| 42 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_MASK 0x3 |
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| 43 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT 4 |
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| 44 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_MASK 0x30 |
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| 45 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT 8 |
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| 46 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_MASK 0x100 |
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| 47 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_SHIFT 12 |
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| 48 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NPRESETDBG_MASK 0x1000 |
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| 49 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT 16 |
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| 50 | #define CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_MASK 0x10000 |
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| 51 | #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_SHIFT 20 |
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| 52 | #define CPU_CA53_CFG_ARM_RST_CONTROL_WARMRSTREQ_MASK 0x300000 |
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| 53 | |
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| 54 | /* CPU_CA53_CFG_ARM_AFFINITY */ |
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| 55 | #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_SHIFT 0 |
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| 56 | #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_1_MASK 0xFF |
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| 57 | #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_SHIFT 8 |
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| 58 | #define CPU_CA53_CFG_ARM_AFFINITY_LEVEL_2_MASK 0xFF00 |
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| 59 | |
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| 60 | /* CPU_CA53_CFG_ARM_DISABLE */ |
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| 61 | #define CPU_CA53_CFG_ARM_DISABLE_CP15S_SHIFT 0 |
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| 62 | #define CPU_CA53_CFG_ARM_DISABLE_CP15S_MASK 0x3 |
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| 63 | #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_SHIFT 4 |
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| 64 | #define CPU_CA53_CFG_ARM_DISABLE_CRYPTO_MASK 0x30 |
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| 65 | #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_SHIFT 8 |
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| 66 | #define CPU_CA53_CFG_ARM_DISABLE_L2_RST_MASK 0x100 |
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| 67 | #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_SHIFT 9 |
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| 68 | #define CPU_CA53_CFG_ARM_DISABLE_DBG_L1_RST_MASK 0x200 |
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| 69 | |
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| 70 | /* CPU_CA53_CFG_ARM_GIC_PERIPHBASE */ |
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| 71 | #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_SHIFT 0 |
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| 72 | #define CPU_CA53_CFG_ARM_GIC_PERIPHBASE_PERIPHBASE_MASK 0x3FFFFF |
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| 73 | |
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| 74 | /* CPU_CA53_CFG_ARM_GIC_IRQ_CFG */ |
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| 75 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_SHIFT 0 |
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| 76 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NREI_MASK 0x3 |
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| 77 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_SHIFT 4 |
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| 78 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NSEI_MASK 0x30 |
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| 79 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_SHIFT 8 |
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| 80 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NIRQ_MASK 0x300 |
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| 81 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_SHIFT 12 |
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| 82 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NFIQ_MASK 0x3000 |
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| 83 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_SHIFT 16 |
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| 84 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVFIQ_MASK 0x30000 |
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| 85 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_SHIFT 20 |
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| 86 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVIRQ_MASK 0x300000 |
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| 87 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_SHIFT 24 |
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| 88 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_NVSEI_MASK 0x3000000 |
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| 89 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_SHIFT 31 |
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| 90 | #define CPU_CA53_CFG_ARM_GIC_IRQ_CFG_GIC_EN_MASK 0x80000000 |
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| 91 | |
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| 92 | /* CPU_CA53_CFG_ARM_PWR_MNG */ |
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| 93 | #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_SHIFT 0 |
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| 94 | #define CPU_CA53_CFG_ARM_PWR_MNG_CLREXMONREQ_MASK 0x1 |
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| 95 | #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_SHIFT 1 |
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| 96 | #define CPU_CA53_CFG_ARM_PWR_MNG_EVENTI_MASK 0x2 |
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| 97 | #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_SHIFT 2 |
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| 98 | #define CPU_CA53_CFG_ARM_PWR_MNG_L2FLUSHREQ_MASK 0x4 |
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| 99 | #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_SHIFT 3 |
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| 100 | #define CPU_CA53_CFG_ARM_PWR_MNG_L2QREQN_MASK 0x8 |
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| 101 | #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_SHIFT 4 |
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| 102 | #define CPU_CA53_CFG_ARM_PWR_MNG_CPUQREQN_MASK 0x30 |
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| 103 | #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_SHIFT 8 |
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| 104 | #define CPU_CA53_CFG_ARM_PWR_MNG_NEONQREQN_MASK 0x300 |
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| 105 | #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_SHIFT 12 |
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| 106 | #define CPU_CA53_CFG_ARM_PWR_MNG_DBGPWRDUP_MASK 0x3000 |
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| 107 | |
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| 108 | /* CPU_CA53_CFG_ARB_DBG_ROM_ADDR */ |
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| 109 | #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_SHIFT 0 |
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| 110 | #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_MASK 0xFFFFFFF |
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| 111 | #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_SHIFT 31 |
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| 112 | #define CPU_CA53_CFG_ARB_DBG_ROM_ADDR_DEBUG_ROM_BASE_ADDR_VALID_MASK 0x80000000 |
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| 113 | |
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| 114 | /* CPU_CA53_CFG_ARM_DBG_MODES */ |
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| 115 | #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_SHIFT 0 |
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| 116 | #define CPU_CA53_CFG_ARM_DBG_MODES_EDBGRQ_MASK 0x3 |
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| 117 | #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_SHIFT 4 |
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| 118 | #define CPU_CA53_CFG_ARM_DBG_MODES_DBGEN_MASK 0x30 |
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| 119 | #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_SHIFT 8 |
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| 120 | #define CPU_CA53_CFG_ARM_DBG_MODES_NIDEN_MASK 0x300 |
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| 121 | #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_SHIFT 12 |
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| 122 | #define CPU_CA53_CFG_ARM_DBG_MODES_SPIDEN_MASK 0x3000 |
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| 123 | #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_SHIFT 16 |
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| 124 | #define CPU_CA53_CFG_ARM_DBG_MODES_SPNIDEN_MASK 0x30000 |
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| 125 | |
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| 126 | /* CPU_CA53_CFG_ARM_PWR_STAT_0 */ |
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| 127 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_SHIFT 0 |
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| 128 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_CLREXMONACK_MASK 0x1 |
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| 129 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_SHIFT 1 |
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| 130 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_EVENTO_MASK 0x2 |
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| 131 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_SHIFT 4 |
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| 132 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFI_MASK 0x30 |
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| 133 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_SHIFT 8 |
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| 134 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFE_MASK 0x300 |
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| 135 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_SHIFT 12 |
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| 136 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_STANDBYWFIL2_MASK 0x1000 |
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| 137 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_SHIFT 13 |
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| 138 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_L2FLUSHDONE_MASK 0x2000 |
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| 139 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_SHIFT 16 |
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| 140 | #define CPU_CA53_CFG_ARM_PWR_STAT_0_SMPEN_MASK 0x30000 |
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| 141 | |
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| 142 | /* CPU_CA53_CFG_ARM_PWR_STAT_1 */ |
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| 143 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_SHIFT 0 |
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| 144 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACTIVE_MASK 0x3 |
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| 145 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_SHIFT 4 |
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| 146 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQDENY_MASK 0x30 |
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| 147 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_SHIFT 8 |
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| 148 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_CPUQACCEPTN_MASK 0x300 |
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| 149 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_SHIFT 12 |
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| 150 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACTIVE_MASK 0x3000 |
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| 151 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_SHIFT 16 |
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| 152 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQDENY_MASK 0x30000 |
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| 153 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_SHIFT 20 |
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| 154 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_NEONQACCEPTN_MASK 0x300000 |
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| 155 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_SHIFT 24 |
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| 156 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACTIVE_MASK 0x1000000 |
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| 157 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_SHIFT 25 |
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| 158 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QDENY_MASK 0x2000000 |
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| 159 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_SHIFT 26 |
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| 160 | #define CPU_CA53_CFG_ARM_PWR_STAT_1_L2QACCEPTN_MASK 0x4000000 |
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| 161 | |
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| 162 | /* CPU_CA53_CFG_ARM_DBG_STATUS */ |
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| 163 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_SHIFT 0 |
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| 164 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGACK_MASK 0x3 |
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| 165 | #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_SHIFT 4 |
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| 166 | #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMRX_MASK 0x30 |
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| 167 | #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_SHIFT 8 |
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| 168 | #define CPU_CA53_CFG_ARM_DBG_STATUS_COMMTX_MASK 0x300 |
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| 169 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_SHIFT 12 |
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| 170 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGRSTREQ_MASK 0x3000 |
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| 171 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_SHIFT 16 |
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| 172 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGNOPWRDWN_MASK 0x30000 |
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| 173 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_SHIFT 20 |
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| 174 | #define CPU_CA53_CFG_ARM_DBG_STATUS_DBGPWRUPREQ_MASK 0x300000 |
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| 175 | |
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| 176 | /* CPU_CA53_CFG_ARM_MEM_ATTR */ |
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| 177 | #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_SHIFT 0 |
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| 178 | #define CPU_CA53_CFG_ARM_MEM_ATTR_RDMEMATTR_MASK 0xFF |
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| 179 | #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_SHIFT 8 |
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| 180 | #define CPU_CA53_CFG_ARM_MEM_ATTR_WRMEMATTR_MASK 0xFF00 |
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| 181 | #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_SHIFT 16 |
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| 182 | #define CPU_CA53_CFG_ARM_MEM_ATTR_RACKM_MASK 0x10000 |
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| 183 | #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_SHIFT 20 |
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| 184 | #define CPU_CA53_CFG_ARM_MEM_ATTR_WACKM_MASK 0x100000 |
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| 185 | |
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| 186 | /* CPU_CA53_CFG_ARM_PMU */ |
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| 187 | #define CPU_CA53_CFG_ARM_PMU_EVENT_SHIFT 0 |
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| 188 | #define CPU_CA53_CFG_ARM_PMU_EVENT_MASK 0x3FFFFFFF |
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| 189 | |
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| 190 | #endif /* ASIC_REG_CPU_CA53_CFG_MASKS_H_ */ |
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| 191 | |
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