| 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | /************************************ |
| 9 | ** This is an auto-generated file ** |
| 10 | ** DO NOT EDIT BELOW ** |
| 11 | ************************************/ |
| 12 | |
| 13 | #ifndef ASIC_REG_DMA_CH_3_REGS_H_ |
| 14 | #define ASIC_REG_DMA_CH_3_REGS_H_ |
| 15 | |
| 16 | /* |
| 17 | ***************************************** |
| 18 | * DMA_CH_3 (Prototype: DMA_CH) |
| 19 | ***************************************** |
| 20 | */ |
| 21 | |
| 22 | #define mmDMA_CH_3_CFG0 0x419000 |
| 23 | |
| 24 | #define mmDMA_CH_3_CFG1 0x419004 |
| 25 | |
| 26 | #define mmDMA_CH_3_ERRMSG_ADDR_LO 0x419008 |
| 27 | |
| 28 | #define mmDMA_CH_3_ERRMSG_ADDR_HI 0x41900C |
| 29 | |
| 30 | #define mmDMA_CH_3_ERRMSG_WDATA 0x419010 |
| 31 | |
| 32 | #define mmDMA_CH_3_RD_COMP_ADDR_LO 0x419014 |
| 33 | |
| 34 | #define mmDMA_CH_3_RD_COMP_ADDR_HI 0x419018 |
| 35 | |
| 36 | #define mmDMA_CH_3_RD_COMP_WDATA 0x41901C |
| 37 | |
| 38 | #define mmDMA_CH_3_WR_COMP_ADDR_LO 0x419020 |
| 39 | |
| 40 | #define mmDMA_CH_3_WR_COMP_ADDR_HI 0x419024 |
| 41 | |
| 42 | #define mmDMA_CH_3_WR_COMP_WDATA 0x419028 |
| 43 | |
| 44 | #define mmDMA_CH_3_LDMA_SRC_ADDR_LO 0x41902C |
| 45 | |
| 46 | #define mmDMA_CH_3_LDMA_SRC_ADDR_HI 0x419030 |
| 47 | |
| 48 | #define mmDMA_CH_3_LDMA_DST_ADDR_LO 0x419034 |
| 49 | |
| 50 | #define mmDMA_CH_3_LDMA_DST_ADDR_HI 0x419038 |
| 51 | |
| 52 | #define mmDMA_CH_3_LDMA_TSIZE 0x41903C |
| 53 | |
| 54 | #define mmDMA_CH_3_COMIT_TRANSFER 0x419040 |
| 55 | |
| 56 | #define mmDMA_CH_3_STS0 0x419044 |
| 57 | |
| 58 | #define mmDMA_CH_3_STS1 0x419048 |
| 59 | |
| 60 | #define mmDMA_CH_3_STS2 0x41904C |
| 61 | |
| 62 | #define mmDMA_CH_3_STS3 0x419050 |
| 63 | |
| 64 | #define mmDMA_CH_3_STS4 0x419054 |
| 65 | |
| 66 | #define mmDMA_CH_3_SRC_ADDR_LO_STS 0x419058 |
| 67 | |
| 68 | #define mmDMA_CH_3_SRC_ADDR_HI_STS 0x41905C |
| 69 | |
| 70 | #define mmDMA_CH_3_SRC_TSIZE_STS 0x419060 |
| 71 | |
| 72 | #define mmDMA_CH_3_DST_ADDR_LO_STS 0x419064 |
| 73 | |
| 74 | #define mmDMA_CH_3_DST_ADDR_HI_STS 0x419068 |
| 75 | |
| 76 | #define mmDMA_CH_3_DST_TSIZE_STS 0x41906C |
| 77 | |
| 78 | #define mmDMA_CH_3_RD_RATE_LIM_EN 0x419070 |
| 79 | |
| 80 | #define mmDMA_CH_3_RD_RATE_LIM_RST_TOKEN 0x419074 |
| 81 | |
| 82 | #define mmDMA_CH_3_RD_RATE_LIM_SAT 0x419078 |
| 83 | |
| 84 | #define mmDMA_CH_3_RD_RATE_LIM_TOUT 0x41907C |
| 85 | |
| 86 | #define mmDMA_CH_3_WR_RATE_LIM_EN 0x419080 |
| 87 | |
| 88 | #define mmDMA_CH_3_WR_RATE_LIM_RST_TOKEN 0x419084 |
| 89 | |
| 90 | #define mmDMA_CH_3_WR_RATE_LIM_SAT 0x419088 |
| 91 | |
| 92 | #define mmDMA_CH_3_WR_RATE_LIM_TOUT 0x41908C |
| 93 | |
| 94 | #define mmDMA_CH_3_CFG2 0x419090 |
| 95 | |
| 96 | #define mmDMA_CH_3_TDMA_CTL 0x419100 |
| 97 | |
| 98 | #define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_LO 0x419104 |
| 99 | |
| 100 | #define mmDMA_CH_3_TDMA_SRC_BASE_ADDR_HI 0x419108 |
| 101 | |
| 102 | #define mmDMA_CH_3_TDMA_SRC_ROI_BASE_0 0x41910C |
| 103 | |
| 104 | #define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_0 0x419110 |
| 105 | |
| 106 | #define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_0 0x419114 |
| 107 | |
| 108 | #define mmDMA_CH_3_TDMA_SRC_START_OFFSET_0 0x419118 |
| 109 | |
| 110 | #define mmDMA_CH_3_TDMA_SRC_STRIDE_0 0x41911C |
| 111 | |
| 112 | #define mmDMA_CH_3_TDMA_SRC_ROI_BASE_1 0x419120 |
| 113 | |
| 114 | #define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_1 0x419124 |
| 115 | |
| 116 | #define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_1 0x419128 |
| 117 | |
| 118 | #define mmDMA_CH_3_TDMA_SRC_START_OFFSET_1 0x41912C |
| 119 | |
| 120 | #define mmDMA_CH_3_TDMA_SRC_STRIDE_1 0x419130 |
| 121 | |
| 122 | #define mmDMA_CH_3_TDMA_SRC_ROI_BASE_2 0x419134 |
| 123 | |
| 124 | #define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_2 0x419138 |
| 125 | |
| 126 | #define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_2 0x41913C |
| 127 | |
| 128 | #define mmDMA_CH_3_TDMA_SRC_START_OFFSET_2 0x419140 |
| 129 | |
| 130 | #define mmDMA_CH_3_TDMA_SRC_STRIDE_2 0x419144 |
| 131 | |
| 132 | #define mmDMA_CH_3_TDMA_SRC_ROI_BASE_3 0x419148 |
| 133 | |
| 134 | #define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_3 0x41914C |
| 135 | |
| 136 | #define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_3 0x419150 |
| 137 | |
| 138 | #define mmDMA_CH_3_TDMA_SRC_START_OFFSET_3 0x419154 |
| 139 | |
| 140 | #define mmDMA_CH_3_TDMA_SRC_STRIDE_3 0x419158 |
| 141 | |
| 142 | #define mmDMA_CH_3_TDMA_SRC_ROI_BASE_4 0x41915C |
| 143 | |
| 144 | #define mmDMA_CH_3_TDMA_SRC_ROI_SIZE_4 0x419160 |
| 145 | |
| 146 | #define mmDMA_CH_3_TDMA_SRC_VALID_ELEMENTS_4 0x419164 |
| 147 | |
| 148 | #define mmDMA_CH_3_TDMA_SRC_START_OFFSET_4 0x419168 |
| 149 | |
| 150 | #define mmDMA_CH_3_TDMA_SRC_STRIDE_4 0x41916C |
| 151 | |
| 152 | #define mmDMA_CH_3_TDMA_DST_BASE_ADDR_LO 0x419170 |
| 153 | |
| 154 | #define mmDMA_CH_3_TDMA_DST_BASE_ADDR_HI 0x419174 |
| 155 | |
| 156 | #define mmDMA_CH_3_TDMA_DST_ROI_BASE_0 0x419178 |
| 157 | |
| 158 | #define mmDMA_CH_3_TDMA_DST_ROI_SIZE_0 0x41917C |
| 159 | |
| 160 | #define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_0 0x419180 |
| 161 | |
| 162 | #define mmDMA_CH_3_TDMA_DST_START_OFFSET_0 0x419184 |
| 163 | |
| 164 | #define mmDMA_CH_3_TDMA_DST_STRIDE_0 0x419188 |
| 165 | |
| 166 | #define mmDMA_CH_3_TDMA_DST_ROI_BASE_1 0x41918C |
| 167 | |
| 168 | #define mmDMA_CH_3_TDMA_DST_ROI_SIZE_1 0x419190 |
| 169 | |
| 170 | #define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_1 0x419194 |
| 171 | |
| 172 | #define mmDMA_CH_3_TDMA_DST_START_OFFSET_1 0x419198 |
| 173 | |
| 174 | #define mmDMA_CH_3_TDMA_DST_STRIDE_1 0x41919C |
| 175 | |
| 176 | #define mmDMA_CH_3_TDMA_DST_ROI_BASE_2 0x4191A0 |
| 177 | |
| 178 | #define mmDMA_CH_3_TDMA_DST_ROI_SIZE_2 0x4191A4 |
| 179 | |
| 180 | #define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_2 0x4191A8 |
| 181 | |
| 182 | #define mmDMA_CH_3_TDMA_DST_START_OFFSET_2 0x4191AC |
| 183 | |
| 184 | #define mmDMA_CH_3_TDMA_DST_STRIDE_2 0x4191B0 |
| 185 | |
| 186 | #define mmDMA_CH_3_TDMA_DST_ROI_BASE_3 0x4191B4 |
| 187 | |
| 188 | #define mmDMA_CH_3_TDMA_DST_ROI_SIZE_3 0x4191B8 |
| 189 | |
| 190 | #define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_3 0x4191BC |
| 191 | |
| 192 | #define mmDMA_CH_3_TDMA_DST_START_OFFSET_3 0x4191C0 |
| 193 | |
| 194 | #define mmDMA_CH_3_TDMA_DST_STRIDE_3 0x4191C4 |
| 195 | |
| 196 | #define mmDMA_CH_3_TDMA_DST_ROI_BASE_4 0x4191C8 |
| 197 | |
| 198 | #define mmDMA_CH_3_TDMA_DST_ROI_SIZE_4 0x4191CC |
| 199 | |
| 200 | #define mmDMA_CH_3_TDMA_DST_VALID_ELEMENTS_4 0x4191D0 |
| 201 | |
| 202 | #define mmDMA_CH_3_TDMA_DST_START_OFFSET_4 0x4191D4 |
| 203 | |
| 204 | #define mmDMA_CH_3_TDMA_DST_STRIDE_4 0x4191D8 |
| 205 | |
| 206 | #define mmDMA_CH_3_MEM_INIT_BUSY 0x4191FC |
| 207 | |
| 208 | #endif /* ASIC_REG_DMA_CH_3_REGS_H_ */ |
| 209 | |