| 1 | /* SPDX-License-Identifier: GPL-2.0 |
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| 2 | * |
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| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
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| 4 | * All Rights Reserved. |
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| 5 | * |
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| 6 | */ |
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| 7 | |
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| 8 | /************************************ |
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| 9 | ** This is an auto-generated file ** |
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| 10 | ** DO NOT EDIT BELOW ** |
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| 11 | ************************************/ |
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| 12 | |
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| 13 | #ifndef ASIC_REG_DMA_QM_0_REGS_H_ |
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| 14 | #define ASIC_REG_DMA_QM_0_REGS_H_ |
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| 15 | |
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| 16 | /* |
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| 17 | ***************************************** |
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| 18 | * DMA_QM_0 (Prototype: QMAN) |
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| 19 | ***************************************** |
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| 20 | */ |
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| 21 | |
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| 22 | #define mmDMA_QM_0_GLBL_CFG0 0x400000 |
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| 23 | |
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| 24 | #define mmDMA_QM_0_GLBL_CFG1 0x400004 |
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| 25 | |
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| 26 | #define mmDMA_QM_0_GLBL_PROT 0x400008 |
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| 27 | |
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| 28 | #define mmDMA_QM_0_GLBL_ERR_CFG 0x40000C |
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| 29 | |
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| 30 | #define mmDMA_QM_0_GLBL_ERR_ADDR_LO 0x400010 |
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| 31 | |
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| 32 | #define mmDMA_QM_0_GLBL_ERR_ADDR_HI 0x400014 |
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| 33 | |
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| 34 | #define mmDMA_QM_0_GLBL_ERR_WDATA 0x400018 |
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| 35 | |
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| 36 | #define mmDMA_QM_0_GLBL_SECURE_PROPS 0x40001C |
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| 37 | |
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| 38 | #define mmDMA_QM_0_GLBL_NON_SECURE_PROPS 0x400020 |
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| 39 | |
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| 40 | #define mmDMA_QM_0_GLBL_STS0 0x400024 |
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| 41 | |
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| 42 | #define mmDMA_QM_0_GLBL_STS1 0x400028 |
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| 43 | |
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| 44 | #define mmDMA_QM_0_PQ_BASE_LO 0x400060 |
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| 45 | |
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| 46 | #define mmDMA_QM_0_PQ_BASE_HI 0x400064 |
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| 47 | |
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| 48 | #define mmDMA_QM_0_PQ_SIZE 0x400068 |
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| 49 | |
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| 50 | #define mmDMA_QM_0_PQ_PI 0x40006C |
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| 51 | |
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| 52 | #define mmDMA_QM_0_PQ_CI 0x400070 |
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| 53 | |
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| 54 | #define mmDMA_QM_0_PQ_CFG0 0x400074 |
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| 55 | |
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| 56 | #define mmDMA_QM_0_PQ_CFG1 0x400078 |
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| 57 | |
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| 58 | #define mmDMA_QM_0_PQ_ARUSER 0x40007C |
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| 59 | |
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| 60 | #define mmDMA_QM_0_PQ_PUSH0 0x400080 |
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| 61 | |
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| 62 | #define mmDMA_QM_0_PQ_PUSH1 0x400084 |
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| 63 | |
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| 64 | #define mmDMA_QM_0_PQ_PUSH2 0x400088 |
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| 65 | |
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| 66 | #define mmDMA_QM_0_PQ_PUSH3 0x40008C |
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| 67 | |
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| 68 | #define mmDMA_QM_0_PQ_STS0 0x400090 |
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| 69 | |
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| 70 | #define mmDMA_QM_0_PQ_STS1 0x400094 |
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| 71 | |
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| 72 | #define mmDMA_QM_0_PQ_RD_RATE_LIM_EN 0x4000A0 |
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| 73 | |
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| 74 | #define mmDMA_QM_0_PQ_RD_RATE_LIM_RST_TOKEN 0x4000A4 |
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| 75 | |
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| 76 | #define mmDMA_QM_0_PQ_RD_RATE_LIM_SAT 0x4000A8 |
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| 77 | |
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| 78 | #define mmDMA_QM_0_PQ_RD_RATE_LIM_TOUT 0x4000AC |
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| 79 | |
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| 80 | #define mmDMA_QM_0_CQ_CFG0 0x4000B0 |
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| 81 | |
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| 82 | #define mmDMA_QM_0_CQ_CFG1 0x4000B4 |
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| 83 | |
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| 84 | #define mmDMA_QM_0_CQ_ARUSER 0x4000B8 |
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| 85 | |
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| 86 | #define mmDMA_QM_0_CQ_PTR_LO 0x4000C0 |
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| 87 | |
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| 88 | #define mmDMA_QM_0_CQ_PTR_HI 0x4000C4 |
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| 89 | |
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| 90 | #define mmDMA_QM_0_CQ_TSIZE 0x4000C8 |
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| 91 | |
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| 92 | #define mmDMA_QM_0_CQ_CTL 0x4000CC |
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| 93 | |
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| 94 | #define mmDMA_QM_0_CQ_PTR_LO_STS 0x4000D4 |
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| 95 | |
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| 96 | #define mmDMA_QM_0_CQ_PTR_HI_STS 0x4000D8 |
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| 97 | |
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| 98 | #define mmDMA_QM_0_CQ_TSIZE_STS 0x4000DC |
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| 99 | |
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| 100 | #define mmDMA_QM_0_CQ_CTL_STS 0x4000E0 |
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| 101 | |
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| 102 | #define mmDMA_QM_0_CQ_STS0 0x4000E4 |
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| 103 | |
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| 104 | #define mmDMA_QM_0_CQ_STS1 0x4000E8 |
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| 105 | |
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| 106 | #define mmDMA_QM_0_CQ_RD_RATE_LIM_EN 0x4000F0 |
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| 107 | |
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| 108 | #define mmDMA_QM_0_CQ_RD_RATE_LIM_RST_TOKEN 0x4000F4 |
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| 109 | |
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| 110 | #define mmDMA_QM_0_CQ_RD_RATE_LIM_SAT 0x4000F8 |
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| 111 | |
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| 112 | #define mmDMA_QM_0_CQ_RD_RATE_LIM_TOUT 0x4000FC |
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| 113 | |
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| 114 | #define mmDMA_QM_0_CQ_IFIFO_CNT 0x400108 |
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| 115 | |
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| 116 | #define mmDMA_QM_0_CP_MSG_BASE0_ADDR_LO 0x400120 |
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| 117 | |
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| 118 | #define mmDMA_QM_0_CP_MSG_BASE0_ADDR_HI 0x400124 |
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| 119 | |
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| 120 | #define mmDMA_QM_0_CP_MSG_BASE1_ADDR_LO 0x400128 |
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| 121 | |
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| 122 | #define mmDMA_QM_0_CP_MSG_BASE1_ADDR_HI 0x40012C |
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| 123 | |
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| 124 | #define mmDMA_QM_0_CP_MSG_BASE2_ADDR_LO 0x400130 |
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| 125 | |
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| 126 | #define mmDMA_QM_0_CP_MSG_BASE2_ADDR_HI 0x400134 |
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| 127 | |
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| 128 | #define mmDMA_QM_0_CP_MSG_BASE3_ADDR_LO 0x400138 |
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| 129 | |
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| 130 | #define mmDMA_QM_0_CP_MSG_BASE3_ADDR_HI 0x40013C |
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| 131 | |
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| 132 | #define mmDMA_QM_0_CP_LDMA_TSIZE_OFFSET 0x400140 |
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| 133 | |
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| 134 | #define mmDMA_QM_0_CP_LDMA_SRC_BASE_LO_OFFSET 0x400144 |
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| 135 | |
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| 136 | #define mmDMA_QM_0_CP_LDMA_SRC_BASE_HI_OFFSET 0x400148 |
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| 137 | |
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| 138 | #define mmDMA_QM_0_CP_LDMA_DST_BASE_LO_OFFSET 0x40014C |
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| 139 | |
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| 140 | #define mmDMA_QM_0_CP_LDMA_DST_BASE_HI_OFFSET 0x400150 |
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| 141 | |
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| 142 | #define mmDMA_QM_0_CP_LDMA_COMMIT_OFFSET 0x400154 |
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| 143 | |
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| 144 | #define mmDMA_QM_0_CP_FENCE0_RDATA 0x400158 |
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| 145 | |
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| 146 | #define mmDMA_QM_0_CP_FENCE1_RDATA 0x40015C |
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| 147 | |
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| 148 | #define mmDMA_QM_0_CP_FENCE2_RDATA 0x400160 |
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| 149 | |
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| 150 | #define mmDMA_QM_0_CP_FENCE3_RDATA 0x400164 |
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| 151 | |
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| 152 | #define mmDMA_QM_0_CP_FENCE0_CNT 0x400168 |
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| 153 | |
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| 154 | #define mmDMA_QM_0_CP_FENCE1_CNT 0x40016C |
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| 155 | |
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| 156 | #define mmDMA_QM_0_CP_FENCE2_CNT 0x400170 |
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| 157 | |
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| 158 | #define mmDMA_QM_0_CP_FENCE3_CNT 0x400174 |
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| 159 | |
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| 160 | #define mmDMA_QM_0_CP_STS 0x400178 |
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| 161 | |
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| 162 | #define mmDMA_QM_0_CP_CURRENT_INST_LO 0x40017C |
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| 163 | |
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| 164 | #define mmDMA_QM_0_CP_CURRENT_INST_HI 0x400180 |
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| 165 | |
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| 166 | #define mmDMA_QM_0_CP_BARRIER_CFG 0x400184 |
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| 167 | |
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| 168 | #define mmDMA_QM_0_CP_DBG_0 0x400188 |
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| 169 | |
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| 170 | #define mmDMA_QM_0_PQ_BUF_ADDR 0x400300 |
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| 171 | |
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| 172 | #define mmDMA_QM_0_PQ_BUF_RDATA 0x400304 |
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| 173 | |
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| 174 | #define mmDMA_QM_0_CQ_BUF_ADDR 0x400308 |
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| 175 | |
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| 176 | #define mmDMA_QM_0_CQ_BUF_RDATA 0x40030C |
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| 177 | |
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| 178 | #endif /* ASIC_REG_DMA_QM_0_REGS_H_ */ |
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| 179 | |
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