1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_MME2_RTR_REGS_H_
14#define ASIC_REG_MME2_RTR_REGS_H_
15
16/*
17 *****************************************
18 * MME2_RTR (Prototype: MME_RTR)
19 *****************************************
20 */
21
22#define mmMME2_RTR_HBW_RD_RQ_E_ARB 0x80100
23
24#define mmMME2_RTR_HBW_RD_RQ_W_ARB 0x80104
25
26#define mmMME2_RTR_HBW_RD_RQ_N_ARB 0x80108
27
28#define mmMME2_RTR_HBW_RD_RQ_S_ARB 0x8010C
29
30#define mmMME2_RTR_HBW_RD_RQ_L_ARB 0x80110
31
32#define mmMME2_RTR_HBW_E_ARB_MAX 0x80120
33
34#define mmMME2_RTR_HBW_W_ARB_MAX 0x80124
35
36#define mmMME2_RTR_HBW_N_ARB_MAX 0x80128
37
38#define mmMME2_RTR_HBW_S_ARB_MAX 0x8012C
39
40#define mmMME2_RTR_HBW_L_ARB_MAX 0x80130
41
42#define mmMME2_RTR_HBW_RD_RS_MAX_CREDIT 0x80140
43
44#define mmMME2_RTR_HBW_WR_RQ_MAX_CREDIT 0x80144
45
46#define mmMME2_RTR_HBW_RD_RQ_MAX_CREDIT 0x80148
47
48#define mmMME2_RTR_HBW_RD_RS_E_ARB 0x80150
49
50#define mmMME2_RTR_HBW_RD_RS_W_ARB 0x80154
51
52#define mmMME2_RTR_HBW_RD_RS_N_ARB 0x80158
53
54#define mmMME2_RTR_HBW_RD_RS_S_ARB 0x8015C
55
56#define mmMME2_RTR_HBW_RD_RS_L_ARB 0x80160
57
58#define mmMME2_RTR_HBW_WR_RQ_E_ARB 0x80170
59
60#define mmMME2_RTR_HBW_WR_RQ_W_ARB 0x80174
61
62#define mmMME2_RTR_HBW_WR_RQ_N_ARB 0x80178
63
64#define mmMME2_RTR_HBW_WR_RQ_S_ARB 0x8017C
65
66#define mmMME2_RTR_HBW_WR_RQ_L_ARB 0x80180
67
68#define mmMME2_RTR_HBW_WR_RS_E_ARB 0x80190
69
70#define mmMME2_RTR_HBW_WR_RS_W_ARB 0x80194
71
72#define mmMME2_RTR_HBW_WR_RS_N_ARB 0x80198
73
74#define mmMME2_RTR_HBW_WR_RS_S_ARB 0x8019C
75
76#define mmMME2_RTR_HBW_WR_RS_L_ARB 0x801A0
77
78#define mmMME2_RTR_LBW_RD_RQ_E_ARB 0x80200
79
80#define mmMME2_RTR_LBW_RD_RQ_W_ARB 0x80204
81
82#define mmMME2_RTR_LBW_RD_RQ_N_ARB 0x80208
83
84#define mmMME2_RTR_LBW_RD_RQ_S_ARB 0x8020C
85
86#define mmMME2_RTR_LBW_RD_RQ_L_ARB 0x80210
87
88#define mmMME2_RTR_LBW_E_ARB_MAX 0x80220
89
90#define mmMME2_RTR_LBW_W_ARB_MAX 0x80224
91
92#define mmMME2_RTR_LBW_N_ARB_MAX 0x80228
93
94#define mmMME2_RTR_LBW_S_ARB_MAX 0x8022C
95
96#define mmMME2_RTR_LBW_L_ARB_MAX 0x80230
97
98#define mmMME2_RTR_LBW_SRAM_MAX_CREDIT 0x80240
99
100#define mmMME2_RTR_LBW_RD_RS_E_ARB 0x80250
101
102#define mmMME2_RTR_LBW_RD_RS_W_ARB 0x80254
103
104#define mmMME2_RTR_LBW_RD_RS_N_ARB 0x80258
105
106#define mmMME2_RTR_LBW_RD_RS_S_ARB 0x8025C
107
108#define mmMME2_RTR_LBW_RD_RS_L_ARB 0x80260
109
110#define mmMME2_RTR_LBW_WR_RQ_E_ARB 0x80270
111
112#define mmMME2_RTR_LBW_WR_RQ_W_ARB 0x80274
113
114#define mmMME2_RTR_LBW_WR_RQ_N_ARB 0x80278
115
116#define mmMME2_RTR_LBW_WR_RQ_S_ARB 0x8027C
117
118#define mmMME2_RTR_LBW_WR_RQ_L_ARB 0x80280
119
120#define mmMME2_RTR_LBW_WR_RS_E_ARB 0x80290
121
122#define mmMME2_RTR_LBW_WR_RS_W_ARB 0x80294
123
124#define mmMME2_RTR_LBW_WR_RS_N_ARB 0x80298
125
126#define mmMME2_RTR_LBW_WR_RS_S_ARB 0x8029C
127
128#define mmMME2_RTR_LBW_WR_RS_L_ARB 0x802A0
129
130#define mmMME2_RTR_DBG_E_ARB 0x80300
131
132#define mmMME2_RTR_DBG_W_ARB 0x80304
133
134#define mmMME2_RTR_DBG_N_ARB 0x80308
135
136#define mmMME2_RTR_DBG_S_ARB 0x8030C
137
138#define mmMME2_RTR_DBG_L_ARB 0x80310
139
140#define mmMME2_RTR_DBG_E_ARB_MAX 0x80320
141
142#define mmMME2_RTR_DBG_W_ARB_MAX 0x80324
143
144#define mmMME2_RTR_DBG_N_ARB_MAX 0x80328
145
146#define mmMME2_RTR_DBG_S_ARB_MAX 0x8032C
147
148#define mmMME2_RTR_DBG_L_ARB_MAX 0x80330
149
150#define mmMME2_RTR_SPLIT_COEF_0 0x80400
151
152#define mmMME2_RTR_SPLIT_COEF_1 0x80404
153
154#define mmMME2_RTR_SPLIT_COEF_2 0x80408
155
156#define mmMME2_RTR_SPLIT_COEF_3 0x8040C
157
158#define mmMME2_RTR_SPLIT_COEF_4 0x80410
159
160#define mmMME2_RTR_SPLIT_COEF_5 0x80414
161
162#define mmMME2_RTR_SPLIT_COEF_6 0x80418
163
164#define mmMME2_RTR_SPLIT_COEF_7 0x8041C
165
166#define mmMME2_RTR_SPLIT_COEF_8 0x80420
167
168#define mmMME2_RTR_SPLIT_COEF_9 0x80424
169
170#define mmMME2_RTR_SPLIT_CFG 0x80440
171
172#define mmMME2_RTR_SPLIT_RD_SAT 0x80444
173
174#define mmMME2_RTR_SPLIT_RD_RST_TOKEN 0x80448
175
176#define mmMME2_RTR_SPLIT_RD_TIMEOUT_0 0x8044C
177
178#define mmMME2_RTR_SPLIT_RD_TIMEOUT_1 0x80450
179
180#define mmMME2_RTR_SPLIT_WR_SAT 0x80454
181
182#define mmMME2_RTR_WPLIT_WR_TST_TOLEN 0x80458
183
184#define mmMME2_RTR_SPLIT_WR_TIMEOUT_0 0x8045C
185
186#define mmMME2_RTR_SPLIT_WR_TIMEOUT_1 0x80460
187
188#define mmMME2_RTR_HBW_RANGE_HIT 0x80470
189
190#define mmMME2_RTR_HBW_RANGE_MASK_L_0 0x80480
191
192#define mmMME2_RTR_HBW_RANGE_MASK_L_1 0x80484
193
194#define mmMME2_RTR_HBW_RANGE_MASK_L_2 0x80488
195
196#define mmMME2_RTR_HBW_RANGE_MASK_L_3 0x8048C
197
198#define mmMME2_RTR_HBW_RANGE_MASK_L_4 0x80490
199
200#define mmMME2_RTR_HBW_RANGE_MASK_L_5 0x80494
201
202#define mmMME2_RTR_HBW_RANGE_MASK_L_6 0x80498
203
204#define mmMME2_RTR_HBW_RANGE_MASK_L_7 0x8049C
205
206#define mmMME2_RTR_HBW_RANGE_MASK_H_0 0x804A0
207
208#define mmMME2_RTR_HBW_RANGE_MASK_H_1 0x804A4
209
210#define mmMME2_RTR_HBW_RANGE_MASK_H_2 0x804A8
211
212#define mmMME2_RTR_HBW_RANGE_MASK_H_3 0x804AC
213
214#define mmMME2_RTR_HBW_RANGE_MASK_H_4 0x804B0
215
216#define mmMME2_RTR_HBW_RANGE_MASK_H_5 0x804B4
217
218#define mmMME2_RTR_HBW_RANGE_MASK_H_6 0x804B8
219
220#define mmMME2_RTR_HBW_RANGE_MASK_H_7 0x804BC
221
222#define mmMME2_RTR_HBW_RANGE_BASE_L_0 0x804C0
223
224#define mmMME2_RTR_HBW_RANGE_BASE_L_1 0x804C4
225
226#define mmMME2_RTR_HBW_RANGE_BASE_L_2 0x804C8
227
228#define mmMME2_RTR_HBW_RANGE_BASE_L_3 0x804CC
229
230#define mmMME2_RTR_HBW_RANGE_BASE_L_4 0x804D0
231
232#define mmMME2_RTR_HBW_RANGE_BASE_L_5 0x804D4
233
234#define mmMME2_RTR_HBW_RANGE_BASE_L_6 0x804D8
235
236#define mmMME2_RTR_HBW_RANGE_BASE_L_7 0x804DC
237
238#define mmMME2_RTR_HBW_RANGE_BASE_H_0 0x804E0
239
240#define mmMME2_RTR_HBW_RANGE_BASE_H_1 0x804E4
241
242#define mmMME2_RTR_HBW_RANGE_BASE_H_2 0x804E8
243
244#define mmMME2_RTR_HBW_RANGE_BASE_H_3 0x804EC
245
246#define mmMME2_RTR_HBW_RANGE_BASE_H_4 0x804F0
247
248#define mmMME2_RTR_HBW_RANGE_BASE_H_5 0x804F4
249
250#define mmMME2_RTR_HBW_RANGE_BASE_H_6 0x804F8
251
252#define mmMME2_RTR_HBW_RANGE_BASE_H_7 0x804FC
253
254#define mmMME2_RTR_LBW_RANGE_HIT 0x80500
255
256#define mmMME2_RTR_LBW_RANGE_MASK_0 0x80510
257
258#define mmMME2_RTR_LBW_RANGE_MASK_1 0x80514
259
260#define mmMME2_RTR_LBW_RANGE_MASK_2 0x80518
261
262#define mmMME2_RTR_LBW_RANGE_MASK_3 0x8051C
263
264#define mmMME2_RTR_LBW_RANGE_MASK_4 0x80520
265
266#define mmMME2_RTR_LBW_RANGE_MASK_5 0x80524
267
268#define mmMME2_RTR_LBW_RANGE_MASK_6 0x80528
269
270#define mmMME2_RTR_LBW_RANGE_MASK_7 0x8052C
271
272#define mmMME2_RTR_LBW_RANGE_MASK_8 0x80530
273
274#define mmMME2_RTR_LBW_RANGE_MASK_9 0x80534
275
276#define mmMME2_RTR_LBW_RANGE_MASK_10 0x80538
277
278#define mmMME2_RTR_LBW_RANGE_MASK_11 0x8053C
279
280#define mmMME2_RTR_LBW_RANGE_MASK_12 0x80540
281
282#define mmMME2_RTR_LBW_RANGE_MASK_13 0x80544
283
284#define mmMME2_RTR_LBW_RANGE_MASK_14 0x80548
285
286#define mmMME2_RTR_LBW_RANGE_MASK_15 0x8054C
287
288#define mmMME2_RTR_LBW_RANGE_BASE_0 0x80550
289
290#define mmMME2_RTR_LBW_RANGE_BASE_1 0x80554
291
292#define mmMME2_RTR_LBW_RANGE_BASE_2 0x80558
293
294#define mmMME2_RTR_LBW_RANGE_BASE_3 0x8055C
295
296#define mmMME2_RTR_LBW_RANGE_BASE_4 0x80560
297
298#define mmMME2_RTR_LBW_RANGE_BASE_5 0x80564
299
300#define mmMME2_RTR_LBW_RANGE_BASE_6 0x80568
301
302#define mmMME2_RTR_LBW_RANGE_BASE_7 0x8056C
303
304#define mmMME2_RTR_LBW_RANGE_BASE_8 0x80570
305
306#define mmMME2_RTR_LBW_RANGE_BASE_9 0x80574
307
308#define mmMME2_RTR_LBW_RANGE_BASE_10 0x80578
309
310#define mmMME2_RTR_LBW_RANGE_BASE_11 0x8057C
311
312#define mmMME2_RTR_LBW_RANGE_BASE_12 0x80580
313
314#define mmMME2_RTR_LBW_RANGE_BASE_13 0x80584
315
316#define mmMME2_RTR_LBW_RANGE_BASE_14 0x80588
317
318#define mmMME2_RTR_LBW_RANGE_BASE_15 0x8058C
319
320#define mmMME2_RTR_RGLTR 0x80590
321
322#define mmMME2_RTR_RGLTR_WR_RESULT 0x80594
323
324#define mmMME2_RTR_RGLTR_RD_RESULT 0x80598
325
326#define mmMME2_RTR_SCRAMB_EN 0x80600
327
328#define mmMME2_RTR_NON_LIN_SCRAMB 0x80604
329
330#endif /* ASIC_REG_MME2_RTR_REGS_H_ */
331

source code of linux/drivers/accel/habanalabs/include/goya/asic_reg/mme2_rtr_regs.h