1/* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright 2016-2018 HabanaLabs, Ltd.
4 * All Rights Reserved.
5 *
6 */
7
8/************************************
9 ** This is an auto-generated file **
10 ** DO NOT EDIT BELOW **
11 ************************************/
12
13#ifndef ASIC_REG_MME3_RTR_REGS_H_
14#define ASIC_REG_MME3_RTR_REGS_H_
15
16/*
17 *****************************************
18 * MME3_RTR (Prototype: MME_RTR)
19 *****************************************
20 */
21
22#define mmMME3_RTR_HBW_RD_RQ_E_ARB 0xC0100
23
24#define mmMME3_RTR_HBW_RD_RQ_W_ARB 0xC0104
25
26#define mmMME3_RTR_HBW_RD_RQ_N_ARB 0xC0108
27
28#define mmMME3_RTR_HBW_RD_RQ_S_ARB 0xC010C
29
30#define mmMME3_RTR_HBW_RD_RQ_L_ARB 0xC0110
31
32#define mmMME3_RTR_HBW_E_ARB_MAX 0xC0120
33
34#define mmMME3_RTR_HBW_W_ARB_MAX 0xC0124
35
36#define mmMME3_RTR_HBW_N_ARB_MAX 0xC0128
37
38#define mmMME3_RTR_HBW_S_ARB_MAX 0xC012C
39
40#define mmMME3_RTR_HBW_L_ARB_MAX 0xC0130
41
42#define mmMME3_RTR_HBW_RD_RS_MAX_CREDIT 0xC0140
43
44#define mmMME3_RTR_HBW_WR_RQ_MAX_CREDIT 0xC0144
45
46#define mmMME3_RTR_HBW_RD_RQ_MAX_CREDIT 0xC0148
47
48#define mmMME3_RTR_HBW_RD_RS_E_ARB 0xC0150
49
50#define mmMME3_RTR_HBW_RD_RS_W_ARB 0xC0154
51
52#define mmMME3_RTR_HBW_RD_RS_N_ARB 0xC0158
53
54#define mmMME3_RTR_HBW_RD_RS_S_ARB 0xC015C
55
56#define mmMME3_RTR_HBW_RD_RS_L_ARB 0xC0160
57
58#define mmMME3_RTR_HBW_WR_RQ_E_ARB 0xC0170
59
60#define mmMME3_RTR_HBW_WR_RQ_W_ARB 0xC0174
61
62#define mmMME3_RTR_HBW_WR_RQ_N_ARB 0xC0178
63
64#define mmMME3_RTR_HBW_WR_RQ_S_ARB 0xC017C
65
66#define mmMME3_RTR_HBW_WR_RQ_L_ARB 0xC0180
67
68#define mmMME3_RTR_HBW_WR_RS_E_ARB 0xC0190
69
70#define mmMME3_RTR_HBW_WR_RS_W_ARB 0xC0194
71
72#define mmMME3_RTR_HBW_WR_RS_N_ARB 0xC0198
73
74#define mmMME3_RTR_HBW_WR_RS_S_ARB 0xC019C
75
76#define mmMME3_RTR_HBW_WR_RS_L_ARB 0xC01A0
77
78#define mmMME3_RTR_LBW_RD_RQ_E_ARB 0xC0200
79
80#define mmMME3_RTR_LBW_RD_RQ_W_ARB 0xC0204
81
82#define mmMME3_RTR_LBW_RD_RQ_N_ARB 0xC0208
83
84#define mmMME3_RTR_LBW_RD_RQ_S_ARB 0xC020C
85
86#define mmMME3_RTR_LBW_RD_RQ_L_ARB 0xC0210
87
88#define mmMME3_RTR_LBW_E_ARB_MAX 0xC0220
89
90#define mmMME3_RTR_LBW_W_ARB_MAX 0xC0224
91
92#define mmMME3_RTR_LBW_N_ARB_MAX 0xC0228
93
94#define mmMME3_RTR_LBW_S_ARB_MAX 0xC022C
95
96#define mmMME3_RTR_LBW_L_ARB_MAX 0xC0230
97
98#define mmMME3_RTR_LBW_SRAM_MAX_CREDIT 0xC0240
99
100#define mmMME3_RTR_LBW_RD_RS_E_ARB 0xC0250
101
102#define mmMME3_RTR_LBW_RD_RS_W_ARB 0xC0254
103
104#define mmMME3_RTR_LBW_RD_RS_N_ARB 0xC0258
105
106#define mmMME3_RTR_LBW_RD_RS_S_ARB 0xC025C
107
108#define mmMME3_RTR_LBW_RD_RS_L_ARB 0xC0260
109
110#define mmMME3_RTR_LBW_WR_RQ_E_ARB 0xC0270
111
112#define mmMME3_RTR_LBW_WR_RQ_W_ARB 0xC0274
113
114#define mmMME3_RTR_LBW_WR_RQ_N_ARB 0xC0278
115
116#define mmMME3_RTR_LBW_WR_RQ_S_ARB 0xC027C
117
118#define mmMME3_RTR_LBW_WR_RQ_L_ARB 0xC0280
119
120#define mmMME3_RTR_LBW_WR_RS_E_ARB 0xC0290
121
122#define mmMME3_RTR_LBW_WR_RS_W_ARB 0xC0294
123
124#define mmMME3_RTR_LBW_WR_RS_N_ARB 0xC0298
125
126#define mmMME3_RTR_LBW_WR_RS_S_ARB 0xC029C
127
128#define mmMME3_RTR_LBW_WR_RS_L_ARB 0xC02A0
129
130#define mmMME3_RTR_DBG_E_ARB 0xC0300
131
132#define mmMME3_RTR_DBG_W_ARB 0xC0304
133
134#define mmMME3_RTR_DBG_N_ARB 0xC0308
135
136#define mmMME3_RTR_DBG_S_ARB 0xC030C
137
138#define mmMME3_RTR_DBG_L_ARB 0xC0310
139
140#define mmMME3_RTR_DBG_E_ARB_MAX 0xC0320
141
142#define mmMME3_RTR_DBG_W_ARB_MAX 0xC0324
143
144#define mmMME3_RTR_DBG_N_ARB_MAX 0xC0328
145
146#define mmMME3_RTR_DBG_S_ARB_MAX 0xC032C
147
148#define mmMME3_RTR_DBG_L_ARB_MAX 0xC0330
149
150#define mmMME3_RTR_SPLIT_COEF_0 0xC0400
151
152#define mmMME3_RTR_SPLIT_COEF_1 0xC0404
153
154#define mmMME3_RTR_SPLIT_COEF_2 0xC0408
155
156#define mmMME3_RTR_SPLIT_COEF_3 0xC040C
157
158#define mmMME3_RTR_SPLIT_COEF_4 0xC0410
159
160#define mmMME3_RTR_SPLIT_COEF_5 0xC0414
161
162#define mmMME3_RTR_SPLIT_COEF_6 0xC0418
163
164#define mmMME3_RTR_SPLIT_COEF_7 0xC041C
165
166#define mmMME3_RTR_SPLIT_COEF_8 0xC0420
167
168#define mmMME3_RTR_SPLIT_COEF_9 0xC0424
169
170#define mmMME3_RTR_SPLIT_CFG 0xC0440
171
172#define mmMME3_RTR_SPLIT_RD_SAT 0xC0444
173
174#define mmMME3_RTR_SPLIT_RD_RST_TOKEN 0xC0448
175
176#define mmMME3_RTR_SPLIT_RD_TIMEOUT_0 0xC044C
177
178#define mmMME3_RTR_SPLIT_RD_TIMEOUT_1 0xC0450
179
180#define mmMME3_RTR_SPLIT_WR_SAT 0xC0454
181
182#define mmMME3_RTR_WPLIT_WR_TST_TOLEN 0xC0458
183
184#define mmMME3_RTR_SPLIT_WR_TIMEOUT_0 0xC045C
185
186#define mmMME3_RTR_SPLIT_WR_TIMEOUT_1 0xC0460
187
188#define mmMME3_RTR_HBW_RANGE_HIT 0xC0470
189
190#define mmMME3_RTR_HBW_RANGE_MASK_L_0 0xC0480
191
192#define mmMME3_RTR_HBW_RANGE_MASK_L_1 0xC0484
193
194#define mmMME3_RTR_HBW_RANGE_MASK_L_2 0xC0488
195
196#define mmMME3_RTR_HBW_RANGE_MASK_L_3 0xC048C
197
198#define mmMME3_RTR_HBW_RANGE_MASK_L_4 0xC0490
199
200#define mmMME3_RTR_HBW_RANGE_MASK_L_5 0xC0494
201
202#define mmMME3_RTR_HBW_RANGE_MASK_L_6 0xC0498
203
204#define mmMME3_RTR_HBW_RANGE_MASK_L_7 0xC049C
205
206#define mmMME3_RTR_HBW_RANGE_MASK_H_0 0xC04A0
207
208#define mmMME3_RTR_HBW_RANGE_MASK_H_1 0xC04A4
209
210#define mmMME3_RTR_HBW_RANGE_MASK_H_2 0xC04A8
211
212#define mmMME3_RTR_HBW_RANGE_MASK_H_3 0xC04AC
213
214#define mmMME3_RTR_HBW_RANGE_MASK_H_4 0xC04B0
215
216#define mmMME3_RTR_HBW_RANGE_MASK_H_5 0xC04B4
217
218#define mmMME3_RTR_HBW_RANGE_MASK_H_6 0xC04B8
219
220#define mmMME3_RTR_HBW_RANGE_MASK_H_7 0xC04BC
221
222#define mmMME3_RTR_HBW_RANGE_BASE_L_0 0xC04C0
223
224#define mmMME3_RTR_HBW_RANGE_BASE_L_1 0xC04C4
225
226#define mmMME3_RTR_HBW_RANGE_BASE_L_2 0xC04C8
227
228#define mmMME3_RTR_HBW_RANGE_BASE_L_3 0xC04CC
229
230#define mmMME3_RTR_HBW_RANGE_BASE_L_4 0xC04D0
231
232#define mmMME3_RTR_HBW_RANGE_BASE_L_5 0xC04D4
233
234#define mmMME3_RTR_HBW_RANGE_BASE_L_6 0xC04D8
235
236#define mmMME3_RTR_HBW_RANGE_BASE_L_7 0xC04DC
237
238#define mmMME3_RTR_HBW_RANGE_BASE_H_0 0xC04E0
239
240#define mmMME3_RTR_HBW_RANGE_BASE_H_1 0xC04E4
241
242#define mmMME3_RTR_HBW_RANGE_BASE_H_2 0xC04E8
243
244#define mmMME3_RTR_HBW_RANGE_BASE_H_3 0xC04EC
245
246#define mmMME3_RTR_HBW_RANGE_BASE_H_4 0xC04F0
247
248#define mmMME3_RTR_HBW_RANGE_BASE_H_5 0xC04F4
249
250#define mmMME3_RTR_HBW_RANGE_BASE_H_6 0xC04F8
251
252#define mmMME3_RTR_HBW_RANGE_BASE_H_7 0xC04FC
253
254#define mmMME3_RTR_LBW_RANGE_HIT 0xC0500
255
256#define mmMME3_RTR_LBW_RANGE_MASK_0 0xC0510
257
258#define mmMME3_RTR_LBW_RANGE_MASK_1 0xC0514
259
260#define mmMME3_RTR_LBW_RANGE_MASK_2 0xC0518
261
262#define mmMME3_RTR_LBW_RANGE_MASK_3 0xC051C
263
264#define mmMME3_RTR_LBW_RANGE_MASK_4 0xC0520
265
266#define mmMME3_RTR_LBW_RANGE_MASK_5 0xC0524
267
268#define mmMME3_RTR_LBW_RANGE_MASK_6 0xC0528
269
270#define mmMME3_RTR_LBW_RANGE_MASK_7 0xC052C
271
272#define mmMME3_RTR_LBW_RANGE_MASK_8 0xC0530
273
274#define mmMME3_RTR_LBW_RANGE_MASK_9 0xC0534
275
276#define mmMME3_RTR_LBW_RANGE_MASK_10 0xC0538
277
278#define mmMME3_RTR_LBW_RANGE_MASK_11 0xC053C
279
280#define mmMME3_RTR_LBW_RANGE_MASK_12 0xC0540
281
282#define mmMME3_RTR_LBW_RANGE_MASK_13 0xC0544
283
284#define mmMME3_RTR_LBW_RANGE_MASK_14 0xC0548
285
286#define mmMME3_RTR_LBW_RANGE_MASK_15 0xC054C
287
288#define mmMME3_RTR_LBW_RANGE_BASE_0 0xC0550
289
290#define mmMME3_RTR_LBW_RANGE_BASE_1 0xC0554
291
292#define mmMME3_RTR_LBW_RANGE_BASE_2 0xC0558
293
294#define mmMME3_RTR_LBW_RANGE_BASE_3 0xC055C
295
296#define mmMME3_RTR_LBW_RANGE_BASE_4 0xC0560
297
298#define mmMME3_RTR_LBW_RANGE_BASE_5 0xC0564
299
300#define mmMME3_RTR_LBW_RANGE_BASE_6 0xC0568
301
302#define mmMME3_RTR_LBW_RANGE_BASE_7 0xC056C
303
304#define mmMME3_RTR_LBW_RANGE_BASE_8 0xC0570
305
306#define mmMME3_RTR_LBW_RANGE_BASE_9 0xC0574
307
308#define mmMME3_RTR_LBW_RANGE_BASE_10 0xC0578
309
310#define mmMME3_RTR_LBW_RANGE_BASE_11 0xC057C
311
312#define mmMME3_RTR_LBW_RANGE_BASE_12 0xC0580
313
314#define mmMME3_RTR_LBW_RANGE_BASE_13 0xC0584
315
316#define mmMME3_RTR_LBW_RANGE_BASE_14 0xC0588
317
318#define mmMME3_RTR_LBW_RANGE_BASE_15 0xC058C
319
320#define mmMME3_RTR_RGLTR 0xC0590
321
322#define mmMME3_RTR_RGLTR_WR_RESULT 0xC0594
323
324#define mmMME3_RTR_RGLTR_RD_RESULT 0xC0598
325
326#define mmMME3_RTR_SCRAMB_EN 0xC0600
327
328#define mmMME3_RTR_NON_LIN_SCRAMB 0xC0604
329
330#endif /* ASIC_REG_MME3_RTR_REGS_H_ */
331

source code of linux/drivers/accel/habanalabs/include/goya/asic_reg/mme3_rtr_regs.h