| 1 | /* SPDX-License-Identifier: GPL-2.0 |
| 2 | * |
| 3 | * Copyright 2016-2018 HabanaLabs, Ltd. |
| 4 | * All Rights Reserved. |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | /************************************ |
| 9 | ** This is an auto-generated file ** |
| 10 | ** DO NOT EDIT BELOW ** |
| 11 | ************************************/ |
| 12 | |
| 13 | #ifndef ASIC_REG_PSOC_SPI_REGS_H_ |
| 14 | #define ASIC_REG_PSOC_SPI_REGS_H_ |
| 15 | |
| 16 | /* |
| 17 | ***************************************** |
| 18 | * PSOC_SPI (Prototype: SPI) |
| 19 | ***************************************** |
| 20 | */ |
| 21 | |
| 22 | #define mmPSOC_SPI_CTRLR0 0xC43000 |
| 23 | |
| 24 | #define mmPSOC_SPI_CTRLR1 0xC43004 |
| 25 | |
| 26 | #define mmPSOC_SPI_SSIENR 0xC43008 |
| 27 | |
| 28 | #define mmPSOC_SPI_MWCR 0xC4300C |
| 29 | |
| 30 | #define mmPSOC_SPI_SER 0xC43010 |
| 31 | |
| 32 | #define mmPSOC_SPI_BAUDR 0xC43014 |
| 33 | |
| 34 | #define mmPSOC_SPI_TXFTLR 0xC43018 |
| 35 | |
| 36 | #define mmPSOC_SPI_RXFTLR 0xC4301C |
| 37 | |
| 38 | #define mmPSOC_SPI_TXFLR 0xC43020 |
| 39 | |
| 40 | #define mmPSOC_SPI_RXFLR 0xC43024 |
| 41 | |
| 42 | #define mmPSOC_SPI_SR 0xC43028 |
| 43 | |
| 44 | #define mmPSOC_SPI_IMR 0xC4302C |
| 45 | |
| 46 | #define mmPSOC_SPI_ISR 0xC43030 |
| 47 | |
| 48 | #define mmPSOC_SPI_RISR 0xC43034 |
| 49 | |
| 50 | #define mmPSOC_SPI_TXOICR 0xC43038 |
| 51 | |
| 52 | #define mmPSOC_SPI_RXOICR 0xC4303C |
| 53 | |
| 54 | #define mmPSOC_SPI_RXUICR 0xC43040 |
| 55 | |
| 56 | #define mmPSOC_SPI_MSTICR 0xC43044 |
| 57 | |
| 58 | #define mmPSOC_SPI_ICR 0xC43048 |
| 59 | |
| 60 | #define mmPSOC_SPI_IDR 0xC43058 |
| 61 | |
| 62 | #define mmPSOC_SPI_SSI_VERSION_ID 0xC4305C |
| 63 | |
| 64 | #define mmPSOC_SPI_DR0 0xC43060 |
| 65 | |
| 66 | #define mmPSOC_SPI_DR1 0xC43064 |
| 67 | |
| 68 | #define mmPSOC_SPI_DR2 0xC43068 |
| 69 | |
| 70 | #define mmPSOC_SPI_DR3 0xC4306C |
| 71 | |
| 72 | #define mmPSOC_SPI_DR4 0xC43070 |
| 73 | |
| 74 | #define mmPSOC_SPI_DR5 0xC43074 |
| 75 | |
| 76 | #define mmPSOC_SPI_DR6 0xC43078 |
| 77 | |
| 78 | #define mmPSOC_SPI_DR7 0xC4307C |
| 79 | |
| 80 | #define mmPSOC_SPI_DR8 0xC43080 |
| 81 | |
| 82 | #define mmPSOC_SPI_DR9 0xC43084 |
| 83 | |
| 84 | #define mmPSOC_SPI_DR10 0xC43088 |
| 85 | |
| 86 | #define mmPSOC_SPI_DR11 0xC4308C |
| 87 | |
| 88 | #define mmPSOC_SPI_DR12 0xC43090 |
| 89 | |
| 90 | #define mmPSOC_SPI_DR13 0xC43094 |
| 91 | |
| 92 | #define mmPSOC_SPI_DR14 0xC43098 |
| 93 | |
| 94 | #define mmPSOC_SPI_DR15 0xC4309C |
| 95 | |
| 96 | #define mmPSOC_SPI_DR16 0xC430A0 |
| 97 | |
| 98 | #define mmPSOC_SPI_DR17 0xC430A4 |
| 99 | |
| 100 | #define mmPSOC_SPI_DR18 0xC430A8 |
| 101 | |
| 102 | #define mmPSOC_SPI_DR19 0xC430AC |
| 103 | |
| 104 | #define mmPSOC_SPI_DR20 0xC430B0 |
| 105 | |
| 106 | #define mmPSOC_SPI_DR21 0xC430B4 |
| 107 | |
| 108 | #define mmPSOC_SPI_DR22 0xC430B8 |
| 109 | |
| 110 | #define mmPSOC_SPI_DR23 0xC430BC |
| 111 | |
| 112 | #define mmPSOC_SPI_DR24 0xC430C0 |
| 113 | |
| 114 | #define mmPSOC_SPI_DR25 0xC430C4 |
| 115 | |
| 116 | #define mmPSOC_SPI_DR26 0xC430C8 |
| 117 | |
| 118 | #define mmPSOC_SPI_DR27 0xC430CC |
| 119 | |
| 120 | #define mmPSOC_SPI_DR28 0xC430D0 |
| 121 | |
| 122 | #define mmPSOC_SPI_DR29 0xC430D4 |
| 123 | |
| 124 | #define mmPSOC_SPI_DR30 0xC430D8 |
| 125 | |
| 126 | #define mmPSOC_SPI_DR31 0xC430DC |
| 127 | |
| 128 | #define mmPSOC_SPI_DR32 0xC430E0 |
| 129 | |
| 130 | #define mmPSOC_SPI_DR33 0xC430E4 |
| 131 | |
| 132 | #define mmPSOC_SPI_DR34 0xC430E8 |
| 133 | |
| 134 | #define mmPSOC_SPI_DR35 0xC430EC |
| 135 | |
| 136 | #define mmPSOC_SPI_RX_SAMPLE_DLY 0xC430F0 |
| 137 | |
| 138 | #define mmPSOC_SPI_RSVD_1 0xC430F8 |
| 139 | |
| 140 | #define mmPSOC_SPI_RSVD_2 0xC430FC |
| 141 | |
| 142 | #endif /* ASIC_REG_PSOC_SPI_REGS_H_ */ |
| 143 | |